ADG1414BRUZ

FEATURES FUNCTIONAL BLOCK DIAGRAM SPI interface Supports daisy-chain mode 9.5 Ω on resistance at 25°C and ±15 V dual supply 1.6 Ω on-resistance flatness at 25°C and ±15 V dual supply Fully specified at ±15 V, +12 V, ±5 V 3 V logic-compatible inputs Rail-to-rail operation 24-lead TSSOP and 24-lead, 4 mm × 4 mm LFCSP ADG1414 APPLICATIONS S1 D1 S2 D2 S3 D3 S4 D4 S5 D5 S6 D6 S7 D7 S8 D8 INPUT SHIFT REGISTER Automatic test equipment Data acquisition systems Battery-powered systems Sample-and-hold systems Audio signal routing Video signal routing Communication systems SCLK DIN SYNC SDO RESET/VL 08497-001 Data Sheet 9.5 Ω RON, ±15 V/+12 V/±5 V iCMOS, Serially-Controlled Octal SPST Switches ADG1414 Figure 1. GENERAL DESCRIPTION The ADG1414 is a monolithic complementary metal-oxide semiconductor (CMOS) device containing eight independently selectable switches designed on an industrial CMOS (iCMOS®) process. iCMOS is a modular manufacturing process combining high voltage CMOS and bipolar technologies. iCMOS components can tolerate high supply voltages while providing increased performance, dramatically lower power consumption, and reduce the package size. The ADG1414 is a set of octal, single-pole, single-throw (SPST) switches controlled via a 3-wire serial interface. On resistance is matched closely between switches and is very flat over the full signal range. Each switch conducts equally well in both directions and the input signal range extends to the supplies. The ADG1414 uses a versatile 3-wire serial interface that operates at clock rates of up to 50 MHz and is compatible with standard SPI, QSPI™, MICROWIRE™, and DSP interface standards. The output of the shift register, SDO, enables a number of these devices to be daisy chained. At power-up, all switches are in the off condition, and the internal registers contain all zeros. PRODUCT HIGHLIGHTS 1. 2. 3. 4. 50 MHz serial interface. 9.5 Ω on resistance. 1.6 Ω on-resistance flatness. 24-lead TSSOP and 4 mm × 4 mm LFCSP packages. Data is written to these devices in the form of eight bits; each bit corresponds to one channel. Rev. B Document Feedback Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective owners. One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. Tel: 781.329.4700 ©2009–2015 Analog Devices, Inc. All rights reserved. Technical Support www.analog.com ADG1414 Data Sheet TABLE OF CONTENTS Features .............................................................................................. 1 ESD Caution...................................................................................9 Applications ....................................................................................... 1 Pin Configurations and Function Descriptions ......................... 10 Functional Block Diagram .............................................................. 1 Typical Performance Characteristics ........................................... 12 Product Highlights ........................................................................... 1 Test Circuits..................................................................................... 15 Revision History ............................................................................... 2 Terminology .................................................................................... 17 Specifications..................................................................................... 3 Theory of Operation ...................................................................... 18 ±15 V Dual Supply ....................................................................... 3 Serial Interface ............................................................................ 18 12 V Single Supply ........................................................................ 4 Input Shift Register .................................................................... 18 ±5 V Dual Supply ......................................................................... 6 Power-On Reset .......................................................................... 18 Continuous Current per Channel .............................................. 7 Daisy Chaining ........................................................................... 18 Timing Characteristics ................................................................ 8 Outline Dimensions ....................................................................... 19 Absolute Maximum Ratings ............................................................ 9 Ordering Guide .......................................................................... 19 Thermal Resistance ...................................................................... 9 REVISION HISTORY 11/15—Rev. A to Rev. B Changes to VDD/VSS Parameter, Table 2 ......................................... 5 Updated Outline Dimensions ....................................................... 19 1/13—Rev. 0 to Rev. A Changes to RESET/VL Pin Description Column, Table 9 ......... 11 Changes to Power-On Reset Section ............................................ 19 Updated Outline Dimensions ....................................................... 20 10/09—Revision 0: Initial Version Rev. B | Page 2 of 19 Data Sheet ADG1414 SPECIFICATIONS ±15 V DUAL SUPPLY VDD = 15 V ± 10%, VSS = −15 V ± 10%, VL = 2.7 V to 5.5 V, GND = 0 V, unless otherwise noted. Table 1. Parameter ANALOG SWITCH Analog Signal Range On Resistance (RON) +25°C −40°C to +85°C VSS to VDD 9.5 11.5 0.55 14 On-Resistance Match Between Channels (ΔRON) 1 1.6 1.5 On-Resistance Flatness (RFLAT (ON)) 1.9 2.15 LEAKAGE CURRENTS Source Off Leakage, IS (Off ) ±0.05 ±0.15 ±0.05 ±1 Drain Off Leakage, ID (Off ) ±0.15 ±0.1 ±0.3 Channel On Leakage, ID, IS (On) DIGITAL INPUTS Input High Voltage (VINH) Input Low Voltage (VINL) Input Current −40°C to +125°C 16 1.7 2.3 High Impedance Leakage Current Ω max Ω typ VDD = +13.5 V, VSS = −13.5 V, VS = ±10 V, IS = −10 mA VDD = +13.5 V, VSS = −13.5 V, VS = ±10 V, IS = −10 mA Ω max VDD = +16.5 V, VSS = −16.5 V ±2 nA max nA typ VS = ±10 V, VD = ∓10 V; see Figure 24 ±1 ±2 VS = VD = ±10 V; see Figure 25 ±2 ±4 nA max nA typ nA max V min V max µA typ µA max pF typ VIN = VGND or VL 2.0 0.8 ±0.001 4 0.4 0.6 0.001 4 Charge Injection Off Isolation Channel-to-Channel Crosstalk Total Harmonic Distortion (THD + N) 75 93 25 35 10 −73 −75 0.05 −3 dB Bandwidth Insertion Loss CD, CS (Off ) CD, CS (On) 256 0.55 8 32 tOFF Ω max Ω typ VDD = +13.5 V, VSS = −13.5 V, VS = ±10 V, IS = −10 mA; see Figure 23 VS = ±10 V, VD = ∓10 V; see Figure 24 ±1 High Impedance Output Capacitance1 DYNAMIC CHARACTERISTICS1 tON V Ω typ Test Conditions/Comments nA typ ±0.1 Digital Input Capacitance (CIN) LOGIC OUTPUTS (SDO) Output Low Voltage (VOL) 1 Unit 110 120 35 35 V max V max µA typ µA max pF typ ISINK = 3 mA ISINK = 6 mA ns typ ns max ns typ ns max pC typ dB typ dB typ % typ RL = 100 Ω, CL = 35 pF VS = 10 V; see Figure 30 RL = 100 Ω, CL = 35 pF VS = 10 V; see Figure 30 VS = 0 V, RS = 0 Ω, CL = 1 nF; see Figure 31 RL = 50 Ω, CL = 5 pF, f = 1 MHz; see Figure 26 RL = 50 Ω, CL = 5 pF, f = 1 MHz; see Figure 27 RL = 110 Ω, 15 V p-p, f = 20 Hz to 20 kHz; see Figure 29 RL = 50 Ω, CL = 5 pF; see Figure 28 RL = 50 Ω, CL = 5 pF, f = 1 MHz; see Figure 28 f = 1 MHz f = 1 MHz MHz typ dB typ pF typ pF typ Rev. B | Page 3 of 19 ADG1414 Parameter POWER REQUIREMENTS IDD Data Sheet +25°C −40°C to +85°C −40°C to +125°C 0.001 1 IL Inactive 0.3 IL Active at 30 MHz 0.26 1 IL Active at 50 MHz ISS 0.3 0.35 0.5 0.55 0.42 0.001 1 ±4.5/±16.5 VDD/VSS 1 Unit µA typ µA max µA typ µA max mA typ mA max mA typ mA max µA typ µA max V min/max Test Conditions/Comments VDD = +16.5 V, VSS = −16.5 V Digital inputs = 0 V or VL Digital inputs = 0 V or VL Digital inputs toggle between 0 V and VL Digital inputs toggle between 0 V and VL Digital inputs = 0 V or VL Guaranteed by design, not subject to production test. 12 V SINGLE SUPPLY VDD = 12 V ± 10%, VSS = 0 V, VL = 2.7 V to 5.5 V, GND = 0 V, unless otherwise noted. Table 2. Parameter ANALOG SWITCH Analog Signal Range On Resistance (RON) +25°C −40°C to +85°C 0 to VDD 18 21.5 0.55 26 On-Resistance Match Between Channels (ΔRON) 1.2 5 1.6 On-Resistance Flatness (RFLAT (ON)) 6 6.9 LEAKAGE CURRENTS Source Off Leakage, IS (Off ) Drain Off Leakage, ID (Off ) Channel On Leakage, ID, IS (On) DIGITAL INPUTS Input High Voltage (VINH) Input Low Voltage (VINL) Input Current −40°C to +125°C ±0.02 ±0.15 ±0.02 ±0.15 ±0.05 ±0.3 28.5 1.8 7.3 ±1 ±2 ±1 ±2 ±2 ±4 2.0 0.8 ±0.001 ±0.1 Digital Input Capacitance (CIN) LOGIC OUTPUTS (SDO) Output Low Voltage (VOL) 1 High Impedance Leakage Current High Impedance Output Capacitance1 4 0.4 0.6 ±1 4 Rev. B | Page 4 of 19 Unit V Ω typ Ω max Ω typ Ω max Ω typ Test Conditions/Comments VDD = 10.8 V, VSS = 0 V; VS = 0 V to 10 V, IS = −10 mA; see Figure 23 VDD = 10.8 V, VSS = 0 V; VS = 0 V to 10 V, IS = −10 mA VDD = 10.8 V, VSS = 0 V; VS = 0 V to 10 V, IS = −10 mA Ω max nA typ nA max nA typ nA max nA typ nA max V min V max µA typ µA max pF typ V max V max µA max pF typ VDD = 10.8 V VS = 1 V/10 V, VD = 10 V/1 V; see Figure 24 VS = 1 V/10 V, VD = 10 V/1 V; see Figure 24 VS = VD = 1 V or 10 V; see Figure 25 VIN = VGND or VL ISINK = 3 mA ISINK = 6 mA Data Sheet Parameter DYNAMIC CHARACTERISTICS1 tON ADG1414 +25°C −40°C to +85°C −40°C to +125°C 220 240 46 46 Test Conditions/Comments ns typ ns max ns typ ns max pC typ dB typ RL = 100 Ω, CL = 35 pF VS = 8 V; see Figure 30 RL = 100 Ω, CL = 35 pF VS = 8 V; see Figure 30 VS = 6 V, RS = 0 Ω, CL = 1 nF; see Figure 31 RL = 50 Ω, CL = 5 pF, f = 1 MHz; see Figure 26 RL = 50 Ω, CL = 5 pF, f = 1 MHz; see Figure 27 RL = 50 Ω, CL = 5 pF; see Figure 28 RL = 50 Ω, CL = 5 pF, f = 1 MHz; see Figure 28 f = 1 MHz f = 1 MHz VDD = +13.2 V Digital inputs = 0 V or VL Charge Injection Off Isolation 145 185 35 45 8 −70 Channel-to-Channel Crosstalk −75 dB typ −3 dB Bandwidth Insertion Loss 240 1.15 MHz typ dB typ 12 33 pF typ pF typ tOFF CD, CS (Off ) CD, CS (On) POWER REQUIREMENTS IDD 0.001 1 IL Inactive 0.3 1 IL Active at 30 MHz IL Active at 50 MHz ISS VDD/VSS 1 Unit 0.26 0.3 0.35 0.5 0.55 0.42 0.001 1 5/16.5 Guaranteed by design, not subject to production test. Rev. B | Page 5 of 19 µA typ µA max µA typ µA max mA typ mA max mA typ mA max µA typ µA max V min/max Digital inputs = 0 V or VL Digital inputs toggle between 0 V and VL Digital inputs toggle between 0 V and VL Digital inputs = 0 V or VL ADG1414 Data Sheet ±5 V DUAL SUPPLY VDD = +5 V ± 10%, VSS = −5 V ± 10%, VL = 2.7 V to VDD, GND = 0 V, unless otherwise noted. Table 3. Parameter ANALOG SWITCH Analog Signal Range On Resistance (RON) On-Resistance Match Between Channels (ΔRON) On-Resistance Flatness (RFLAT (ON)) +25°C −40°C to +85°C VSS to VDD 21 25 0.6 29 1.3 5.2 6.4 1.7 1.9 7.3 7.6 LEAKAGE CURRENTS Source Off Leakage, IS (Off ) ±0.02 ±1 Drain Off Leakage, ID (Off ) ±0.15 ±0.02 ±0.15 ±0.05 ±0.3 Channel On Leakage, ID, IS (On) DIGITAL INPUTS Input High Voltage (VINH) Input Low Voltage (VINL) Input Current −40°C to +125°C 32 V Ω typ Ω max Ω typ Ω max Ω typ Ω max Test Conditions/Comments VDD = +4.5 V, VSS = −4.5 V, VS = ±4.5 V, IS = −10 mA; see Figure 23 VDD = +4.5 V, VSS = −4.5 V, VS = ±4.5V, IS = −10 mA VDD = +4.5 V, VSS = −4.5 V, VS = ±4.5 V; IS = −10 mA VDD = +5.5 V, VSS = −5.5 V nA typ VS = ±4.5 V, VD = ∓4.5 V; see Figure 24 ±2 nA max nA typ VS = ±4.5 V, VD = ∓4.5 V; see Figure 24 ±1 ±2 VS = VD = ±4.5 V; see Figure 25 ±2 ±4 nA max nA typ nA max V min V max µA typ µA max pF typ VIN = VGND or VL 2.0 0.8 ±0.001 ±0.1 Digital Input Capacitance (CIN) LOGIC OUTPUTS (SDO) Output Low Voltage (VOL) 1 Unit 4 ISINK = 3 mA ISINK = 6 mA 4 V max V max µA max pF typ Charge Injection Off Isolation Channel-to-Channel Crosstalk Total Harmonic Distortion (THD + N) 190 250 45 60 7 –70 –75 0.14 ns typ ns max ns typ ns max pC typ dB typ dB typ % typ −3 dB Bandwidth Insertion Loss CD, CS (Off ) CD, CS (On) 256 1 11 35 RL = 100 Ω, CL = 35 pF VS = 3 V; see Figure 30 RL = 100 Ω, CL = 35 pF VS = 3 V; see Figure 30 VS = 0 V, RS = 0 Ω, CL = 1 nF; see Figure 31 RL = 50 Ω, CL = 5 pF, f = 1 MHz; see Figure 26 RL = 50 Ω, CL = 5 pF, f = 1 MHz; see Figure 27 RL = 110 Ω, 5 V p-p, f = 20 Hz to 20 kHz; see Figure 29 RL = 50 Ω, CL = 5 pF; see Figure 28 RL = 50 Ω, CL = 5 pF, f = 1 MHz; see Figure 28 f = 1 MHz f = 1 MHz High Impedance Leakage Current High Impedance Output Capacitance1 DYNAMIC CHARACTERISTICS1 tON tOFF 0.4 0.6 ±1 290 320 65 70 MHz typ dB typ pF typ pF typ Rev. B | Page 6 of 19 Data Sheet ADG1414 Parameter POWER REQUIREMENTS IDD +25°C −40°C to +85°C −40°C to +125°C 0.001 1 IL Inactive 0.3 IL Active at 30 MHz 0.26 1 IL Active at 50 MHz 0.3 0.35 0.5 0.55 0.42 ISS 0.001 1 ±4.5/±16.5 VDD/VSS 1 Unit µA typ µA max µA typ µA max mA typ mA max mA typ mA max µA typ µA max V min/max Test Conditions/Comments VDD = +5.5 V, VSS = −5.5 V Digital inputs = 0 V or VL Digital inputs = 0 V or VL Digital inputs toggle between 0 V and VL Digital inputs toggle between 0 V and VL Digital inputs = 0 V or VL Guaranteed by design, not subject to production test. CONTINUOUS CURRENT PER CHANNEL Guaranteed by design, not subject to production test. Table 4. Eight Channels On Parameter CONTINUOUS CURRENT PER CHANNEL ±15 V Dual Supply 24-Lead TSSOP (θJA = 112.6°C/W) 24-Lead LFCSP (θJA = 30.4°C/W) 12 V Single Supply 24-Lead TSSOP (θJA = 112.6°C/W) 24-Lead LFCSP (θJA = 30.4°C/W) ±5 V Dual Supply 24-Lead TSSOP (θJA = 112.6°C/W) 24-Lead LFCSP (θJA = 30.4°C/W) 25°C 85°C 125°C Unit 67 121 46 75 31 42 mA max mA max 64 115 44 72 30 41 mA max mA max 48 86 35 57 22 36 mA max mA max Test Conditions/Comments VDD = +13.5 V, VSS = −13.5 V VDD = 10.8 V, VSS = 0 V VDD = +4.5 V, VSS = −4.5 V Guaranteed by design and characterization, not production tested. Table 5. One Channel On Parameter CONTINUOUS CURRENT PER CHANNEL ±15 V Dual Supply 24-Lead TSSOP (θJA = 112.6°C/W) 24-Lead LFCSP (θJA = 30.4°C/W) 12 V Single Supply 24-Lead TSSOP (θJA = 112.6°C/W) 24-Lead LFCSP (θJA = 30.4°C/W) ±5 V Dual Supply 24-Lead TSSOP (θJA = 112.6°C/W) 24-Lead LFCSP (θJA = 30.4°C/W) 25°C 85°C 125°C Unit 169 295 97 139 48 55 mA max mA max 161 281 93 135 47 54 mA max mA max 122 214 76 114 43 51 mA max mA max Test Conditions/Comments VDD = +13.5 V, VSS = −13.5 V VDD = 10.8 V, VSS = 0 V VDD = +4.5 V, VSS = −4.5 V Rev. B | Page 7 of 19 ADG1414 Data Sheet TIMING CHARACTERISTICS All input signals are specified with tR = tF = 1 ns/V (10% to 90% of VDD) and timed from a voltage level of (VIL + VIH)/2 (see Figure 2). VDD = 4.5 V to 16.5 V; VSS = −16.5 V to 0 V; VL = 2.7 V to 5.5 V or VDD (whichever is less); GND = 0 V; all specifications TMIN to TMAX, unless otherwise noted. Guaranteed by design and characterization, not production tested. Table 6. Parameter t11 t2 t3 t4 t5 t6 t7 t8 t9 t10 t112 t12 1 2 Limit at TMIN, TMAX 20 9 9 5 5 5 5 15 5 5 40 15 Unit ns min ns min ns min ns min ns min ns min ns min ns min ns min ns min ns max ns min Conditions/Comments SCLK cycle time SCLK high time SCLK low time SYNC to SCLK active edge setup time Data setup time Data hold time SCLK active edge to SYNC rising edge Minimum SYNC high time SYNC rising edge to next SCLK active edge ignored SCLK active edge to SYNC falling edge ignored SCLK rising edge to SDO valid Minimum RESET pulse width Maximum SCLK frequency is 50 MHz at VDD = 4.5 V to 16.5 V; VSS = −16.5 V to 0 V, VL = 2.7 V to 5.5 V or VDD (whichever is less); GND = 0 V. Measured with the 1 kΩ pull-up resistor to VL and 20 pF load. t11 determines the maximum SCLK frequency in daisy-chain mode. Timing Diagrams t10 t1 t9 SCLK t8 t2 t3 t4 t7 SYNC t5 DIN t6 DB0 DB7 08497-002 RESET t12 Figure 2. Serial Write Operation t1 SCLK 8 t8 t3 t4 16 t9 t2 t7 SYNC t5 DIN t6 DB7 DB0 DB0 DB7 INPUT WORD FOR DEVICE N + 1 INPUT WORD FOR DEVICE N t11 DB0 DB31 UNDEFINED INPUT WORD FOR DEVICE N Figure 3. Daisy-Chain Timing Diagram Rev. B | Page 8 of 19 08497-003 SDO Data Sheet ADG1414 ABSOLUTE MAXIMUM RATINGS TA = 25°C, unless otherwise noted. Table 7. Parameter VDD to VSS VDD to GND VSS to GND VL to GND Analog Inputs1 Digital Inputs1 Continuous Current, Sx or Dx Pins Peak Current, Sx or Dx (Pulsed at 1 ms, 10% Duty Cycle Maximum) TSSOP Package LFCSP Package Operating Temperature Range Industrial (B Version) Storage Temperature Range Junction Temperature Reflow Soldering Peak Temperature, Pb free Time at Peak Temperature 1 Rating 35 V −0.3 V to +25 V +0.3 V to −25 V −0.3 V to +7 V VSS − 0.3 V to VDD + 0.3 V or 30 mA, whichever occurs first GND − 0.3 V to VL + 0.3 V or 30 mA, whichever occurs first Table 4 specifications + 15% 300 mA 400 mA Stresses at or above those listed under Absolute Maximum Ratings may cause permanent damage to the product. This is a stress rating only; functional operation of the product at these or any other conditions above those indicated in the operational section of this specification is not implied. Operation beyond the maximum operating conditions for extended periods may affect product reliability. Only one absolute maximum rating may be applied at any one time. THERMAL RESISTANCE Table 8. Thermal Resistance Package Type 24-Lead TSSOP1 24-Lead LFCSP2 1 2 –40°C to +125°C −65°C to +150°C 150°C 260°C θJA 112.6 30.4 4-layer board. 4-layer board and exposed paddle soldered to VSS. ESD CAUTION 10 sec to 40 sec Overvoltages at the analog and digital inputs are clamped by internal diodes. Limit the current to the maximum ratings given. Rev. B | Page 9 of 19 θJC 50 Unit °C/W °C/W ADG1414 Data Sheet D1 6 21 VSS ADG1414 21 SYNC 18 VSS GND 1 20 S8 S1 2 17 S8 19 D8 D1 3 ADG1414 16 D8 18 S7 S2 4 15 S7 D2 8 17 D7 D2 5 TOP VIEW (Not to Scale) S3 9 16 S6 D3 10 15 D6 S4 11 14 S5 D4 12 13 D5 14 D7 S3 6 D6 12 S5 11 D5 10 D4 9 S4 8 13 S6 D3 7 TOP VIEW (Not to Scale) 08497-004 S2 7 NOTES 1. EXPOSED PAD TIED TO SUBSTRATE, VSS. Figure 4. TSSOP Pin Configuration 08497-005 S1 5 22 SCLK 22 SDO GND 4 23 VDD 23 RESET/VL DIN 3 24 DIN 24 SYNC VDD 2 19 SDO SCLK 1 20 RESET/VL PIN CONFIGURATIONS AND FUNCTION DESCRIPTIONS Figure 5. LFCSP Pin Configuration Table 9. Pin Function Descriptions TSSOP 1 Pin No. LFCSP 22 Mnemonic SCLK 2 3 23 24 VDD DIN 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 GND S1 D1 S2 D2 S3 D3 S4 D4 D5 S5 D6 S6 D7 S7 D8 S8 VSS 22 19 SDO 23 20 RESET/VL Description Serial Clock Input. Data is clocked into the input shift register on the falling edge of the serial clock input. Data can be transferred at rates of up to 50 MHz. Most Positive Power Supply Potential. Serial Data Input. This device has an 8-bit shift register. Data is clocked into the register on the falling edge of the serial clock input. Ground (0 V) Reference. Source Terminal 1. This pin can be an input or an output. Drain Terminal 1. This pin can be an input or an output. Source Terminal 2. This pin can be an input or an output. Drain Terminal 2. This pin can be an input or an output. Source Terminal 3. This pin can be an input or an output. Drain Terminal 3. This pin can be an input or an output. Source Terminal 4. This pin can be an input or an output. Drain Terminal 4. This pin can be an input or an output. Drain Terminal 5. This pin can be an input or an output. Source Terminal 5. This pin can be an input or an output. Drain Terminal 6. This pin can be an input or an output. Source Terminal 6. This pin can be an input or an output. Drain Terminal 7. This pin can be an input or an output. Source Terminal 7. This pin can be an input or an output. Drain Terminal 8. This pin can be an input or an output. Source Terminal 8. This pin can be an input or an output. Most Negative Power Supply Potential. In single-supply applications, it can be connected to ground. Serial Data Output. This pin can be used for daisy-chaining a number of these devices together or for reading back the data in the shift register for diagnostic purposes. The serial data is transferred on the rising edge of SCLK and is valid on the falling edge of the clock. Pull this open-drain output to the supply with an external resistor. RESET/Logic Power Supply Input (VL). Under normal operation, drive the RESET/VL pin with a 2.7 V to 5 V supply. Pull the pin low (