2.1 Ω On Resistance, ±15 V/+12 V/±5 V
iCMOS Dual SPST Switches
ADG1421/ADG1422/ADG1423
Data Sheet
FEATURES
FUNCTIONAL BLOCK DIAGRAM
2.1 Ω on resistance
0.5 Ω maximum on resistance flatness
Up to 250 mA continuous current
Fully specified at +12 V, ±15 V, ±5 V
No VL supply required
3 V logic-compatible inputs
Rail-to-rail operation
10-lead MSOP and 10-lead, 3 mm × 3 mm LFCSP packages
ADG1421
S1
IN1
D1
D2
IN2
SWITCHES SHOWN FOR A LOGIC 0 INPUT
08487-001
S2
Figure 1. ADG1421 Functional Block Diagram
APPLICATIONS
Automatic test equipment
Data acquisition systems
Relay replacements
Battery-powered systems
Sample-and-hold systems
Audio signal routing
Video signal routing
Communication systems
ADG1422
S1
IN1
D1
D2
IN2
SWITCHES SHOWN FOR A LOGIC 0 INPUT
08487-002
S2
Figure 2. ADG1422 Functional Block Diagram
GENERAL DESCRIPTION
The iCMOS® (industrial CMOS) modular manufacturing process
combines high voltage, complementary metal-oxide semiconductor
(CMOS) and bipolar technologies. It enables the development
of a wide range of high performance analog ICs capable of 33 V
operation in a footprint that no other generation of high voltage
parts has achieved. Unlike analog ICs using conventional CMOS
processes, iCMOS components can tolerate high supply voltages
while providing increased performance, dramatically lower
power consumption, and reduced package size.
Rev. A
ADG1423
S1
IN1
D1
D2
IN2
S2
SWITCHES SHOWN FOR A LOGIC 0 INPUT
08487-003
The ADG1421/ADG1422/ADG1423 contain two independent
single-pole/single-throw (SPST) switches. The ADG1421 and
ADG1422 differ only in that the digital control logic is inverted.
The ADG1421 switches are turned on with Logic 1 on the
appropriate control input, and Logic 0 is required for the
ADG1422. The ADG1423 has one switch with digital control
logic similar to that of the ADG1421; the logic is inverted on
the other switch. The ADG1423 exhibits break-before-make
switching action for use in multiplexer applications. Each
switch conducts equally well in both directions when on and
has an input signal range that extends to the supplies. In the
off condition, signal levels up to the supplies are blocked.
Figure 3. ADG1423 Functional Block Diagram
The on resistance profile is very flat over the full analog input
range ensuring excellent linearity and low distortion when
switching audio signals. The iCMOS construction ensures
ultralow power dissipation, making the part ideally suited for
portable and battery-powered instruments.
PRODUCT HIGHLIGHTS
1.
2.
3.
4.
5.
2.4 Ω maximum on resistance at 25°C.
Minimum distortion.
3 V logic-compatible digital inputs: VINH = 2.0 V, VINL = 0.8 V.
No VL logic power supply required.
10-lead MSOP and 10-lead, 3 mm × 3 mm LFCSP packages.
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Technical Support
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ADG1421/ADG1422/ADG1423
Data Sheet
TABLE OF CONTENTS
Features .............................................................................................. 1
Continuous Current per Channel, S or D ..................................6
Applications ....................................................................................... 1
Absolute Maximum Ratings ............................................................7
General Description ......................................................................... 1
Thermal Resistance .......................................................................7
Functional Block Diagram .............................................................. 1
ESD Caution...................................................................................7
Product Highlights ........................................................................... 1
Pin Configuration and Function Descriptions..............................8
Revision History ............................................................................... 2
Typical Performance Characteristics ..............................................9
Specifications..................................................................................... 3
Test Circuits..................................................................................... 12
±15 V Dual Supply ....................................................................... 3
Terminology .................................................................................... 14
+12 V Single Supply ..................................................................... 4
Outline Dimensions ....................................................................... 15
±5 V Dual Supply ......................................................................... 5
Ordering Guide .......................................................................... 16
REVISION HISTORY
7/14—Rev. 0 to Rev. A
Changes to Table 1 ............................................................................ 3
Updated Outline Dimensions ....................................................... 15
10/09—Revision 0: Initial Version
Rev. A | Page 2 of 16
Data Sheet
ADG1421/ADG1422/ADG1423
SPECIFICATIONS
±15 V DUAL SUPPLY
VDD = +15 V ± 10%, VSS = −15 V ± 10%, GND = 0 V, unless otherwise noted.
Table 1.
Parameter
ANALOG SWITCH
Analog Signal Range
On Resistance, RON
On Resistance Match Between Channels, ∆RON
On Resistance Flatness, RFLAT (ON)
LEAKAGE CURRENTS
Source Off Leakage, IS (Off)
Drain Off Leakage, ID (Off)
Channel On Leakage, ID, IS (On)
DIGITAL INPUTS
Input High Voltage, VINH
Input Low Voltage, VINL
Input Current, IINL or IINH
25°C
−40°C to
+85°C
−40°C to
+105°C
−40°C to
+125°C
VDD to VSS
2.1
2.4
0.02
0.1
0.4
0.5
±0.1
±0.5
±0.1
±0.5
±0.2
±1
2.8
2.95
3.2
0.12
0.124
0.13
0.6
0.63
0.65
±2
±9
±75
±2
±9
±75
±2
±9
±75
2.0
0.8
0.005
±0.1
Digital Input Capacitance, CIN
DYNAMIC CHARACTERISTICS1
tON
4
V
Ω typ
Ω max
Ω typ
Ω max
Ω typ
Ω max
nA typ
nA max
nA typ
nA max
nA typ
nA max
V min
V max
μA typ
μA max
pF typ
Break-Before-Make Time Delay, tD (ADG1423 Only)
115
145
115
145
45
Charge Injection
−5
ns typ
ns max
ns typ
ns max
ns typ
ns min
pC typ
Off Isolation
−64
dB typ
Channel-to-Channel Crosstalk
−74
dB typ
Total Harmonic Distortion + Noise
0.016
% typ
−3 dB Bandwidth
Insertion Loss
180
0.12
MHz typ
dB typ
18
22
86
pF typ
pF typ
pF typ
tOFF
180
210
165
190
30
CS (Off)
CD (Off)
CD, CS (On)
POWER REQUIREMENTS
IDD
0.002
1.0
IDD
120
190
ISS
0.002
1.0
±4.5/±16.5
VDD/VSS
1
Unit
Guaranteed by design, not subject to production test.
Rev. A | Page 3 of 16
μA typ
μA max
μA typ
μA max
μA typ
μA max
V min/max
Test Conditions/Comments
VS = ±10 V, IS = −10 mA; see Figure 23
VDD = +13.5 V, VSS = −13.5 V
VS = ±10 V, IS = −10 mA
VS = ±10 V, IS = −10 mA
VDD = +16.5 V, VSS = −16.5 V
VS = ±10 V, VD = ±10 V; see Figure 24
VS = ±10 V, VD = ±10 V; see Figure 24
VS = VD = ±10 V; see Figure 25
VIN = VGND or VDD
RL = 300 Ω, CL = 35 pF
VS = 10 V; see Figure 26
RL = 300 Ω, CL = 35 pF
VS = 10 V; see Figure 26
RL = 300 Ω, CL = 35 pF
VS1 = VS2 = 10 V; see Figure 27
VS = 0 V, RS = 0 Ω, CL = 1 nF;
see Figure 28
RL = 50 Ω, CL = 5 pF, f = 1 MHz;
see Figure 29
RL = 50 Ω, CL = 5 pF, f = 1 MHz;
see Figure 30
RL = 10 kΩ, 5 V rms, f = 20 Hz to 20 kHz;
see Figure 32
RL = 50 Ω, CL = 5 pF; see Figure 31
RL = 50 Ω, CL = 5 pF, f = 1 MHz;
see Figure 31
f = 1 MHz; VS = 0 V
f = 1 MHz; VS = 0 V
f = 1 MHz; VS = 0 V
VDD = +16.5 V, VSS = −16.5 V
Digital inputs = 0 V or VDD
Digital inputs = 5 V
Digital inputs = 0 V, 5 V, or VDD
Ground = 0 V
ADG1421/ADG1422/ADG1423
Data Sheet
+12 V SINGLE SUPPLY
VDD = 12 V ± 10%, VSS = 0 V, GND = 0 V, unless otherwise noted.
Table 2.
Parameter
ANALOG SWITCH
Analog Signal Range
On Resistance, RON
On Resistance Match Between Channels, ∆RON
On Resistance Flatness, RFLAT (ON)
LEAKAGE CURRENTS
Source Off Leakage, IS (Off )
Drain Off Leakage, ID (Off )
Channel On Leakage, ID, IS (On)
DIGITAL INPUTS
Input High Voltage, VINH
Input Low Voltage, VINL
Input Current, IINL or IINH
25°C
−40°C to
+85°C
−40°C to
+125°C
0 V to VDD
4
4.6
0.03
0.15
1.2
1.5
±0.05
±0.5
±0.05
±0.5
±0.1
±1
5.5
6.2
0.17
0.18
1.75
1.9
±2
±75
±2
±75
±2
±75
2.0
0.8
0.005
±0.1
Digital Input Capacitance, CIN
DYNAMIC CHARACTERISTICS1
tON
4
V
Ω typ
Ω max
Ω typ
Ω max
Ω typ
Ω max
nA typ
nA max
nA typ
nA max
nA typ
nA max
V min
V max
µA typ
µA max
pF typ
Break-Before-Make Time Delay, tD (ADG1423 Only)
180
230
130
165
70
Charge Injection
30
ns typ
ns max
ns typ
ns max
ns typ
ns min
pC typ
Off Isolation
−60
dB typ
Channel-to-Channel Crosstalk
−70
dB typ
−3 dB Bandwidth
Insertion Loss
140
0.26
MHz typ
dB typ
31
36
90
pF typ
pF typ
pF typ
tOFF
295
340
205
235
48
CS (Off )
CD (Off )
CD, CS (On)
POWER REQUIREMENTS
IDD
0.001
1.0
IDD
VDD
1
Unit
120
190
5/16.5
Guaranteed by design, not subject to production test.
Rev. A | Page 4 of 16
µA typ
µA max
µA typ
µA max
V min/max
Test Conditions/Comments
VS = 0 V to 10 V, IS = −10 mA; see Figure 23
VDD = 10.8 V, VSS = 0 V
VS = 0 V to 10 V, IS = −10 mA
VS = 0V to 10 V, IS = −10 mA
VDD = 13.2 V, VSS = 0 V
VS = 1 V/10 V, VD = 10 V/1 V; see Figure 24
VS = 1 V/10 V, VD = 10 V/1 V; see Figure 24
VS = VD = 1 V or 10 V; see Figure 25
VIN = VGND or VDD
RL = 300 Ω, CL = 35 pF
VS = 8 V; see Figure 26
RL = 300 Ω, CL = 35 pF
VS = 8 V; see Figure 26
RL = 300 Ω, CL = 35 pF
VS1 = VS2 = 8 V; see Figure 27
VS = 6 V, RS = 0 Ω, CL = 1 nF;
see Figure 28
RL = 50 Ω, CL = 5 pF, f = 1 MHz;
see Figure 29
RL = 50 Ω, CL = 5 pF, f = 1 MHz;
see Figure 30
RL = 50 Ω, CL = 5 pF; see Figure 31
RL = 50 Ω, CL = 5 pF, f = 1 MHz;
see Figure 31
f = 1 MHz; VS = 6 V
f = 1 MHz; VS = 6 V
f = 1 MHz; VS = 6 V
VDD = 13.2 V
Digital inputs = 0 V or VDD
Digital inputs = 5 V
Ground = 0 V, VSS = 0 V
Data Sheet
ADG1421/ADG1422/ADG1423
±5 V DUAL SUPPLY
VDD = +5 V ± 10%, VSS = −5 V ± 10%, GND = 0 V, unless otherwise noted.
Table 3.
Parameter
ANALOG SWITCH
Analog Signal Range
On Resistance, RON
On Resistance Match Between Channels, ∆RON
On Resistance Flatness, RFLAT (ON)
25°C
−40°C to
+85°C
−40°C to
+125°C
VDD to VSS
4.5
5.2
0.04
0.18
1.3
1.6
6.2
7
0.2
0.21
1.85
2
Unit
V
Ω typ
Ω max
Ω typ
Ω max
Ω typ
Ω max
Test Conditions/Comments
VS = ±4.5 V, IS = −10 mA; see Figure 23
VDD = +4.5 V, VSS = −4.5 V
VS = ±4.5V; IS = −10 mA
VS = ±4.5 V, IS = −10 mA
LEAKAGE CURRENTS
Source Off Leakage, IS (Off)
±0.05
±0.5
±0.05
±2
±75
Drain Off Leakage, ID (Off)
nA max
nA typ
±0.5
±0.1
±1
±2
±75
VS = VD = ±4.5 V; see Figure 25
±2
±75
nA max
nA typ
nA max
V min
V max
μA typ
μA max
pF typ
VIN = VGND or VDD
Channel On Leakage, ID, IS (On)
DIGITAL INPUTS
Input High Voltage, VINH
Input Low Voltage, VINL
Input Current, IINL or IINH
VDD = +5.5 V, VSS = −5.5 V
nA typ
2.0
0.8
0.005
±0.1
Digital Input Capacitance, CIN
DYNAMIC CHARACTERISTICS1
tON
4
Break-Before-Make Time Delay, tD (ADG1423 Only)
285
370
220
295
85
Charge Injection
82
ns typ
ns max
ns typ
ns max
ns typ
ns min
pC typ
Off Isolation
−60
dB typ
Channel-to-Channel Crosstalk
−70
dB typ
Total Harmonic Distortion + Noise
0.04
% typ
−3 dB Bandwidth
Insertion Loss
150
0.25
MHz typ
dB typ
CS (Off)
CD (Off)
CD, CS (On)
POWER REQUIREMENTS
IDD
25
30
100
pF typ
pF typ
pF typ
tOFF
460
520
350
395
45
0.001
1.0
ISS
VDD/VSS
1
0.001
1.0
±4.5/±16.5
Guaranteed by design, not subject to production test.
Rev. A | Page 5 of 16
μA typ
μA max
μA typ
μA max
V min/max
VS = ±4.5 V, VD = ∓4.5 V; see Figure 24
VS = ±4.5 V, VD = ∓4.5 V; see Figure 24
RL = 300 Ω, CL = 35 pF
VS = 3 V; see Figure 26
RL = 300 Ω, CL = 35 pF
VS = 3 V; see Figure 26
RL = 300 Ω, CL = 35 pF
VS1 = VS2 = 3 V; see Figure 27
VS = 0 V, RS = 0 Ω, CL = 1 nF;
see Figure 28
RL = 50 Ω, CL = 5 pF, f = 1 MHz;
see Figure 29
RL = 50 Ω, CL = 5 pF, f = 1 MHz;
see Figure 30
RL = 10 kΩ, 5 V p-p, f = 20 Hz to 20 kHz;
see Figure 32
RL = 50 Ω, CL = 5 pF; see Figure 31
RL = 50 Ω, CL = 5 pF, f = 1 MHz;
see Figure 31
VS = 0V, f = 1 MHz
VS = 0V, f = 1 MHz
VS = 0V, f = 1 MHz
VDD = 5.5 V, VSS = −5.5 V
Digital inputs = 0 V or VDD
Digital inputs = 0 V or VDD
Ground = 0 V
ADG1421/ADG1422/ADG1423
Data Sheet
CONTINUOUS CURRENT PER CHANNEL, S OR D
Table 4.
Parameter
CONTINUOUS CURRENT PER CHANNEL1
±15 V Dual Supply
10-Lead MSOP (θJA = 142°C/W)
10-Lead LFCSP (θJA = 76°C/W)
+12 V Single Supply
10-Lead MSOP (θJA = 142°C/W)
10-Lead LFCSP (θJA = 76°C/W)
±5 V Dual Supply
10-Lead MSOP (θJA = 142°C/W)
10-Lead LFCSP (θJA = 76°C/W)
1
25°C
85°C
125°C
Unit
185
250
120
155
75
85
mA maximum
mA maximum
150
205
100
130
65
80
mA maximum
mA maximum
145
195
100
125
65
75
mA maximum
mA maximum
Test Conditions/Comments
VDD = +13.5 V, VSS = −13.5 V
VDD = 10.8 V, VSS = 0 V
VDD = +4.5 V, VSS = −4.5 V
Guaranteed by design, not subject to production test.
Rev. A | Page 6 of 16
Data Sheet
ADG1421/ADG1422/ADG1423
ABSOLUTE MAXIMUM RATINGS
TA = 25°C, unless otherwise noted.
THERMAL RESISTANCE
Table 5.
Table 6. Thermal Resistance
Parameter
VDD to VSS
VDD to GND
VSS to GND
Analog Inputs1
Digital Inputs
1
Peak Current, S or D
(Pulsed at 1 ms, 10%
Duty-Cycle Maximum)
10-Lead MSOP (4-Layer Board)
10-Lead LFCSP
Continuous Current per
Channel, S or D
Operating Temperature Range
Industrial
Storage Temperature Range
Junction Temperature
Reflow Soldering Peak
Temperature, Pb Free
1
Rating
35 V
−0.3 V to +25 V
+0.3 V to −25 V
VSS − 0.3 V to VDD + 0.3 V or
30 mA, whichever occurs first
GND − 0.3 V to VDD + 0.3 V or
30 mA, whichever occurs first
Package Type
10-Lead MSOP (4-Layer Board)
10-Lead LFCSP
ESD CAUTION
300 mA
400 mA
Data in Table 4 + 15% mA
−40°C to +125°C
−65°C to +150°C
150°C
260°C
Over voltages at IN, S, or D are clamped by internal diodes. Current should
be limited to the maximum ratings given.
Stresses above those listed under Absolute Maximum Ratings
may cause permanent damage to the device. This is a stress
rating only; functional operation of the device at these or any
other conditions above those indicated in the operational
section of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect
device reliability.
Rev. A | Page 7 of 16
θJA
142
76
θJC
44
Unit
°C/W
°C/W
ADG1421/ADG1422/ADG1423
Data Sheet
PIN CONFIGURATIONS AND FUNCTION DESCRIPTIONS
S2 2
NC 3
GND 4
ADG1421/
ADG1422/
ADG1423
10 D1
TOP VIEW
(Not to Scale)
VDD 5
9
D2
8
VSS
S1 1
7
IN1
S2 2
6
NC 3
IN2
GND 4
VDD 5
08487-004
NOTES
1. EXPOSED PAD TIED TO SUBSTRATE, VSS.
2. NC = NO CONNECT
10 D1
ADG1421/
ADG1422/
ADG1423
TOP VIEW
(Not to Scale)
9
D2
8
VSS
7
IN1
6
IN2
NC = NO CONNECT
Figure 4. 10-Lead LFCSP Pin Configuration
08487-005
S1 1
Figure 5. 10-Lead MSOP Pin Configuration
Table 7. 10-Lead LFCSP Pin Function Descriptions
Table 8. 10-Lead MSOP Pin Function Descriptions
Pin No.
1
Mnemonic
S1
Pin No.
1
Mnemonic
S1
2
S2
2
S2
3
4
5
6
7
8
9
NC
GND
VDD
IN2
IN1
VSS
D2
3
4
5
6
7
8
9
NC
GND
VDD
IN2
IN1
VSS
D2
10
D1
10
D1
EPAD
Description
Source Terminal. This pin can be an
input or output.
Source Terminal. This pin can be an
input or output.
No Connect.
Ground (0 V) Reference.
Most Positive Power Supply Potential.
Logic Control Input.
Logic Control Input.
Most Negative Power Supply Potential.
Drain Terminal. This pin can be an
input or output.
Drain Terminal. This pin can be an
input or output.
Exposed pad tied to substrate, VSS.
Description
Source Terminal. This pin can be an
input or output.
Source Terminal. This pin can be an
input or output.
No Connect.
Ground (0 V) Reference.
Most Positive Power Supply Potential.
Logic Control Input.
Logic Control Input.
Most Negative Power Supply Potential.
Drain Terminal. This pin can be an
input or output.
Drain Terminal. This pin can be an
input or output.
Table 9. ADG1421/ADG1422 Truth Table
ADG1421 INx
1
0
ADG1422 INx
0
1
Switch Condition
On
Off
Switch 1 Condition
Off
On
Switch 2 Condition
On
Off
Table 10. ADG1423 Truth Table
ADG1423 INx
0
1
Rev. A | Page 8 of 16
Data Sheet
ADG1421/ADG1422/ADG1423
TYPICAL PERFORMANCE CHARACTERISTICS
4.0
3.5
VDD = +15V
VSS = –15V
TA = 25°C
3.5
3.0
VDD = +10V
VSS = –10V
ON RESISTANCE (Ω)
ON RESISTANCE (Ω)
3.0
VDD = +12V
VSS = –12V
2.5
VDD = +13.5V
VSS = –13.5V
2.0
TA = +125°C
2.5
TA = +85°C
2.0
TA = +25°C
1.5
TA = –40°C
1.0
1.5
VDD = +16.5V
VSS = –16.5V
–11.5
–6.5
–1.5
3.5
VS, VD (V)
8.5
13.5
0
–15
0
–5
5
10
15
VS, VD (V)
Figure 9. On Resistance as a Function of VD (VS) for Different Temperatures,
±15 V Dual Supply
Figure 6. On Resistance as a Function of VD (VS) for Dual Supply
6
9
TA = 25°C
8
VDD = 5V
VSS = 0V
5
7
VDD = 10.8V
VSS = 0V
6
VDD = 8V
VSS = 0V
5
ON RESISTANCE (Ω)
ON RESISTANCE (Ω)
–10
08487-020
1.0
–16.5
0.5
08487-033
VDD = +15V
VSS = –15V
VDD = 12V
VSS = 0V
VDD = 13.2V
VSS = 0V
VDD = 15V
VSS = 0V
TA= +125°C
4
TA= +85°C
3
TA= +25°C
TA= –40°C
2
4
1
3
2
4
6
8
10
12
08487-032
0
0
14
VS, VD (V)
Figure 7. On Resistance as a Function of VD (VS) for Single Supply
0
4
6
8
10
12
VS, VD (V)
Figure 10. On Resistance as a Function of VD (VS) for Different Temperatures,
+12 V Single Supply
5.0
7
TA = 25°C
VDD = +5V
VSS = –5V
4.5
6
VDD = +4.5V
VSS = –4.5V
4.0
ON RESISTANCE (Ω)
3.5
3.0
2.5
2.0
VDD = +5V
VSS = –5V
1.5
VDD = +5.5V
VSS = –5.5V
1.0
VDD = +7V
VSS = –7V
5
TA = +125°C
TA = +85°C
4
TA = +25°C
3
TA = –40°C
2
1
0
–7
–5
–3
–1
1
3
5
7
VS, VD (V)
Figure 8. On Resistance as a Function of VD (VS) for Dual Supply
0
–5
–4
–3
–2
–1
0
1
VS, VD (V)
2
3
4
5
08487-017
0.5
08487-031
ON RESISTANCE (Ω)
2
08487-019
VDD= 12V
VSS= 0V
2
Figure 11. On Resistance as a Function of VD (VS) for Different Temperatures,
±5 V Dual Supply
Rev. A | Page 9 of 16
ADG1421/ADG1422/ADG1423
Data Sheet
25
90
VDD = +15V
VSS = –15V
VBIAS = ±10V
20
IDD PER CHANNEL
TA = 25°C
80
60
15
50
10
IDD (µA)
LEAKAGE CURRENT (nA)
70
ID (OFF) – +
IS (OFF) + –
IS (OFF) – +
ID (OFF) + –
ID, IS (ON) + +
ID, IS (ON) – –
5
40
VDD = +15V
VSS = –15V
VDD = +12V
VSS = 0V
30
20
VDD = +5V
VSS = –5V
10
0
20
60
40
80
100
120
TEMPERATURE (°C)
–10
08487-014
0
0
2
8
10
12
16
14
LOGIC LEVEL, IN (V)
Figure 12. Leakage Currents as a Function of Temperature,
±15 V Dual Supply
Figure 15. IDD vs. Logic Level
500
25
TA = 25°C
VDD = 12V
VSS = 0V
VBIAS = 1V/10V
20
VDD = +5V
VSS = –5V
400
300
CHARGE INJECTION (pC)
LEAKAGE CURRENT (nA)
6
4
08487-013
0
–5
15
IS (OFF) + –
ID (OFF) – +
ID (OFF) + –
IS (OFF) – +
ID, IS (ON) + +
ID, IS (ON) – –
10
5
200
VDD = +15V
VSS = –15V
VDD = +12V
VSS = 0V
100
0
–100
–200
–300
0
0
20
40
60
80
100
120
TEMPERATURE (°C)
–500
–15
10
15
Figure 16. Charge Injection vs. Source Voltage
350
VDD = +5V
VSS = –5V
VBIAS = ±4.5V
300
20
250
15
tOFF (±5V)
IS (OFF) + –
ID (OFF) – +
IS (OFF) – +
ID (OFF) + –
ID, IS (ON) + +
ID, IS (ON) – –
5
200
tON (±5V)
150
100
0
tON (+12V)
tOFF (+12V)
tOFF (±15V)
tON (±15V)
50
0
20
40
60
80
TEMPERATURE( °C)
100
120
08487-016
–5
Figure 14. Leakage Currents as a Function of Temperature, ±5 V Dual Supply
Rev. A | Page 10 of 16
0
–40
–20
0
20
40
60
80
100
TEMPERATURE (°C)
Figure 17. tTRANSITION Times vs. Temperature
120
08487-006
10
TIME (ns)
LEAKAGE CURRENT (nA)
5
0
VS (V)
Figure 13. Leakage Currents as a Function of Temperature, +12 V Single Supply
25
–5
–10
08487-034
–5
08487-015
–400
Data Sheet
0
0.050
TA = 25°C
VDD = +15V
VSS = –15V
–20
VDD = 5V, VSS = 5V, VS = 5V p-p
0.045
0.040
0.035
–40
THD + N (%)
–60
–80
0.030
0.025
0.020
VDD = 15V, VSS = 15V, VS = 10V p-p
0.015
0.010
–100
0.005
10k
100k
1M
10M
100M
1G
FREQUENCY (Hz)
0
08487-008
–120
1k
RL = 110Ω
TA= 25°C
0
0
–10
20M
TA = 25°C
VDD = +15V
VSS = –15V
–20
–1.0
–30
–1.5
ACPSRR (dB)
INSERTION LOSS (dB)
15M
Figure 21. THD + N vs. Frequency
TA = 25°C
VDD = +15V
VSS = –15V
–0.5
10M
FREQUENCY (Hz)
Figure 18. Off Isolation vs. Frequency
0
5M
08487-011
OFF ISOLATION (dB)
ADG1421/ADG1422/ADG1423
–2.0
–2.5
NO DECOUPLING
CAPACITORS
–40
–50
–60
DECOUPLING
CAPACITORS
–70
–3.0
–80
–3.5
1M
10M
100M
1G
FREQUENCY (Hz)
08487-007
100k
–100
Figure 19. On Response vs. Frequency
0
TA = 25°C
VDD = +15V
VSS = –15V
–40
–60
–80
–100
–120
10k
100k
1M
10M
100M
FREQUENCY (Hz)
10k
100k
1M
FREQUENCY (Hz)
Figure 22. ACPSRR vs. Frequency
1G
08487-012
CROSSTALK (dB)
–20
1k
Figure 20. Crosstalk vs. Frequency
Rev. A | Page 11 of 16
10M
08487-009
–90
–4.0
10k
ADG1421/ADG1422/ADG1423
Data Sheet
TEST CIRCUITS
V
S
ID (ON)
D
S
NC
D
A
IDS
Figure 23. On Resistance
IS (OFF)
S
A
D
VD
NC = NO CONNECT
08487-023
08487-021
VS
Figure 25. On Leakage
ID (OFF)
A
VD
08487-022
VS
Figure 24. Off Leakage
VDD
VSS
0.1µF
VDD
VSS
S
VS
VIN
ADG1421
50%
50%
VIN
ADG1422
50%
50%
VOUT
D
CL
35pF
RL
300Ω
IN
90%
VOUT
90%
GND
tOFF
tON
08487-024
0.1µF
Figure 26. Switching Times
VDD
VSS
D1
S2
D2
RL
300Ω
IN1,
IN2
CL
35pF
RL
300Ω
VOUT2
CL
35pF
VOUT1
VOUT1
VOUT2
ADG1423
50%
90%
90%
0V
90%
90%
0V
tD
GND
tD
Figure 27. Break-Before-Make Time Delay
RS
VS
VDD
VSS
VDD
VSS
S
D
VIN
CL
1nF
IN
GND
ADG1421
ON
VOUT
VIN
OFF
ADG1422
VOUT
QINJ = CL × ∆VOUT
Figure 28. Charge Injection
Rev. A | Page 12 of 16
∆VOUT
08487-026
VS2
VSS
S1
50%
0V
08487-025
VDD
VS1
VIN
0.1µF
0.1µF
Data Sheet
ADG1421/ADG1422/ADG1423
VSS
VDD
0.1µF
VDD
NETWORK
ANALYZER
VSS
S
0.1µF
VDD
50Ω
50Ω
IN
VSS
0.1µF
S
VS
RL
50Ω
GND
50Ω
IN
VS
D
VIN
D
VOUT
VIN
RL
50Ω
VOUT
VS
08487-027
GND
OFF ISOLATION = 20 LOG
INSERTION LOSS = 20 LOG
Figure 29. Off Isolation
VDD
VOUT
RL
50Ω
VOUT
VOUT WITH SWITCH
VOUT WITHOUT SWITCH
Figure 31. Bandwidth
VSS
0.1µF
0.1µF
NETWORK
ANALYZER
NETWORK
ANALYZER
VSS
08487-029
VDD
0.1µF
VDD
VDD
VSS
VSS
0.1µF
0.1µF
S1
D
S2
VDD
R
50Ω
AUDIO PRECISION
VSS
RS
S
IN
VS
GND
GND
08487-028
VOUT
VS
Figure 30. Channel-to-Channel Crosstalk
RL
10kΩ
Figure 32. THD + N
Rev. A | Page 13 of 16
VOUT
08487-030
VIN
CHANNEL-TO-CHANNEL CROSSTALK = 20 LOG
VS
V p-p
D
ADG1421/ADG1422/ADG1423
Data Sheet
TERMINOLOGY
tON (EN)
Delay time between the 50% and 90% points of the digital input
and switch on condition. See Figure 26.
IDD
The positive supply current.
ISS
The negative supply current.
tOFF (EN)
Delay time between the 50% and 90% points of the digital input
and switch off condition. See Figure 26.
VD (VS)
The analog voltage on Terminal D and Terminal S.
RON
The ohmic resistance between Terminal D and Terminal S.
RFLAT (ON)
Flatness is defined as the difference between the maximum and
minimum value of on resistance as measured over the specified
analog signal range.
IS (Off)
The source leakage current with the switch off.
TBBM
Off time measured between the 80% point of both switches
when switching from one address state to another. See Figure 27.
Charge Injection
A measure of the glitch impulse transferred from the digital
input to the analog output during switching. See Figure 28.
ID (Off)
The drain leakage current with the switch off.
Off Isolation
A measure of unwanted signal coupling through an off switch.
See Figure 29.
ID, IS (On)
The channel leakage current with the switch on.
VINL
The maximum input voltage for Logic 0.
Crosstalk
A measure of unwanted signal that is coupled through from one
channel to another as a result of parasitic capacitance. See
Figure 30.
VINH
The minimum input voltage for Logic 1.
IINL (IINH)
The input current of the digital input.
CS (Off)
The off switch source capacitance, measured with reference to
ground.
CD (Off)
The off switch drain capacitance, measured with reference to
ground.
CD, CS (On)
The on switch capacitance, measured with reference to ground.
CIN
The digital input capacitance.
tTRANSITION
Delay time between the 50% and 90% points of the digital
inputs and the switch on condition when switching from one
address state to another.
Bandwidth
The frequency at which the output is attenuated by 3 dB. See
Figure 31.
On Response
The frequency response of the on switch.
Insertion Loss
The loss due to the on resistance of the switch. See Figure 31.
THD + N
The ratio of the harmonic amplitude plus noise of the signal to
the fundamental. See Figure 32.
AC Power Supply Rejection Ratio (ACPSRR)
ACPSRR measures the ability of a part to avoid coupling noise
and spurious signals that appear on the supply voltage pin to the
output of the switch. The dc voltage on the device is modulated
by a sine wave of 0.62 V p-p. The ratio of the amplitude of signal on
the output to the amplitude of the modulation is the ACPSRR.
See Figure 22.
Rev. A | Page 14 of 16
Data Sheet
ADG1421/ADG1422/ADG1423
OUTLINE DIMENSIONS
3.10
3.00
2.90
10
3.10
3.00
2.90
1
5.15
4.90
4.65
6
5
PIN 1
IDENTIFIER
0.50 BSC
0.95
0.85
0.75
15° MAX
1.10 MAX
0.30
0.15
0.70
0.55
0.40
0.23
0.13
6°
0°
091709-A
0.15
0.05
COPLANARITY
0.10
COMPLIANT TO JEDEC STANDARDS MO-187-BA
Figure 33. 10-Lead Mini Small Outline Package [MSOP]
(RM-10)
Dimensions shown in millimeters
2.48
2.38
2.23
3.10
3.00 SQ
2.90
0.50 BSC
10
6
PIN 1 INDEX
AREA
1.74
1.64
1.49
EXPOSED
PAD
0.50
0.40
0.30
1
5
BOTTOM VIEW
TOP VIEW
SEATING
PLANE
0.30
0.25
0.20
0.05 MAX
0.02 NOM
COPLANARITY
0.08
0.20 REF
*FOR PROPER CONNECTION OF THE EXPOSED PAD, REFER TO
THE PIN CONFIGURATIONS AND FUNCTION DESCRIPTIONS SECTION
OF THIS DATA SHEET.
Figure 34. 10-Lead Lead Frame Chip Scale Package [LFCSP_WD]
3 mm × 3 mm Body, Very Very Thin, Dual Lead
(CP-10-9)
Dimensions shown in millimeters
Rev. A | Page 15 of 16
02-05-2013-C
0.80
0.75
0.70
0.20 MIN
PIN 1
INDICATOR
(R 0.15)
ADG1421/ADG1422/ADG1423
Data Sheet
ORDERING GUIDE
Model1
ADG1421BRMZ
ADG1421BRMZ-REEL7
ADG1421BCPZ-REEL7
ADG1422BRMZ
ADG1422BRMZ-REEL7
ADG1422BCPZ-REEL7
ADG1423BRMZ
ADG1423BRMZ-REEL7
ADG1423BCPZ-REEL7
1
Temperature Range
−40°C to +125°C
−40°C to +125°C
−40°C to +125°C
−40°C to +125°C
−40°C to +125°C
−40°C to +125°C
−40°C to +125°C
−40°C to +125°C
−40°C to +125°C
Package Description
10-Lead Mini Small Outline Package [MSOP]
10-Lead Mini Small Outline Package [MSOP]
10- Lead Frame Chip Scale Package [LFCSP_WD]
10-Lead Mini Small Outline Package [MSOP]
10-Lead Mini Small Outline Package [MSOP]
10- Lead Frame Chip Scale Package [LFCSP_WD]
10-Lead Mini Small Outline Package [MSOP]
10-Lead Mini Small Outline Package [MSOP]
10- Lead Frame Chip Scale Package [LFCSP_WD]
Z = RoHS Compliant Part.
©2009–2014 Analog Devices, Inc. All rights reserved. Trademarks and
registered trademarks are the property of their respective owners.
D08487-0-7/14(A)
Rev. A | Page 16 of 16
Package Option
RM-10
RM-10
CP-10-9
RM-10
RM-10
CP-10-9
RM-10
RM-10
CP-10-9
Branding
S2V
S2V
S2V
S2W
S2W
S2W
S2X
S2X
S2X
工商网监
湘ICP备2023018690号
