4.5 Ω RON, 16-Channel, Differential 8-Channel,
±5 V,+12 V,+5 V, and +3.3 V Multiplexers
ADG1606/ADG1607
Data Sheet
FEATURES
FUNCTIONAL BLOCK DIAGRAMS
4.5 Ω typical on resistance
1.1 Ω on resistance flatness
±3.3 V to ±8 V dual supply operation
3.3 V to 16 V single supply operation
No VL supply required
3 V logic-compatible inputs
Rail-to-rail operation
Up to 378 mA of continuous current per channel
28-lead TSSOP and 32-lead, 5 mm × 5 mm LFCSP
ADG1606
S1
D
S16
08489-001
1-OF-16
DECODER
A0 A1 A2 A3 EN
APPLICATIONS
Figure 1.
Communication systems
Medical systems
Audio signal routing
Video signal routing
Automatic test equipment
Data acquisition systems
Battery-powered systems
Sample-and-hold systems
Relay replacements
ADG1607
S1A
DA
S8A
S1B
DB
S8B
A0 A1 A2 EN
08489-002
1-OF-8
DECODER
Figure 2.
GENERAL DESCRIPTION
PRODUCT HIGHLIGHTS
The ADG1606 and ADG1607 are monolithic iCMOS® analog
multiplexers comprising of 16 single channels and eight
differential channels, respectively. The ADG1606 switches one of
16 inputs to a common output, as determined by the 4-bit
binary address lines (A0, A1, A2, and A3). The ADG1607
switches one of eight differential inputs to a common differential
output, as determined by the 3-bit binary address lines (A0, A1,
and A2). An EN input on both devices enables or disables the
device. When disabled, all channels switch off. When enabled,
each channel conducts equally well in both directions and has an
input signal range that extends to the supplies.
1.
2.
3.
4.
7.5 Ω maximum on resistance over temperature.
Minimum distortion: THD + N = 0.04%
3 V logic-compatible digital inputs: VINH = 2.0 V, VINL = 0.8 V.
No VL logic power supply required.
The ultralow on resistance and on-resistance flatness of these
switches make them ideal solutions for data acquisition and
gain switching applications where low distortion is critical.
iCMOS® construction ensures ultralow power dissipation,
making the parts ideally suited for portable and batterypowered instruments.
Rev. A
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Technical Support
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ADG1606/ADG1607
Data Sheet
TABLE OF CONTENTS
Features .............................................................................................. 1
Continuous Current per Channel, S or D ..................................7
Applications ....................................................................................... 1
Absolute Maximum Ratings ............................................................8
Functional Block Diagrams ............................................................. 1
Thermal Resistance .......................................................................8
General Description ......................................................................... 1
ESD Caution...................................................................................8
Product Highlights ........................................................................... 1
Pin Configurations and Function Descriptions ............................9
Revision History ............................................................................... 2
Typical Performance Characteristics ........................................... 13
Specifications..................................................................................... 3
Test Circuits..................................................................................... 17
±5 V Dual Supply ......................................................................... 3
Terminology .................................................................................... 20
12 V Single Supply ........................................................................ 4
Outline Dimensions ....................................................................... 21
5 V Single Supply .......................................................................... 5
Ordering Guide .......................................................................... 21
3.3 V Single Supply ....................................................................... 6
REVISION HISTORY
8/2016—Rev. 0 to Rev. A
Changed CP-32-2 to CP-32-7 ...................................... Throughout
Changes to Figure 4 .......................................................................... 9
Changes to Figure 6 ........................................................................ 11
Updated Outline Dimensions ....................................................... 21
Changes to Ordering Guide .......................................................... 21
10/2009—Revision 0: Initial Version
Rev. A | Page 2 of 22
Data Sheet
ADG1606/ADG1607
SPECIFICATIONS
±5 V DUAL SUPPLY
VDD = +5 V ± 10%, VSS = −5 V ± 10%, GND = 0 V, unless otherwise noted.
Table 1.
Parameter
ANALOG SWITCH
Analog Signal Range
On Resistance (RON)
On Resistance Match Between Channels (∆RON)
On Resistance Flatness (RFLAT(ON))
LEAKAGE CURRENTS
Source Off Leakage, IS (Off)
Drain Off Leakage, ID (Off)
ADG1606
Channel On Leakage, ID, IS (On)
DIGITAL INPUTS
Input High Voltage, VINH
Input Low Voltage, VINL
Input Current, IINL or IINH
25°C
−40°C to
+85°C
−40°C to
+125°C
VDD to VSS
4.5
5.5
0.2
0.5
1.1
1.4
6.7
7.5
0.8
0.9
1.7
2
tON (EN)
tOFF (EN)
Break-Before-Make Time Delay, tBBM
VDD/VSS
1
VS = ±4.5 V, IS = −10 mA; see Figure 26
VDD = ±4.5 V, VSS = ±4.5 V
VS = ±4.5 V, IS = −10 mA
VS = ±4.5 V, IS = −10 mA
nA typ
VS = ±4.5 V, VD = ∓4.5 V; see Figure 27
VS = ±4.5 V, VD = ∓4.5 V; see Figure 27
±0.15
±0.05
±0.5
±3
nA max
nA typ
±0.2
±0.1
±0.3
±3
±25
VS = VD = ±4.5 V; see Figure 28
±3
±25
nA max
nA typ
nA max
V min
V max
µA typ
µA max
pF typ
VIN = VGND or VDD
2.0
0.8
±0.003
4
175
214
132
162
124
153
42
27
−62
−62
0.04
ns typ
ns max
ns typ
ns max
ns typ
ns max
ns typ
ns min
pC typ
dB typ
dB typ
% typ
21
37
18
MHz typ
MHz typ
pF typ
VS = 0 V, f = 1 MHz
248
123
pF typ
pF typ
VS = 0 V, f = 1 MHz
VS = 0 V, f = 1 MHz
271
146
pF typ
pF typ
VS = 0 V, f = 1 MHz
VS = 0 V, f = 1 MHz
VDD = +5.5 V, VSS = −5.5 V
Digital inputs = 0 V or VDD
247
275
180
188
176
202
15
Charge Injection
Off Isolation
Channel-to-Channel Crosstalk
Total Harmonic Distortion + Noise (THD + N)
−3 dB Bandwidth
ADG1606
ADG1607
CS (Off)
CD (Off)
ADG1606
ADG1607
CD, CS (On)
ADG1606
ADG1607
POWER REQUIREMENTS
IDD
V
Ω typ
Ω max
Ω typ
Ω max
Ω typ
Ω max
Test Conditions/Comments
VDD = +5.5 V, VSS = −5.5 V
±0.02
±0.1
Digital Input Capacitance, CIN
DYNAMIC CHARACTERISTICS 1
Transition Time, tTRANSITION
Unit
0.001
1.0
±3.3/±8
Guaranteed by design, not subject to production test.
Rev. A | Page 3 of 22
µA typ
µA max
V min/max
RL = 300 Ω, CL = 35 pF
VS = 2.5 V; see Figure 29
RL = 300 Ω, CL = 35 pF
VS = 2.5 V; see Figure 31
RL = 300 Ω, CL = 35 pF
VS = 2.5 V; see Figure 31
RL = 300 Ω, CL = 35 pF
VS1 = VS2 = 2.5 V; see Figure 30
VS = 0 V, RS = 0 Ω, CL = 1 nF; see Figure 32
RL = 50 Ω, CL = 5 pF, f = 1 MHz; see Figure 33
RL = 50 Ω, CL = 5 pF, f = 1 MHz; see Figure 35
RL = 110 Ω, 5 V p-p, f = 20 Hz to 20 kHz; see Figure 36
RL = 50 Ω, CL = 5 pF; see Figure 34
ADG1606/ADG1607
Data Sheet
12 V SINGLE SUPPLY
VDD = 12 V ± 10%, VSS = 0 V, GND = 0 V, unless otherwise noted.
Table 2.
Parameter
ANALOG SWITCH
Analog Signal Range
On Resistance (RON)
On Resistance Match Between Channels (∆RON)
On Resistance Flatness (RFLAT(ON))
LEAKAGE CURRENTS
Source Off Leakage, IS (Off)
Drain Off Leakage, ID (Off)
ADG1606
Channel On Leakage, ID, IS (On)
DIGITAL INPUTS
Input High Voltage, VINH
Input Low Voltage, VINL
Input Current, IINL or IINH
25°C
−40°C to
+85°C
−40°C to
+125°C
0 V to VDD
4
5
0.2
0.5
1
1.3
±0.02
±0.15
±0.05
±0.2
±0.1
±0.3
6.2
7
0.8
0.9
1.6
1.9
±0.5
±3
±3
±25
±3
±25
2.0
0.8
±0.003
±0.1
Digital Input Capacitance, CIN
DYNAMIC CHARACTERISTICS1
Transition Time, tTRANSITION
tON (EN)
tOFF (EN)
Break-Before-Make Time Delay, tBBM
4
143
170
108
128
90
109
40
VDD
1
V min
V max
µA typ
µA max
pF typ
VS = 0 V to 10 V, IS = −10 mA
VDD = 13.2 V, VSS = 0 V
VS = 1 V/10 V, VD = 10 V/1 V; see Figure 27
VS = 1 V/10 V, VD = 10 V/1 V; see Figure 27
VS = VD = 1 V or 10 V; see Figure 28
VIN = VGND or VDD
22
38
18
MHz typ
MHz typ
pF typ
VS = 6 V, f = 1 MHz
240
120
pF typ
pF typ
VS = 6 V, f = 1 MHz
VS = 6 V, f = 1 MHz
263
143
pF typ
pF typ
VS = 6 V, f = 1 MHz
VS = 6 V, f = 1 MHz
VDD = 12 V
Digital inputs = 0 V or VDD
136
142
132
150
0.001
300
480
ADG1607
nA typ
nA max
nA typ
nA max
nA typ
nA max
VS = 0 V to 10 V, IS = −10 mA; see Figure 26
VDD = 10.8 V, VSS = 0 V
VS = 10 V, IS = −10 mA
33
−62
−62
0.04
221
1.0
ADG1606
V
Ω typ
Ω max
Ω typ
Ω max
Ω typ
Ω max
Test Conditions/Comments
ns typ
ns max
ns typ
ns max
ns typ
ns max
ns typ
ns min
pC typ
dB typ
dB typ
% typ
198
15
Charge Injection
Off Isolation
Channel-to-Channel Crosstalk
Total Harmonic Distortion + Noise (THD + N)
−3 dB Bandwidth
ADG1606
ADG1607
CS (Off)
CD (Off)
ADG1606
ADG1607
CD, CS (On)
ADG1606
ADG1607
POWER REQUIREMENTS
IDD
Unit
370
600
3.3/16
Guaranteed by design, not subject to production test.
Rev. A | Page 4 of 22
µA typ
µA max
µA typ
µA max
µA typ
µA max
V min/max
RL = 300 Ω, CL = 35 pF
VS = 8 V; see Figure 29
RL = 300 Ω, CL = 35 pF
VS = 8 V; see Figure 31
RL = 300 Ω, CL = 35 pF
VS = 8 V; see Figure 31
RL = 300 Ω, CL = 35 pF
VS1 = VS2 = 8 V; see Figure 30
VS = 6 V, RS = 0 Ω, CL = 1 nF; see Figure 32
RL = 50 Ω, CL = 5 pF, f = 1 MHz; see Figure 33
RL = 50 Ω, CL = 5 pF, f = 1 MHz; see Figure 35
RL = 110 Ω, 5 V p-p, f = 20 Hz to 20 kHz; see Figure 36
RL = 50 Ω, CL = 5 pF; see Figure 34
Digital inputs = 5 V
Digital inputs = 5 V
Data Sheet
ADG1606/ADG1607
5 V SINGLE SUPPLY
VDD = 5 V ± 10%, VSS = 0 V, GND = 0 V, unless otherwise noted.
Table 3.
Parameter
ANALOG SWITCH
Analog Signal Range
On Resistance (RON)
On Resistance Match Between Channels (∆RON)
On Resistance Flatness (RFLAT(ON))
LEAKAGE CURRENTS
Source Off Leakage, IS (Off)
Drain Off Leakage, ID (Off)
ADG1606
Channel On Leakage, ID, IS (On)
DIGITAL INPUTS
Input High Voltage, VINH
Input Low Voltage, VINL
Input Current, IINL or IINH
25°C
−40°C to
+85°C
−40°C to
+125°C
0 V to VDD
8.5
9.5
0.3
0.8
1.8
2.4
±0.01
±0.15
±0.02
±0.2
±0.05
±0.3
11.5
12.5
1.1
1.2
2.7
3
±0.5
±3
±3
±25
±3
±25
2.0
0.8
±0.003
±0.1
Digital Input Capacitance, CIN
DYNAMIC CHARACTERISTICS1
Transition Time, tTRANSITION
4
V
Ω typ
Ω max
Ω typ
Ω max
Ω typ
Ω max
nA typ
nA max
nA typ
nA max
nA typ
nA max
V min
V max
µA typ
µA max
pF typ
Test Conditions/Comments
VS = 0 V to 4.5 V, IS = −10 mA; see Figure 26
VDD = 4.5 V, VSS = 0 V
VS = 0 V to 4.5 V, IS = −10 mA
VS = 0 V to 4.5 V, IS = −10 mA
VDD = 5.5 V, VSS = 0 V
VS = 1 V/4.5 V, VD = 4.5 V/1 V; see Figure 27
VS = 1 V/4.5 V, VD = 4.5 V/1 V; see Figure 27
VS = VD = 1 V or 4.5 V; see Figure 28
VIN = VGND or VDD
Break-Before-Make Time Delay, tBBM
220
280
160
202
154
197
45
Charge Injection
Off Isolation
Channel-to-Channel Crosstalk
Total Harmonic Distortion + Noise (THD + N)
12
−62
−62
0.35
ns typ
ns max
ns typ
ns max
ns typ
ns max
ns typ
ns min
pC typ
dB typ
dB typ
% typ
19
34
20
MHz typ
MHz typ
pF typ
VS = 2.5 V, f = 1 MHz
270
137
pF typ
pF typ
VS = 2.5 V, f = 1 MHz
VS = 2.5 V, f = 1 MHz
300
160
pF typ
pF typ
VS = 2.5 V, f = 1 MHz
VS = 2.5 V, f = 1 MHz
VDD = 5.5 V
Digital inputs = 0 V or VDD
tON (EN)
tOFF (EN)
324
360
221
234
232
259
15
−3 dB Bandwidth
ADG1606
ADG1607
CS (Off)
CD (Off)
ADG1606
ADG1607
CD, CS (On)
ADG1606
ADG1607
POWER REQUIREMENTS
IDD
VDD
1
Unit
0.001
1.0
3.3/16
Guaranteed by design, not subject to production test.
Rev. A | Page 5 of 22
µA typ
µA max
V min/max
RL = 300 Ω, CL = 35 pF
VS = 2.5 V; see Figure 29
RL = 300 Ω, CL = 35 pF
VS = 2.5 V; see Figure 31
RL = 300 Ω, CL = 35 pF
VS = 2.5 V; see Figure 31
RL = 300 Ω, CL = 35 pF
VS1 = VS2 = 2.5 V; see Figure 30
VS = 2.5 V, RS = 0 Ω, CL = 1 nF; see Figure 32
RL = 50 Ω, CL = 5 pF, f = 1 MHz; see Figure 33
RL = 50 Ω, CL = 5 pF, f = 1 MHz; see Figure 35
RL = 110 Ω, f = 20 Hz to 20 kHz, VS = 3.5 V p-p; see
Figure 36
RL = 50 Ω, CL = 5 pF; see Figure 34
ADG1606/ADG1607
Data Sheet
3.3 V SINGLE SUPPLY
VDD = 3.3 V, VSS = 0 V, GND = 0 V, unless otherwise noted.
Table 4.
Parameter
ANALOG SWITCH
Analog Signal Range
On Resistance (RON)
25°C
−40°C to
+85°C
−40°C to
+125°C
Unit
14
14.5
0 V to VDD
15.5
V
Ω typ
On Resistance Match Between Channels (∆RON)
On Resistance Flatness (RFLAT(ON))
LEAKAGE CURRENTS
Source Off Leakage, IS (Off)
0.6
5
0.7
5.5
0.8
6
Ω typ
Ω typ
±0.5
±3
±3
±25
±3
±25
Drain Off Leakage, ID (Off)
ADG1606
Channel On Leakage, ID, IS (On)
DIGITAL INPUTS
Input High Voltage, VINH
Input Low Voltage, VINL
Input Current, IINL or IINH
±0.01
±0.15
±0.02
±0.2
±0.05
±0.3
2.0
0.8
±0.003
±0.1
Digital Input Capacitance, CIN
DYNAMIC CHARACTERISTICS 1
Transition Time, tTRANSITION
4
V min
V max
µA typ
µA max
pF typ
VS = 0 V to VDD, IS = −10 mA; see Figure 26
VDD = 3.3 V, VSS = 0 V
VS = 0 V to VDD, IS = −10 mA
VS = 0 V to VDD, IS = −10 mA
VDD = 3.6 V, VSS = 0 V
VS = 0.6 V/3 V, VD = 3 V/0.6 V; see Figure 27
VS = 0.6 V/3 V, VD = 3 V/0.6 V; see Figure 27
VS = VD = 0.6 V or 3 V; see Figure 28
VIN = VGND or VDD
Break-Before-Make Time Delay, tBBM
353
482
263
362
262
348
74
Charge Injection
Off Isolation
Channel-to-Channel Crosstalk
Total Harmonic Distortion + Noise (THD + N)
6
−62
−62
0.6
ns typ
ns max
ns typ
ns max
ns typ
ns max
ns typ
ns min
pC typ
dB typ
dB typ
% typ
17
31
22
MHz typ
MHz typ
pF typ
VS = 1.5 V, f = 1 MHz
290
145
pF typ
pF typ
VS = 1.5 V, f = 1 MHz
VS = 1.5 V, f = 1 MHz
350
168
pF typ
pF typ
VS = 1.5 V, f = 1 MHz
VS = 1.5 V, f = 1 MHz
VDD = 3.6 V
Digital inputs = 0 V or VDD
tON (EN)
tOFF (EN)
536
575
385
396
391
424
15
−3 dB Bandwidth
ADG1606
ADG1607
CS (Off)
CD (Off)
ADG1606
ADG1607
CD, CS (On)
ADG1606
ADG1607
POWER REQUIREMENTS
IDD
VDD
1
nA typ
nA max
nA typ
nA max
nA typ
nA max
Test Conditions/Comments
0.001
1.0
3.3/16
Guaranteed by design, not subject to production test.
Rev. A | Page 6 of 22
µA typ
µA max
V min/max
RL = 300 Ω, CL = 35 pF
VS = 1.5 V; see Figure 29
RL = 300 Ω, CL = 35 pF
VS = 1.5 V; see Figure 31
RL = 300 Ω, CL = 35 pF
VS = 1.5 V; see Figure 31
RL = 300 Ω, CL = 35 pF
VS1 = VS2 = 1.5 V; see Figure 30
VS = 1.5 V, RS = 0 Ω, CL = 1 nF; see Figure 32
RL = 50 Ω, CL = 5 pF, f = 1 MHz; see Figure 33
RL = 50 Ω, CL = 5 pF, f = 1 MHz; see Figure 35
RL = 110 Ω, f = 20 Hz to 20 kHz, VS = 2 V p-p;
see Figure 36
RL = 50 Ω, CL = 5 pF; see Figure 34
Data Sheet
ADG1606/ADG1607
CONTINUOUS CURRENT PER CHANNEL, S OR D
Table 5. ADG1606
Parameter
CONTINUOUS CURRENT, S OR D
VDD = +5 V, VSS = −5 V
TSSOP (θJA = 97.9°C/W)
LFCSP (θJA = 46°C/W)
VDD = 12 V, VSS = 0 V
TSSOP (θJA = 97.9°C/W)
LFCSP (θJA = 46°C/W)
VDD = 5 V, VSS = 0 V
TSSOP (θJA = 97.9°C/W)
LFCSP (θJA = 46°C/W)
VDD = 3.3 V, VSS = 0 V
TSSOP (θJA = 97.9°C/W)
LFCSP (θJA = 46°C/W)
25°C
85°C
125°C
Unit
259
357
168
217
105
122
mA maximum
mA maximum
273
378
175
224
108
122
mA maximum
mA maximum
199
276
136
178
91
108
mA maximum
mA maximum
164
227
119
154
80
98
mA maximum
mA maximum
25°C
85°C
125°C
Unit
192
266
133
175
91
108
mA maximum
mA maximum
203
280
140
178
91
108
mA maximum
mA maximum
147
206
108
140
70
94
mA maximum
mA maximum
122
168
91
119
56
84
mA maximum
mA maximum
Table 6. ADG1607
Parameter
CONTINUOUS CURRENT, S OR D
VDD = +5 V, VSS = −5 V
TSSOP (θJA = 97.9°C/W)
LFCSP (θJA = 46°C/W)
VDD = 12 V, VSS = 0 V
TSSOP (θJA = 97.9°C/W)
LFCSP (θJA = 46°C/W)
VDD = 5 V, VSS = 0 V
TSSOP (θJA = 97.9°C/W)
LFCSP (θJA = 46°C/W)
VDD = 3.3 V, VSS = 0 V
TSSOP (θJA = 97.9°C/W)
LFCSP (θJA = 46°C/W)
Rev. A | Page 7 of 22
ADG1606/ADG1607
Data Sheet
ABSOLUTE MAXIMUM RATINGS
TA = 25°C, unless otherwise noted.
THERMAL RESISTANCE
Table 7.
θJA is specified for the worst-case conditions, that is, a device
soldered in a circuit board for surface-mount packages.
Parameter
VDD to VSS
VDD to GND
VSS to GND
Analog Inputs1
Digital Inputs2
Peak Current, S or D
Continuous Current, S or D3
Operating Temperature Range
Industrial (B Version)
Storage Temperature Range
Junction Temperature
Reflow Soldering Peak
Temperature, Pb Free
Rating
18 V
−0.3 V to +18 V
+0.3 V to −18 V
VSS − 0.3 V to VDD + 0.3 V or
30 mA, whichever occurs first
GND − 0.3 V to VDD + 0.3 V or
30 mA, whichever occurs first
1.1 A (pulsed at 1 ms,
10% duty cycle maximum)
Data + 15%
Table 8. Thermal Resistance
Package Type
28-Lead TSSOP
32-Lead LFCSP
ESD CAUTION
−40°C to +125°C
−65°C to +150°C
150°C
260°C
Overvoltages at IN, S, or D are clamped by internal diodes. Current should be
limited to the maximum ratings given.
2
Overvoltages at the Ax, EN, Sx, or Dx pins are clamped by internal diodes.
Current should be limited to the maximum ratings given.
3
See Table 5.
1
Stresses at or above those listed under Absolute Maximum
Ratings may cause permanent damage to the product. This is a
stress rating only; functional operation of the product at these
or any other conditions above those indicated in the operational
section of this specification is not implied. Operation beyond
the maximum operating conditions for extended periods may
affect product reliability.
Only one absolute maximum rating may be applied at any
one time.
Rev. A | Page 8 of 22
θJA
97.9
46
θJC
14
Unit
°C/W
°C/W
Data Sheet
ADG1606/ADG1607
3
4
S15
5
ADG1606
S14
6
S13
7
TOP VIEW
(Not to Scale)
S12
8
S11
25
S7
24
S6
23
S5
22
S4
21
S3
9
20
S2
S10 10
19
S1
S9 11
18
EN
GND 12
17
A0
NC 13
16
A1
A3 14
15
A2
NC = NO CONNECT
S16
S15
S14
S13
S12
S11
S10
S9
1
2
3
4
5
6
7
8
ADG1606
TOP VIEW
(Not to Scale)
24
23
22
21
20
19
18
17
S8
S7
S6
S5
S4
S3
S2
S1
9
10
11
12
13
14
15
16
26 S8
NC
S16
GND
A3
A2
NC
NC
A1
A0
EN
27 VSS
32
31
30
29
28
27
26
25
28 D
2
NOTES
1. NC = NO CONNECT.
2. EXPOSED PAD TIED TO SUBSTRATE, VSS.
08489-003
NC
Figure 3. ADG1606 TSSOP Pin Configuration
08489-004
VDD 1
NC
VDD
NC
D
NC
NC
NC
VSS
PIN CONFIGURATIONS AND FUNCTION DESCRIPTIONS
Figure 4. ADG1606 LFCSP Pin Configuration
Table 9. ADG1606 Pin Function Descriptions
TSSOP
1
2, 3, 13
4
5
6
7
8
9
10
11
12
14
15
16
17
18
Pin No.
LFCSP
31
12, 13, 26,
27, 28, 30, 32
1
2
3
4
5
6
7
8
9
10
11
14
15
16
Mnemonic
VDD
NC
Description
Most Positive Power Supply Potential.
No Connect.
S16
S15
S14
S13
S12
S11
S10
S9
GND
A3
A2
A1
A0
EN
Source Terminal 16. This pin can be an input or an output.
Source Terminal 15. This pin can be an input or an output.
Source Terminal 14. This pin can be an input or an output.
Source Terminal 13. This pin can be an input or an output.
Source Terminal 12. This pin can be an input or an output.
Source Terminal 11. This pin can be an input or an output.
Source Terminal 10. This pin can be an input or an output.
Source Terminal 9. This pin can be an input or an output.
Ground (0 V) Reference.
Logic Control Input.
Logic Control Input.
Logic Control Input.
Logic Control Input.
Active High Digital Input. When this pin is low, the device is disabled and all switches are
turned off. When this pin is high, the Ax logic inputs determine which switch is turned on.
Source Terminal 1. This pin can be an input or an output.
Source Terminal 2. This pin can be an input or an output.
Source Terminal 3. This pin can be an input or an output.
Source Terminal 4. This pin can be an input or an output.
Source Terminal 5. This pin can be an input or an output.
Source Terminal 6. This pin can be an input or an output.
Source Terminal 7. This pin can be an input or an output.
Source Terminal 8. This pin can be an input or an output.
Most Negative Power Supply Potential. In single-supply applications, this pin can be
connected to ground.
Drain Terminal. This pin can be an input or an output.
The exposed pad is connected internally. For increased reliability of the solder joints and
maximum thermal capability, it is recommended that the pad be soldered to the substrate, VSS.
19
20
21
22
23
24
25
26
27
17
18
19
20
21
22
23
24
25
S1
S2
S3
S4
S5
S6
S7
S8
VSS
28
29
EPAD
D
Exposed Pad
Rev. A | Page 9 of 22
ADG1606/ADG1607
Data Sheet
Table 10. ADG1606 Truth Table
A3
X1
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
1
A2
X1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
A1
X1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
A0
X1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
EN
0
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
X = don’t care.
Rev. A | Page 10 of 22
On Switch
None
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
ADG1606/ADG1607
27 VSS
26 S8A
NC
3
S8B
4
S7B
5
ADG1607
S6B
6
S5B
7
TOP VIEW
(Not to Scale)
S4B
8
21 S3A
S3B
9
20 S2A
32
31
30
29
28
27
26
25
28 DA
2
25 S7A
S8B
S7B
S6B
S5B
S4B
S3B
S2B
S1B
24 S6A
23 S5A
19 S1A
S1B 11
18 EN
GND 12
17 A0
NC 13
16 A1
NC 14
15 A2
NC = NO CONNECT
ADG1607
TOP VIEW
(Not to Scale)
24
23
22
21
20
19
18
17
S8A
S7A
S6A
S5A
S4A
S3A
S2A
S1A
GND
A2
NC
NC
NC
A1
A0
EN
S2B 10
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
22 S4A
NOTES
1. NC = NO CONNECT.
2. EXPOSED PAD TIED TO SUBSTRATE, VSS.
08489-005
DB
Figure 5. ADG1607 TSSOP Pin Configuration
08489-006
VDD 1
NC
DB
NC
VDD
NC
DA
NC
VSS
Data Sheet
Figure 6. ADG1607 LFCSP Pin Configuration
Table 11. ADG1607 Pin Function Descriptions
TSSOP
1
2
3, 13, 14
4
5
6
7
8
9
10
11
12
15
16
17
18
Pin No.
LFCSP
29
31
11, 12, 13, 26,
28, 30, 32
1
2
3
4
5
6
7
8
9
10
14
15
16
Mnemonic
VDD
DB
NC
Description
Most Positive Power Supply Potential.
Drain Terminal B. This pin can be an input or an output.
No Connect.
S8B
S7B
S6B
S5B
S4B
S3B
S2B
S1B
GND
A2
A1
A0
EN
Source Terminal 8B. This pin can be an input or an output.
Source Terminal 7B. This pin can be an input or an output.
Source Terminal 6B. This pin can be an input or an output.
Source Terminal 5B. This pin can be an input or an output.
Source Terminal 4B. This pin can be an input or an output.
Source Terminal 3B. This pin can be an input or an output.
Source Terminal 2B. This pin can be an input or an output.
Source Terminal 1B. This pin can be an input or an output.
Ground (0 V) Reference.
Logic Control Input.
Logic Control Input.
Logic Control Input.
Active High Digital Input. When this pin is low, the device is disabled and all switches are
turned off. When this pin is high, the Ax logic inputs determine which switch is turned on.
Source Terminal 1A. This pin can be an input or an output.
Source Terminal 2A. This pin can be an input or an output.
Source Terminal 3A. This pin can be an input or an output.
Source Terminal 4A. This pin can be an input or an output.
Source Terminal 5A. This pin can be an input or an output.
Source Terminal 6A. This pin can be an input or an output.
Source Terminal 7A. This pin can be an input or an output.
Source Terminal 8A. This pin can be an input or an output.
Most Negative Power Supply Potential. In single-supply applications, this pin can be
connected to ground.
Drain Terminal A. This pin can be an input or an output.
The exposed pad is connected internally. For increased reliability of the solder joints and
maximum thermal capability, it is recommended that the pad be soldered to the substrate, VSS.
19
20
21
22
23
24
25
26
27
17
18
19
20
21
22
23
24
25
S1A
S2A
S3A
S4A
S5A
S6A
S7A
S8A
VSS
28
27
EPAD
DA
Exposed Pad
Rev. A | Page 11 of 22
ADG1606/ADG1607
Data Sheet
Table 12. ADG1607 Truth Table
A2
X1
0
0
0
0
1
1
1
1
1
A1
X1
0
0
1
1
0
0
1
1
A0
X1
0
1
0
1
0
1
0
1
EN
0
1
1
1
1
1
1
1
1
On Switch Pair
None
1
2
3
4
5
6
7
8
X = don’t care.
Rev. A | Page 12 of 22
Data Sheet
ADG1606/ADG1607
TYPICAL PERFORMANCE CHARACTERISTICS
7
7
VDD = 12V
VSS = 0V
TA = 25°C
6
6
ON RESISTANCE (Ω)
VDD = +3.3V
VSS = –3.3V
4
3
VDD = +5V
VSS = –5V
2
VDD = +8V
VSS = –8V
1
5
TA = +125°C
4
TA = +85°C
TA = +25°C
3
TA = –40°C
2
1
0
–2
0
4
2
6
8
SOURCE OR DRAIN VOLTAGE (V)
0
Figure 7. On Resistance as a Function of VD (VS) for Dual Supply
6
4
2
0
12
10
Figure 10. On Resistance as a Function of VD (VS) for Different Temperatures,
12 V Single Supply
16
12
TA = 25°C
VDD = 3.3V
VSS = 0V
14
10
TA = +125°C
ON RESISTANCE (Ω)
12
ON RESISTANCE (Ω)
8
SOURCE OR DRAIN VOLTAGE (V)
08489-010
–4
–6
08489-007
–8
10
VDD = 5V
VSS = 0V
8
6
VDD = 16V
VSS = 0V
VDD = 12V
VSS = 0V
4
TA = +85°C
8
TA = +25°C
6
TA = –40°C
4
2
2
VDD = 5V
VSS = 0V
0
6
4
8
12
10
14
16
SOURCE OR DRAIN VOLTAGE (V)
0
08489-008
2
0
Figure 8. On Resistance as a Function of VD (VS) for Single Supply
0
0.5
1.0
1.5
2.0
2.5
3.0
3.5
4.0
4.5
5.0
SOURCE OR DRAIN VOLTAGE (V)
08489-011
ON RESISTANCE (Ω)
5
Figure 11. On Resistance as a Function of VD (VS) for Different Temperatures,
5 V Single Supply
7
18
VDD = +5V
VSS = –5V
VDD = 3.3V
VSS = 0V
16
6
ON RESISTANCE (Ω)
ON RESISTANCE (Ω)
14
TA = +125°C
5
TA = +85°C
4
TA = +25°C
3
TA = –40°C
2
12
TA = +125°C
TA = +85°C
TA = +25°C
TA = –40°C
10
8
6
4
1
–3
–2
–1
0
1
2
SOURCE OR DRAIN VOLTAGE (V)
3
4
5
0
Figure 9. On Resistance as a Function of VD (VS) for Different Temperatures,
±5 V Dual Supply
0
0.5
1.0
1.5
2.0
2.5
SOURCE OR DRAIN VOLTAGE (V)
3.0
08489-012
–4
08489-009
0
–5
2
Figure 12. On Resistance as a Function of VD (VS) for Different Temperatures,
3.3 V Single Supply
Rev. A | Page 13 of 22
ADG1606/ADG1607
Data Sheet
25
12
VDD = +5V
VSS = –5V
VBIAS = +4.5V/–4.5V
20
VDD = 3.3V
VSS = 0V
VBIAS = 0.6V/3V
ID (OFF) – +
10
ID (ON) + +
ID, IS (ON) + +
LEAKAGE CURRENT (nA)
LEAKAGE CURRENT (nA)
15
IS (OFF) + –
10
IS (OFF) – +
5
0
–5
ID (ON) – –
–10
ID (OFF) + –
ID (OFF) – +
8
6
ID, IS (ON) – –
IS (OFF) + –
4
ID (OFF) + –
IS (OFF) – +
2
0
20
40
60
80
100
120 130
TEMPERATURE (°C)
0
08489-013
–20
Figure 13. Leakage Currents as a Function of Temperature, ±5 V Dual Supply
0
60
120 130
100
80
Figure 16. Leakage Currents as a Function of Temperature, 3.3 V Single Supply
1000
VDD = 12V
VSS = 0V
VBIAS = 1V/10V
15
IDD = ALL LOGIC HIGH
TA = 25°C
ID (ON) + +
ID (OFF) – +
800
IS (OFF) + –
10
VDD = +12V
VSS = 0V
IS (OFF) – +
600
IDD (µA)
5
0
400
VDD = +5V
VSS = –5V
ID (ON) – –
200
ID (OFF) + –
0
20
40
60
80
100
120 130
TEMPERATURE (°C)
0
08489-014
–15
VDD = +5V
VSS = 0V
VDD = +3.3V
VSS = 0V
0
2
4
6
8
10
12
14
LOGIC LEVEL (V)
Figure 14. Leakage Currents as a Function of Temperature, 12 V Single Supply
08489-017
–5
–10
Figure 17. IDD vs. Logic Level
45
30
TA = 25°C
ID, IS (ON) + +
20
ID (OFF) – +
15
ID, IS (ON) – –
IS (OFF) – +
5
VDD = +5V
VSS = –5V
35
IS (OFF) + –
10
VDD = +12V
VSS = 0V
40
CHARGE INJECTION (pC)
VDD = 5V
VSS = 0V
VBIAS = 1V/4.5V
25
LEAKAGE CURRENT (nA)
40
TEMPERATURE (°C)
20
LEAKAGE CURRENT (nA)
20
08489-016
–15
IS (OFF) + –
30
25
20
VDD = +5V
VSS = 0V
15
10
VDD = +3.3V
VSS = 0V
–5
0
20
40
60
80
TEMPERATURE (°C)
100
120 130
08489-015
0
Figure 15. Leakage Currents as a Function of Temperature, 5 V Single Supply
Rev. A | Page 14 of 22
–5
–6
–4
–2
0
2
4
6
8
10
VS (V)
Figure 18. Charge Injection vs. Source Voltage
12
08489-018
5
0
Data Sheet
ADG1606/ADG1607
450
0
TA = 25°C
–10
400
VDD = +3.3V, VSS = 0V
–20
350
–30
250
ISOLATOIN (dB)
VDD = +5V, VSS = 0V
200
150
VDD = +12V, VSS = 0V
100
–40
–50
–60
–70
VDD = +5V, VSS = –5V
–80
50
–20
0
20
40
60
80
100
TEMPERATURE (°C)
120
–100
30k
08489-019
0
–40
10M
100M
500M
Figure 21. ADG1606 Crosstalk vs. Frequency
0
0
TA = 25°C
VDD = +5V
VSS = –5V
–20
TA = 25°C
VDD = +5V
VSS = –5V
ADJACENT
CHANNEL
CROSSTALK (dB)
–40
–60
–80
–100
–40
–60
NONADJACENT
CHANNEL
–80
–100
100k
1M
10M
100M
FREQUENCY (Hz)
500M
08489-020
OFF ISOLATOIN (dB)
1M
FREQUENCY (Hz)
Figure 19. Transition Time vs. Temperature
–120
30k
100k
08489-021
–90
Figure 20. Off Isolation vs. Frequency
–120
30k
100k
1M
10M
100M
FREQUENCY (Hz)
Figure 22. ADG1607 Crosstalk vs. Frequency
Rev. A | Page 15 of 22
500M
08489-022
TIME (ns)
300
–20
TA = 25°C
VDD = +5V
VSS = –5V
ADG1606/ADG1607
Data Sheet
0
0
–10
–20
NO DECOUPLING
CAPACITORS
–30
–2
ACPSRR (dB)
–3
–4
–40
–50
–60
–70
–80
TA = 25°C
VDD = +5V
VSS = –5V
–6
30k
100k
1M
10M
40M
FREQUENCY (Hz)
VDD = 3.3V, VS = 2V p-p
0.4
VDD = 5V, VS = 3.5V p-p
0.3
0.2
VDD = 12V, VS = 5V p-p
0.1
VDD = 5V, VSS = 5V, VS = 5V p-p
0
0
5k
10k
15k
20k
08489-024
THD + N (%)
0.5
10k
100k
1M
Figure 25. ACPSRR vs. Frequency
RL = 110Ω
TA = 25°C
0.6
–100
1k
FREQUENCY (Hz)
Figure 23. ADG1606 On Response vs. Frequency
0.7
DECOUPLING
CAPACITORS ON
SUPPLIES
–90
08489-023
–5
FREQUENCY (Hz)
Figure 24. THD + N vs. Frequency
Rev. A | Page 16 of 22
10M
100M
08489-025
INSERTION LOSS (dB)
–1
TA = 25°C
VDD = +5V
VSS = –5V
Data Sheet
ADG1606/ADG1607
TEST CIRCUITS
V
ID (ON)
D
S
NC
D
A
IDS
08489-026
VS
Figure 28. On Leakage
Figure 26. On Resistance
IS (OFF)
A
S
D
VD
NC = NO CONNECT
08489-028
S
ID (OFF)
A
VD
08489-027
VS
Figure 27. Off Leakage
3V
ADDRESS
DRIVE (VIN)
50%
50%
tr < 20ns
tf < 20ns
VDD
VSS
VDD
VSS
A0
0V
VIN
tTRANSITION
50Ω
S1
A1
A2
VS1
S2 TO S15
A3
tTRANSITION
VS16
S16
ADG16061
90%
2.4V
OUTPUT
OUTPUT
D
EN
GND
300Ω
35pF
08489-029
90%
1SIMILAR CONNECTION FOR ADG1607.
Figure 29. Address to Output Switching Times, tTRANSITION
3V
ADDRESS
DRIVE (VIN)
VDD
VSS
VDD
VSS
A0
VIN
0V
50Ω
S1
A1
A2
VS
S2 TO S15
A3
S16
80%
ADG16061
80%
OUTPUT
2.4V
OUTPUT
D
EN
GND
300Ω
35pF
1SIMILAR CONNECTION FOR ADG1607.
Figure 30. Break-Before-Make Delay, tBBM
Rev. A | Page 17 of 22
08489-030
tBBM
ADG1606/ADG1607
Data Sheet
3V
ENABLE
DRIVE (VIN)
50%
VDD
VSS
VDD
VSS
A0
50%
S1
A1
A2
0V
VS
S2 TO S16
A3
tOFF (EN)
0.9VOUT
ADG16061
0.9VOUT
OUTPUT
VIN
OUTPUT
D
EN
GND
50Ω
1SIMILAR
300Ω
35pF
08489-031
tON (EN)
CONNECTION FOR ADG1607.
Figure 31. Enable Delay, tON (EN), tOFF (EN)
3V
VDD
VSS
VDD
A0
VSS
A1
A2
VIN
A3
ADG16061
VOUT
∆VOUT
S
VS
QINJ = CL × ∆VOUT
VIN
1SIMILAR
Figure 32. Charge Injection
Rev. A | Page 18 of 22
D
EN
GND
CL
1nF
CONNECTION FOR ADG1607.
VOUT
08489-032
RS
Data Sheet
VDD
ADG1606/ADG1607
VDD
VSS
VDD
NETWORK
ANALYZER
NETWORK
ANALYZER
VSS
S
VSS
0.1µF
0.1µF
0.1µF
0.1µF
VOUT
50Ω
50Ω
VDD
VSS
S1
RL
50Ω
D
VS
S2
R
50Ω
D
OFF ISOLATION = 20 log
VS
VOUT
VS
CHANNEL-TO-CHANNEL CROSSTALK = 20 log
Figure 33. Off Isolation
VDD
GND
08489-035
GND
VOUT
08489-033
RL
50Ω
VOUT
VS
Figure 35. Channel-to-Channel Crosstalk
VSS
0.1µF
0.1µF
VDD
VDD
VSS
VSS
0.1µF
0.1µF
NETWORK
ANALYZER
AUDIO PRECISION
VDD
50Ω
S
VS
VSS
RS
S
D
IN
RL
50Ω
GND
D
VIN
VOUT WITHOUT SWITCH
GND
RL
10kΩ
VOUT
08489-036
VOUT WITH SWITCH
08489-034
INSERTION LOSS = 20 log
VS
V p-p
VOUT
Figure 34. Bandwidth
Figure 36. THD + N
Rev. A | Page 19 of 22
ADG1606/ADG1607
Data Sheet
TERMINOLOGY
tBBM
Off time measured between the 80% points of the switches
when switching from one address state to another.
RON
Ohmic resistance between the D and S terminals.
∆RON
Difference between the RON of any two channels.
RFLAT(ON)
Flatness is defined as the difference between the maximum and
minimum value of on resistance as measured.
VINL
Maximum input voltage for Logic 0.
VINH
Minimum input voltage for Logic 1.
IS (Off)
Source leakage current when the switch is off.
IINL, IINH
Input current of the digital input.
ID (Off)
Drain leakage current when the switch is off.
IDD
Positive supply current.
ID, IS (On)
Channel leakage current when the switch is on.
ISS
Negative supply current.
VD, VS
Analog voltage on Terminal D and Terminal S.
Off Isolation
A measure of unwanted signal coupling through an off channel.
CS (Off)
Channel input capacitance for the off condition.
Charge Injection
A measure of the glitch impulse transferred from the digital
input to the analog output during switching.
CD (Off)
Channel output capacitance for the off condition.
Bandwidth
The frequency at which the output is attenuated by 3 dB.
CD, CS (On)
On switch capacitance.
On Response
The frequency response of the on switch.
CIN
Digital input capacitance.
tON (EN)
Delay time between the 50% and 90% points of the digital input
and the switch on condition.
tOFF (EN)
Delay time between the 50% and 90% points of the digital input
and the switch off condition.
tTRANSITION
Delay time between the 50% and 90% points of the digital
inputs and the switch on condition when switching from one
address state to another.
THD + N
The ratio of the harmonic amplitude plus noise of the signal
to the fundamental.
AC Power Supply Rejection Ratio (ACPSRR)
Measures the ability of a part to avoid coupling noise and
spurious signals that appear on the supply voltage pin to the
output of the switch. The dc voltage on the device is modulated by a sine wave of 0.62 V p-p. The ratio of the amplitude
of signal on the output to the amplitude of the modulation is
the ACPSRR.
Rev. A | Page 20 of 22
Data Sheet
ADG1606/ADG1607
OUTLINE DIMENSIONS
9.80
9.70
9.60
28
15
4.50
4.40
4.30
6.40 BSC
1
14
PIN 1
0.65
BSC
0.15
0.05
0.30
0.19
COPLANARITY
0.10
1.20 MAX
SEATING
PLANE
8°
0°
0.20
0.09
0.75
0.60
0.45
COMPLIANT TO JEDEC STANDARDS MO-153-AE
Figure 37. 28-Lead Thin Shrink Small Outline Package [TSSOP]
(RU-28)
Dimensions shown in millimeters
0.30
0.25
0.18
32
25
0.50
BSC
TOP VIEW
0.80
0.75
0.70
8
16
0.05 MAX
0.02 NOM
COPLANARITY
0.08
0.20 REF
SEATING
PLANE
3.25
3.10 SQ
2.95
EXPOSED
PAD
17
0.50
0.40
0.30
PIN 1
INDICATOR
1
24
9
BOTTOM VIEW
0.25 MIN
FOR PROPER CONNECTION OF
THE EXPOSED PAD, REFER TO
THE PIN CONFIGURATION AND
FUNCTION DESCRIPTIONS
SECTION OF THIS DATA SHEET.
COMPLIANT TO JEDEC STANDARDS MO-220-WHHD.
112408-A
PIN 1
INDICATOR
5.10
5.00 SQ
4.90
Figure 38. 32-Lead Lead Frame Chip Scale Package [LFCSP]
5 mm × 5 mm Body and 0.75 mm Package Height
(CP-32-7)
Dimensions shown in millimeters
ORDERING GUIDE
Model 1
ADG1606BRUZ
ADG1606BRUZ-REEL7
ADG1606BCPZ-REEL7
ADG1607BRUZ
ADG1607BRUZ-REEL7
ADG1607BCPZ-REEL7
1
Temperature Range
−40°C to +125°C
−40°C to +125°C
−40°C to +125°C
−40°C to +125°C
−40°C to +125°C
−40°C to +125°C
Package Description
28-Lead Thin Shrink Small Outline Package [TSSOP]
28-Lead Thin Shrink Small Outline Package [TSSOP]
32-Lead Lead Frame Chip Scale Package [LFCSP]
28-Lead Thin Shrink Small Outline Package [TSSOP]
28-Lead Thin Shrink Small Outline Package [TSSOP]
32-Lead Lead Frame Chip Scale Package [LFCSP]
Z = RoHS Compliant Part.
Rev. A | Page 21 of 22
Package Option
RU-28
RU-28
CP-32-7
RU-28
RU-28
CP-32-7
ADG1606/ADG1607
Data Sheet
NOTES
©2009–2016 Analog Devices, Inc. All rights reserved. Trademarks and
registered trademarks are the property of their respective owners.
D08489-0-8/16(A)
Rev. A | Page 22 of 22
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