LC2MOS
Quad SPST Switches
ADG211A/ADG212A
Data Sheet
FEATURES
FUNCTIONAL BLOCK DIAGRAM
44 V supply maximum rating
±15 V analog signal range
Low RON: 115 Ω maximum
Low leakage: 0.5 nA typical
Break-before-make switching
Single supply operation possible
Extended plastic temperature range: −40°C to +85°C
TTL/CMOS compatible
Available in 16-lead PDIP/SOIC and 20-pead PLCC packages
Pin compatible to DG211/DG212
ADG211A
S1
IN1
D1
S2
IN2
D2
S3
IN3
D3
S4
IN4
NOTES
1. SWITCHES SHOWN FOR A LOGIC 1 INPUT.
10950-001
D4
Figure 1.
ADG212A
S1
IN1
D1
S2
IN2
D2
S3
IN3
D3
S4
IN4
NOTES
1. SWITCHES SHOWN FOR A LOGIC 1 INPUT.
10950-002
D4
Figure 2.
GENERAL DESCRIPTION
PRODUCT HIGHLIGHTS
The ADG211A and ADG212A are monolithic CMOS devices
comprising four independently selectable switches. They are
designed on an enhanced LC2MOS process, which gives an
increased signal handling capability of ±15 V. These switches
also feature high switching speeds and low RON.
1.
The ADG211A and ADG212A consist of four SPST switches.
They differ only in that the digital control logic is inverted. In
multiplexer applications, all switches exhibit break-before-make
switching action when driven simultaneously. Inherent in the
design is low charge injection for minimum transients when
switching the digital inputs.
Rev. C
2.
3.
Extended Signal Range.
These switches are fabricated on an enhanced LC2MOS
process, resulting in high breakdown and an increased
analog signal range of ±15 V.
Single Supply Operation.
For applications where the analog signal is unipolar (0 V to
15 V), the switches can be operated from a single 15 V
supply.
Low Leakage.
Leakage currents in the range of 500 pA make these
switches suitable for high precision circuits. The added
feature of break-before-make allows for multiple outputs
to be tied together for multiplexer applications while
keeping leakage errors to a minimum.
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ADG211A/ADG212A
Data Sheet
TABLE OF CONTENTS
Features .............................................................................................. 1
ESD Caution...................................................................................4
Functional Block Diagram .............................................................. 1
Pin Configurations and Function Descriptions ............................5
General Description ......................................................................... 1
Typical Performance Characteristics ..............................................6
Product Highlights ........................................................................... 1
Terminology .......................................................................................9
Revision History ............................................................................... 2
Test Circuits ..................................................................................... 10
Specifications..................................................................................... 3
Outline Dimensions ....................................................................... 12
Absolute Maximum Ratings............................................................ 4
Ordering Guide .......................................................................... 13
REVISION HISTORY
10/12—Rev. B to Rev. C
Updated Format .................................................................. Universal
Added Pin Descriptions, Table 3 .................................................... 5
Moved Table 4 ................................................................................... 5
Changes to Figure 5, Figure 6, Figure 8, and Figure 9 ................. 6
Updated Outline Dimensions ....................................................... 13
Changes to Ordering Guide .......................................................... 14
9/02—Rev. A to Rev. B
Rev. C | Page 2 of 16
Data Sheet
ADG211A/ADG212A
SPECIFICATIONS
VDD = +15 V, VSS = −15 V, VL = 5 V, unless otherwise noted.
Table 1.
Parameter
ANALOG SWITCH
Analog Signal Range
RON
RON vs. VD (VS)
RON Drift
RON Match
LEAKAGE CURRENTS
IS (Off )
Off Input Leakage
ID (Off )
Off Output Leakage
ID (On)
On Channel Leakage
DIGITAL CONTROL
VINH, Input High Voltage
VINL, Input Low Voltage
INL or INH
CIN, Digital Input Capacitance
DYNAMIC CHARACTERISTICS
tOPEN 1
tON1
tOFF1
Off Isolation
Min
Channel-to-Channel Crosstalk
CS (Off )
CD (Off )
CS, CD (On)
QINJ, Charge Injection
POWER SUPPLY
IDD
IDD
ISS
ISS
IL
1
25°C
Typ
Max
−40°C to +85°C
Min Typ Max
±15
±15
115
175
20
0.5
5
0.5
5
100
5
100
5
200
0.5
0.5
2.4
Unit
V
Ω
%
%/°C
%
nA
nA
nA
nA
nA
nA
Test Conditions/Comments
−10 V ≤ VS ≤ +10 V, IDS = 1 mA, see Figure 21
VS = 0 V, IDS = 1 mA
VD = ±14 V; VS = 14 V; see Figure 22
VD = ±14 V; VS = 14 V; see Figure 22
VD = VS = ±14 V; see Figure 23
V
V
µA
pF
TTL compatibility is independent of VL
80
ns
ns
ns
dB
80
5
5
16
20
dB
pF
pF
pF
pC
See Figure 24
See Figure 25
See Figure 25
VS = 10 V (p-p); f = 100 kHz;
RL = 75 Ω; see Figure 26
See Figure 27
0.8
1
5
30
600
450
0.6
mA
mA
mA
mA
mA
1
0.1
0.2
0.9
Sample tested at 25°C to ensure compliance.
Rev. C | Page 3 of 16
RS = 0 Ω; CL = 1000 pF; VS = 0 V; see Figure 28
Digital inputs = VINL or VINH
ADG211A/ADG212A
Data Sheet
ABSOLUTE MAXIMUM RATINGS
TA = 25°C, unless otherwise stated.
Stresses above those listed under Absolute Maximum Ratings
may cause permanent damage to the device. This is a stress
rating only; functional operation of the device at these or any
other conditions above those indicated in the operational
section of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect
device reliability.
Table 2.
Parameter
VDD to VSS
VDD to GND
VSS to GND
VL to GND
Analog Inputs1
Voltage at S, D
Continuous Current, S or D
Pulsed Current S or D
1 ms Duration, 10% Duty Cycle
Digital Inputs1
Voltage at IN
Power Dissipation (Any Package)
Up to +75°C
Derates above +75°C by
Operating Temperature
Storage Temperature Range
Lead Temperature (Soldering 10 sec)
1
Rating
44 V
25 V
−25 V
−0.3 V, 25 V
VSS − 0.3 V to VDD + 0.3 V
30 mA
ESD CAUTION
70 mA
VSS − 2 V to VDD + 2 V or
20 mA, Whichever
Occurs First
470 mW
6 mW/°C
−40°C to +85°C
−65°C to +150°C
+300°C
Overvoltage at IN, S, or D will be clamped by diodes. Current should be
limited to the Maximum Rating listed in Table 2.
Rev. C | Page 4 of 16
Data Sheet
ADG211A/ADG212A
D4 7
IN4 8
13 VDD
12 VL
11 S3
10 D3
9
IN3
GND
7
S4
8
IN1
NIC
IN2
D2
PIN 1
INDENTFIER
15 VL
14 S3
9
10
11
12
13
Figure 4. PLCC Pin Configuration
Mnemonic
IN1
D1
S1
VSS
GND
S4
D4
IN4
IN3
D3
S3
VL
VDD
S2
D2
IN2
NIC
Description
Logic Control Input.
Drain Terminal. Can be an input or output.
Source Terminal. Can be an input or output.
Most Negative Power Supply Potential.
Ground (0 V) Reference.
Source Terminal. Can be an input or output.
Drain Terminal. Can be an input or output.
Logic Control Input.
Logic Control Input.
Drain Terminal. Can be an input or output.
Source Terminal. Can be an input or output.
Logic Supply Voltage.
Most Positive Power Supply Potential.
Source Terminal. Can be an input or output.
Drain Terminal. Can be an input or output.
Logic Control Input.
No Internal Connection.
ADG212A In
1
0
Switch Condition
On
Off
Table 4. Truth Table
ADG211A In
0
1
16 NIC
TOP VIEW
(Not to Scale)
Table 3. Pin Function Descriptions
Pin No.
PLCC
2
3
4
5
7
8
9
10
12
13
14
15
17
18
19
20
1, 6, 11, 16
17 VDD
ADG211A/
ADG212A
NOTES
1. NIC = NO INTERNAL CONNECTION.
Figure 3. PDIP, SOIC Pin Configuration
PDIP, SOIC
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
18 S2
Rev. C | Page 5 of 16
10950-004
S4 6
TOP VIEW
(Not to Scale)
14 S2
19
D3
GND 5
15 D2
6
20
IM3
VSS 4
ADG211A/
ADG212A
NIC
1
NIC
S1 3
10950-003
D1 2
5
2
D4
16 IN2
4
3
IN4
IN1 1
S1
VSS
D1
PIN CONFIGURATIONS AND FUNCTION DESCRIPTIONS
ADG211A/ADG212A
Data Sheet
TYPICAL PERFORMANCE CHARACTERISTICS
The switches can comfortably operate anywhere in the 10 V to 15 V single or dual supply range, with only a slight degradation in
performance. The following graphs show the relevant performance curves. The test circuits and test conditions are given in a following
section, Test Circuits.
120
120
VDD = +15V
VSS = –15V
90
VDD = 15V
VSS = 0V
90
70°C
RON (Ω)
RON (Ω)
25°C
60
70°C
0°C
60
25°C
0°C
–10
–5
0
5
10
15
VD (VS) (V)
0
0
10
15
VD (VS) (V)
Figure 5. RON as a Function of VD (VS), Dual ±15 V Supplies
120
5
10950-008
0
–15
30
10950-005
30
Figure 8. RON as a Function of VD (VS), Single +15 V Supply
150
VDD = +10V
VSS = –10V
VDD = 10V
VSS = 0V
70°C
120
90
RON (Ω)
RON (Ω)
25°C
90
70°C
25°C
60
0°C
60
0°C
30
–5
0
5
10
VD (VS) (V)
0
10950-006
0
–10
0
Figure 6. RON as a Function of VD (VS), Dual ±10 V Supplies
100
5
10
VD (VS) (V)
10950-009
30
Figure 9. RON as a Function of VD (VS), Single +10 V Supply
2.5
VDD = +15V
VSS = –15V
TEMP = 0°C TO 70°C
2.0
TRIGGER LEVEL (V)
CURRENT (nA)
10
ID (ON)
1
IS (OFF)
ID (OFF)
1.5
1.0
0.1
30
40
50
60
TEMPERATURE (°C)
70
80
90
0
10
10950-007
0.01
20
Figure 7. Leakage Current as a Function of Temperature
(Note That Leakage Current Reduces as the Supply Voltages Reduce)
11
12
13
SUPPLY VOLTAGE (V)
14
15
10950-010
0.5
Figure 10. Trigger Levels vs. Power Supply Voltage, Dual or Single Supply
Voltage
Rev. C | Page 6 of 16
Data Sheet
ADG211A/ADG212A
220
220
200
200
180
180
160
160
tON (ns)
tON (ns)
70°C
70°C
140
25°C
140
0°C
25°C
120
120
0°C
11
12
13
14
15
SUPPLY VOLTAGE (±V)
80
10
10950-011
80
10
11
12
13
14
15
SUPPLY VOLTAGE (V)
10950-014
100
100
Figure 14. tON vs. Supply Voltage (Single Supply)
Figure 11. tON vs. Supply Voltage (Dual Supply)
80
80
70°C
25°C
60
60
25°C
tOFF (ns)
40
40
0°C
20
20
11
12
13
14
15
SUPPLY VOLTAGE (±V)
0
10
10950-012
0
10
70°C
11
12
13
14
15
SUPPLY VOLTAGE (V)
10950-015
tOFF (ns)
0°C
Figure 15. tOFF vs. Supply Voltage (Single Supply)
Figure 12. tOFF vs. Supply Voltage (Dual Supply)
60
50
40
CHARGE INJECTION (pC)
OFF ISOLATION (dB)
60
70
SINGLE SUPPLY
80
VDD = +15V
VSS = –15V
20
VDD = +15V
VSS = 0V
0
–20
11
12
13
SUPPLY VOLTAGE (V)
14
15
–40
–16
10950-013
90
10
Figure 13. Off Isolation and Channel-to-Channel Crosstalk vs. Supply Voltage
–12
–8
–4
0
VS (V)
4
8
12
16
10950-016
DUAL SUPPLY
Figure 16. Charge Injection vs. Source Voltage (VS) for Dual and Single 15 V
Supplies
Rev. C | Page 7 of 16
ADG211A/ADG212A
Data Sheet
60
0.7
0.6
VDD = +10V
VSS = –10V
0°C
0.5
25°C
20
IDD (mA)
VDD = +10V
VSS = 0V
0
0.4
70°C
0.3
–20
–12
–8
–4
0
4
8
12
16
VS (V)
0.1
10
10950-017
–40
–16
0.2
11
12
13
14
15
SUPPLY VOLTAGE (±V)
10950-019
CHARGE INJECTION (pC)
40
Figure 19. IDD vs. Supply Voltage, (Dual Supply)
Figure 17. Charge Injection vs. Source Voltage for Dual and Single 10 V
Supplies
0.7
0.4
0.6
0°C
0.3
0.5
IDD (mA)
0.2
25°C
0.4
70°C
0.3
0.1
0.2
0
10
11
12
13
14
SUPPLY VOLTAGE (±V)
15
Figure 18. ISS vs. Supply Voltage (Dual Supply)
0.1
10
11
12
13
14
SUPPLY VOLTAGE (V)
Figure 20. IDD vs. Supply Voltage (Single Supply)
Rev. C | Page 8 of 16
15
10950-020
70°C
25°C
10950-018
ISS (µA)
0°C
Data Sheet
ADG211A/ADG212A
TERMINOLOGY
tOFF
Delay time between the 50% and 90% points of the digital input
and switch off condition.
RON
Ohmic resistance between the out and S terminals.
RON Match
Difference between the RON of any two channels.
tOPEN
Off time measured between 50% points of both switches, which
are connected as a multiplexer when switching from one
address state to another.
IS (Off)
Source terminal leakage current when the switch is off.
ID (Off)
Drain terminal leakage current when the switch is off.
ID (On)
Leakage current that flows from the closed switch into the body.
VD (VS)
Analog voltage on the D, S terminals.
VINL
Maximum input voltage for a logic low.
VINH
Minimum input voltage for a logic high.
IINL (IINH)
Input current of the digital input.
CS (Off)
Switch input capacitance off condition.
VDD
Most positive voltage supply.
CD (Off)
Switch output capacitance off condition.
VSS
Most negative voltage supply.
CIN
Digital input capacitance.
VL
Logic supply voltage.
CD, CS (On)
Input or output capacitance when the switch is on.
tON
Delay time between the 50% and 90% points of the digital input
and switch on condition.
IDD
Positive supply current.
ISS
Negative supply current.
Rev. C | Page 9 of 16
ADG211A/ADG212A
Data Sheet
TEST CIRCUITS
IDS
V1
10950-021
VS
S
RON = V1/IDS
VD
Figure 23.
ID (OFF)
D
A
VD
10950-022
Figure 22.
2V
+5V
+15V
VL
VDD
S1
D1
S2
D2
VIN
VOUT
14pF
330Ω
ADG212A
*
VIN
*
3V
ADG211A
3V
VIN
IN1
IN2
GND
VOUT
50%
VSS
–15V
10950-024
tOPEN
* BOTH THE BUFFER AND INVERTER SHOULD
HAVE THE SAME PROPAGATION DELAY.
Figure 24.
+5V
VDD
VL
VDD
S
VIN
VOUT
330Ω
IN
GND
VIN
D
2V
3V
ADG211A
14pF
50%
50%
50%
50%
3V
ADG212A
VIN
VSS
90%
90%
VOUT
VSS
tON
Figure 25.
Rev. C | Page 10 of 16
tOFF
10950-025
VS
S
A
A
VS
Figure 21.
IS (OFF)
ID (ON)
D
10950-023
D
S
Data Sheet
ADG211A/ADG212A
+5V
VDD
VL
VDD
+5V
VDD
VL
VDD
S
D
D
S
75Ω
VIN
VOUT
VIN
RL
75Ω
VIN
GND
ADG211A: V IN = 5V
ADG212A: V IN = 0V
RL
75Ω
VSS
OFF ISOLATION =
20 × log |VS/VOUT|
VSS
10950-026
VS
VOUT
ADG211A: V IN = 0V
ADG212A: V IN = 5V
VS
+5V
VDD
VL
VDD
S
VSS
CHANNEL-TO-CHANNEL
CROSSTALK = 20 × log |VS/VOUT|
5V
AD711
D
CL
1µF
VIN
GND
NC
VSS
Figure 27. Channel-to-Channel Crosstalk
Figure 26. Off Isolation
RS
GND
VIN
VOUT
0V
ΔVOUT
VOUT
VSS
QINJ = CL × ΔVOUT
VSS
Figure 28. Charge Injection
Rev. C | Page 11 of 16
10950-027
D
10950-028
S
VS
ADG211A/ADG212A
Data Sheet
OUTLINE DIMENSIONS
0.800 (20.32)
0.790 (20.07)
0.780 (19.81)
16
9
1
8
0.280 (7.11)
0.250 (6.35)
0.240 (6.10)
0.325 (8.26)
0.310 (7.87)
0.300 (7.62)
0.100 (2.54)
BSC
0.060 (1.52)
MAX
0.210 (5.33)
MAX
0.195 (4.95)
0.130 (3.30)
0.115 (2.92)
0.015
(0.38)
MIN
0.150 (3.81)
0.130 (3.30)
0.115 (2.92)
0.015 (0.38)
GAUGE
PLANE
SEATING
PLANE
0.022 (0.56)
0.018 (0.46)
0.014 (0.36)
0.014 (0.36)
0.010 (0.25)
0.008 (0.20)
0.430 (10.92)
MAX
0.005 (0.13)
MIN
0.070 (1.78)
0.060 (1.52)
0.045 (1.14)
073106-B
COMPLIANT TO JEDEC STANDARDS MS-001-AB
CONTROLLING DIMENSIONS ARE IN INCHES; MILLIMETER DIMENSIONS
(IN PARENTHESES) ARE ROUNDED-OFF INCH EQUIVALENTS FOR
REFERENCE ONLY AND ARE NOT APPROPRIATE FOR USE IN DESIGN.
CORNER LEADS MAY BE CONFIGURED AS WHOLE OR HALF LEADS.
Figure 29. 16-Lead Plastic Dual In-Line Package [PDIP]
Narrow Body
(N-16)
Dimensions shown in inches and (millimeters)
10.00 (0.3937)
9.80 (0.3858)
4.00 (0.1575)
3.80 (0.1496)
9
16
1
8
1.27 (0.0500)
BSC
0.25 (0.0098)
0.10 (0.0039)
COPLANARITY
0.10
0.51 (0.0201)
0.31 (0.0122)
6.20 (0.2441)
5.80 (0.2283)
1.75 (0.0689)
1.35 (0.0531)
SEATING
PLANE
0.50 (0.0197)
0.25 (0.0098)
45°
8°
0°
0.25 (0.0098)
0.17 (0.0067)
1.27 (0.0500)
0.40 (0.0157)
Figure 30.16-Lead Standard Small Outline Package [SOIC_N]
Narrow Body
(R-16)
Dimensions shown in millimeters and (inches)
Rev. C | Page 12 of 16
060606-A
COMPLIANT TO JEDEC STANDARDS MS-012-AC
CONTROLLING DIMENSIONS ARE IN MILLIMETERS; INCH DIMENSIONS
(IN PARENTHESES) ARE ROUNDED-OFF MILLIMETER EQUIVALENTS FOR
REFERENCE ONLY AND ARE NOT APPROPRIATE FOR USE IN DESIGN.
Data Sheet
ADG211A/ADG212A
0.180 (4.57)
0.165 (4.19)
0.048 (1.22 )
0.042 (1.07)
3
0.048 (1.22)
0.042 (1.07)
4
0.056 (1.42)
0.042 (1.07)
0.20 (0.51)
MIN
19
PIN 1
IDENTIFIER
0.021 (0.53)
0.013 (0.33)
18
0.050
(1.27)
BSC
TOP VIEW
0.330 (8.38)
0.032 (0.81) 0.290 (7.37)
0.026 (0.66)
(PINS DOWN)
14
8
0.020
(0.51)
R
9
0.020 (0.50)
R
BOTTOM
VIEW
(PINS UP)
13
0.356 (9.04)
SQ
0.350 (8.89)
0.395 (10.03)
SQ
0.385 (9.78)
0.045 (1.14)
R
0.025 (0.64)
0.120 (3.04)
0.090 (2.29)
COMPLIANT TO JEDEC STANDARDS MO-047-AA
CONTROLLING DIMENSIONS ARE IN INCHES; MILLIMETER DIMENSIONS
(IN PARENTHESES) ARE ROUNDED-OFF INCH EQUIVALENTS FOR
REFERENCE ONLY AND ARE NOT APPROPRIATE FOR USE IN DESIGN.
Figure 31. 20-Lead Plastic Leaded Chip Carrier [PLCC]
(P-20)
Dimensions shown in inches and (millimeters)
ORDERING GUIDE
Model1
ADG211AKN
ADG211AKNZ
ADG211AKPZ
ADG211AKR
ADG211AKRZ
ADG211AKRZ-REEL
ADG211AKRZ-REEL7
ADG212AKNZ
ADG212AKPZ
ADG212AKPZ-REEL
ADG212AKR
ADG212AKRZ
ADG212AKRZ-REEL
1
Temperature Range
−40°C to +85°C
−40°C to +85°C
−40°C to +85°C
−40°C to +85°C
−40°C to +85°C
−40°C to +85°C
−40°C to +85°C
−40°C to +85°C
−40°C to +85°C
−40°C to +85°C
−40°C to +85°C
−40°C to +85°C
−40°C to +85°C
Package Description
16-Lead PDIP
16-Lead PDIP
20-Lead PLCC
16-Lead SOIC_N
16-Lead SOIC_N
16-Lead SOIC_N
16-Lead SOIC_N
16-Lead PDIP
20-Lead PLCC
20-Lead PLCC
16-Lead SOIC_N
16-Lead SOIC_N
16-Lead SOIC_N
Z = RoHS Compliant Part.
Rev. C | Page 13 of 16
Package Option
N-16
N-16
P-20
R-16
R-16
R-16
R-16
N-16
P-20
P-20
R-16
R-16
R-16
ADG211A/ADG212A
Data Sheet
NOTES
Rev. C | Page 14 of 16
Data Sheet
ADG211A/ADG212A
NOTES
Rev. C | Page 15 of 16
ADG211A/ADG212A
Data Sheet
NOTES
©2012 Analog Devices, Inc. All rights reserved. Trademarks and
registered trademarks are the property of their respective owners.
D10950-0-10/12(C)
Rev. C | Page 16 of 16
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