Data Sheet
ADG3246
2.5 V/3.3 V, 10-Bit, 2-Port Level Translating, Bus Switch
FEATURES
►
►
►
►
►
►
►
►
FUNCTIONAL BLOCK DIAGRAM
225 ps Propagation Delay through the Switch
4.5 Ω Switch Connection between Ports
Data Rate 1.244 Gbps
2.5 V/3.3 V Supply Operation
Selectable Level Shifting/Translation
Small Signal Bandwidth 610 MHz
Level Translation
► 3.3 V to 2.5 V
► 3.3 V to 1.8 V
► 2.5 V to 1.8 V
24-Lead LFCSP Package
Figure 1.
APPLICATIONS
►
►
►
►
►
►
►
►
3.3 V to 1.8 V Voltage Translation
3.3 V to 2.5 V Voltage Translation
2.5 V to 1.8 V Voltage Translation
Bus Switching
Bus Isolation
Hot Swap
Hot Plug
Analog Signal Switching
GENERAL DESCRIPTION
The ADG3246 is a 2.5 V or 3.3 V, 10-bit, 2-port digital switch. It
is designed on Analog Devices’ low voltage CMOS process, which
provides low power dissipation yet gives high switching speed
and very low on resistance, allowing inputs to be connected to outputs without additional propagation delay or generating additional
ground bounce noise.
The switches are enabled by means of the bus enable (BE)
input signal. These digital switches allow bidirectional signals to
be switched when ON. In the OFF condition, signal levels up to the
supplies are blocked.
PRODUCT HIGHLIGHTS
1.
2.
3.
4.
5.
3.3 V or 2.5 V supply operation.
Extremely low propagation delay through switch.
4.5 Ω switches connect inputs to outputs.
Level/voltage translation.
24-lead 4 mm × 4 mm LFCSP package.
This device is ideal for applications requiring level translation. When
operated from a 3.3 V supply, level translation from 3.3 V inputs
to 2.5 V outputs occurs. Similarly, if the device is operated from a
2.5 V supply and 2.5 V inputs are applied, the device will translate
the outputs to 1.8 V. In addition to this, the ADG3246 has a level
translating select pin (SEL). When SEL is low, VCC is reduced
internally, allowing for level translation between 3.3 V inputs and 1.8
V outputs. This makes the device suited to applications requiring
level translation between different supplies, such as converter to
DSP/microcontroller interfacing.
Rev. B
DOCUMENT FEEDBACK
TECHNICAL SUPPORT
Information furnished by Analog Devices is believed to be accurate and reliable "as is". However, no responsibility is assumed by Analog
Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications subject to
change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and
registered trademarks are the property of their respective owners.
Data Sheet
ADG3246
TABLE OF CONTENTS
Features................................................................ 1
Applications........................................................... 1
Functional Block Diagram......................................1
General Description...............................................1
Product Highlights................................................. 1
Specifications........................................................ 3
Absolute Maximum Ratings...................................6
Thermal Resistance........................................... 6
Electrostatic Discharge (ESD) Ratings ..............6
ESD Ratings for ADG3246.................................6
ESD Caution.......................................................6
Pin Configuration and Function Descriptions........ 7
Typical Performance Characteristics..................... 8
Test Circuits......................................................... 12
Terminology......................................................... 13
Applications Information...................................... 14
Bus Switch Applications................................... 14
Package and Pinout......................................... 16
Outline Dimensions............................................. 17
Ordering Guide.................................................17
REVISION HISTORY
8/2022—Rev. A to Rev. B
Updated Format (Universal).............................................................................................................................1
Changes to Table 1.......................................................................................................................................... 3
Changes to Table 2.......................................................................................................................................... 6
Added Thermal Resistance Section and Table 3; Renumbered Sequentially..................................................6
Added Electrostatic Discharge (ESD) Ratings Section....................................................................................6
Added ESD Ratings for ADG3246 Section and Table 4.................................................................................. 6
Changes to Figure 3 Caption to Figure 8 Caption........................................................................................... 8
Changes to Figure 9 Caption and Figure 10 Caption...................................................................................... 9
Changes to Figure 18 Caption and Figure 19 Caption.................................................................................. 10
Changed Timing Measurement Information Section to Test Circuits Section................................................ 12
Changed High Impedance During Power-Up/Power-Down Section to High Impedance During PowerUp and Power-Down Section.......................................................................................................................16
Updated Outline Dimensions......................................................................................................................... 17
Changes to Ordering Guide........................................................................................................................... 17
analog.com
Rev. B | 2 of 17
Data Sheet
ADG3246
SPECIFICATIONS
VCC = 2.3 V to 3.6 V, GND = 0 V, all specifications TMIN to TMAX, unless otherwise noted.
Table 1.
Parameter
+25°C
DC ELECTRICAL CHARACTERISTICS
Input High Voltage (VINH)
Input Low Voltage (VINL)
Input Leakage Current (II)
±0.01
OFF State Leakage Current (IOZ OFF)
±0.01
ON State Leakage Current (IOZ ON)
±0.01
Maximum Pass Voltage (VP)
2.5
−40°C to
+85°C
−40°C to
+105°C
2.0
1.7
0.8
0.7
2.0
1.7
0.8
0.7
±1
±1
±1
±1
±1
±1
2.0
2.9
2.0
2.9
1.5
2.1
1.5
2.1
1.5
2.1
1.5
2.1
1.8
1.8
CAPACITANCE
A Port Off Capacitance (CA OFF)
B Port Off Capacitance (CB OFF)
A, B Port On Capacitance (CA, CB ON)
Control Input Capacitance (CIN)
SWITCHING CHARACTERISTICS
Propagation Delay A to B or B to A1 (tPD)
5
5
10
6
0.225
3.5
0.275
2
Propagation Delay Matching2 (ΔtPD)
22.5
200
37.5
200
Bus Enable Time BE to A or B3 (tPZH, tPZL)
3.2
1
4.8
2.2
0.5
3.3
2.2
0.5
3
Bus Disable Time BE to A or B3 (tPHZ, tPLZ)
3.2
1
4.8
analog.com
Unit
Test Conditions/Comments
V min
V min
V max
V max
μA typ
μA max
μA typ
μA max
μA typ
μA max
V typ
V min
Vmax
V typ
V min
V max
V typ
V min
V max
VCC = 2.7 V to 3.6 V
VCC = 2.3 V to 2.7 V
VCC = 2.7 V to 3.6 V
VCC = 2.3 V to 2.7 V
0 ≤ A, B ≤ VCC
0 ≤ A, B ≤ VCC
0 ≤ A, B ≤ VCC
0 ≤ A, B ≤ VCC
VA/VB = VCC = SEL = 3.3 V, IO = –5 μA
VA/VB = VCC = SEL = 2.5 V, IO = –5 μA
VA/VB = VCC = 3.3 V, SEL = 0 V, IO = –5 μA
pF
pF
pF
pF
f = 1 MHz
f = 1 MHz
f = 1 MHz
f = 1 MHz
ns typ
ns max
ns typ
ns max
ps typ
ps max
ps typ
ps max
ns typ
ns min
ns max
ns typ
ns min
ns max
ns typ
ns min
ns max
ns typ
ns min
ns max
CL = 50 pF, VCC = 3 V, SEL = 3 V
CL = 50 pF, VCC = 3.3 V, SEL = 0 V
CL = 50 pF, VCC = 3 V, SEL = 3 V
CL = 50 pF, VCC = 3.3 V, SEL = 0 V
VCC = 3.0 V to 3.6 V, SEL = VCC
VCC = 3.0 V to 3.6 V, SEL = 0 V
VCC = 2.3 V to 2.7 V, SEL = VCC
VCC = 3.0 V to 3.6 V, SEL = VCC
Rev. B | 3 of 17
Data Sheet
ADG3246
SPECIFICATIONS
Table 1.
Parameter
+25°C
−40°C to
+85°C
−40°C to
+105°C
1.7
0.5
2.9
1.75
0.5
2.6
Maximum Data Rate
1.244
Channel Jitter
Operating Frequency—Bus Enable (fBE)
50
0.2
DIGITAL SWITCH
On Resistance (RON)
10
4.5
8
15
28
5
9
11
18
5
8
40
5.5
40
14
240
11
40
On Resistance Matching (ΔRON)
0.45
4
0.75
4
0.65
4
0.85
4
POWER REQUIREMENTS
Positive Power Supply Voltage (VCC)
Quiescent Power Supply Current (ICC)
2.3
3.6
2.3
3.6
0.001
1
2
1.2
1.3
0.65
analog.com
Unit
Test Conditions/Comments
ns typ
ns min
ns max
ns typ
ns min
ns max
Gbps typ
Gbps max
ps p-p
MHz max
VCC = 3.0 V to 3.6 V, SEL = 0 V
Ω typ
Ω max
Ω typ
Ω max
Ω typ
Ω max
Ω typ
Ω max
Ω typ
Ω max
Ω typ
Ω max
Ω typ
Ω max
Ω typ
Ω max
Ω typ
Ω max
Ω typ
Ω max
Ω typ
Ω max
Ω typ
Ω max
VCC = 3 V, SEL = 3 V, VA = 0 V, IBA = 8 mA
V min
V max
μA typ
μA max
mA typ
mA max
VCC = 2.3 V to 2.7 V, SEL = VCC
VCC = 3.3 V, SEL = 3.3 V; VA/VB = 2 V
VCC = 3.3 V, SEL = 3.3 V; VA/VB = 2 V
VCC = 3 V, SEL = 3 V, VA = 1.7 V, IBA = 8 mA
VCC = 2.3 V, SEL = 2.3 V, VA = 0 V, IBA = 8 mA
VCC = 2.3 V, SEL = 2.3 V, VA = 1 V, IBA = 8 mA
VCC = 3 V, SEL = 0 V, VA = 0 V, IBA = 8 mA
VCC = 3.3 V, SEL = 0 V, VA = 0 V, IBA = 8 mA
VCC = 3 V, SEL= 0 V, VA = 1 V, IBA = 8 mA
VCC = 3.3 V, SEL= 0 V, VA = 1 V, IBA = 8 mA
VCC = 3 V, SEL = 3 V, VA = 0 V, IBA = 8 mA
VCC = 3.3 V, SEL= 0 V, VA = 0 V, IBA = 8 mA
VCC = 3 V, SEL = 3 V, VA = 1 V, IBA = 8 mA
VCC = 3.3 V, SEL= 0 V, VA = 1 V, IBA = 8 mA
Digital Inputs = 0 V or VCC, SEL = VCC
Digital Inputs = 0 V or VCC, SEL = 0 V
Rev. B | 4 of 17
Data Sheet
ADG3246
SPECIFICATIONS
Table 1.
Parameter
Increase in ICC per Input4 (ΔICC)
+25°C
−40°C to
+85°C
130
−40°C to
+105°C
Unit
Test Conditions/Comments
μA max
VCC = 3.6 V, SEL = 3.6 V, BE = 3.0 V
1
The digital switch contributes no propagation delay other than the RC delay of the typical RON of the switch and the load capacitance when driven by an ideal voltage
source. Since the time constant is much smaller than the rise/fall times of typical driving signals, it adds very little propagation delay to the system. Propagation delay
of the digital switch when used in a system is determined by the driving circuit on the driving side of the switch and its interaction with the load on the driven side. This
specification is calculated by using the following equation: tPD = RON × CL, where RON is 4.5 Ω and CL is 50 pF.
2
Propagation delay matching between channels is calculated from the on resistance matching and load capacitance of 50 pF. This specification is calculated by using the
following equation: ∆tPD = ∆RON × CL, where RON is 0.45 Ω and CL is 50 pF.
3
See the Test Circuits section.
4
This current applies to the control pin (BE) only. The A and B ports contribute no significant AC or DC currents as they transition.
analog.com
Rev. B | 5 of 17
Data Sheet
ADG3246
ABSOLUTE MAXIMUM RATINGS
TA = 25 ℃, unless otherwise noted.
ELECTROSTATIC DISCHARGE (ESD) RATINGS
Table 2.
The following ESD information is provided for handling of ESD-sensitive devices in an ESD protected area only.
Parameter
Rating
VCC to GND
Digital Inputs to GND
DC Input Voltage
DC Output Current
Operating Temperature Range
Storage Temperature Range
Junction Temperature
Reflow Soldering Peak Temperature, Pb-Free
–0.5 V to +4.6 V
–0.5 V to +4.6 V
–0.5 V to +4.6 V
25 mA per channel
–40°C to +105°C
–65°C to +150°C
150°C
As per JEDEC J-STD-020
Stresses at or above those listed under Absolute Maximum Ratings
may cause permanent damage to the product. This is a stress
rating only; functional operation of the product at these or any other
conditions above those indicated in the operational section of this
specification is not implied. Operation beyond the maximum operating conditions for extended periods may affect product reliability.
THERMAL RESISTANCE
Human body model (HBM) per ANSI/ESDA/JEDEC JS-001.
ESD RATINGS FOR ADG3246
Table 4. ADG3246, 24-Lead LFCSP
ESD Model
Withstand Threshold (kV)
Class
HBM1
1
Class 1
1
This is the HBM for the input/output port to supplies, the input/output port to
input/output port, and for all other pins.
ESD CAUTION
ESD (electrostatic discharge) sensitive device. Charged devices and circuit boards can discharge without detection. Although
this product features patented or proprietary protection circuitry,
damage may occur on devices subjected to high energy ESD.
Therefore, proper ESD precautions should be taken to avoid
performance degradation or loss of functionality.
Thermal performance is directly linked to printed circuit board
(PCB) design and operating environment. Careful attention to PCB
thermal design is required.
θJA is the natural convection junction-to-ambient thermal resistance
measured in a one cubic foot sealed enclosure.
Table 3. Thermal Resistance
Package Type1
θJA
Unit
CP-24-10
35
℃/W
1
Test Condition 1: Thermal impedance simulated values are based on JEDEC
2S2P thermal test board with four thermal vias. See the JEDEC JESD-51.
analog.com
Rev. B | 6 of 17
Data Sheet
ADG3246
PIN CONFIGURATION AND FUNCTION DESCRIPTIONS
Figure 2. Pin Configuration
Table 5. Pin Function Descriptions
Pin No.
Mnemonic
Description
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
EP
SEL
A5
A6
A7
A8
A9
GND
B9
B8
B7
B6
B5
B4
B3
B2
B1
B0
BE
VCC
A0
A1
A2
A3
A4
EPAD
Level Translation Select (Active Low).
Port A5. This pin can be an input or output.
Port A6. This pin can be an input or output.
Port A7. This pin can be an input or output.
Port A8. This pin can be an input or output.
Port A9. This pin can be an input or output.
Ground (0 V) Reference.
Port B9. This pin can be an input or output.
Port B8. This pin can be an input or output.
Port B7. This pin can be an input or output.
Port B6. This pin can be an input or output.
Port B5. This pin can be an input or output.
Port B4. This pin can be an input or output.
Port B3. This pin can be an input or output.
Port B2. This pin can be an input or output.
Port B1. This pin can be an input or output.
Port B0. This pin can be an input or output.
Bus Enable (Active Low).
Positive Power Supply Potential.
Port A0. This pin can be an input or output.
Port A1. This pin can be an input or output.
Port A2. This pin can be an input or output.
Port A3. This pin can be an input or output.
Port A4. This pin can be an input or output.
Exposed Pad. It is recommended that the exposed pad be thermally connected to a copper plane enhanced thermal
performance. The pad should be grounded as well.
Table 6. Truth Table
BE
SEL1
Function
L
L
H
L
H
X
A = B, 3.3 V to 1.8 V level shifting.
A = B, 3.3 V to 2.5 V/2.5 V to 1.8 V level shifting.
Disconnect.
1
SEL = 0 only when VCC = 3.3 V ± 10%.
analog.com
Rev. B | 7 of 17
Data Sheet
ADG3246
TYPICAL PERFORMANCE CHARACTERISTICS
Figure 3. On Resistance vs. Input Voltage, VCC = 3 V, 3.3 V, and 3.6 V
Figure 4. On Resistance vs. Input Voltage, VCC = 2.3 V, 2.5 V, and 2.7 V
Figure 6. On Resistance vs. Input Voltage for Different Temperatures, VCC =
3.3 V
Figure 7. On Resistance vs. Input Voltage for Different Temperatures, VCC =
2.5 V
Figure 5. On Resistance vs. Input Voltage, SEL = 0 V
Figure 8. Pass Voltage vs. VCC, VCC = 3 V, 3.3 V, and 3.6 V
analog.com
Rev. B | 8 of 17
Data Sheet
ADG3246
TYPICAL PERFORMANCE CHARACTERISTICS
Figure 9. Pass Voltage vs. VCC, VCC = 2.3 V, 2.5 V, and 2.7 V
Figure 12. Output Low Characteristic
Figure 10. Pass Voltage vs. VCC, SEL = 0 V
Figure 13. Output High Characteristic
Figure 11. ICC vs. Enable Frequency
Figure 14. Charge Injection vs. Source Voltage
analog.com
Rev. B | 9 of 17
Data Sheet
ADG3246
TYPICAL PERFORMANCE CHARACTERISTICS
analog.com
Figure 15. Bandwidth vs. Frequency
Figure 18. Enable/Disable Time vs. Temperature, VCC = 3.3 V
Figure 16. Crosstalk vs. Frequency
Figure 19. Enable/Disable Time vs. Temperature, VCC = 2.5 V
Figure 17. Off Isolation vs. Frequency
Figure 20. Jitter vs. Data Rate; PRBS 31
Rev. B | 10 of 17
Data Sheet
ADG3246
TYPICAL PERFORMANCE CHARACTERISTICS
Figure 21. Eye Width vs. Data Rate; PRBS 31
Figure 24. Jitter at 1.244 Gbps, PRBS 31
Figure 22. Eye Pattern; 1.244 Gbps, VCC = 3.3 V, PRBS 31
Figure 23. Eye Pattern; 1 Gbps, VCC = 2.5 V, PRBS 31
analog.com
Rev. B | 11 of 17
Data Sheet
ADG3246
TEST CIRCUITS
For the following load circuit and waveforms, the notation that is used is VIN and VOUT, where VIN = VA and VOUT = VB or VIN = VB and VOUT =
VA.
For VCC = 3.3 V ± 0.3 V (SEL = VCC), RL = 500 Ω, VA = 300 mV, CL = 50 pF, and VT = 1.5 V.
For VCC = 2.5 V ± 0.2 V (SEL = VCC), RL = 500 Ω, VA = 150 mV, CL = 30 pF, and VT = 0.9 V.
Figure 27. Enable and Disable Time
Figure 25. Load Circuit
Table 7. Switch Position
Test
S1
tPLZ, tPZL
2 × VCC
tPHZ, tPZH
GND
Figure 26. Propagation Delay
analog.com
Rev. B | 12 of 17
Data Sheet
ADG3246
TERMINOLOGY
VCC
ΔICC
Positive Power Supply Voltage.
Extra power supply current component for the BE control input
when the input is not driven at the supplies.
GND
Ground (0 V) Reference.
tPLH, tPHL
Minimum Input Voltage for Logic 1.
Data Propagation Delay through the Switch in the ON State. Propagation delay is related to the RC time constant RON × CL, where
CLL is the load capacitance.
VINL
tPZH, tPZL
Minimum Input Voltage for Logic 0.
II
Bus Enable Times. These are times taken to cross the VT voltage
at the switch output when the switch turns on in response to the
control signal, BE.
Input Leakage Current at the Control Inputs.
tPHZ, tPLZ
IOZ
Bus Disable Times. This is the time taken to place the switch in
the high impedance OFF state in response to the control signal. It
is measured as the time taken for the output voltage to change by
V∆ from the original quiescent level, with reference to the logic level
transition at the control input. (Refer to Figure 27 for enable and
disable times.)
VINH
OFF State Leakage Current. It is the maximum leakage current at
the switch pin in the OFF state.
IOL
ON State Leakage Current. It is the maximum leakage current at
the switch pin in the ON state.
Max Data Rate
VP
Maximum Rate at which Data Can be Passed through the Switch.
Maximum Pass Voltage. The maximum pass voltage relates to the
clipped output voltage of an NMOS device when the switch input
voltage is equal to the supply voltage.
Channel Jitter
RON
Ohmic Resistance Offered by a Switch in the ON State. It is
measured at a given voltage by forcing a specified amount of
current through the switch.
Peak-to-Peak Value of the Sum of the Deterministic and Random
Jitter of the Switch Channel.
fBE
Operating Frequency of Bus Enable. This is the maximum frequency at which bus enable (BE) can be toggled.
ΔRON
On Resistance Match between Any Two Channels, that is, RON Max
– RON Min.
CX OFF
OFF Switch Capacitance.
CX ON
ON Switch Capacitance.
CIN
Control Input Capacitance. This consists of BE and SEL.
ICC
Quiescent Power Supply Current. It is measured when all control
inputs are at a logic HIGH or LOW level and the switches are OFF.
analog.com
Rev. B | 13 of 17
Data Sheet
ADG3246
APPLICATIONS INFORMATION
BUS SWITCH APPLICATIONS
Bus switches can used to provide an ideal solution for interfacing
between mixed voltage systems. The ADG3246 is suitable for
applications where voltage translation from 3.3 V technology to a
lower voltage technology is needed. This device can translate from
3.3 V to 1.8 V, from 2.5 V to 1.8 V, or from 3.3 V directly to 2.5 V.
Figure 28 shows a block diagram of a typical application in which
a user needs to interface between a 3.3 V ADC and a 2.5 V microprocessor. The microprocessor may not have 3.3 V tolerant inputs,
therefore placing the ADG3246 between the two devices allows the
devices to communicate easily. The bus switch directly connects
the two blocks, thus introducing minimal propagation delay, timing
skew, or noise.
Figure 30. 3.3 V to 2.5 V Voltage Translation, SEL = VCC
This device can be used for translation from 2.5 V to 3.3 V devices
and also between two 3.3 V devices.
2.5 V to 1.8 V Translation
Figure 28. Level Translation Between a 3.3 V ADC and a 2.5 V Microprocessor
When VCC is 2.5 V (SEL = VCC) and the input signal range is 0 V
to VCC, the maximum output signal will, as before, be clamped to
within a voltage threshold below the VCC supply.
Mixed Voltage Operation, Level Translation
3.3 V to 2.5 V Translation
When VCC is 3.3 V (SEL = VCC) and the input signal range is 0 V to
VCC, the maximum output signal will be clamped to within a voltage
threshold below the VCC supply.
Figure 31. 2.5 V to 1.8 V Voltage Translation, SEL = VCC
In this case, the output is limited to approximately 1.8 V, as shown
in Figure 32.
Figure 29. 3.3 V to 2.5 V Voltage Translation, SEL = VCC
In this case, the output will be limited to 2.5 V, as shown in Figure
30.
Figure 32. 2.5 V to 1.8 V Voltage Translation, SEL = VCC
analog.com
Rev. B | 14 of 17
Data Sheet
ADG3246
APPLICATIONS INFORMATION
3.3 V to 1.8 V Translation
The ADG3246 offers the option of interfacing between a 3.3 V
device and a 1.8 V device. This is possible through use of the SEL
pin.
SEL pin: An active low control pin. SEL activates internal circuitry in
the ADG3246 that allows voltage translation between 3.3 V devices
and 1.8 V devices.
Figure 35. Location of Bus Switch in a Bus Isolation Application
Hot Plug and Hot Swap Isolation
The ADG3246 is suitable for hot swap and hot plug applications.
The output signal of the ADG3246 is limited to a voltage that is
below the VCC supply, as shown in Figure 30, Figure 32, and
Figure 34. Therefore the switch acts like a buffer to take the impact
from hot insertion, protecting vital and expensive chipsets from
damage.
Figure 33. 3.3 V to 1.8 V Voltage Translation, SEL = 0 V
When VCC is 3.3 V and the input signal range is 0 V to VCC, the
maximum output signal will be clamped to 1.8 V, as shown in Figure
34. To do this, the SEL pin must be tied to Logic 0. If SEL is
unused, it should be tied directly to VCC.
In hot-plug applications, the system cannot be shut down when
new hardware is being added. To overcome this, a bus switch can
be positioned on the backplane between the bus devices and the
hot plug connectors. The bus switch is turned off during hot plug.
Figure 36 shows a typical example of this type of application.
Figure 36. ADG3246 in a Hot Plug Application
Figure 34. 3.3 V to 1.8 V Voltage Translation, SEL = 0 V
Bus Isolation
A common requirement of bus architectures is low capacitance
loading of the bus. Such systems require bus bridge devices
that extend the number of loads on the bus without exceeding
the specifications. Because the ADG3246 is designed specifically
for applications that do not need drive yet require simple logic
functions, it solves this requirement. The device isolates access to
the bus, thus minimizing capacitance loading.
analog.com
There are many systems that require the ability to handle hot swapping, such as docking stations, PCI boards for servers, and line
cards for telecommunications switches. If the bus can be isolated
prior to insertion or removal, then there is more control over the
hot swap event. This isolation can be achieved using a bus switch.
The bus switches are positioned on the hot swap card between the
connector and the devices. During hot swap, the ground pin of the
hot swap card must connect to the ground pin of the back plane
before any other signal or power pins.
Analog Switching
Bus switches can be used in many analog switching applications,
for example, video graphics. Bus switches can have lower on
resistance, smaller ON and OFF channel capacitance and thus
improved frequency performance than their analog counterparts.
The bus switch channel itself consisting solely of an NMOS switch
limits the operating voltage (see Figure 3 for a typical plot), but in
many cases, this does not present an issue.
Rev. B | 15 of 17
Data Sheet
ADG3246
APPLICATIONS INFORMATION
High Impedance During Power-Up and PowerDown
To ensure the high impedance state during power-up or powerdown, BE should be tied to VCC through a pull-up resistor; the
minimum value of the resistor is determined by the current-sinking
capability of the driver.
PACKAGE AND PINOUT
The ADG3246 is packaged in a tiny 24-lead LFCSP package. The
area of the LFCSP option is 16 mm2. This makes the LFCSP option
an excellent choice for space-constrained applications.
analog.com
Rev. B | 16 of 17
Data Sheet
ADG3246
OUTLINE DIMENSIONS
Figure 37. 24-Lead Lead Frame Chip Scale Package (LFCSP)
4 mm × 4 mm Body and 0.75 mm Package Height
(CP-24-10)
Dimension shown in millimeters
Updated: April 30, 2022
ORDERING GUIDE
Model1
Temperature Range
Package Description
Packing Quantity
Package
Option
ADG3246BCPZ
ADG3246BCPZ-REEL7
-40°C to +105°C
-40°C to +105°C
24-Lead LFCSP (4mm x 4mm x 0.75mm w/ EP)
24-Lead LFCSP (4mm x 4mm x 0.75mm w/ EP)
Reel, 1500
CP-24-10
CP-24-10
1
Z = RoHS Compliant Part.
©2016-2022 Analog Devices, Inc. All rights reserved. Trademarks and
registered trademarks are the property of their respective owners.
One Analog Way, Wilmington, MA 01887-2356, U.S.A.
Rev. B | 17 of 17
工商网监
湘ICP备2023018690号
