ADG3249BRJ-REEL7

2.5 V/3.3 V, 2:1 Multiplexer/ Demultiplexer Bus Switch ADG3249 FEATURES 225 ps Propagation Delay through the Switch 4.5
Switch Connection between Ports Data Rate 1.244 Gbps 2.5 V/3.3 V Supply Operation Selectable Level Shifting/Translation Level Translation 3.3 V to 2.5 V 3.3 V to 1.8 V 2.5 V to 1.8 V Small Signal Bandwidth 610 MHz 8-Lead SOT-23 Package FUNCTIONAL BLOCK DIAGRAM ADG3249 A0 B A1 CONTROL LOGIC IN EN APPLICATIONS 3.3 V to 1.8 V Voltage Translation 3.3 V to 2.5 V Voltage Translation 2.5 V to 1.8 V Voltage Translation Docking Stations Memory Switching Analog Switch Applications GENERAL DESCRIPTION PRODUCT HIGHLIGHTS The ADG3249 is a 2.5 V or 3.3 V, high performance 2:1 multiplexer/demultiplexer bus switch. It is designed on a low voltage CMOS process, which provides low power dissipation yet gives high switching speed and very low on resistance. This allows the input to be connected to the output without additional propagation delay or generating additional ground bounce noise. 1. 2. 3. 4. 3.3 V or 2.5 V supply operation. Extremely low propagation delay through switch. 4.5 Ω switches connect inputs to outputs. Tiny SOT-23 package. Each switch of the ADG3249 conducts equally well in both directions when on. The ADG3249 exhibits break-before-make switching action, preventing momentary shorting when switching channels. This device is ideal for applications requiring level translation. When operated from a 3.3 V supply, level translation from 3.3 V inputs to 2.5 V outputs is allowed. Similarly, if the device is operated from 2.5 V supply and 2.5 V inputs are applied, the device will translate the outputs to 1.8 V. In addition, a level translating pin (SEL) is included. When SEL is low, VCC is reduced internally, allowing for level translating between 3.3 V inputs and 1.8 V outputs. The ADG3249 is available in a tiny 8-lead SOT-23 package. REV. 0 Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective companies. One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. Tel: 781/329-4700 www.analog.com Fax: 781/326-8703 © 2003 Analog Devices, Inc. All rights reserved. ADG3249* Product Page Quick Links Last Content Update: 11/01/2016 Comparable Parts Design Resources View a parametric search of comparable parts • • • • Documentation Data Sheet • ADG3249: 2.5 V/3.3 V, 2:1 Multiplexer/Demultiplexer Bus Switch Data Sheet Reference Materials Product Selection Guide • Switches and Multiplexers Product Selection Guide Technical Articles • CMOS Switches Offer High Performance in Low Power, Wideband Applications • Data-acquisition system uses fault protection ADG3249 Material Declaration PCN-PDN Information Quality And Reliability Symbols and Footprints Discussions View all ADG3249 EngineerZone Discussions Sample and Buy Visit the product page to see pricing options Technical Support Submit a technical question or find your regional support number * This page was dynamically generated by Analog Devices, Inc. and inserted into this data sheet. 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This content may be frequently modified. ADG3249–SPECIFICATIONS1 Parameter Symbol DC ELECTRICAL CHARACTERISTICS Input High Voltage VINH VINH Input Low Voltage VINL VINL Input Leakage Current II OFF State Leakage Current IOZ ON State Leakage Current Maximum Pass Voltage VP CAPACITANCE3 A Port Off Capacitance B Port Off Capacitance A, B Port On Capacitance Control Input Capacitance SWITCHING CHARACTERISTICS3 Propagation Delay A to B or B to A, tPD4 Propagation Delay Matching5 Bus Enable Time EN to A or B6 Bus Disable Time EN to A or B6 Bus Enable Time EN to A or B6 Bus Disable Time EN to A or B6 Bus Enable Time EN to A or B6 Bus Disable Time EN to A or B6 Break-before-Make Time Transition Time On Resistance Matching POWER REQUIREMENTS VCC Quiescent Power Supply Current Increase in ICC per Input7 Conditions Min VCC = 2.7 V to 3.6 V VCC = 2.3 V to 2.7 V VCC = 2.7 V to 3.6 V VCC = 2.3 V to 2.7 V 2.0 1.7 0 ≤ A, B ≤ VCC 0 ≤ A, B ≤ VCC VA/VB = VCC = SEL = 3.3 V, IO = –5 µA VA/VB = VCC = SEL = 2.5 V, IO= –5 µA VA/VB = VCC = 3.3 V, SEL = 0 V, IO = –5 µA CA OFF CB OFF CA, CB ON CIN, CSEL CEN f = 1 MHz; EN = VCC f = 1 MHz; EN = VCC f = 1 MHz f = 1 MHz f = 1 MHz tPHL, tPLH CL = 50 pF, VCC = SEL = 3 V tPZH, tPZL tPHZ, tPLZ tPZH, tPZL tPHZ, tPLZ tPZH, tPZL tPHZ, tPLZ tBBM tTRANS VCC = 3.0 V to 3.6 V; SEL = VCC VCC = 3.0 V to 3.6 V; SEL = VCC VCC = 3.0 V to 3.6 V; SEL = 0 V VCC = 3.0 V to 3.6 V; SEL = 0 V VCC = 2.3 V to 2.7 V; SEL = VCC VCC = 2.3 V to 2.7 V; SEL = VCC RL = 510 Ω, CL = 50 pF RL = 510 Ω, CL = 50 pF; SEL = VCC RL = 510 Ω, CL = 50 pF; SEL = 0 V VCC = SEL = 3.3 V; VA/VB = 2 V VCC = SEL = 3.3 V; VA/VB = 2 V RON VCC = 3 V, SEL = VCC, VA = 0 V, IBA = 8 mA VCC = 3 V, SEL = VCC, VA = 1.7 V, IBA = 8 mA VCC = 2.3 V, SEL = VCC, VA = 0 V, IBA = 8 mA VCC = 2.3 V, SEL = VCC, VA = 1 V, IBA = 8 mA VCC = 3 V, SEL = 0 V VA = 0 V, IBA = 8 mA VCC = 3 V, SEL = 0 V, VA = 1 V, IBA = 8 mA VCC = 3 V, SEL = VCC, VA = 0 V, IA = 8 mA VCC = 3 V, SEL = 0 V, VA = 0 V, IA = 8 mA Maximum Data Rate Channel Jitter DIGITAL SWITCH On Resistance (VCC = 2.3 V to 3.6 V, GND = 0 V, all specifications TMIN to TMAX, unless otherwise noted.) ⌬RON 2.0 1.5 1.5 B Version Typ2 Max ± 0.01 ± 0.01 ± 0.01 2.5 1.8 1.8 3.5 4.5 8.5 4 6.5 1 1 1 1 1 1 5 3.5 5.5 3.2 4.5 3.5 4 10 16 15 1.244 45 4.5 12 5 9 5 12 0.1 0.1 2.3 ICC ⌬ICC Digital Inputs = 0 V or VCC; SEL = VCC Digital Inputs = 0 V or VCC; SEL = 0 V VCC = 3.6 V, EN = 3.0 V; SEL = VCC; IN = VCC 0.8 0.7 ±1 ±1 ±1 2.9 2.1 2.1 0.01 0.1 0.15 Unit V V V V µA µA µA V V V pF pF pF pF pF 0.225 5 4.8 8.2 4.5 7.7 4.6 5.8 29 22 ns ps ns ns ns ns ns ns ns ns ns Gbps ps p-p 0.5 0.5 Ω Ω Ω Ω Ω Ω Ω Ω 3.6 1 0.2 8 V µA mA µA 8 28 9 18 8 NOTES 1 Temperature range is as follows: B Version: –40°C to +85°C. 2 Typical values are at 25°C, unless otherwise stated. 3 Guaranteed by design, not subject to production test. 4 The digital switch contributes no propagation delay other than the RC delay of the typical R ON of the switch and the load capacitance when driven by an ideal voltage source. Since the time constant is much smaller than the rise/fall times of typical driving signals, it adds very little propagation delay to the system. Propagation delay of the digital switch when used in a system is determined by the driving circuit on the driving side of the switch and its interaction with the load on the driven side. 5 Propagation delay matching between channels is calculated from the on resistance matching and load capacitance of 50 pF. 6 See Timing Measurement Information section. 7 This current applies to the control pin EN only. The A and B ports contribute no significant ac or dc currents as they transition. Specifications subject to change without notice. –2– REV. 0 ADG3249 ABSOLUTE MAXIMUM RATINGS* PIN CONFIGURATION 8-Lead SOT-23 (TA = 25°C, unless otherwise noted.) VCC to GND . . . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to +4.6 V Digital Inputs to GND . . . . . . . . . . . . . . . . . –0.5 V to +4.6 V DC Input Voltage . . . . . . . . . . . . . . . . . . . . . –0.5 V to +4.6 V DC Output Current . . . . . . . . . . . . . . . . . 25 mA per Channel Operating Temperature Range Industrial (B Version) . . . . . . . . . . . . . . . . . –40°C to +85°C Storage Temperature Range . . . . . . . . . . . . –65°C to +150°C Junction Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . 150°C ␪JA Thermal Impedance . . . . . . . . . . . . . . . . . . . . . . 206°C/W Lead Temperature, Soldering (10 sec) . . . . . . . . . . . . . 300°C IR Reflow, Peak Temperature (