ADG333

a FEATURES 44 V Supply Maximum Ratings VSS to VDD Analog Signal Range Low On Resistance (45 max) Low ∆R ON (5 max) Low RON Match (4 max) Low Power Dissipation Fast Switching Times tON < 175 ns t OFF < 145 ns Low Leakage Currents (5 nA max) Low Charge Injection (10 pC max) Break-Before-Make Switching Action APPLICATIONS Audio and Video Switching Battery Powered Systems Test Equipment Communication Systems S1A D1 S1B IN1 Quad SPDT Switch ADG333A FUNCTIONAL BLOCK DIAGRAM S4A D2 S4B IN4 ADG333A IN2 S2B D2 S2A IN3 S3B D3 S3A SWITCHES SHOWN FOR A LOGIC “1” INPUT GENERAL DESCRIPTION PRODUCT HIGHLIGHTS The ADG333A is a monolithic CMOS device comprising four independently selectable SPDT switches. It is designed on an LC2MOS process which provides low power dissipation yet achieves a high switching speed and a low on resistance. The on resistance profile is very flat over the full analog input range ensuring good linearity and low distortion when switching audio signals. High switching speed also makes the part suitable for video signal switching. CMOS construction ensures ultralow power dissipation making the part ideally suited for portable, battery powered instruments. When they are ON, each switch conducts equally well in both directions and has an input signal range which extends to the power supplies. In the OFF condition, signal levels up to the supplies are blocked. All switches exhibit break-before-make switching action for use in multiplexer applications. Inherent in the design is low charge injection for minimum transients when switching the digital inputs. 1. Extended Signal Range The ADG333A is fabricated on an enhanced LC2MOS process, giving an increased signal range which extends to the supply rails. 2. Low Power Dissipation 3. Low RON 4. Single Supply Operation For applications where the analog signal is unipolar, the ADG333A can be operated from a single rail power supply. The part is fully specified with a single +12 V supply. REV. 0 Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. © Analog Devices, Inc., 1995 One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. Tel: 617/329-4700 Fax: 617/326-8703 ADG333A–SPECIFICATIONS1 DUAL SUPPLY Parameter ANALOG SWITCH Analog Signal Range RON ∆RON RON Match LEAKAGE CURRENTS Source OFF Leakage IS (OFF) Channel ON Leakage ID, IS (ON) DIGITAL INPUTS Input High Voltage, VINH Input Low Voltage, VINL Input Current IINL or IINH DYNAMIC CHARACTERISTICS2 tON tOFF Break-Before-Make Delay, tOPEN Charge Injection OFF Isolation Channel-to-Channel Crosstalk CS (OFF) CD, CS (ON) POWER REQUIREMENTS IDD ISS VDD/VSS NOTES 1 Temperature range is as follows: B Version: –40 °C to +85°C. 2 Guaranteed by design, not subject to production test. Specifications subject to change without notice. (VDD = +15 V, VSS = –15 V, GND = 0 V, unless otherwise noted) +25 C –40 C to +85 C VSS to VDD 20 45 45 5 4 Units V Ω typ Ω max Ω max Ω max nA typ nA max nA typ nA max V min V max µA typ µA max ns typ ns max ns typ ns max ns min pC typ pC max dB typ dB typ pF typ pF typ mA typ Digital Inputs = 0 V or 5 V mA max µA typ µA max V min/V max |VDD| = |VSS| VIN = 0 V or VDD Test Conditions/Comments VD = ± 10 V, IS = –1 mA VD = ± 5 V, IS = –10 mA VD = ± 10 V, IS = –10 mA VDD = +16.5 V, VSS = –16.5 V VD = ± 15.5 V, VS = +15.5 V Test Circuit 2 VS = VD = ± 15.5 V Test Circuit 3 ± 0.1 ± 0.25 ± 0.1 ± 0.4 ±3 ±5 2.4 0.8 ± 0.005 ± 0.5 90 175 80 145 10 2 10 72 85 5 20 0.05 0.25 0.01 1 RL = 300 Ω, CL = 35 pF; VS = ± 10 V; Test Circuit 4 RL = 300 Ω, CL = 35 pF; VS = ± 10 V; Test Circuit 4 RL = 300 Ω, CL = 35 pF; VS = +5 V; Test Circuit 5 VD = 0 V, RD = 0 Ω, CL = 10 nF; VDD = +15 V, VSS = –15 V; Test Circuit 6 RL = 75 Ω, CL = 5 pF, f = 1 MHz; VS = 2.3 V rms, Test Circuit 7 RL = 75 Ω, CL = 5 pF, f = 1 MHz; VS = 2.3 V rms, Test Circuit 8 0.35 5 ± 3/± 20 –2– REV. 0 ADG333A SINGLE SUPPLY Parameter ANALOG SWITCH Analog Signal Range RON LEAKAGE CURRENTS Source OFF Leakage IS (OFF) Channel ON Leakage ID, IS (ON) DIGITAL INPUTS Input High Voltage, VINH Input Low Voltage, VINL Input Current IINL or IINH DYNAMIC CHARACTERISTICS2 tON tOFF Break-Before-Make Delay, tOPEN Charge Injection OFF Isolation Channel-to-Channel Crosstalk CS (OFF) CD, CS (ON) POWER REQUIREMENTS IDD VDD NOTES 1 Temperature range is as follows: B Version: –40 °C to +85°C. 2 Guaranteed by design, not subject to production test. Specifications subject to change without notice. (VDD = +12 V, VSS = 0 V 10%, GND = 0 V, unless otherwise noted) –40 C to +85 C 0 to VDD Units V Ω typ Ω max nA typ nA max nA typ nA max V min V max µA typ µA max ns typ ns max ns typ ns max ns min ns min pC typ dB typ dB typ pF typ pF typ VDD = +13.5 V mA typ Digital Inputs = 0 V or 5 V mA max V min/V max VIN = 0 V or VDD Test Conditions/Comments +25 C 35 75 ± 0.1 ± 0.25 ± 0.1 ± 0.4 VD = +1 V, +10 V, IS = –1 mA VDD = +13.2 V VD = 12.2 V/1 V, VS = 1 V/12.2 V Test Circuit 2 VS = VD = 12.2 V/1 V Test Circuit 3 ±3 ±5 2.4 0.8 ± 0.005 ± 0.5 110 200 100 180 10 5 72 85 5 20 0.05 0.25 RL = 300 Ω, CL = 35 pF; VS = +8 V; Test Circuit 4 RL = 300 Ω, CL = 35 pF; VS = +8 V; Test Circuit 4 RL = 300 Ω , CL = 35 pF; VS = +5 V; Test Circuit 5 VD = 6 V, RD = 0 Ω, CL = 10 nF; VDD = +12 V, VSS = –0 V; Test Circuit 6 RL = 75 Ω, CL = 5 pF, f = 1 MHz; VS = 1.15 V rms, Test Circuit 7 RL = 75 Ω, CL = 5 pF, f = 1 MHz; VS = 1.15 V rms, Test Circuit 8 0.35 +3/+30 REV. 0 –3– ADG333A ABSOLUTE MAXIMUM RATINGS 1 (TA = +25°C unless otherwise noted) VDD to VSS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . +44 V VDD to GND . . . . . . . . . . . . . . . . . . . . . . . . . –0.3 V to +30 V VSS to GND . . . . . . . . . . . . . . . . . . . . . . . . . . +0.3 V to –30 V Analog, Digital Inputs2 . . . . . . . . . . . . VSS – 2 V to VDD + 2 V . . . . . . . . . . . . . . . . . . . . . . or 20 mA, Whichever Occurs First Continuous Current, S or D . . . . . . . . . . . . . . . . . . . . 20 mA Peak Current, S or D . . . . . . . . . . . . . . . . . . . . . . . . . . 40 mA (Pulsed at 1 ms, 10% Duty Cycle Max) Operating Temperature Range Industrial (B Version) . . . . . . . . . . . . . . . . –40°C to +85°C Storage Temperature Range . . . . . . . . . . . . –65°C to +125°C Junction Temperature . . . . . . . . . . . . . . . . . . . . . . . . +150°C Plastic Package θJA, Thermal Impedance . . . . . . . . . . . . . . . . . . . . 103°C/W Lead Temperature, Soldering (10 sec) . . . . . . . . . . +260°C SOIC Package θJA, Thermal Impedance . . . . . . . . . . . . . . . . . . . . . 74°C/W Lead Temperature, Soldering Vapor Phase (60 sec) . . . . . . . . . . . . . . . . . . . . . . +215°C Infrared (15 sec) . . . . . . . . . . . . . . . . . . . . . . . . . . +220°C SSOP Package θJA, Thermal Impedance . . . . . . . . . . . . . . . . . . . . 130°C/W Lead Temperature, Soldering Vapor Phase (60 sec) . . . . . . . . . . . . . . . . . . . . . . +215°C Infrared (15 sec) . . . . . . . . . . . . . . . . . . . . . . . . . . +220°C NOTES 1 Stresses above those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those listed in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. Only one absolute maximum rating may be applied at any one time. 2 Overvoltages at IN, S or D will be clamped by internal diodes. Current should be limited to the maximum ratings given. CAUTION ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on the human body and test equipment and can discharge without detection. Although the ADG333A features proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high energy electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance degradation or loss of functionality. WARNING! ESD SENSITIVE DEVICE ORDERING GUIDE Table I. Truth Table Model ADG333ABN ADG333ABR ADG333ABRS Temperature Range –40°C to +85°C –40°C to +85°C –40°C to +85°C Package Option* N-20 R-20 RS-20 Logic 0 1 Switch A OFF ON Switch B ON OFF *N = Plastic DIP, R = Small Outline IC (SOIC). RS = Shrink Small Outline Package (SSOP). –4– REV. 0 ADG333A TERMINOLOGY S D IN RON ∆RON RON Match IS (OFF) ID (OFF) ID, IS (ON) V D ( VS ) CS (OFF) CD (OFF) Source Terminal. May be an input or output. Drain Terminal. May be an input or output. Logic Control Input. Ohmic resistance between D and S. RON variation due to a change in the analog input voltage with a constant load current. Difference between the RON of any two channels. Source leakage current with the switch “OFF.” Drain leakage current with the switch “OFF.” Channel leakage current with the switch “ON.” Analog voltage on terminals D, S. “OFF” Switch Source Capacitance. “OFF” Switch Drain Capacitance. CD, CS (ON) tON “ON” Switch Capacitance. Delay between applying the digital control input and the output switching on. tOFF Delay between applying the digital control input and the output switching off. tOPEN Break Before Make delay when switches are configured as a multiplexer. VINL Maximum input voltage for logic “0.” VINH Minimum input voltage for logic “1.” Input current of the digital input. IINL (IINH) Crosstalk A measure of unwanted signal which is coupled through from one channel to another as a result of parasitic capacitance. Off Isolation A measure of unwanted signal coupling through an “OFF” switch. Charge Injection A measure of the glitch impulse transferred from the digital input to the analog output during switching. PIN CONFIGURATION DIP/SOIC/SSOP IN1 1 S1A 2 D1 3 S1B 4 VSS 5 GND 6 S2B 7 D2 8 S2A 9 IN2 10 20 IN4 19 S4A 18 D4 17 S4B ADG333A 16 VDD TOP VIEW 15 NC (Not to Scale) 14 S3B 13 D3 12 S3A 11 IN3 NC = NO CONNECT REV. 0 –5– ADG333A–Typical Performance Graphs 60 TA = +25°C 50 VDD = +5V VSS = –5V 40 RON – Ω 50 60 VDD = +15V VSS = 0V 20 CL = 10nF 15 10 RON – Ω 40 +125°C +85°C 5 Q – pC 0 –5 30 VDD = +10V VSS = –10V 30 VDD = +16.5V VSS = –16.5V VDD = +12V VSS = –0V 20 20 –40°C +25°C –10 –15 VDD = +15V VSS = –15V 10 10 –15 –10 –5 0 5 VD, VS – Volts 10 15 0 3 6 9 VD, VS – Volts 12 15 –20 –15 –10 –5 0 5 VS – Volts 10 15 Figure 1. RON as a Function of VD (VS): Dual Supply Figure 4. RON as a Function of VD (VS) for Different Temperatures: Single Supply Figure 7. Charge Injection as a Function of VS 100 TA = +25°C 90 80 RON – Ω 70 60 50 40 30 20 VDD = +10V VSS = 0V VDD = +15V VSS = 0V LEAKAGE CURRENT – nA 0.004 0.002 0 –0.002 –0.004 –0.006 –0.008 –0.01 –15 ID (ON) VDD = +16.5V VSS = –16.5V TA = +25°C 160 VD = +2V VS = –2V IS (OFF) SWITCHING TIME – ns 10 15 VDD = +5V VSS = 0V 140 120 IS (ON) 100 80 0 3 6 9 VD, VS – Volts 12 15 –10 –5 0 5 VD, VS – Volts 60 0 5 10 VDD – Volts 15 20 Figure 2. RON as a Function of VD (VS): Single Power Supply Figure 5. Leakage Currents as a Function of VD (VS): Dual Supply Figure 8. Switching Time as a Function of VDD 45 40 35 VDD = +15V VSS = –15V 0.001 IS (OFF) LEAKAGE CURRENT – nA 1 VDD = +16.5V VSS = –16.5V TA = +25°C 0 VDD = +16.5V VSS = –16.5V TA = +25°C 0.8 RON – Ω 30 25 20 15 10 –15 +85°C –0.002 ID (ON) IS (ON) IDD – mA +125°C –0.001 0.6 0.4 –0.003 0.2 –40°C +25°C –0.004 –10 –5 0 5 VD, VS – Volts 10 15 0 0 3 6 VD, VS – Volts 9 12 0 400 600 800 200 SWITCHING FREQUENCY – kHz 1000 Figure 3. RON as a Function of VD (VS) for Different Temperatures: Dual Supply Figure 6. Leakage Currents as a Function of VD (VS): Single Supply Figure 9. IDD as a Function of Switching Frequency –6– REV. 0 ADG333A IDS V1 IS (OFF) ID (ON) S RON = V1/IDS D VD VS A S D VD NC S D A VD Test Circuit 1. On Resistance VDD 0.1µF Test Circuit 2. Off Leakage Test Circuit 3. On Leakage VS –10V +10V IN SB SA VDD D RL 300Ω VOUT CL 35pF 3V VIN 0V 50% 50% +10V VS 0V –10V tOFF 50% 50% GND VSS tON 0.1µF VSS Test Circuit 4. Switching Times VDD 0.1µF VS IN SB SA VDD D VOUT RL 300Ω CL 35pF 3V VIN 0V VS VOUT 50% 50% GND VSS 0.1µF VSS tOPEN Test Circuit 5. Break-Before-Make Delay, tOPEN VDD VDD RD VD IN D SA CL 10nF 0V VOUT 3V VIN 0V VOUT ∆VOUT GND VSS QINJ = CL x ∆VOUT VSS Test Circuit 6. Charge Injection 0.1µF VDD VDD 0.1µF VDD S D 75Ω VDD VS VOUT S VIN VS GND VSS D RL 75Ω VIN1 S VOUT RL 75Ω GND VSS D VIN2 NC 0.1µF VSS 0.1µF VSS CHANNEL TO CHANNEL CROSSTALK 20 x LOG |VS / VOUT | Test Circuit 7. Off Isolation Test Circuit 8. Channel-to-Channel Crosstalk REV. 0 –7– ADG333A APPLICATIONS INFORMATION ADG333A Supply Voltages The ADG333A can operate off a dual or signal supply. VSS should be connected to GND when operating with a single supply. When using a dual supply the ADG333A can also operate with unbalanced supplies, for example VDD = 20 V and VSS = –5 V. The only restrictions are that VDD to GND must not exceed 30 V, VSS to GND must not drop below –30 V and VDD to VSS must not exceed +44 V. It is important to remember that the ADG333A supply voltage directly affects the input signal range, the switch ON resistance and the switching times of the part. The effects of the power supplies on these characteristics can be clearly seen from the characteristic curves in this data sheet. Power Supply Sequencing OUTLINE DIMENSIONS Dimensions shown in inches and (mm). 20-Pin Plastic DIP (N-20) 1.060 (26.90) 0.925 (23.50) 20 1 11 10 20-Pin SOIC (R-20) 0.5118 (13.00) 0.4961 (12.60) 0.4193 (10.65) 0.325 (8.25) 0.060 (1.52) PIN 1 0.210 (5.33) MAX 0.160 (4.06) 0.115 (2.93) 0.022 (0.558) 0.014 (0.356) 0.100 (2.54) BSC 0.015 (0.38) 0.300 (7.62) 0.195 (4.95) 0.115 (2.93) 1 10 0.130 (3.30) MIN 0.070 (1.77) SEATING PLANE 0.045 (1.15) 0.015 (0.381) 0.008 (0.204) PIN 1 0.1043 (2.65) 0.0926 (2.35) 0.3937 (10.00) 0.280 (7.11) 0.240 (6.10) 20 11 0.2992 (7.60) 0.2914 (7.40) 0.0291 (0.74) 0.0098 (0.25) x 45° 0.0118 (0.30) 0.0040 (0.10) 8° 0.0500 0.0192 (0.49) 0° (1.27) 0.0138 (0.35) SEATING 0.0125 (0.32) PLANE 0.0091 (0.23) BSC 0.0500 (1.27) 0.0157 (0.40) 20-Pin SSOP (RS-20) 0.295 (7.50) 0.271 (6.90) 20 11 0.311 (7.9) 0.301 (7.64) 0.212 (5.38) 0.205 (5.21) 1 10 0.078 (1.98) PIN 1 0.068 (1.73) 0.07 (1.78) 0.066 (1.67) 0.008 (0.203) 0.002 (0.050) 0.0256 (0.65) BSC SEATING 0.009 (0.229) PLANE 0.005 (0.127) 8° 0° 0.037 (0.94) 0.022 (0.559) LEADS WILL BE EITHER TIN PLATED OR SOLDIER DIPPED IN ACCORDANCE WITH MIL-M-38510 REQUIREMENTS –8– REV. 0 PRINTED IN U.S.A. C2076–18–10/95 When using CMOS devices care must be taken to ensure correct power-supply sequencing. Incorrect power-supply sequencing can result in the device being subjected to stresses beyond those maximum ratings listed in the data sheet. This is also true for the ADG333A. Always sequence VDD on first followed by VSS and the logic signals. An external signal within the maximum specified ratings can then be safely presented to the source or drain of the switch