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ADG333ABR

ADG333ABR

  • 厂商:

    AD(亚德诺)

  • 封装:

    20-SOIC(0.295",7.50mm宽)

  • 描述:

    QUAD SPDT SWITCH

  • 数据手册
  • 价格&库存
ADG333ABR 数据手册
Quad SPDT Switch ADG333A Data Sheet FEATURES FUNCTIONAL BLOCK DIAGRAM 44 V supply maximum ratings VSS to VDD analog signal range Low on resistance (45 Ω max) Low ∆RON (5 Ω max) Low RON match (4 Ω max) Low power dissipation Fast switching times tON < 175 ns tOFF < 145 ns Low leakage currents (5 nA max) Low charge injection (10 pC max) Break-before-make switching action S4A S1A D4 D1 S1B S4B IN1 IN4 ADG333A IN2 IN3 S2B S3B D2 S3A SWITCHES SHOWN FOR A LOGIC 1 INPUT 01212-001 D3 S2A Figure 1. APPLICATIONS Audio and video switching Battery-powered systems Test equipment Communication systems GENERAL DESCRIPTION PRODUCT HIGHLIGHTS The ADG333A is a monolithic complementary metal-oxide semiconductor (CMOS) device comprising four independently selectable single-pole, double-throw (SPDT) switches. It is designed on a linear compatible CMOS (LC2MOS) process, which provides low power dissipation yet achieves a high switching speed and a low on resistance. 1. The on-resistance profile is very flat over the full analog input range, ensuring good linearity and low distortion when switching audio signals. High switching speed also makes the device suitable for video signal switching. CMOS construction ensures ultralow power dissipation, making the device ideally suited for portable, battery-powered instruments. 2. 3. 4. Extended signal range. The ADG333A is fabricated on an enhanced LC2MOS process, giving an increased signal range which extends to the supply rails. Low power dissipation. Low RON. Single-supply operation. For applications in which the analog signal is unipolar, the ADG333A can be operated from a single rail power supply. The device is fully specified with a single 12 V supply. When they are on, each switch conducts equally well in both directions and has an input signal range that extends to the power supplies. In the off condition, signal levels up to the supplies are blocked. All switches exhibit break-before-make switching action for use in multiplexer applications. Low charge inject is inherent in the design. Rev. B Document Feedback Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective owners. One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. Tel: 781.329.4700 ©1995–2016 Analog Devices, Inc. All rights reserved. Technical Support www.analog.com Data Sheet ADG333A TABLE OF CONTENTS Features .............................................................................................. 1 Terminology .......................................................................................6 Applications ....................................................................................... 1 Pin Configurations and Function Descriptions ............................7 Functional Block Diagram .............................................................. 1 Typical Performance Characteristics ..............................................8 General Description ......................................................................... 1 Test Circuits ..................................................................................... 10 Product Highlights ........................................................................... 1 Applications Information .............................................................. 11 Specifications..................................................................................... 3 ADG333A Supply Voltages ....................................................... 11 Dual Supply ................................................................................... 3 Power Supply Sequencing ......................................................... 11 Single Supply ................................................................................. 4 Outline Dimensions ....................................................................... 12 Absolute Maximum Ratings............................................................ 5 Ordering Guide .......................................................................... 13 ESD Caution .................................................................................. 5 REVISION HISTORY 6/2016—Rev. A to Rev. B Changes to VDD Parameter, Table 2 ................................................ 4 Updated Outline Dimensions ....................................................... 12 Changes to Ordering Guide .......................................................... 13 3/2005—Rev. 0 to Rev. A Updated Format .................................................................. Universal Changes to Specifications Section .................................................. 3 Updated Outline Dimensions ....................................................... 12 Changes to Ordering Guide .......................................................... 12 10/1995—Revision 0: Initial Version Rev. B | Page 2 of 13 Data Sheet ADG333A SPECIFICATIONS DUAL SUPPLY VDD = +15 V, VSS = −15 V, GND = 0 V, unless otherwise noted. 1 Table 1. Parameter ANALOG SWITCH Analog Signal Range RON ∆RON RON Match LEAKAGE CURRENTS Source Off Leakage IS (OFF) Channel On Leakage ID, IS (ON) +25°C 20 45 ±0.1 ±0.25 ±0.1 ±0.4 Unit VSS to VDD V Ω typ Ω max Ω max Ω max 45 5 4 Off Isolation Channel-to-Channel Crosstalk CS (OFF) CD, CS (ON) POWER REQUIREMENTS IDD ISS VDD/VSS 1 2 VD = ±5 V, IS = −10 mA VD = ±10 V, IS = −10 mA VDD = +16.5 V, VSS = −16.5 V VD = ±15.5 V, VS = +15.5 V Figure 15 VS = VD = ±15.5 V Figure 16 2.4 0.8 V min V max ±0.005 ±0.5 µA typ µA max VIN = 0 V or VDD RL= 300 Ω, CL = 35 pF; VS = ±10 V; Figure 17 10 2 ns typ ns max ns typ ns max ns min pC typ 10 72 85 7 26 pC max dB typ dB typ pF typ pF typ 90 80 145 Break-Before-Make Delay, tOPEN Charge Injection VD = ±10 V, IS = –1 mA ±5 ±3 175 tOFF Test Conditions/Comments nA typ nA max nA typ nA max DIGITAL INPUTS Input High Voltage, VINH Input Low Voltage, VINL Input Current IINL or IINH DYNAMIC CHARACTERISTICS 2 tON −40°C to +85°C 0.05 0.25 0.01 1 0.35 5 ±3/±20 mA typ mA max µA typ µA max V min/V max Temperature range is as follows: B version: −40°C to +85°C. Guaranteed by design; not subject to production test. Rev. B | Page 3 of 13 RL = 300 Ω, CL = 35 pF; VS = ±10 V; Figure 17 RL = 300 Ω, CL= 35 pF; VS = +5 V; Figure 18 VD = 0 V, RD = 0 Ω, CL= 10 nF; VDD = +15 V, VSS = −15 V; Figure 19 RL = 75 Ω, CL = 5 pF, f = 1 MHz; VS = 2.3 V rms; Figure 20 RL = 75 Ω, CL = 5 pF, f = 1 MHz; VS = 2.3 V rms; Figure 21 Digital inputs = 0 V or 5 V |VDD| = |VSS| Data Sheet ADG333A SINGLE SUPPLY VDD = +12 V, VSS = 0 V ± 10%, GND = 0 V, unless otherwise noted. 1 Table 2. Parameter ANALOG SWITCH Analog Signal Range RON +25°C −40°C to +85°C Unit Test Conditions/Comments 0 V to VDD V Ω typ Ω max VD = 1 V, 10 V, IS = −1 mA 35 75 LEAKAGE CURRENTS Source Off Leakage IS (OFF) Channel On Leakage ID, IS (ON) ±0.1 ±0.25 ±0.1 ±0.4 DIGITAL INPUTS Input High Voltage, VINH Input Low Voltage, VINL Input Current IINL or IINH DYNAMIC CHARACTERISTICS 2 tON ±5 2.4 0.8 V min V max ±0.005 ±0.5 µA typ µA max VIN = 0 V or VDD ns typ ns max ns typ ns max ns min pC typ dB typ dB typ pF typ pF typ RL = 300 Ω, CL = 35 pF; VS = 8 V; Figure 17 ±3 110 200 tOFF 100 180 Break-Before-Make Delay, tOPEN Charge Injection Off Isolation Channel-to-Channel Crosstalk CS (OFF) CD, CS (ON) POWER REQUIREMENTS IDD VDD 1 2 10 5 72 85 12 25 0.05 0.25 VDD = 13.2 V VD = 12.2 V/1 V, VS = 1 V/12.2 V Figure 15 VS = VD = 12.2 V/1 V Figure 16 nA typ nA max nA typ nA max 0.35 3/30 mA typ mA max V min/V max Temperature range is as follows: B Version: −40°C to +85°C. Guaranteed by design; not subject to production test. Rev. B | Page 4 of 13 RL = 300 Ω, CL = 35 pF; VS = 8 V; Figure 17 RL = 300 Ω, CL = 35 pF; VS = 5 V; Figure 18 VD = 6 V, RD = 0 W, CL = 10 nF; VDD = 12 V, VSS = 0 V; Figure 19 RL = 75 Ω, CL = 5 pF, f = 1 MHz; VS = 1.15 V rms; Figure 20 RL = 75 Ω, CL = 5 pF, f = 1 MHz; VS = 1.15 V rms; Figure 21 VDD = 13.5 V Digital inputs = 0 V or 5 V Data Sheet ADG333A ABSOLUTE MAXIMUM RATINGS TA = 25°C unless otherwise noted. Table 3. Parameter VDD to VSS VDD to GND VSS to GND Analog, Digital Inputs 1 Continuous Current, S or D Peak Current, S or D (Pulsed at 1 ms, 10% Duty Cycle Max) Operating Temperature Range Industrial (B Version) Storage Temperature Range Junction Temperature θJA, Thermal Impedance PDIP Package SOIC Package SSOP Package Lead Temperature, Soldering 10 sec Vapor Phase (60 sec) Infrared (15 sec) 1 Min +44 V −0.3 V to +30 V +0.3 V to −30 V VSS − 2 V to VDD + 2 V or 20 mA, whichever occurs first 20 mA 40 mA −40°C to +85°C −65°C to +125°C 150°C Stresses at or above those listed under Absolute Maximum Ratings may cause permanent damage to the product. This is a stress rating only; functional operation of the product at these or any other conditions above those indicated in the operational section of this specification is not implied. Operation beyond the maximum operating conditions for extended periods may affect product reliability. Table 4. Truth Table Logic 0 1 Switch A Off On ESD CAUTION 103°C/W 74°C/W 130°C/W 260°C 215°C 220°C Overvoltage at IN, S, or D is clamped by internal diodes. Current should be limited to the maximum ratings given. Rev. B | Page 5 of 13 Switch B On Off Data Sheet ADG333A TERMINOLOGY RON Ohmic resistance between D and S. ∆RON RON variation due to a change in the analog input voltage with a constant load current. RON Match Difference between the RON of any two channels. IS (OFF) Source leakage current with the switch off. ID (OFF) Drain leakage current with the switch off. ID, IS (ON) Channel leakage current with the switch on. VD (VS) Analog voltage on Terminal D and Terminal S. tON Delay between applying the digital control input and the output switching on. tOFF Delay between applying the digital control input and the output switching off. tOPEN Break-before-make delay when switches are configured as a multiplexer. VINL Maximum input voltage for Logic 0. VINH Minimum input voltage for Logic 1. IINL (IINH) Input current of the digital input. CS (OFF) Off switch source capacitance. Crosstalk A measure of unwanted signal which is coupled through from one channel to another as a result of parasitic capacitance. CD (OFF) Off switch drain capacitance. Off Isolation A measure of unwanted signal coupling through an off switch. CD, CS (ON) On switch capacitance. Charge Injection A measure of the glitch impulse transferred from the digital input to the analog output during switching. Rev. B | Page 6 of 13 Data Sheet ADG333A IN4 19 S4A 18 D4 17 S4B D1 3 ADG333A S1B 4 TOP VIEW (Not to Scale) VSS 5 16 VDD GND 6 15 NC S2B 7 14 S3B D2 8 13 D3 S2A 9 12 S3A 11 IN3 IN2 10 NC = NO CONNECT IN1 1 20 IN4 IN1 1 20 IN4 S1A 2 19 S4A S1A 2 19 S4A D1 3 18 D4 S1B 4 17 S4B VSS 5 ADG333A D1 3 16 VDD TOP VIEW GND 6 (Not to Scale) 15 NC 14 S3B S2B 7 D2 8 13 12 S3A IN2 10 11 IN3 NC = NO CONNECT Figure 2. PDIP Pin Configuration D4 ADG333A 17 S4B VSS 5 TOP VIEW (Not to Scale) 16 VDD S2B 7 D3 S2A 9 18 S1B 4 GND 6 Figure 3. SOIC Pin Configuration 15 NC 14 S3B D2 8 13 D3 S2A 9 12 S3A 11 IN3 IN2 10 01212-003 20 01212-002 IN1 1 S1A 2 NC = NO CONNECT 01212-004 PIN CONFIGURATIONS AND FUNCTION DESCRIPTIONS Figure 4. SSOP Pin Configuration Table 5. Pin Function Descriptions Pin No. 1, 10, 11, 20 2, 4, 7, 9, 12, 14, 17, 19 3, 8, 13, 18 5 Mnemonic IN1, IN2, IN3, IN4 S1A, S1B, S2B, S2A, S3A, S3B, S4B, S4A D1, D2, D3, D4 VSS 6 15 16 GND NC VDD Description Logic Control Input. Source Terminal. Can be an input or an output. Drain Terminal. Can be an input or an output. Most Negative Power Supply Potential in Dual Supplies. In single-supply applications, it can be connected to ground. Ground (0 V) Reference. No Connect. Most Positive Power Supply Potential. Rev. B | Page 7 of 13 Data Sheet ADG333A TYPICAL PERFORMANCE CHARACTERISTICS 60 60 VDD = 15V VSS = 0V TA = 25°C 50 50 +125°C RON (Ω) 40 30 VDD = +10V VSS = –10V 20 20 VDD = +15V VSS = –15V 10 –15 –10 –5 0 VDD, VS (V) 5 10 0 6 3 12 9 15 VDD, VS (V) Figure 8. RON as a Function of VD (VS) for Different Temperatures, Single Supply 0.004 100 TA = 25°C 90 VDD = +16.5V VSS = –16.5V TA = 25°C 0.002 LEAKAGE CURRENT (nA) VDD = +5V VSS = –5V 70 60 50 VDD = +10V VSS = –10V 40 VDD = +15V VSS = –15V 20 0 3 6 9 12 0 –0.002 IS (ON) –0.004 –0.006 ID (ON) –0.008 01212-006 30 IS (OFF) –0.010 –15 15 01212-009 80 RON (Ω) +25°C –40°C 10 15 Figure 5. RON as a Function of VD (VS), Dual Supply –10 –5 VDD, VS (V) 45 40 0 VD, VS (V) 5 10 15 Figure 9. Leakage Currents as a Function of VD (VS), Dual Supply Figure 6. RON as a Function of VD (VS), Single Supply 0.001 VDD = +15V VSS = –15V IS (OFF) LEAKAGE CURRENT (nA) 0 35 +125°C RON (Ω) +85°C 40 01212-008 30 01212-005 RON (Ω) VDD = +5V VSS = –5V 30 +85°C 25 20 VDD = +16.5V VSS = –16.5V TA = 25°C –0.001 ID (ON) –0.002 IS (ON) 10 –15 –40°C –10 +25°C –5 0 VDD, VS (V) 5 01212-007 15 10 01212-010 –0.003 –0.004 0 15 Figure 7. RON as a Function of VD (VS) for Different Temperatures, Dual Supply 3 6 VD, VS (V) 9 Figure 10. Leakage Currents as a Function of VD (VS), Single Supply Rev. B | Page 8 of 13 12 Data Sheet ADG333A 20 1 CL = 10nF VDD = +16.5V VSS = –16.5V TA = 25°C 15 0.8 10 IDD (mA) Q (pC) 5 VDD = +16.5V VSS = –16.5V 0 VDD = +12V VSS = 0V –5 0.6 0.4 –10 01212-011 –20 –15 –5 –10 0 VS (V) 5 10 0 15 0 Figure 11. Charge Injection as a Function of VS VD = +2V VS = –2V 120 100 80 01212-012 SWITCHING TIME (ns) 140 0 5 10 VDD (V) 15 200 800 600 400 SWITCHING FREQUENCY (kHz) Figure 13. IDD as a Function of Switching Frequency 160 60 01212-013 0.2 –15 20 Figure 12. Switching Time as a Function of VD Rev. B | Page 9 of 13 1000 Data Sheet ADG333A TEST CIRCUITS IS (OFF) ID (ON) NC V1 D VD RON = V1/IDS A S D VD NC = NO CONNECT Figure 16. On Leakage VDD 0.1µF +3V VDD SB 50% VIN D VS VOUT RL 300Ω SA +10V VD Figure 15. Off Leakage Figure 14. On Resistance –10V D 01212-014 S S VS 01212-015 A CL 35pF 50% 0V +10V IN tOFF VS 0V VSS GND tON 50% 50% 01212-017 –10V 0.1µF VSS Figure 17. Switching Times VDD 0.1µF 3V VDD VS SB VIN D VOUT CL 35pF RL 300Ω SA IN 0V VS 50% VOUT 50% VSS GND 01212-018 tOPEN 0.1µF VSS Figure 18. Break-Before-Make Delay, tOPEN VDD VDD 3V VD D SA CL 10nF IN GND VIN VOUT 0V VOUT VSS QINJ = CL × ∆VOUT 0V ∆VOUT 01212-019 RD VSS Figure 19. Charge Injection VDD 0.1µF VDD S VDD RL 75Ω D VIN VOUT S 0.1µF VSS 75Ω D VIN2 VIN1 VS VSS GND S 01212-020 VS VDD VOUT D NC RL 75Ω VSS GND 0.1µF VSS Figure 20. Off Isolation CHANNEL-TO-CHANNEL CROSSTALK 20 × LOG |VS/VOUT| Figure 21. Channel-to-Channel Crosstalk Rev. B | Page 10 of 13 01212-021 0.1µF 01212-016 IDS Data Sheet ADG333A APPLICATIONS INFORMATION ADG333A SUPPLY VOLTAGES POWER SUPPLY SEQUENCING The ADG333A can operate from a dual or signal supply. VSS should be connected to GND when operating with a single supply. When using a dual supply, the ADG333A can also operate with unbalanced supplies; for example VDD = 20 V and VSS = −5 V. The only restrictions are that VDD to GND must not exceed 30 V, VSS to GND must not drop below −30 V, and VDD to VSS must not exceed +44 V. It is important to remember that the ADG333A supply voltage directly affects the input signal range, the switch on resistance and the switching times of the device. The effects of the power supplies on these characteristics can be clearly seen from the Typical Performance Characteristics curves. When using CMOS devices, care must be taken to ensure correct power-supply sequencing. Incorrect power-supply sequencing can result in the device being subjected to stresses beyond those listed in the Absolute Maximum Ratings. This is also true for the ADG333A. Always turn on VDD first, followed by VSS and the logic signals. An external signal within the maximum specified ratings can then be safely presented to the source or drain of the switch. Rev. B | Page 11 of 13 Data Sheet ADG333A OUTLINE DIMENSIONS 1.060 (26.92) 1.030 (26.16) 0.980 (24.89) 20 11 1 10 0.280 (7.11) 0.250 (6.35) 0.240 (6.10) 0.325 (8.26) 0.310 (7.87) 0.300 (7.62) PIN 1 0.100 (2.54) BSC 0.060 (1.52) MAX 0.210 (5.33) MAX 0.015 (0.38) MIN 0.150 (3.81) 0.130 (3.30) 0.115 (2.92) 0.195 (4.95) 0.130 (3.30) 0.115 (2.92) 0.015 (0.38) GAUGE PLANE 0.014 (0.36) 0.010 (0.25) 0.008 (0.20) SEATING PLANE 0.022 (0.56) 0.018 (0.46) 0.014 (0.36) 0.430 (10.92) MAX 0.005 (0.13) MIN 0.070 (1.78) 0.060 (1.52) 0.045 (1.14) COMPLIANT TO JEDEC STANDARDS MS-001-AD CONTROLLING DIMENSIONS ARE IN INCHES; MILLIMETER DIMENSIONS (IN PARENTHESES) ARE ROUNDED-OFF INCH EQUIVALENTS FOR REFERENCE ONLY AND ARE NOT APPROPRIATE FOR USE IN DESIGN. CORNER LEADS MAY BE CONFIGURED AS WHOLE OR HALF LEADS. Figure 22. 20-Lead Plastic Dual In-Line Package [PDIP] Narrow Body (N-20) Dimensions shown in inches and (millimeters) 13.00 (0.5118) 12.60 (0.4961) 20 11 7.60 (0.2992) 7.40 (0.2913) 10 2.65 (0.1043) 2.35 (0.0925) 0.30 (0.0118) 0.10 (0.0039) COPLANARITY 0.10 10.65 (0.4193) 10.00 (0.3937) 1.27 (0.0500) BSC 0.51 (0.0201) 0.31 (0.0122) SEATING PLANE 0.75 (0.0295) 45° 0.25 (0.0098) 8° 0° 0.33 (0.0130) 0.20 (0.0079) COMPLIANT TO JEDEC STANDARDS MS-013-AC CONTROLLING DIMENSIONS ARE IN MILLIMETERS; INCH DIMENSIONS (IN PARENTHESES) ARE ROUNDED-OFF MILLIMETER EQUIVALENTS FOR REFERENCE ONLY AND ARE NOT APPROPRIATE FOR USE IN DESIGN. Figure 23. 20-Lead Standard Small Outline Package [SOIC_W] Wide Body (RW-20) Dimensions shown in millimeters and (inches) Rev. B | Page 12 of 13 1.27 (0.0500) 0.40 (0.0157) 06-07-2006-A 1 Data Sheet ADG333A 7.50 7.20 6.90 20 11 1 10 5.60 5.30 8.20 5.00 7.80 7.40 PIN 1 2.00 MAX 0.65 BSC 0.05 MIN COPLANARITY 0.10 1.85 1.75 1.65 0.38 0.22 0.25 0.09 SEATING PLANE 8° 4° 0° 0.95 0.75 0.55 COMPLIANT TO JEDEC STANDARDS MO-150AE Figure 24. 20-Lead Shrink Small Outline Package [SSOP] (RS-20) Dimensions shown in millimeters ORDERING GUIDE Model 1 ADG333ABNZ ADG333ABR ADG333ABR-REEL ADG333ABRZ ADG333ABRZ-REEL ADG333ABRS ADG333ABRS-REEL ADG333ABRSZ ADG333ABRSZ-REEL 1 Temperature Range −40°C to +85°C −40°C to +85°C −40°C to +85°C −40°C to +85°C −40°C to +85°C −40°C to +85°C −40°C to +85°C −40°C to +85°C −40°C to +85°C Package Description 20-Lead Plastic Dual In-Line Package [PDIP] 20-Lead Standard Small Outline Package [SOIC_W] 20-Lead Standard Small Outline Package [SOIC_W] 20-Lead Standard Small Outline Package [SOIC_W] 20-Lead Standard Small Outline Package [SOIC_W] 20-Lead Shrink Small Outline Package [SSOP] 20-Lead Shrink Small Outline Package [SSOP] 20-Lead Shrink Small Outline Package [SSOP] 20-Lead Shrink Small Outline Package [SSOP] Z = RoHS Compliant Part. ©1995–2016 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. D01212-0-6/16(B) Rev. B | Page 13 of 13 Package Option N-20 RW-20 RW-20 RW-20 RW-20 RS-20 RS-20 RS-20 RS-20
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