ADG426

a FEATURES 44 V Supply Maximum Ratings VSS to VDD Analog Signal Range Low On Resistance (80 Ω max) Low Power Fast Switching tON < 160 ns t OFF < 150 ns Break Before Make Switching Action Plug-In Upgrade for DG506A/ADG506A, DG507A/ADG507A, DG526/ADG526A ADG406/ADG407 are Plug-In Replacements for DG406/DG407 APPLICATIONS Audio and Video Routing Automatic Test Equipment Data Acquisition Systems Battery Powered Systems Sample Hold Systems Communication Systems Avionics GENERAL DESCRIPTION LC2MOS 8-/16-Channel High Performance Analog Multiplexers ADG406/ADG407/ADG426 FUNCTIONAL BLOCK DIAGRAMS ADG406 S1 S1A DA S8A D S1B S16 1 OF 16 DECODER A0 A1 A2 A3 EN DB S8B 1 OF 8 DECODER A0 A1 A2 EN ADG407 ADG426 S1 D S16 WR DECODER/ LATCHES A0 A1 A2 A3 EN RS PRODUCT HIGHLIGHTS The ADG406, ADG407 and ADG426 are monolithic CMOS analog multiplexers. The ADG406 and ADG426 switch one of sixteen inputs to a common output as determined by the 4-bit binary address lines A0, A1, A2 and A3. The ADG426 has onchip address and control latches that facilitate microprocessor interfacing. The ADG407 switches one of eight differential inputs to a common differential output as determined by the 3bit binary address lines A0, A1 and A2. An EN input on all devices is used to enable or disable the device. When disabled, all channels are switched OFF. The ADG406/ADG407/ADG426 are designed on an enhanced LC2MOS process that provides low power dissipation yet gives high switching speed and low on resistance. These features make the parts suitable for high speed data acquisition systems and audio signal switching. Low power dissipation makes the parts suitable for battery powered systems. Each channel conducts equally well in both directions when ON and has an input signal range which extends to the supplies. In the OFF condition, signal levels up to the supplies are blocked. All channels exhibit break before make switching action preventing momentary shorting when switching channels. Inherent in the design is low charge injection for minimum transients when switching the digital inputs. 1. Extended Signal Range The ADG406/ADG407/ADG426 are fabricated on an enhanced LC2MOS process giving an increased signal range which extends to the supply rails 2. Low Power Dissipation 3. Low RON 4. Single/Dual Supply Operation 5. Single Supply Operation For applications where the analog signal is unipolar, the ADG406/ADG407/ADG426 can be operated from a single rail power supply. The parts are fully specified with a single +12 V power supply and will remain functional with single supplies as low as +5 V. REV. 0 Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. One Technology Way, P.O. Box 9106, Norwood. MA 02062-9106, U.S.A. Tel: 617/329-4700 Fax: 617/326-8703 ADG406/ADG407/ADG426–SPECIFICATIONS1 DUAL SUPPLY Parameter ANALOG SWITCH Analog Signal Range RON RON Match LEAKAGE CURRENTS Source OFF Leakage IS (OFF) Drain OFF Leakage ID (OFF) ADG406, ADG426 ADG407 Channel ON Leakage ID, IS (ON) ADG406, ADG426 ADG407 DIGITAL INPUTS Input High Voltage, VINH Input Low Voltage, VINL Input Current IINL or IINH CIN, Digital Input Capacitance DYNAMIC CHARACTERISTICS2 tTRANSITION (VDD = +15 V ± 10%, VSS = –15 V ± 10%, GND = 0 V, unless otherwise noted) B Version –40°C to +25°C +85°C VSS to VDD 50 80 4 ± 0.5 ±1 ±1 ±1 ±1 125 50 80 4 ± 0.5 ±1 ±1 ±1 ±1 T Version –55°C to +25°C +125°C VSS to VDD 125 Units V Ω typ Ω max Ω typ nA max nA max nA max nA max nA max V min V max µA max pF typ ns typ ns max ns min ns typ ns max ns typ ns max ns min ns min ns min ns min pC typ dB typ dB typ pF typ pF typ pF typ Test Conditions/Comments VD = ± 10 V, IS = –1 mA VDD = +13.5 V, VSS = –13.5 V VD = 0 V, IS = –1 mA VDD = +16.5 V, VSS = –16.5 V VD = ± 10 V, VS = 10 V, Test Circuit 2 VD = ± 10 V, VS = 10 V; Test Circuit 3 VS = VD = ± 10 V; Test Circuit 4 ± 20 ± 20 ± 20 ± 20 ± 20 2.4 0.8 ±1 ± 50 ± 200 ± 100 ± 200 ± 100 2.4 0.8 ±1 8 120 150 10 120 160 110 150 8 120 150 10 120 160 110 150 VIN = 0 or VDD f = 1 MHz RL = 300 Ω, CL = 35 pF; V1 = ± 10 V, V2 = 10 V; Test Circuit 5 RL = 300 Ω, CL = 35 pF; VS = +5 V, Test Circuit 6 RL = 300 Ω, CL = 35 pF; VS = +5 V, Test Circuit 7 RL = 300 Ω, CL = 35 pF; VS = +5 V, Test Circuit 7 250 10 175 225 130 180 100 100 10 100 250 10 175 225 130 180 100 100 10 100 Break Before Make Delay, tOPEN tON (EN, WR) tOFF (EN, RS) ADG426 Only tW, Write Pulse Width tS, Address, Enable Setup Time tH, Address, Enable Hold Time tRS, Reset Pulse Width Charge Injection OFF Isolation Channel-to-Channel Crosstalk CS (OFF) CD (OFF) ADG406, ADG426 ADG407 CD, CS (ON) ADG406, ADG426 ADG407 POWER REQUIREMENTS IDD ISS IDD ISS NOTES 1 2 8 –75 85 5 50 25 60 40 1 5 1 5 100 200 500 1 5 8 –75 85 5 50 25 60 40 1 5 1 5 100 200 500 1 5 V S = +5 V VS = 0 V, RS = 0 Ω, CL = 1 nF; Test Circuit 10 RL = 1 kΩ, f = 100 kHz; VEN = 0 V, Test Circuit 11 RL = 1 kΩ, f = 100 kHz, Test Circuit 12 f = 1 MHz f = 1 MHz f = 1 MHz pF typ pF typ µA typ µA max µA typ µA max µA typ µA max µA typ µA max VDD = +16.5 V, VSS = –16.5 V VIN = 0 V, VEN = 0 V VIN = 0 V, VEN = 2.4 V Temperature ranges are as follows: B Versions: –40°C to +85°C; T Versions: –55 °C to +125°C. Guaranteed by design, not subject to production test. Specifications subject to change without notice. –2– REV. 0 ADG406/ADG407/ADG426 SINGLE SUPPLY (V Parameter ANALOG SWITCH Analog Signal Range RON LEAKAGE CURRENTS Source OFF Leakage IS (OFF) Drain OFF Leakage ID (OFF) ADG406, ADG426 ADG407 Channel ON Leakage ID, IS (ON) ADG406, ADG426 ADG407 DIGITAL INPUTS Input High Voltage, VINH Input Low Voltage, VINL Input Current IINL or IINH CIN, Digital Input Capacitance DYNAMIC CHARACTERISTICS2 tTRANSITION DD = +12 V ± 10%, VSS = 0 V, GND = 0 V, unless otherwise noted) B Version –40°C to +25°C +85°C 0 to VDD 90 125 ± 0.5 ±1 ±1 ±1 ±1 200 ± 20 ± 20 ± 20 ± 20 ± 20 2.4 0.8 ±1 8 180 220 10 180 240 135 180 8 180 220 10 180 240 135 180 90 125 ± 0.5 ±1 ±1 ±1 ±1 T Version –55°C to +25°C +125°C 0 to VDD 200 ± 50 ± 200 ± 100 ± 200 ± 100 2.4 0.8 ±1 Units V Ω typ Ω max nA max Test Conditions/Comments VD = +3 V, +8.5 V, IS = –1 mA; VDD = +10.8 V VDD = +13.2 V VD = 8 V/0.1 V, VS = 0.1 V/8 V; Test Circuit 2 VD = 8 V/0.1 V, VS = 0.1 V/8 V; Test Circuit 3 VS = VD = 8 V/0.1 V, Test Circuit 4 nA max nA max nA max nA max V min V max µA max pF typ ns typ ns max ns typ ns typ ns max ns typ ns max ns min ns min ns min ns min pC typ dB typ dB typ pF typ pF typ pF typ VIN = 0 or VDD f = 1 MHz RL = 300 Ω, CL = 35 pF; V1 = 8 V/0 V, V2 = 0 V/8 V; Test Circuit 5 RL = 300 Ω, CL = 35 pF; VS = +5 V, Test Circuit 6 RL = 300 Ω, CL = 35 pF; VS = +5 V, Test Circuit 7 RL = 300 Ω, CL = 35 pF; VS = +5 V, Test Circuit 7 350 350 Break Before Make Delay, tOPEN tON (EN, WR) tOFF (EN, RS) ADG426 Only tW, Write Pulse Width tS, Address, Enable Setup Time tH, Address, Enable Hold Time tRS, Reset Pulse Width Charge Injection OFF Isolation Channel-to-Channel Crosstalk CS (OFF) CD (OFF) ADG406, ADG426 ADG407 CD, CS (ON) ADG406, ADG426 ADG407 POWER REQUIREMENTS IDD IDD 350 220 100 100 10 100 350 220 100 100 10 100 5 –75 85 8 80 40 100 50 1 5 100 200 500 5 –75 85 8 80 40 100 50 1 5 100 200 500 V S = +5 V VS = 6 V, RS = 0 Ω, CL = 1 nF; Test Circuit 10 RL = 1 kΩ, f = 100 kHz; Test Circuit 11 RL = 1 kΩ, f = 100 kHz; Test Circuit 12 f = 1 MHz f = 1 MHz f = 1 MHz pF typ pF typ µA typ µA max µA typ µA max VDD = +13.2 V VIN = 0 V, VEN = 0 V VIN = 0 V, VEN = 2.4 V NOTES 1 Temperature ranges are as follows: B Versions: –40 °C to +85°C; T Versions: –55°C to +125°C. 2 Guaranteed by design, not subject to production test. Specifications subject to change without notice. REV. 0 –3– ADG406/ADG407/ADG426 ABSOLUTE MAXIMUM RATINGS 1 (TA = +25°C unless otherwise noted) ORDERING GUIDE VDD to VSS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . +44 V VDD to GND . . . . . . . . . . . . . . . . . . . . . . . . . . –0.3 V to +25 V VSS to GND . . . . . . . . . . . . . . . . . . . . . . . . . . . +0.3 V to –25 V Analog, Digital Inputs2. . . . . . . . . . . . . VSS – 2 V to VDD + 2 V or 20 mA, Whichever Occurs First Continuous Current, S or D . . . . . . . . . . . . . . . . . . . . . 20 mA Peak Current, S or D . . . . . . . . . . . . . . . . . . . . . . . . . . . 40 mA (Pulsed at 1 ms, 10% Duty Cycle Max) Operating Temperature Range Industrial (B Version) . . . . . . . . . . . . . . . . . –40°C to +85°C Extended (T Version) . . . . . . . . . . . . . . . . . –55°C to +125°C Storage Temperature Range . . . . . . . . . . . . . –65°C to +150°C Junction Temperature . . . . . . . . . . . . . . . . . . . . . . . . . +150°C Plastic Package θJA, Thermal Impedance . . . . . . . . . . . . . . . . . . . . . . 75°C/W Lead Temperature, Soldering (10 sec) . . . . . . . . . . . +260°C PLCC Package θJA, Thermal Impedance . . . . . . . . . . . . . . . . . . . . . . 80°C/W Lead Temperature, Soldering Vapor Phase (60 sec) . . . . . . . . . . . . . . . . . . . . . . +215°C Infrared (15 sec) . . . . . . . . . . . . . . . . . . . . . . . . . . +220°C SSOP Package θJA, Thermal Impedance . . . . . . . . . . . . . . . . . . . . . 122°C/W Lead Temperature, Soldering Vapor Phase (60 sec) . . . . . . . . . . . . . . . . . . . . . . +215°C Infrared (15 sec) . . . . . . . . . . . . . . . . . . . . . . . . . . +220°C NOTES 1 Stresses above those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those listed in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. Only one absolute maximum rating may be applied at any one time. 2 Overvoltages at A, S, D, WR or RS will be clamped by internal diodes. Current should be limited to the maximum ratings given. Model ADG406BN ADG406BP ADG407BN ADG407BP ADG426BN ADG426BRS Temperature Range –40°C to +85°C –40°C to +85°C –40°C to +85°C –40°C to +85°C –40°C to +85°C –40°C to +85°C Package Option* N-28 P-28A N-28 P-28A N-28 RS-28 *N = Plastic DIP, P = Plastic Leaded Chip Carrier (PLCC), RS = Shrink Small Outline Package (SSOP). CAUTION ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on the human body and test equipment and can discharge without detection. Although these devices feature proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high energy electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance degradation or loss of functionality. WARNING! ESD SENSITIVE DEVICE – 4– REV. 0 ADG406/ADG407/ADG426 Table I. Truth Table (ADG406) PIN CONFIGURATIONS DIP VDD NC NC S16 S15 S14 S13 S12 S11 1 2 3 4 5 6 7 8 9 28 27 D VSS A3 X 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 A2 X 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 A1 X 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 A0 X 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 EN 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 ON SWITCH NONE 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 PLCC S16 VDD VSS NC NC 26 S8 25 24 23 S7 S6 S5 S4 S3 S2 S1 EN 4 S15 S14 S13 S12 S11 5 6 7 8 9 3 2 1 28 27 26 25 S7 24 S6 S8 23 S5 22 S4 21 S3 20 S2 19 S1 S8A ADG406 ADG406 TOP VIEW (Not to Scale) 22 TOP VIEW (Not to Scale) 21 20 19 18 17 16 15 S10 10 S9 11 12 13 14 15 16 17 18 NC GND S10 10 S9 11 GND 12 NC 13 A3 14 A1 A2 NC = NO CONNECT Table II. Truth Table (ADG407) VDD A2 X 0 0 0 0 1 1 1 1 A1 X 0 0 1 1 0 0 1 1 A0 X 0 1 0 1 0 1 0 1 EN 0 1 1 1 1 1 1 1 1 ON SWITCH PAIR NONE 1 2 3 4 5 6 7 8 DB NC S8B S7B S6B S5B S4B S3B 2 3 4 5 6 7 8 9 27 VSS 26 S8A 25 S7A 24 S6A 23 S5A 22 S4A TOP VIEW 21 S3A (Not to Scale) 20 S2A 19 18 17 16 15 S1A EN A0 A1 A2 4 S7B S6B S5B S4B S3B 5 6 7 8 9 3 2 1 28 27 26 25 S7A 24 S6A VSS NC DB DA VDD 1 28 DA S8B EN A3 A2 A1 A0 A0 D ADG407 TOP VIEW (Not to Scale) 23 S5A 22 S4A 21 S3A 20 S2A 19 S1A ADG407 S2B 10 S1B 11 12 13 14 15 16 17 18 GND NC NC EN A2 A1 A0 S2B 10 S1B 11 GND 12 NC 13 Table III. Truth Table (ADG426) A3 X X A2 X X A1 X X A0 X X EN X X WR RS 1 X 0 ON SWITCH Retains Previous Switch Condition NONE (Address and Enable Latches Cleared) NONE 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 NC = NO CONNECT NC 14 PIN CONFIGURATION DIP/SSOP X 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 X 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 X 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 X 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 VDD NC RS S16 S15 S14 S13 S12 S11 1 2 3 4 5 6 7 8 9 28 27 D VSS 26 S8 25 24 23 S7 S6 S5 S4 S3 S2 S1 EN A0 A1 A2 ADG426 22 TOP VIEW (Not to Scale) 21 20 19 18 17 16 15 S10 10 S9 11 GND 12 WR 13 A3 14 NC = NO CONNECT REV. 0 – 5– ADG406/ADG407/ADG426 TIMING DIAGRAMS (ADG426) 3V WR 0V 50% 50% TERMINOLOGY VDD VSS tW tS tH 0.8V 3V A0, A1, A2, (A3) EN 0V 2V GND RON RON Match IS (OFF) ID (OFF) ID, IS (ON) VD (VS) CS (OFF) CD (OFF) Figure 1. Figure 1 shows the timing sequence for latching the switch address and enable inputs. The latches are level sensitive; therefore, while WR is held low, the latches are transparent and the switches respond to the address and enable inputs. This input data is latched on the rising edge of WR. 3V RS 0V 50% 50% t RS t OFF (RS ) V0 SWITCH OUTPUT 0V 0.8V0 CD, CS (ON) CIN tON (EN) tOFF (EN) Figure 2. Figure 2 shows the Reset Pulse Width, tRS, and the Reset Turn Off Time, tOFF (RS). Note: All digital input signals rise and fall times are measured from 10% to 90% of 3 V. tR = tF = 20 ns. tTRANSITION tOPEN VINL VINH IINL (IINH) Crosstalk Off Isolation Charge Injection IDD ISS Most positive power supply potential. Most negative power supply potential in dual supplies. In single supply applications, it may be connected to ground. Ground (0 V) reference. Ohmic resistance between D and S. Difference between the RON of any two channels. Source leakage current when the switch is off. Drain leakage current when the switch is off. Channel leakage current when the switch is on. Analog voltage on terminals D, S. Channel input capacitance for “OFF” condition. Channel output capacitance for “OFF” condition. “ON” switch capacitance. Digital input capacitance. Delay time between the 50% and 90% points of the digital input and switch “ON” condition. Delay time between the 50% and 90% points of the digital input and switch “OFF” condition. Delay time between the 50% and 90% points of the digital inputs and the switch “ON” condition when switching from one address state to another. “OFF” time measured between 80% points of both switches when switching from one address state to another. Maximum input voltage for logic “0.” Minimum input voltage for logic “1.” Input current of the digital input. A measure of unwanted signal which is coupled through from one channel to another as a result of parasitic capacitance. A measure of unwanted signal coupling through an “OFF” channel. A measure of the glitch impulse transferred from the digital input to the analog output during switching. Positive supply current. Negative supply current. – 6– REV. 0 ADG406/ADG407/ADG426 Typical Performance Graphs 150 TA = +25°C 400 TA = +25°C 350 VDD = +5V VSS = 0V 120 VDD = +5V VSS = –5V 90 300 250 RON – Ω RON – Ω VDD = +10V VSS = –10V 200 150 100 50 0 0 2.5 5 V DD = +15V V SS = 0V 60 VDD = +10V VSS = 0V VDD = +12V VSS = 0V 30 VDD = +15V VSS = –15V VDD = +12V VSS = –12V 0 –15 –10 –5 0 VD (V S) – Volts 5 10 15 7.5 10 VD (V S) – Volts 12.5 15 Figure 3. RON as a Function of VD (VS): Dual Supplies 100 VDD = +15V VSS = –15V 80 +125°C 60 Figure 6. RON as a Function of VD (VS): Single Supplies 150 VDD = +12V VSS = 0V 120 +125°C 90 +85°C +25°C 60 RON – Ω +85°C 40 +25°C 20 RON – Ω 0 5 VD (V S) – Volts 10 15 30 0 –15 0 –10 –5 0 2 4 6 8 VD (V S) – Volts 10 12 Figure 4. RON as a Function of VD (VS) for Different Temperatures Figure 7. RON as a Function of VD (VS) for Different Temperatures 0.10 VDD = +15V VSS = –15V TA = +25°C LEAKAGE CURRENT – nA ID(ON) 0.06 0.02 V DD = +12V V SS = 0V TA = +25°C 0.01 0.08 LEAKAGE CURRENT – nA 0.04 ID(OFF) 0.02 IS(OFF) 0.00 ID(OFF) ID(ON) –0.01 0.00 IS(OFF) –0.02 –15 –0.02 –10 –5 0 5 VD (V S) – Volts 10 15 0 2 4 6 VD (V S) – Volts 8 10 12 Figure 5. Leakage Currents as a Function of VD (VS) Figure 8. Leakage Currents as a Function of VD (VS) REV. 0 – 7– ADG406/ADG407/ADG426 100 VDD = +15V VSS = –15V 10 100 VDD = +15V VSS = –15V 10 IDD – mA ISS – mA 1 EN = 2.4V 0.1 EN = 0V 0.01 EN = 2.4V 1 EN = 0V 0.1 2 10 0.001 10 3 10 4 10 5 10 6 10 7 0.0001 2 10 10 3 10 4 10 5 10 6 10 7 FREQUENCY – Hz FREQUENCY – Hz Figure 9. Positive Supply Current vs. Switching Frequency Figure 12. Negative Supply Current vs. Switching Frequency 160 tON 140 VDD = +15V VSS = –15V 220 VDD = +12V VSS = 0V 200 tON tTRANSITION t – ns 180 tTRANSITION 120 t – ns 160 140 120 100 80 tOFF 60 1 3 5 7 VIN – V 9 11 13 15 tOFF 100 80 2 4 6 VIN – V 8 10 12 Figure 10. Switching Time vs. VIN (Bipolar Supply) Figure 13. Switching Time vs. VIN (Single Supply) 300 VIN = +5V 500 VIN = +5V 400 tTRANSITION tON 200 300 t – ns tON tTRANSITION tOFF t – ns 200 100 tOFF 100 0 ±5 ±7 ±9 ±11 ±13 ±15 ±17 ±19 ±21 0 5 7 9 11 SUPPLY VOLTAGE – Volts 13 15 SUPPLY VOLTAGE – Volts Figure 11. Switching Time vs. Bipolar Supply Figure 14. Switching Time vs. Single Supply – 8– REV. 0 ADG406/ADG407/ADG426 140 VDD = +15V 120 VSS = –15V 140 VDD = +15V 120 VSS = –15V OFF ISOLATION – dB 100 CROSSTALK – dB 3 100 80 80 60 60 40 2 10 10 10 4 10 5 10 6 10 7 40 10 2 10 3 10 4 10 5 10 6 10 7 FREQUENCY – Hz FREQUENCY – Hz Figure 15. OFF Isolation vs. Frequency Figure 16. Crosstalk vs. Frequency Test Circuits IDS VDD VSS V1 VDD S1 S2 D VSS ID (OFF) A VD EN VS +0.8V S D S16 VS RON = V1/IDS Test Circuit 1. On Resistance Test Circuit 3. ID (OFF) VDD VSS VDD VSS IS (OFF) A S1 S2 VDD VSS D VDD S1 VSS ID (ON) D A VD EN 2.4V S16 VS VD EN +0.8V S16 VS Test Circuit 2. IS (OFF) Test Circuit 4. ID (ON) REV. 0 – 9– ADG406/ADG407/ADG426 VDD VDD A3 VIN 50 Ω A2 A1 A0 2.4V EN RS GND WR VSS VSS S1 S2 THRU S15 S16 V2 VOUT RL 300 Ω CL 35pF VOUT 90% V1 3V ADDRESS DRIVE – V IN 50% 50% ADG426* D 90% tTRANSITION *SIMILAR CONNECTION FOR ADG406/ADG407 tTRANSITION Test Circuit 5. Switching Time of Multiplexer, tTRANSITION VDD VSS VDD A3 VIN 50 Ω VSS S1 VS 3V ADDRESS DRIVE – V IN A2 S2 THRU S15 A1 A0 RS 2.4V EN GND WR D RL 300Ω VOUT CL 35pF ADG426* S16 OUTPUT 0V 80% 80% tOPEN *SIMILAR CONNECTION FOR ADG406/ADG407 Test Circuit 6. Break-Before-Make Delay, tOPEN VDD VSS VDD A3 A2 A1 A0 2.4V RS EN VIN GND 50 Ω VSS S1 VS ENABLE DRIVE–V IN 0V 3V 50% 50% S2 THRU S16 ADG426* tOFF (EN) VO D WR RL 300 Ω VOUT CL 35pF OUTPUT 0V 90% 90% tON (EN) *SIMILAR CONNECTION FOR ADG406/ADG407 Test Circuit 7. Enable Delay, tON (EN), tOFF (EN) – 10– REV. 0 ADG406/ADG407/ADG426 VDD VSS VDD A3 VSS S1 VS 3V WR 0V D RL 300 Ω GND CL 35pF VOUT V0 OUTPUT 0V 50% A2 S2 THRU S16 A1 A0 2.4V EN RS VRS WR VWR ADG426 tON (WR) 0.2V0 Test Circuit 8. Write Turn-On Time, tON (WR) VDD VSS VDD A3 A2 A1 A0 2.4V EN RS VIN GND VSS S1 VS 3V RS 0V 50% S2 THRU S16 ADG426 V0 D WR RL 300 Ω VOUT CL 35pF tOFF (RS ) 0.8V 0 OUTPUT 0V Test Circuit 9. Reset Turn-Off Time, tOFF (RS) VDD VSS VDD A3 A2 A1 VSS RS 2.4V 3V ADG426* A0 S VS RS EN VIN D CL 1nF GND WR VOUT LOGIC INPUT (VIN ) ∆ VOUT QINJ = C L x ∆VOUT VOUT *SIMILAR CONNECTION FOR ADG406/ADG407 Test Circuit 10. Charge Injection REV. 0 – 11– ADG406/ADG407/ADG426 VDD VDD S16 A3 A2 A1 A0 2.4V RS EN GND WR D VSS RL 1kΩ VOUT 2.4V VDD S1 S16 VIN S2 VIN 1k Ω A0 A2 A3 EN RS GND WR VSS S1 VDD D 1kΩ VOUT ADG426* A1 ADG426* VSS *SIMILAR CONNECTION FOR ADG406/407 VSS *SIMILAR CONNECTION FOR ADG406/407 Test Circuit 11. OFF Isolation Test Circuit 12. Crosstalk OUTLINE DIMENSIONS Dimensions shown in inches an (mm). 28-Pin Plastic (N-28) 28-Pin PLCC (P-28A) 0.180 (4.57) 0.165 (4.19) 0.025 (0.63) 0.015 (0.38) 0.048 (1.21) 0.042 (1.07) 28 15 0.580 (14.73) 0.485 (12.32) 1 1.565 (39.70) 1.380 (35.10) 0.250 (6.35) MAX 0.200 (5.05) 0.125 (3.18) 0.022 (0.558) 0.014 (0.356) 0.100 (2.54) BSC 0.070 (1.77) MAX 14 0.625 (15.87) 0.600 (15.24) 0.195 (4.95) 0.125 (3.18) 0.015 (0.381) 0.008 (0.204) 0.056 (1.42) 0.042 (1.07) 26 0.048 (1.21) 0.042 (1.07) 5 4 PIN 1 IDENTIFIER 25 0.021 (0.53) 0.013 (0.33) 0.430 (10.92) 0.390 (9.91) 0.032 (0.81) 0.026 (0.66) PIN 1 0.050 (1.27) BSC TOP VIEW 0.060 (1.52) 0.015 (0.38) 0.150 (3.81) MIN SEATING PLANE 11 0.020 (0.50) R 12 0.456 (11.58) SQ 0.450 (11.43) 0.495 (12.57) SQ 0.485 (12.32) 18 19 0.040 (1.01) 0.025 (0.64) 0.110 (2.79) 0.085 (2.16) 28-Pin SSOP (RS-28) 28 15 0.212 (5.38) 0.205 (5.207) 0.311 (7.9) 0.301 (7.64) PIN 1 1 14 0.407 (10.34) 0.397 (10.08) 0.07 (1.78) 0.066 (1.67) 0.008 (0.203) 0.002 (0.050) 0.0256 (0.65) BSC 0.009 (0.229) 0.005 (0.127) 8° 0° 0.03 (0.762) 0.022 (0.558) 1. LEAD NO. 1 IDENTIFIED BY A DOT. 2. LEADS WILL BE EITHER TIN PLATED OR SOLDER DIPPED IN ACCORDANCE WITH MIL-M-38510 REQUIREMENTS – 12– REV. 0 PRINTED IN U.S.A. C1905–18–4/94