FEATURES
FUNCTIONAL BLOCK DIAGRAM
Fault and overvoltage protection up to ±40 V
Signal paths open circuit with power off
Signal path resistance of RON with power on
Supply maximum ratings (VDD to VSS): 44 V
Low on resistance (RON): 80 Ω typical
±1 nA maximum path current leakage at 25°C
Low power dissipation: 0.8 µW typical
Latch-up proof construction
VDD VSS
VIN
VIN
VD1
VS1
ADG465
VDD
VOUT
VOUT
VDD
OUTPUT CLAMPED
AT VDD – 1.5V
APPLICATIONS
09538-001
Data Sheet
Single Channel Protector
in a SOT-23 Package and a MSOP Package
ADG465
Figure 1.
ATE equipment
Sensitive measurement equipment
Hot insertion rack systems
ADC input channel protection
GENERAL DESCRIPTION
The ADG465 is a single channel protector that comes in SOT-23
and MSOP packages. The channel protector is in series with the
signal path and protects sensitive components from voltage
transience in the signal path whether or not the power supplies
are present. Because the channel protection works regardless of
the presence of the supplies, the channel protectors are ideal for
use in applications where correct power sequencing cannot
always be guaranteed to protect the analog inputs (for example, hot
insertion rack systems). See the Applications Information section
for further details.
A channel protector consists of an N channel, metal-oxide
semiconductor field-effect transistor (MOSFET), a P channel
MOSFET, and another N channel MOSFET connected in series.
The channel protector behaves like a series resistor during normal
operation, that is, (VSS + 1.5 V) < VIN < (VDD − 1.5 V). When the
analog input of a channel exceeds the power supplies (including
VDD and VSS = 0 V), one of the MOSFETs switches off, clamping
the output to either VSS + 1.5 V or VDD − 1.5 V. Circuitry and
signal source protection are provided in the event of an overvoltage
or power loss. The channel protectors can withstand overvoltage
inputs from −40 V to +40 V. See the Theory of Operation
section for further details.
Rev. C
The ADG465 can operate from both bipolar and unipolar supplies.
The channels are normally on when power is connected, and
open circuit when power is disconnected. With power supplies of
±15 V, the on resistance of the ADG465 is 80 Ω typical, with a
leakage current of ±1 nA maximum. When power is disconnected,
the input leakage current is approximately ±0.005 µA typical.
The ADG465 is available in a 6-lead SOT-23 package, and an
8-lead MSOP package.
PRODUCT HIGHLIGHTS
1.
2.
3.
4.
Fault Protection.
The ADG465 can withstand continuous voltage inputs from
−40 V to +40 V. When a fault occurs due to the power supplies
being turned off, or due to an overvoltage being applied to
the ADG465, the output is clamped. When power is turned
off, current is limited to the nanoampere level.
Low Power Dissipation.
Low RON 80 Ω typical.
Trench Isolation Latch-Up Proof Construction.
A dielectric trench separates the P channel and the
N channel MOSFETs thereby preventing latch up.
Document Feedback
Information furnished by Analog Devices is believed to be accurate and reliable. However, no
responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other
rights of third parties that may result from its use. Specifications subject to change without notice. No
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
Trademarks and registered trademarks are the property of their respective owners.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700 ©1997–2018 Analog Devices, Inc. All rights reserved.
Technical Support
www.analog.com
ADG465
Data Sheet
TABLE OF CONTENTS
Features .............................................................................................. 1
Typical Performance Characteristics ..............................................6
Applications ....................................................................................... 1
Test Circuits ........................................................................................8
Functional Block Diagram .............................................................. 1
Theory of Operation .........................................................................9
General Description ......................................................................... 1
Overvoltage Protection .................................................................9
Product Highlights ........................................................................... 1
Trench Isolation .......................................................................... 10
Revision History ............................................................................... 2
Applications Information .............................................................. 11
Specifications..................................................................................... 3
Overvoltage and Power Supply Sequencing Protection............ 11
Dual Supply ................................................................................... 3
High Voltage Surge Suppression .............................................. 11
Absolute Maximum Ratings............................................................ 4
Outline Dimensions ....................................................................... 12
Thermal Resistance ...................................................................... 4
Ordering Guide .......................................................................... 12
ESD Caution .................................................................................. 4
Pin Configurations and Function Descriptions ........................... 5
REVISION HISTORY
8/2018—Rev. B to Rev. C
Changes to VS, VD, Analog Input Overvoltage with Power Off
Parameter, Table 2............................................................................. 4
Change to High Voltage Surge Suppression Section ................. 11
12/2017—Rev. A to Rev. B
Updated Format .................................................................. Universal
Changes to Product Title and General Description Section....... 1
Changes to Table 1 ............................................................................ 3
Added Thermal Resistance Section and Table 3; Renumbered
Sequentially ....................................................................................... 4
Changes to Figure 2, Figure 3, and Table 4 ................................... 5
Changes to Figure 4 to Figure 8 ...................................................... 6
Added Figure 9; Renumbered Sequentially .................................. 6
Added Figure 10 ................................................................................7
Added Test Circuits Section and Figure 11 to Figure 13 ..............8
Changed Circuit Information Section to Theory of Operation
Section.................................................................................................9
Changes to Figure 16.........................................................................9
Changes to Overvoltage Protection ............................................. 10
Changes to Overvoltage and Power Supply Sequencing Protection
Section.............................................................................................. 11
Updated Outline Dimensions ....................................................... 12
Changes to Ordering Guide .......................................................... 12
1/1997—Revision 0: Initial Version
Rev. C | Page 2 of 12
Data Sheet
ADG465
SPECIFICATIONS
DUAL SUPPLY
VDD = +15 V, VSS = −15 V, GND = 0 V, unless otherwise noted.
Table 1.
Symbols
On Resistance
RON Flatness
LEAKAGE CURRENTS
Channel Output Leakage
(Without Fault Condition)
Channel Input Leakage (With
Fault Condition)
Channel Input Leakage (With
Power Off and Fault)
Channel Input Leakage (With
Power Off and Output Short
Circuit)
POWER REQUIREMENTS
Positive Supply Current
Negative Supply Current
Positive/Negative Power Supply
RON
80
99.5
8.5
IS (ON)
±0.1
±1
ID (ON)
±0.2
ID (OFF)
1
2
Min
25°C
Typ
Max
Parameter
FAULT PROTECTED CHANNEL
Fault Free Analog Signal Range1
−40°C to +85°C
Min
Typ Max
Unit
Test Conditions/Comments
VDD –
1.5
126.5
9
V
Output open circuit
Ω
Ω
−10 V ≤ VS2 ≤ +10 V, IS = 1 mA
−5 V ≤ VS2 ≤ +5 V
±1
±5
nA
VS2 = VD2 = ±10 V
±2
±0.4
±5
nA
VS2 = ±25 V, VD2 = open circuit
±0.5
±2
±2
±10
nA
ID (OFF)
±0.005
±0.015
±0.1
±0.5
µA
VDD = 0 V, VSS = 0 V, VS2 = ±35 V,
VD2 = open circuit
VDD = 0 V, VSS = 0 V, VS2 = ±35 V,
VD2 = 0 V
IDD
ISS
VDD/VSS
±0.05
±0.05
±0.5
±0.5
±20
±5
±5
±20
µA
µA
V
VSS +
1.5
0
0
Guaranteed by design, not subject to production test.
VS is the voltage at the source of the switch and VD is the voltage at the drain of the switch.
Rev. C | Page 3 of 12
ADG465
Data Sheet
ABSOLUTE MAXIMUM RATINGS
TA = 25°C, unless otherwise noted.
THERMAL RESISTANCE
Table 2.
θJA is specified for the worst-case conditions, that is, a device
soldered in a circuit board for surface-mount packages.
Parameter
VDD to VSS
VS, VD, Analog Input Overvoltage with
Power On1
VS, VD, Analog Input Overvoltage with
Power Off1
Continuous Current, S or D
Peak Current, S or D (Pulsed at 1 ms,
10% Duty Cycle Maximum)
Operating Temperature Range
Storage Temperature Range
Junction Temperature
Lead Temperature, Soldering
Vapor Phase (60 sec)
Infrared (15 sec)
1
Rating
44 V
VSS – 20 V to VDD + 20 V
−40 V to +40 V
Table 3. Thermal Resistance
Package Type
6-Lead SOT-231
8-Lead MSOP2
θJA
230
206
θJC
92
44
Unit
°C/W
°C/W
Thermal impedance simulated values are based on JEDEC 1S 2-layer test
board. See EIA/JEDEC standard JESD51.
2
Thermal impedance simulated values are based on JEDEC 2S2P 4-layer test
board. See EIA/JEDEC standard JESD51.
1
20 mA
40 mA
−40°C to +85°C
−65°C to +125°C
150°C
ESD CAUTION
215°C
220°C
The channel protector clamps overvoltages at the source (S) or the drain (D)
of the switch. See the Theory of Operation section for more information.
Stresses at or above those listed under Absolute Maximum
Ratings may cause permanent damage to the product. This is a
stress rating only; functional operation of the product at these
or any other conditions above those indicated in the operational
section of this specification is not implied. Operation beyond
the maximum operating conditions for extended periods may
affect product reliability.
Rev. C | Page 4 of 12
Data Sheet
ADG465
VD1 1
6
NIC 1
VDD
ADG465
5 NIC
TOP VIEW
(Not to Scale)
4 VS1
VSS 3
NIC 2
NIC
ADG465
7
VD1
VS1 3
TOP VIEW
(Not to Scale)
6
VSS
5
NIC
NIC 4
09538-002
NOTES
1. NIC = NOT INTERNALLY CONNECTED.
DO NOT CONNECT.
8
VDD 2
NOTES
1. NIC = NOT INTERNALLY CONNECTED.
DO NOT CONNECT.
Figure 2. 6-Lead SOT-23 Pin Configuration
09538-003
PIN CONFIGURATIONS AND FUNCTION DESCRIPTIONS
Figure 3. 8-Lead MSOP Pin Configuration
Table 4. Pin Function Descriptions
Pin No.
6-Lead SOT-23 8-Lead MSOP
1
7
Mnemonic
VD1
2, 5
3
1, 4, 5, 8
6
NIC
VSS
4
3
VS1
6
2
VDD
Description
One Terminal of the Channel Protector. The channel protector is bidirectional so this
terminal can be used as an input or an output.
Not Internally Connected. Do not connect.
Negative Power Supply (0 V to −20 V). The clamping point for a negative overvoltage is
also defined as VSS. See the Overvoltage Protection section.
One Terminal of the Channel Protector. The channel protector is bidirectional so this
terminal can be used as an input or an output.
Positive Power Supply (0 V to 20 V). The clamping point for a positive overvoltage is also
defined as VDD. See the Overvoltage Protection section.
Rev. C | Page 5 of 12
ADG465
Data Sheet
TYPICAL PERFORMANCE CHARACTERISTICS
30
150
POSITIVE OVERVOLTAGE ON INPUT
RLOAD = 100kΩ
CLOAD = 100pF
VDD = +10V
VSS = –10V
140
25
130
20
120
–5V TO +15V
STEP INPUT
VOLTAGE (V)
RON (Ω)
110
VDD = +5V
VSS = –5V
100
90
80
VDD = +10V
VSS = –10V
70
15
10
5
CHANNEL PROTECTOR
OUTPUT
0
60
50
–5
0
5
10
VS (V)
–10
09538-004
30
–10
TA = 25°C
0
150
200
250
300
350
400
450
500
Figure 7. Positive Overvoltage Transience Response
10
VDD = +15V
VSS = –15V
120
100
TIME (ns)
Figure 4. On Resistance (RON) vs. Input Voltage (VS) as a Function of VDD/VSS
130
50
09538-006
–5
VDD = +16.5V
VSS = –16.5V
40
5
110
0
90
TA = 125°C
80
TA = 80°C
70
CHANNEL PROTECTOR
OUTPUT
–5
–10
–15
NEGATIVE OVERVOLTAGE
ON INPUT
RLOAD = 100kΩ
CLOAD = 100pF
VDD = +10V
VSS = –10V
–20
60
TA = 25°C
50
–25
–5
0
5
10
VS (V)
–30
09538-005
40
–10
0
100
150
200
250
300
350
400
450
500
TIME (ns)
Figure 5. On Resistance (RON) vs. Input Voltage (VS) as a Function of
Temperature
Figure 8. Negative Overvoltage Transience Response
15
0
VDD = +15V
VSS = –15V
TA = 25°C
INPUT = 0dBm
–1
–10V TO +10V INPUT
10
–2
–3
INSERTION LOSS (dB)
VCLAMP = +4.5V
5
OUTPUT
0
–5
VCLAMP = –4.1V
–4
–5
–6
–7
–8
–9
–10
–11
RLOAD = 100kΩ
VDD = +5V
VSS = –5V
–15
0
100
200
–12
–13
300
400
500
600
700
TIME (ns)
800
900
1000
Figure 6. Overvoltage Ramp
–14
100
1k
10k
100k
1M
10M
100M
FREQUENCY (Hz)
Figure 9. Frequency Response (Magnitude)
Rev. C | Page 6 of 12
1G
09538-021
–10
09538-020
VOLTAGE (V)
50
+5V TO –15V
STEP INPUT
09538-007
VOLTAGE (V)
RON (Ω)
100
Data Sheet
ADG465
0
VDD = +15V
VSS = –15V
V p-p = 0.62V
TA = 25°C
–10
–20
ACPSRR (dB)
–30
NO DECOUPLING
CAPACITORS
–40
–50
–60
–70
DECOUPLING
CAPACITORS
ON SUPPLIES
–80
–100
100
1k
10k
100k
1M
10M
FREQUENCY (Hz)
09538-022
–90
Figure 10. AC Power Supply Rejection Ratio (ACPSRR) vs. Frequency,
±15 V Dual Supply
Rev. C | Page 7 of 12
ADG465
Data Sheet
TEST CIRCUITS
VDD
IDS
VSS
0.1µF
0.1µF
V1
NETWORK
ANALYZER
VSS
D
50Ω
S
IN
VS
RON = V1/IDS
VS
D
VIN
RL
50Ω
09538-023
NOTES
1. IDS IS THE CURRENT FROM THE SWITCH
DRAIN TO THE SWITCH SOURCE.
INSERTION LOSS = 20 log
ID (ON)
S
D
A
VD
NIC = NOT INTERNALLY CONNECTED.
09538-024
NC
VOUT WITH SWITCH
VOUT WITHOUT SWITCH
Figure 13. Bandwidth
Figure 11. On Resistance
Figure 12. On Leakage
Rev. C | Page 8 of 12
VOUT
09538-025
S
VDD
Data Sheet
ADG465
THEORY OF OPERATION
OVERVOLTAGE PROTECTION
Figure 14 shows a simplified schematic of a channel protector
circuit. The circuit is comprised of four metal-oxide semiconductor
(MOS) transistors: two negative metal-oxide semiconductor
(NMOS) and two positive metal-oxide semiconductor (PMOS).
One of the PMOS devices does not lie directly in the signal path;
however, it connects the source of the second PMOS device to
its back gate, which has the effect of lowering the threshold voltage
and increasing the input signal range of the channel for normal
operation. The source and back gate of the NMOS devices are
connected for the same reason. During normal operation, the
channel protectors have a resistance of 80 Ω typical. The channel
protectors are low power devices; even under fault conditions,
the supply current is limited to submicroampere levels. All
transistors are dielectrically isolated from each other using
trench isolation. Using trench isolation makes it impossible to
latch up the channel protectors. For further details, see the
Trench Isolation section.
When a fault condition occurs on the input of a channel protector,
the voltage on the input exceeds some threshold voltage set by
the supply rail voltages. The threshold voltages (VTP and VTN)
are related to the supply rails. For a positive overvoltage, the
threshold voltage is given by VDD − VTN, where VTN is the threshold
voltage of the NMOS transistor (1.5 V typical). For a negative
overvoltage, the threshold voltage is given by VSS − VTP, where
VTP is the threshold voltage of the PMOS device (1.5 V typical).
If the input voltage exceeds these threshold voltages, the output
of the channel protector (with no load) is clamped at these
threshold voltages. However, the channel protector output
clamps at a voltage inside these thresholds if the output is loaded.
For example, with an output load of 1 kΩ, VDD = 15 V and a
positive overvoltage. The output clamps at VDD − VTN − ΔV = 15
V − 1.5 V − 0.6 V = 12.9 V, where ΔV is due to IR voltage drops
across the channels of the MOS devices (see Figure 16). As
shown in Figure 16, the current during fault condition is
determined by the load on the output (that is, VCLAMP/RL).
However, if the supplies are off, the fault current is limited to
the nanoampere level.
VSS
PMOS
NMOS
VSS
09538-010
PMOS
VDD
The first NMOS transistor goes into a saturated mode of
operation as the voltage on its drain exceeds the gate voltage
(VDD) − the threshold voltage, VTN (see Figure 16). The potential
at the source of the NMOS device is equal to VDD − VTN. The
other MOS devices are in a nonsaturated mode of operation.
Figure 14. Channel Protector Circuit Schematic
VDD – VTN*
(+13.5V)
POSITIVE
OVERVOLTAGE
(+20V)
NMOS
PMOS
NONSATURATED
SATURATED
VDD (+15V)
NMOS
VSS (–15V)
NONSATURATED
VDD (+15V)
09538-011
*VTN = NMOS THRESHOLD VOLTAGE (+1.5V)
Figure 15. Positive Overvoltage on the Channel Protector
VD
VG
(+20V)
ΔV
VS
(+13.5V)
(VDD = +15V)
PMOS
OVERVOLTAGE
OPERATION
(SATURATED)
N+
EFFECTIVE
SPACE CHARGE
REGION
VT = 1.5V
P–
N+
N+
NMOS
NONSATURATED
OPERATION
N-CHANNEL
(VG – VT = 13.5V)
VCLAMP
IOUT
NOTES
1. VD IS THE VOLTAGE AT THE DRAIN OF THE SWITCH, VG IS THE VOLTAGE AT THE
GATE OF THE SWITCH, AND VS IS THE VOLTAGE AT THE SOURCE OF THE SWITCH.
Figure 16. Negative Overvoltage Operation on the Channel Protector
Rev. C | Page 9 of 12
RL
09538-012
VDD
Figure 15, Figure 18, and Figure 19 show the operating
conditions of the signal path transistors during various fault
conditions. Figure 15 shows how the channel protectors operate
when a positive overvoltage is applied to the channel protector.
NMOS
ADG465
Data Sheet
When a negative overvoltage is applied to the channel protector
circuit, the PMOS transistor enters a saturated mode of operation
as the drain voltage exceeds VSS − VTP (see Figure 18). As in the
case of the positive overvoltage, the other MOS devices are in a
nonsaturated mode of operation.
(CMOS) transistors. Latch up is caused when PN junctions that
are normally reverse biased become forward biased, causing
large currents to flow, which can be destructive.
CMOS devices are normally isolated from each other by junction
isolation. In junction isolation, the N and P wells of the CMOS
transistors form a diode that is reverse biased under normal
operation. However, during overvoltage conditions, this diode
becomes forward biased. Two transistors form a silicon-controlled
rectifier (SCR) type circuit, causing a significant amplification
of the current that, in turn, leads to latch up. With trench isolation,
this diode is removed, resulting in a latch-up proof circuit.
The channel protector is also functional when the supply
rails are down (for example, power failure) or momentarily
unconnected (for example, rack system). The channel protector is
in the off high impedance state with no supply rail voltage applied,
this known power supply state is where the channel protector has
an advantage over more conventional protection methods, such
as diode clamping (see the Applications Information section).
When VDD and VSS equal 0 V, all transistors are off, and the
current is limited to microampere levels (see Figure 19).
T
R
E
N
C
H
TRENCH ISOLATION
The MOS devices that make up the channel protector are isolated
from each other by an oxide layer (trench, see Figure 17). When
the NMOS and PMOS devices are not electrically isolated from
each other, there is a latch-up possibility caused by parasitic
junctions between complementary metal-oxide semiconductor
P+
VSS – VTP*
(–13V)
NMOS
SATURATED
VSS (–15V)
NONSATURATED
VDD (+15V)
Figure 18. Negative Overvoltage on the Channel Protector
0V
VDD (0V)
NMOS
OFF
OFF
VSS (0V)
VDD (0V)
Figure 19. Channel Protector Supplies Equal to 0 V
Rev. C | Page 10 of 12
09538-014
PMOS
OFF
N-CHANNEL
P–
Figure 17. Trench Isolation
*VTP = PMOS THRESHOLD VOLTAGE (+2V)
NMOS
N+
N+
T
R
E
N
C
H
09538-015
BURIED OXIDE LAYER
NONSATURATED
POSITIVE OR
NEGATIVE
OVERVOLTAGE
T
R
E
N
C
H
P+
VD
SUBSTRATE (BACKGATE)
PMOS
VDD (+15V)
P-CHANNEL
VS
09538-013
NMOS
VD
N–
NEGATIVE
OVERVOLTAGE
(–20V)
NEGATIVE
OVERVOLTAGE
(–20V)
VG
VG
VS
Data Sheet
ADG465
APPLICATIONS INFORMATION
The ADG465 is ideal for use in applications where input
overvoltage protection is required and correct power supply
sequencing cannot always be guaranteed. The overvoltage
protection ensures that the output voltage of the channel protector
does not exceed the threshold voltages set by the supplies (see
the Theory of Operation section) when there is an overvoltage
on the input. When the input voltage does not exceed these
threshold voltages, the channel protector behaves like a series
resistor (80 Ω typical). The resistance of the channel protector
does vary slightly with operating conditions (see the Typical
Performance Characteristics section).
When a voltage is not applied to VDD and VSS, the channel protector
is in an off state and presents high impedance, which is particularly
useful when considering power sequencing and protection of
downstream circuitry during a system power up. When there is
no voltage applied to the supply rails, all transistors in the channel
protector are off, and the only currents that flow are leakage
currents, which are at the microampere levels.
Figure 20 shows a typical application requiring overvoltage and
power supply sequencing protection. The application shows a
hot insertion rack system that involves plugging a circuit board
or module into a live rack via an edge connector. In this type of
application, it is not possible to guarantee correct power supply
sequencing. Power supplies must be connected prior to any
external signals for correct power supply sequencing. Incorrect
power sequencing can cause a CMOS device to latch up, which is
true of most CMOS devices, regardless of the functionality (see
the Trench Isolation section). Use RC networks on the supplies
of the channel protector (see Figure 20) to ensure that the rest of
the circuitry is powered up before the channel protectors. The
outputs of the channel protectors are clamped well below VDD and
VSS until the capacitors are charged. The diodes ensure that the
supplies on the channel protectors never exceed the supply rails
of the board when it is disconnected, and ensure that any signals
on the inputs of the CMOS devices never exceed the supplies.
HIGH VOLTAGE SURGE SUPPRESSION
The ADG465 is not intended for use in high voltage applications,
such as surge suppression. The ADG465 has breakdown voltages
of VSS − 20 V and VDD + 20 V on the inputs when the power
supplies are connected. When the power supplies are disconnected,
the breakdown voltages on the input of the channel protector
are ±40 V. In applications where inputs are likely to be subject
to overvoltages exceeding the breakdown voltages quoted for
the channel protectors, use transient voltage suppressors (TVSs).
These devices protect vulnerable circuits from electric overstress
such as that caused by electrostatic discharge, inductive load
switching, and induced lightning. However, TVSs can have a
substantial standby (leakage) current (300 µA typical) at the
reverse standoff voltage. The reverse standoff voltage of a TVS
is the normal peak operating voltage of the circuit. In addition,
TVSs offer no protection against latch up of sensitive CMOS
devices when the power supplies are off. To provide the best
leakage current specification and circuit protection, the best
solution is to use a channel protector in conjunction with a TVS.
Figure 21 shows an input protection scheme that uses both a TVS
and channel protector. The TVS is selected with a reverse standoff
voltage much greater than the operating voltage of the circuit
(TVSs with higher breakdown voltages tend to have better
standby leakage current specifications); however, inside the
breakdown voltage of the channel protector. This circuit protects
the circuitry whether or not the power supplies are present.
EDGE
CONNECTOR
VDD
+5V
VSS
–5V
ANALOG IN
–2.5V TO +2.5V
ADC
ADG465
LOGIC
GND
CONTROL
LOGIC
09538-016
LOGIC
Figure 20. Overvoltage and Power Supply Sequencing Protection
Rev. C | Page 11 of 12
VDD = +5V VSS = –5V
ADG465
ADC
TVSs
BREAKDOWN
VOLTAGE = 20V
Figure 21. High Voltage Protection
09538-017
OVERVOLTAGE AND POWER SUPPLY SEQUENCING
PROTECTION
ADG465
Data Sheet
OUTLINE DIMENSIONS
3.00
2.90
2.80
1.70
1.60
1.50
6
5
4
1
2
3
3.00
2.80
2.60
PIN 1
INDICATOR
0.95 BSC
1.90
BSC
1.30
1.15
0.90
0.20 MAX
0.08 MIN
0.15 MAX
0.05 MIN
10°
4°
0°
SEATING
PLANE
0.50 MAX
0.30 MIN
0.60
BSC
0.55
0.45
0.35
12-16-2008-A
1.45 MAX
0.95 MIN
COMPLIANT TO JEDEC STANDARDS MO-178-AB
Figure 22. 6-Lead Small Outline Transistor Package [SOT-23]
(RJ-6)
Dimensions shown in millimeters
3.20
3.00
2.80
8
3.20
3.00
2.80
1
5.15
4.90
4.65
5
4
PIN 1
IDENTIFIER
0.65 BSC
0.95
0.85
0.75
15° MAX
1.10 MAX
0.40
0.25
6°
0°
0.23
0.09
COMPLIANT TO JEDEC STANDARDS MO-187-AA
0.80
0.55
0.40
10-07-2009-B
0.15
0.05
COPLANARITY
0.10
Figure 23. 8-Lead Mini Small Outline Package [MSOP]
(RM-8)
Dimensions shown in millimeters
ORDERING GUIDE
Model1
ADG465BRTZ-REEL7
ADG465BRMZ
1
Temperature Range
−40°C to +85°C
−40°C to +85°C
Package Description
6-Lead Small Outline Transistor Package [SOT-23], Reel
8-Lead Mini Small Outline Package [MSOP], Reel
Z = RoHS Compliant Part.
©1997–2018 Analog Devices, Inc. All rights reserved. Trademarks and
registered trademarks are the property of their respective owners.
D09538-0-8/18(C)
Rev. C | Page 12 of 12
Marking Code
S1E
S1E
Package Option
RJ-6
RM-8
