ADG506AKP-REEL

a CMOS 8-/16-Channel Analog Multiplexers ADG506A/ADG507A FUNCTIONAL BLOCK DIAGRAM FEATURES 44 V Supply Maximum Rating V SS to VDD Analog Signal Range Single/Dual Supply Specifications Wide Supply Ranges (10.8 V to 16.5 V) Extended Plastic Temperature Range (–40ⴗC to +85ⴗC) Low Power Dissipation (28 mW max) Low Leakage (20 pA typ) Available in 28-Lead DIP, SOIC, PLCC, TSSOP and LCCC Packages Superior Alternative to: DG506A, Hl-506 DG507A, Hl-507 GENERAL DESCRIPTION The ADG506A and ADG507A are CMOS monolithic analog multiplexers with 16 channels and dual 8 channels, respectively. The ADG506A switches one of 16 inputs to a common output, depending on the state of four binary addresses and an enable input. The ADG507A switches one of eight differential inputs to a common differential output, depending on the state of three binary addresses and an enable input. Both devices have TTL and 5 V CMOS logic compatible digital inputs. The ADG506A and ADG507A are designed on an enhanced LC2MOS process, which gives an increased signal capability of VSS to VDD and enables operation over a wide range of supply voltages. The devices can operate comfortably anywhere in the 10.8 V to 16.5 V single or dual supply range. These multiplexers also feature high switching speeds and low RON. PRODUCT HIGHLIGHTS 1. Single/Dual Supply Specifications with a Wide Tolerance The devices are specified in the 10.8 V to 16.5 V range for both single and dual supplies. 2. Extended Signal Range The enhanced LC2MOS processing results in a high breakdown and an increased analog signal range of VSS to VDD. 3. Break-Before-Make Switching Switches are guaranteed break-before-make so input signals are protected against momentary shorting. ORDERING GUIDE Model1 Temperature Range Package Option2 ADG506AKN ADG506AKR ADG506AKP ADG506ABQ ADG506ATQ ADG506ATE –40°C to +85°C –40°C to +85°C –40°C to +85°C –40°C to +85°C –55°C to +125°C –55°C to +125°C N-28 R-28 P-28A Q-28 Q-28 E-28A ADG507AKN ADG507AKR ADG507AKP ADG507AKRU ADG507ABQ ADG507ATQ ADG507ATE –40°C to +85°C –40°C to +85°C –40°C to +85°C –40°C to +85°C –40°C to +85°C –55°C to +125°C –55°C to +125°C N-28 R-28 P-28A RU-28 Q-28 Q-28 E-28A NOTES 1 To order MIL-STD-883, Class B processed parts, add /883B to part number. See Analog Devices’ Military/Aerospace Reference Manual (1994) for military data sheet. 2 E = Leadless Ceramic Chip Carrier (LCCC); N = Plastic DIP; P = Plastic Leaded Chip Carrier (PLCC); Q = Cerdip; R = 0.3" Small Outline IC (SOIC); RU = Thin Shrink Small Outline Package (TSSOP). 4. Low Leakage Leakage currents in the range of 20 pA make these multiplexers suitable for high precision circuits. REV. C Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. Tel: 781/329-4700 World Wide Web Site: http://www.analog.com Fax: 781/326-8703 © Analog Devices, Inc., 1998 ADG506A/ADG507A–SPECIFICATIONS Dual Supply (V DD = +10.8 V to +16.5 V, VSS = –10.8 V to –16.5 V unless otherwise noted) Parameter ANALOG SWITCH Analog Signal Range RON ADG506A ADG506A ADG507A ADG507A K Version B Version –40ⴗC to –40ⴗC to +25ⴗC +85ⴗC +25ⴗC +85ⴗC ADG506A ADG507A T Version –55ⴗC to +25ⴗC +125ⴗC VSS VDD 280 450 300 VSS VDD 280 450 VSS VDD 300 0.6 5 400 RON Drift RON Match 0.6 5 IS (OFF), Off Input Leakage 0.02 1 0.04 1 1 0.04 1 1 ID (OFF), Off Output Leakage ADG506A ADG507A ID (ON), On Channel Leakage ADG506A ADG507A IDIFF, Differential Off Output Leakage (ADG507A Only) DIGITAL CONTROL VINH, Input High Voltage VINL, Input Low Voltage IINL or IINH CIN Digital Input Capacitance DYNAMIC CHARACTERISTICS tTRANSITION 1 tOPEN 1 tON (EN)1 tOFF (EN) 1 OFF Isolation CS (OFF) CD (OFF) ADG506A ADG507A QINJ, Charge Injection POWER SUPPLY IDD VSS VDD 600 400 50 200 100 200 100 0.02 1 0.04 1 1 0.04 1 1 50 200 100 200 100 0.02 1 0.04 1 1 0.04 1 1 600 V1 = ± 10 V, V2 = ⫿10 V; Test Circuit 5 2.4 0.8 1 2.4 0.8 1 2.4 0.8 1 V min V max µA max pF max 10 400 400 200 300 50 25 200 300 200 300 8 400 10 400 400 200 300 50 25 200 300 200 300 VDD = 15 V (± 10%), VSS = –15 V (± 10%) VDD = 15 V (± 5%), VSS = –15 V (± 5%) –10 V ≤ VS ≤ +10 V, IDS = 1 mA –10 V ≤ VS ≤ +10 V, IDS = 1 mA 200 100 200 100 nA max 400 –10 V ≤ VS ≤ +10 V, IDS = 1 mA; Test Circuit 1 V1 = ± 10 V, V2 = ⫿10 V; Test Circuit 2 25 8 Comments nA typ nA max nA typ nA max nA max nA typ nA max nA max 50 25 400 10 400 400 ns typ ns max ns typ ns min ns typ ns max ns typ ns max V1 = ± 10 V, V2 = ⫿10 V; Test Circuit 3 V1 = ± 10 V, V2 = ⫿10 V; Test Circuit 4 VIN = 0 to VDD V1 = ± 10 V, V2 = +10 V; Test Circuit 6 Test Circuit 7 Test Circuit 8 Test Circuit 8 68 50 5 68 50 5 68 50 5 dB typ dB min pF typ VEN = 0.8 V, RL = 1 kΩ, CL = 15 pF, VS = 7 V rms, f = 100 kHz VEN = 0.8 V 44 22 4 44 22 4 44 22 4 pF typ pF typ pC typ VEN = 0.8 V 0.6 0.6 20 0.6 1.5 20 0.2 Power Dissipation 600 400 V min V max Ω typ Ω max Ω max Ω max %/°C typ % typ 25 1.5 ISS VSS VDD 0.6 5 8 200 300 50 25 200 300 200 300 VSS VDD 280 450 300 Units 10 20 0.2 10 28 1.5 0.2 10 28 28 RS = 0 Ω, VS = 0 V; Test Circuit 9 mA typ VIN = VINL or VlNH mA max µA typ VIN = VIN or VINH mA max mW typ mW max NOTES 1 Sample tested at +25°C to ensure compliance. Specifications subject to change without notice. –2– REV. C Single Supply (V ADG506A/ADG507A DD = +10.8 V to +16.5 V, VSS = GND = 0 V unless otherwise noted) Parameter ANALOG SWITCH Analog Signal Range RON RON Drift RON Match IS (OFF), Off Input Leakage ID (OFF), Off Output Leakage ADG506A ADG507A ID (ON), On Channel Leakage ADG506A ADG507A IDIFF, Differential Off Output Leakage (ADG507A Only) DIGITAL CONTROL VINH, Input High Voltage VINL, Input Low Voltage IINL or IINH CIN Digital Input Capacitance DYNAMIC CHARACTERISTICS tTRANSITION 1 tOPEN 1 tON (EN)1 tOFF (EN) 1 OFF Isolation CS (OFF) CD (OFF) ADG506A ADG507A QINJ, Charge Injection POWER SUPPLY IDD ADG506A ADG506A ADG507A ADG507A K Version B Version –40ⴗC to –40ⴗC to +25ⴗC +85ⴗC +25ⴗC +85ⴗC ADG506A ADG507A T Version –55ⴗC to +25ⴗC +125ⴗC Units VSS VDD 500 700 0.6 5 VSS VDD 500 700 0.6 5 V min V max Ω typ 0 V ≤ VS ≤ +10 V, IDS = 0.5 mA; Test Circuit 1 Ω max %/°C typ 0 V ≤ VS ≤ +10 V, IDS = 0.5 mA % typ 0 V ≤ VS ≤ +10 V, IDS = 0.5 mA 0.02 1 0.04 1 1 0.04 1 1 VSS VDD 1000 50 200 100 200 100 VSS VDD 1000 0.02 1 0.04 1 1 0.04 1 1 200 100 200 100 1000 200 100 nA typ nA max nA typ nA max nA max nA typ nA max nA max 50 200 100 25 25 nA max 2.4 0.8 1 2.4 0.8 1 2.4 0.8 1 V min V max µA max pF max 8 600 10 600 600 8 300 450 50 25 250 450 250 450 300 450 50 25 250 450 250 450 600 10 600 600 600 10 600 600 V1 = +10 V/0 V, V2 = 0 V/ +10 V; Test Circuit 4 V1 = +10 V/0 V, V2 = 0 V/ +10 V; Test Circuit 5 VIN = 0 to VDD ns typ ns max ns typ ns min ns typ ns max ns typ ns max V1 = +10 V/0 V, V2 = +10 V; Test Circuit 6 Test Circuit 7 Test Circuit 8 Test Circuit 8 68 50 5 68 50 5 dB typ dB min pF typ VEN = 0.8 V, RL = 1 kΩ, CL = 15 pF, VS = 3.5 V rms, f = 100 kHz VEN = 0.8 V 44 22 4 44 22 4 44 22 4 pF typ pF typ pC typ VEN = 0.8 V 0.6 0.6 0.6 10 1.5 1.5 10 10 25 25 25 NOTES 1 Sample tested at +25°C to ensure compliance. Specifications subject to change without notice. RS = 0 Ω, VS = 0 V; Test Circuit 9 mA typ VIN = VINL or VlNH mA max mW typ mW max Truth Table (ADG506A) Truth Table (ADG507A) A3 EN On Switch A2 A1 A0 EN On Switch Pair 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 X 0 0 0 0 1 1 1 1 X 0 0 1 1 0 0 1 1 X 0 1 0 1 0 1 0 1 0 1 1 1 1 1 1 1 1 X 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 REV. C V1 = +10 V/0 V, V2 = 0 V/ +10 V; Test Circuit 2 V1 = +10 V/0 V, V2 = 0 V/ +10 V; Test Circuit 3 68 50 5 1.5 Power Dissipation 0.02 1 0.04 1 1 0.04 1 1 50 VSS VDD 25 8 300 450 50 25 250 450 250 450 VSS VDD 500 700 0.6 5 Comments A2 X 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 A1 X 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 A0 X 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 –3– NONE 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 X = Don’t Care NONE 1 2 3 4 5 6 7 8 ADG506A/ADG507A Power Dissipation (Any Package) Up to +75°C . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 470 mW Derates above +75°C by . . . . . . . . . . . . . . . . . . 6 mW/°C Operating Temperature Commercial (K Version) . . . . . . . . . . . . . . –40°C to +85°C Industrial (B Version) . . . . . . . . . . . . . . . . –40°C to +85°C Extended (T Version) . . . . . . . . . . . . . . . –55°C to +125°C Storage Temperature Range . . . . . . . . . . . . –65°C to +150°C Lead Temperature (Soldering, 10 secs) . . . . . . . . . . . . +300°C ABSOLUTE MAXIMUM RATINGS 1 (TA = 25°C unless otherwise noted) VDD to VSS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44 V VDD to GND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 V VSS to GND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –25 V Analog Inputs2 Voltage at S, D . . . . . . . . . . . . . . . . . . . . . . . VSS – 2 V to VDD . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . + 2 V or . . . . . . . . . . . . . . . . . . . . . . 20 mA, Whichever Occurs First Continuous Current, S or D . . . . . . . . . . . . . . . . . . . . . 20 mA Pulsed Current S or D 1 ms Duration, 10% Duty Cycle . . . . . . . . . . . . . . . . 40 mA Digital Inputs2 Voltage at A, EN . . . . . . . . . . . . . . . . . . . . . . . . . . VSS – 4 V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . to VDD + 4 V or . . . . . . . . . . . . . . . . . . . . . . 20 mA, Whichever Occurs First NOTES 1 Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. 2 Overvoltage at A, EN, S or D will be clamped by diodes. Current should be limited to the Maximum Rating above. CAUTION ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on the human body and test equipment and can discharge without detection. Although the ADG506A /ADG507A feature proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high energy electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance degradation or loss of functionality. WARNING! ESD SENSITIVE DEVICE PIN CONFIGURATIONS DIP, SOIC LCCC S6 ADG506A 24 S14 6 TOP VIEW 23 S5 S13 7 (Not to Scale) 22 S4 S15 5 25 S7 S14 6 24 S6 3 2 1 28 27 26 S8 VSS VDD D 4 PIN 1 IDENTIFIER S15 5 25 S7 S14 6 24 S6 ADG506A 23 S5 TOP VIEW (Not to Scale) 22 S4 S13 7 ADG506A 23 S5 21 S3 S12 8 TOP VIEW (Not to Scale) 22 S4 S13 7 S12 8 NC 28 27 26 S16 1 NC 2 S8 3 D 4 VSS 25 S7 NC 26 S8 S16 4 VDD 27 VSS NC 3 S16 NC 2 S15 5 PLCC 28 D NC VDD 1 S12 8 21 S3 S11 9 S11 9 20 S2 S10 10 20 S2 S11 9 21 S3 S10 10 19 S1 S9 11 19 S1 S10 10 20 S2 S9 11 19 S1 A0 18 EN 16 17 A1 14 15 A2 15 A2 NC = NO CONNECT NC GND 12 13 NC = NO CONNECT A3 EN A0 A1 16 A1 A3 14 A2 NC 13 12 13 14 15 16 17 18 A3 17 A0 NC 18 EN GND S9 11 GND 12 NC = NO CONNECT DIP, SOIC, TSSOP TOP VIEW 23 S5A S5B 7 (Not to Scale) 22 S4A S7B 5 25 S7A S6B 6 24 S6A S5A S5B 7 ADG507A 23 S4B 8 TOP VIEW (Not to Scale) 22 S4A 21 DA 4 3 2 1 28 27 26 VSS VDD 28 27 26 DB 1 S8B 2 NC S8A S6A ADG507A 24 S6B 6 3 DA S7B 5 4 VSS 25 S7A DB 26 S8A S8B 4 VDD 27 VSS NC 3 S8B DB 2 NC 28 DA S8A PLCC LCCC VDD 1 PIN 1 IDENTIFIER S7B 5 25 S7A S6B 6 24 S6A S5B 7 ADG507A 23 S5A S3A S4B 8 TOP VIEW (Not to Scale) 22 S4A S4B 8 21 S3A S3B 9 20 S2A S2B 10 20 S2A S3B 9 21 S3A S2B 10 19 S1A S1B 11 19 S1A S2B 10 20 S2A S1B 11 19 S1A NC = NO CONNECT 18 EN A0 16 17 A1 A2 14 15 NC NC NC = NO CONNECT 12 13 GND EN 15 A2 A0 NC 14 A1 16 A1 A2 NC 13 12 13 14 15 16 17 18 NC 17 A0 NC 18 EN GND S1B 11 GND 12 S3B 9 NC = NO CONNECT –4– REV. C Typical Performance Characteristics–ADG506A/ADG507A The multiplexers are guaranteed functional with reduced single or dual supplies down to 4.5 V. Figure 1. RON as a Function of VD (VS): Dual Supply Voltage, TA = +25 °C Figure 4. RON as a Function of VD (VS) Single Supply Voltage, TA = +25 °C Figure 2. Leakage Current as a Function of Temperature (Note: Leakage Currents Reduce as the Supply Voltages Reduce) Figure 5. Trigger Levels vs. Power Supply Voltage, Dual or Single Supply, TA = +25 °C Figure 3. tTRANSITION vs. Supply Voltage: Dual and Single Supplies, TA = + 25°C (Note: For VDD and /VSS / < 10 V; V1 = VDD /VSS, V2 = VSS /VDD. See Test Circuit 6) REV. C Figure 6. IDD vs. Supply Voltage: Dual or Single Supply, TA = +25 °C –5– ADG506A/ADG507A–Test Circuits Note: All Digital Input Signal Rise and Fall Times Measured from 10% to 90% of 3 V. tR = tF = 20 ns. Test Circuit 2. IS (OFF) Test Circuit 1. RON Test Circuit 3. ID (OFF) Test Circuit 5. IDIFF Test Circuit 4. ID (ON) Test Circuit 6. Switching Time of Multiplexer, tTRANSITION Test Circuit 7. Break-Before-Make Delay, tOPEN –6– REV. C ADG506A/ADG507A Test Circuit 8. Enable Delay, tON (EN), tOFF (EN) Test Circuit 9. Charge Injection SINGLE SUPPLY AUTOMOTIVE APPLICATION The excellent performance of the multiplexers under single supply conditions makes the ADG506A/ADG507A suitable in applications such as automotive and disc drives where only positive power supply voltages are normally available. The following application circuit shows the ADG507A connected as an 8-channel differential multiplexer in an automotive, data acquisition application circuit. The AD7580 is a 10-bit successive approximation ADC, which has an on-chip sample-hold amplifier and provides a conversion result in 20 µs. The ADC has differential analog inputs and is configured in the application circuit for a span of 2.5 V over a common-mode range 0 V to + 5 V. Wider common-mode ranges can be accommodated. See the AD7579/AD7580 data sheet for more details. The complete system operates from +12 V (+10%) and +5 V supplies. The analog input signals to the ADG507A contain information such as temperature, pressure, speed etc. Figure 7. ADG507A in a Single Supply Automotive Data Acquisition Application REV. C –7– TERMINOLOGY tOFF (EN) RON RON Match RON Drift IS (OFF) tTRANSITION Ohmic resistance between terminals D and S Difference between the RON of any two channels Change in RON versus temperature Source terminal leakage current when the switch is off Drain terminal leakage current when the switch is off Leakage current that flows from the closed switch into the body Analog voltage on terminal S or D Channel input capacitance for “OFF” condition Channel output capacitance for “OFF” condition Digital input capacitance Delay time between the 50% and 90% points of the digital input and switch “ON” condition ID (OFF) ID (ON) VS (VD) CS (OFF) CD (OFF) CIN tON (EN) Delay time between the 50% and 10% points of the digital input and switch “OFF” condition Delay time between the 50% and 90% points of the digital inputs and switch “ON” condition when switching from one address state to another “OFF” time measured between 50% points of both switches when switching from one address state to another Maximum input voltage for Logic “0” Minimum input voltage for Logic “1” Input current of the digital input Most positive voltage supply Most negative voltage supply Positive supply current Negative supply current tOPEN VINL VINH IINL (IINH) VDD VSS IDD ISS C1150c–0–6/98 ADG506A/ADG507A OUTLINE DIMENSIONS Dimensions shown in inches and (mm). 28-Lead Cerdip (Suffix Q) 28-Lead Plastic DIP (Suffix N) 1.490 (37.84) MAX 0.550 (13.97) 0.53 (13.47) 0.525 (13.33) 0.515 (13.08) 1.45(36.83) 1.44 (36.58) 0.606 (15.4) 0.594 (15.09) 0.16 (4.07) 0.14 (3.56) 0.22 (5.59) GLASS MAX SEALANT 0.2 (5.08) MAX 0.020 (0.508) 0.105 (2.67) 0.015 (0.381) 0.095 (2.42) 0.012 (0.305) 0.175 (4.45) 0.008 (0.203) 0.12 (3.05) 0.11 (2.79) 0.099 (2.28) 0.386 (9.80) 0.378 (9.60) 0.1043 (2.65) 0.0926 (2.35) PIN 1 IDENTIFIER 8° 0.0500 (1.27) 0.0192 (0.49) 0° 0.0157 (0.40) SEATING 0.0125 (0.32) 0.0138 (0.35) PLANE 0.0091 (0.23) 26 25 TOP VIEW 11 12 19 18 0.456 (11.582) 0.450 (11.430) SQ 0.498 (12.57) SQ 0.485 (12.32) 14 SEATING PLANE 0.0433 (1.10) MAX 0.0256 (0.65) 0.0118 (0.30) BSC 0.0075 (0.19) 0.028 (0.70) 0.020 (0.50) 8° 0° 0.0079 (0.20) 0.0035 (0.090) 28-Terminal Leadless Ceramic Chip Carrier (Suffix E) 0.050 ⴞ0.005 01.27 ⴞ0.13 0.021 (0.533) 0.430 (10.5) 0.013 (0.331) 0.390 (9.9) 0.032 (0.812) 0.026 (0.661) (PINS DOWN) 1 PIN 1 0.006 (0.15) 0.002 (0.05) 0.0291 (0.74) x 45° 0.0098 (0.25) 28-Terminal Plastic Leaded Chip Carrier (Suffix P) 4 15 0.256 (6.50) 0.246 (6.25) 14 28 0.177 (4.50) 0.169 (4.30) 1 0.4193 (10.65) 0.3937 (10.00) 15 0.2992 (7.60) 0.2914 (7.40) 28 5 0.012 (0.305) 0.008 (0.203) 15° 0° 28-Lead TSSOP (Suffix RU) 0.7125 (18.10) 0.6969 (17.70) 0.0500 (1.27) BSC 0.02 (0.5) 0.016 (0.406) 0.18(4.57) MAX LEAD NO. 1 IDENTIFIED BY DOT OR NOTCH LEADS ARE SOLDER OR TIN PLATED KOVAR OR ALLOY 42 28-Lead SOIC (Suffix R) 0.0118 (0.30) 0.0040 (0.10) 0.125 (3.175) MIN 15ⴗ 0 LEAD NO. 1 IDENTIFIED BY DOT OR NOTCH LEADS ARE SOLDER OR TIN PLATED KOVAR OR ALLOY 42 PIN 1 0.62 (15.74) 0.59 (14.93) 0.075 (1.91) REF 0.100 (2.54) 0.064 (1.63) 0.458 (11.63) 0.442 (11.23) 0.458 SQ (11.63) MAX SQ 0.120 (3.04) 0.090 (2.29) 0.180 (4.51) 0.165 (4.20) 0.095 (2.41) 0.075 (1.90) 0.011 (0.28) 0.007 (0.18) R TYP 0.075 (1.91) REF 0.088 (2.24) 0.054 (1.37) –8– 26 2 5 0.300 (7.62) BSC 0.150 (3.51) BSC 4 28 5 1 BOTTOM VIEW 19 18 0.055 (1.40) 0.045 (1.14) 12 11 0.200 (5.08) BSC 0.015 (0.38) MIN 0.028 (0.71) 0.022 (0.56) 0.050 (1.27) BSC 45° TYP REV. C PRINTED IN U.S.A. 0.065 (1.66) 0.045 (1.15) 0.06 (1.52) 0.05 (1.27)