4-Channel/8-Channel
Fault-Protected Analog Multiplexers
ADG508F/ADG509F/ADG528F
FEATURES
FUNCTIONAL BLOCK DIAGRAMS
Low on resistance (300 Ω typical)
Fast switching times
tON 250 ns maximum
tOFF 250 ns maximum
Low power dissipation (3.3 mW maximum)
Fault and overvoltage protection (−40 V to +55 V)
All switches off with power supply off
Analog output of on channel clamped within power
supplies if an overvoltage occurs
Latch-up proof construction
Break-before-make construction
TTL and CMOS compatible inputs
ADG508F/
ADG528F
ADG509F
S1
S1A
DA
S4A
D
S1B
DB
S4B
S8
1 OF 4
DECODER
A0 A1 A2 EN
A0 A1 EN
00035-101
APPLICATIONS
1 OF 8
DECODER
00035-001
ADG528F WR
ONLY RS
Figure 1.
Existing multiplexer applications (both fault-protected and
nonfault-protected)
New designs requiring multiplexer functions
GENERAL DESCRIPTION
The ADG508F, ADG509F, and ADG528F are CMOS analog
multiplexers, with the ADG508F and ADG528F comprising
eight single channels and the ADG509F comprising four
differential channels. These multiplexers provide fault protection. Using a series n-channel, p-channel, n-channel MOSFET
structure, both device and signal source protection is provided
in the event of an overvoltage or power loss. The multiplexer
can withstand continuous overvoltage inputs from −40 V to
+55 V. During fault conditions, the multiplexer input (or output) appears as an open circuit and only a few nanoamperes of
leakage current will flow. This protects not only the multiplexer
and the circuitry driven by the multiplexer, but also protects
the sensors or signal sources that drive the multiplexer.
The ADG508F and ADG528F switch one of eight inputs to a
common output as determined by the 3-bit binary address lines
A0, A1, and A2. The ADG509F switches one of four differential
inputs to a common differential output as determined by the
2-bit binary address lines A0 and A1. The ADG528F has onchip address and control latches that facilitate microprocessor
interfacing. An EN input on each device is used to enable or
disable the device. When disabled, all channels are switched off.
PRODUCT HIGHLIGHTS
1.
2.
3.
4.
5.
6.
Fault Protection.
The ADG508F/ADG509F/ADG528F can withstand
continuous voltage inputs from −40 V to +55 V. When a
fault occurs due to the power supplies being turned off, all
the channels are turned off and only a leakage current of a
few nanoamperes flows.
On channel turns off while fault exists.
Low RON.
Fast switching times.
Break-before-make switching.
Switches are guaranteed break-before-make so that input
signals are protected against momentary shorting.
Trench isolation eliminates latch-up.
A dielectric trench separates the p and n-channel
MOSFETs thereby preventing latch-up.
Rev. E
Information furnished by Analog Devices is believed to be accurate and reliable. However, no
responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other
rights of third parties that may result from its use. Specifications subject to change without notice. No
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
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One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700
www.analog.com
Fax: 781.461.3113 ©2001–2009 Analog Devices, Inc. All rights reserved.
ADG508F/ADG509F/ADG528F
TABLE OF CONTENTS
Features .............................................................................................. 1
Absolute Maximum Ratings ............................................................6
Applications ....................................................................................... 1
ESD Caution...................................................................................6
Functional Block Diagrams ............................................................. 1
Pin Configuration and Function Descriptions..............................7
General Description ......................................................................... 1
Typical Performance Characteristics ..............................................8
Product Highlights ........................................................................... 1
Terminology .................................................................................... 10
Revision History ............................................................................... 2
Theory of Operation ...................................................................... 11
Specifications..................................................................................... 3
Test Circuits ..................................................................................... 12
Dual Supply ................................................................................... 3
Outline Dimensions ....................................................................... 15
Truth Tables ................................................................................... 4
Ordering Guide .......................................................................... 18
Timing Diagrams.......................................................................... 5
REVISION HISTORY
7/09—Rev. D: Rev. E
Updated Format .................................................................. Universal
Added TSSOP ..................................................................... Universal
Updated Outline Dimensions ....................................................... 15
Changes to Ordering Guide .......................................................... 18
4/01—Data Sheet Changed from Rev. C to Rev. D.
Changes to Ordering Guide ............................................................ 1
Changes to Specifications Table ...................................................... 2
Max Ratings Changed ...................................................................... 4
Deleted 16-Lead Cerdip from Outline Dimensions .................. 11
Deleted 18-Lead Cerdip from Outline Dimensions .................. 12
Rev. E | Page 2 of 20
ADG508F/ADG509F/ADG528F
SPECIFICATIONS
DUAL SUPPLY
VDD = +15 V ± 10%, VSS = −15 V ± 10%, GND = 0 V, unless otherwise noted.
Table 1.
Parameter
ANALOG SWITCH
Analog Signal Range
RON
RON Drift
RON Match
LEAKAGE CURRENTS
Source OFF Leakage IS (OFF)
Drain OFF Leakage ID (OFF)
ADG508F/ADG528F
ADG509F
Channel ON Leakage ID, IS (ON)
ADG508F/ADG528F
ADG509F
FAULT
Output Leakage Current
(With Overvoltage)
Input Leakage Current
(With Overvoltage)
Input Leakage Current
(With Power Supplies OFF)
DIGITAL INPUTS
Input High Voltage, VINH
Input Low Voltage, VINL
Input Current, IINL or IINH
CIN, Digital Input Capacitance
DYNAMIC CHARACTERISTICS 1
tTRANSITION
tOPEN
tON (EN, WR)
tOFF (EN, RS)
tSETT, Settling Time
0.1%
0.01%
ADG528F Only
tW, Write Pulse Width
tS, Address, Enable Setup Time
tH, Address, Enable Hold Time
tRS, Reset Pulse Width
+25°C
300
B Version
−40°C to +85°C
Unit
VSS + 3
VDD − 1.5
350
V min
V max
Ω typ
400
Ω max
Test Conditions/Comments
−10 V ≤ VS ≤ +10 V, IS = 1 mA;
VDD = +15 V ± 10%, VSS = −15 V ± 10%
−10 V ≤ VS ≤ +10 V, IS = 1 mA;
VDD = +15 V ± 5%, VSS = −15 V ± 5%
VS = 0 V, IS = 1 mA
VS = 0 V, IS = 1 mA
0.6
5
%/°C typ
% max
±0.02
±1
±0.04
±1
±1
±0.04
±1
±1
nA typ
nA max
nA typ
nA max
nA max
nA typ
nA max
nA max
VD = ±10 V, VS = +10 V;
See Figure 22
VD = ±10 V, VS = +10 V;
See Figure 23
nA typ
μA max
μA typ
μA max
μA typ
μA max
VS = ±33 V, VD = 0 V, see Figure 23
±0.02
±2
±0.005
±2
±0.001
±2
±50
±60
±30
±60
±30
±2
2.4
0.8
±1
5
200
300
50
25
200
250
200
250
100
V min
V max
μA max
pF typ
400
1
2.5
ns typ
ns max
ns typ
ns min
ns typ
ns max
ns typ
ns max
μs typ
μs typ
120
100
10
100
ns min
ns min
ns min
ns min
400
10
400
Rev. E | Page 3 of 20
VS = VD = ± 10 V;
See Figure 24
VS = ±25 V, VD = +10 V, see Figure 25
VS = ±25 V, VD = VEN = A0, A1, A2 = 0 V
See Figure 26
VIN = 0 or VDD
RL = 1 MΩ, CL = 35 pF;
VS1 = ±10 V, VS8 = +10 V; see Figure 27
RL = 1 kΩ, CL = 35 pF;
VS = 5 V; see Figure 28
RL = 1 kΩ, CL = 35 pF;
VS = 5 V; see Figure 29
RL = 1 kΩ, CL = 35 pF;
VS = 5 V; see Figure 29
RL = 1 kΩ, CL = 35 pF;
VS = 5 V
ADG508F/ADG509F/ADG528F
Parameter
Charge Injection
OFF Isolation
+25°C
4
68
50
5
CS (OFF)
CD (OFF)
ADG508F/ADG528F
ADG509F
POWER REQUIREMENTS
IDD
ISS
1
B Version
−40°C to +85°C
50
25
Unit
pC typ
dB typ
dB min
pF typ
Test Conditions/Comments
VS = 0 V, RS = 0 Ω,CL= 1 nF; see Figure 32
RL = 1 kΩ, CL = 15 pF, f = 100 kHz;
VS = 7 V rms; see Figure 33
pF typ
pF typ
0.1
0.1
0.2
0.1
mA max
mA max
VIN = 0 V or 5 V
Guaranteed by design, not subject to production test.
TRUTH TABLES
Table 2. ADG508F Truth Table
A2
X
0
0
0
0
1
1
1
1
A1
X
0
0
1
1
0
0
1
1
A0
X
0
1
0
1
0
1
0
1
EN
0
1
1
1
1
1
1
1
1
ON Switch
None
1
2
3
4
5
6
7
8
X = Don’t Care
Table 3. ADG509F Truth Table
A1
X
0
0
1
1
A0
X
0
1
0
1
EN
0
1
1
1
1
ON Switch Pair
None
1
2
3
4
X = Don’t Care
Table 4. ADG528F Truth Table
A2
X
X
X
0
0
0
0
1
1
1
1
A1
X
X
X
0
0
1
1
0
0
1
1
A0
X
X
X
0
1
0
1
0
1
0
1
EN
X
X
0
1
1
1
1
1
1
1
1
WR
RS
X
0
0
0
0
0
0
0
0
0
1
0
1
1
1
1
1
1
1
1
1
ON Switch
Retains previous switch condition
None (address and enable latches cleared)
None
1
2
3
4
5
6
7
8
X = Don’t Care
Rev. E | Page 4 of 20
ADG508F/ADG509F/ADG528F
TIMING DIAGRAMS
Figure 2 shows the timing sequence for latching the switch address and enable inputs. The latches are level sensitive; therefore, while WR
is held low, the latches are transparent and the switches respond to the address and enable inputs. This input data is latched on the rising
edge of WR.
3V
WR
50%
50%
0V
tW
tS
tH
3V
00035-002
2V
A0, A1, A2
EN
0.8V
0V
.
Figure 2. ADG528F Timing Sequence for Latching the Switch Address and Enable Inputs
Figure 3 shows the reset pulsewidth, tRS, and the reset turnoff time, tOFF (RS). Note that all digital input signals rise and fall times are
measured from 10% to 90% of 3 V. tR = tF = 20 ns.
3V
RS
50%
50%
0V
tRS
tOFF (RS)
VO
0.8VO
00035-003
SWITCH
OUTPUT
0V
Figure 3. ADG528F Reset Pulse Width
Rev. E | Page 5 of 20
ADG508F/ADG509F/ADG528F
ABSOLUTE MAXIMUM RATINGS
TA = +25°C unless otherwise noted.
Table 5.
Parameter
VDD to VSS
VDD to GND
VSS to GND
Digital Input, EN, Ax
VS, Analog Input Overvoltage with
Power On
VS, Analog Input Overvoltage with
Power Off
Continuous Current, S or D
Peak Current, S or D
(Pulsed at 1 ms, 10% Duty Cycle Max)
Operating Temperature Range
Industrial (B Version)
Storage Temperature Range
Junction Temperature
TSSOP
θJA, Thermal Impedance
Plastic Package
θJA, Thermal Impedance
16-Lead
18-Lead
Lead Temperature, Soldering (10 sec)
SOIC Package
θJA, Thermal Impedance
Narrow Body
Wide Body
Lead Temperature, Soldering
Vapor Phase (60 sec)
Infrared (15 sec)
PLCC Package
θJA, Thermal Impedance
Lead Temperature, Soldering
Vapor Phase (60 sec)
Infrared (15 sec)
Rating
44 V
−0.3 V to +25 V
+0.3 V to −25 V
−0.3 V to VDD + 2 V or 20 mA,
whichever occurs first
VSS − 25 V to VDD + 40 V
Stresses above those listed under Absolute Maximum Ratings
may cause permanent damage to the device. This is a stress
rating only; functional operation of the device at these or any
other conditions above those indicated in the operational
section of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect
device reliability.
ESD CAUTION
−40 V to +55 V
20 mA
40 mA
−40°C to +85°C
−65°C to +150°C
150°C
112°C/W
117°C/W
110°C/W
260°C
77°C/W
75°C/W
215°C
220°C
90°C/W
215°C
220°C
Rev. E | Page 6 of 20
ADG508F/ADG509F/ADG528F
PIN CONFIGURATION AND FUNCTION DESCRIPTIONS
A0 1
16 A1
WR 1
18 RS
EN 2
15 A2
A0 2
17 A1
14 GND
EN 3
TOP VIEW 13 VDD
S2 5 (Not to Scale) 12 S5
16 A2
VSS 4
S1 4
15 GND
ADG528F
S1 5
11 S6
S4 7
10 S7
S3 7
TOP VIEW 13 S1B
S2A 5 (Not to Scale) 12 S2B
S3A 6
11 S3B
S4A 7
10 S4B
DA 8
9
DB
00035-005
S1A 4
EN
4
VSS
5
S1
6
S2
7
S3
8
RS
A1
3
2
1
20
19
PIN 1
INDENTFIER
ADG528F
TOP VIEW
(Not to Scale)
9
10
11
12
13
S7
14 VDD
NC
15 GND
ADG509F
WR
16 A1
S8
VSS 3
10 S8
NC
A0 1
11 S7
D 9
Figure 6. ADG528F Pin Configuration
DIP
Figure 4. ADG508F Pin Configuration
TSSOP/DIP/SOIC
EN 2
12 S6
S4 8
A0
S8
D
9
S4
D 8
00035-004
S3 6
TOP VIEW 14 VDD
S2 6 (Not to Scale) 13 S5
00035-006
ADG508F
NC = NO CONNECT
Figure 5. ADG509F Pin Configuration
TSSOP/DIP/SOIC
18
A2
17
GND
16
VDD
15
S5
14
S6
00035-007
VSS 3
Figure 7. ADG528F Pin Configuration
PLCC
Rev. E | Page 7 of 20
ADG508F/ADG509F/ADG528F
TYPICAL PERFORMANCE CHARACTERISTICS
2000
2000
TA = 25°C
1750
1500
1500
1250
VDD = +5V
VSS = –5V
1000
RON (Ω)
750
750
TA = 85°C
VDD = +10V
VSS = –10V
250
00035-008
250
0
–15
–10
–5
0
VD, VS (V)
5
10
TA = 25°C
0
–15
15
Figure 8. On Resistance as a Function of VD (VS)
–5
0
VD, VS (V)
5
10
15
1m
100µ
100µ
VDD = 0V
VSS = 0V
VD = 0V
1µ
100n
10n
OPERATING RANGE
1n
VDD = +15V
VSS = –15V
VD = 0V
10µ
IS INPUT LEAKAGE (A)
10µ
100p
1µ
100n
10n
OPERATING RANGE
1n
100p
00035-009
10p
–40
–30
–20
–10
0
10
20
30
VIN INPUT VOLTAGE (V)
40
50
10p
1p
–50
60
Figure 9. Input Leakage Current as a Function of VS (Power Supplies Off)
During Overvoltage Conditions
00035-012
IS INPUT LEAKAGE (A)
–10
Figure 11. On Resistance as a Function of VD (VS) for Different Temperatures
1m
–40
–30
–20
–10
0
10
20
INPUT VOLTAGE (V)
30
40
50
60
Figure 12. Input Leakage Current as a Function of VS (Power Supplies On)
During Overvoltage Conditions
1m
0.3
100µ
VDD = +15V
VSS = –15V
VD = 0V
1µ
100n
10n
1n
VDD = +15V
VSS = –15V
TA = 25°C
0.2
LEAKAGE CURRENTS (nA)
10µ
ID INPUT LEAKAGE (A)
TA = 125°C
500
00035-011
500
OPERATING RANGE
100p
IS (OFF)
0.1
IS (OFF)
0.0
IS (ON)
–0.1
00035-010
10p
1p
–50
1000
–40
–30
–20
–10
0
10
20
30
VIN INPUT VOLTAGE (V)
40
50
–0.2
–14
60
Figure 10. Output Leakage Current as a Function of VS (Power Supplies On)
During Overvoltage Conditions
Rev. E | Page 8 of 20
00035-013
RON (Ω)
1250
1p
–50
VDD = +15V
VSS = –15V
1750
–10
–6
–2
2
VS, VD (V)
6
10
Figure 13. Leakage Currents as a Function of VD (VS)
14
ADG508F/ADG509F/ADG528F
280
1
IS (OFF)
0.01
45
55
65
75
85
95
TEMPERATURE (°C)
105
115
125
tON (EN)
180
tTRANSITION
tOFF (EN)
120
100
00035-015
SWITCHING TIME (ns)
220
140
10
11
12
13
POWER SUPPLY (V)
14
tOFF (EN)
25
45
65
85
TEMPERATURE (°C)
105
Figure 16. Switching Time vs. Temperature
VIN = 2V
160
160
100
260
200
tTRANSITION
180
120
Figure 14. Leakage Currents as a Function of Temperature
240
200
140
ID (ON)
35
220
15
Figure 15. Switching Time vs. Power Supply
Rev. E | Page 9 of 20
00035-016
0.1
25
tON (EN)
240
ID (OFF)
SWITCHING TIME (ns)
10
VDD = +15V
VSS = –15V
VIN = +5V
260
VDD = +15V
VSS = –15V
VD = +10V
VS = –10V
00035-014
LEAKAGE CURRENTS (nA)
100
125
ADG508F/ADG509F/ADG528F
TERMINOLOGY
VDD
Most Positive Power Supply Potential.
VSS
Most Negative Power Supply Potential.
GND
Ground (0 V) Reference.
RON
Ohmic Resistance between D and S.
RON Drift
Change in RON when temperature changes by one degree
Celsius.
RON Match
Difference between the RON of any two channels.
IS (OFF)
Source leakage current when the switch is off.
ID (OFF)
Drain leakage current when the switch is off.
ID, IS (ON)
Channel leakage current when the switch is on.
VD (VS)
Analog Voltage on Terminals D, S.
tON (EN)
Delay time between the 50% and 90% points of the digital input
and switch on condition.
tOFF (EN)
Delay time between the 50% and 90% points of the digital input
and switch off condition.
tTRANSITION
Delay time between the 50% and 90% points of the digital
inputs and the switch on condition when switching from one
address state to another.
tOPEN
“OFF” time measured between 80% points of both switches
when switching from one address state to another.
VINL
Maximum input voltage for Logic 0.
VINH
Minimum input voltage for Logic 1.
IINL (IINH)
Input current of the digital input.
Off Isolation
A measure of unwanted signal coupling through an off channel.
CS (OFF)
Channel input capacitance for off condition.
Charge Injection
A measure of the glitch impulse transferred from the digital
input to the analog output during switching.
CD (OFF)
Channel output capacitance for off condition.
IDD
Positive Supply Current.
CD, CS (ON)
On Switch Capacitance.
ISS
Negative Supply Current.
CIN
Digital Input Capacitance.
Rev. E | Page 10 of 20
ADG508F/ADG509F/ADG528F
THEORY OF OPERATION
During fault conditions, the leakage current into and out of the
ADG508F/ADG509F/ADG528F is limited to a few microamps.
This protects the multiplexer and succeeding circuitry from
over stresses as well as protecting the signal sources which drive
the multiplexer. Also, the other channels of the multiplexer will
be undisturbed by the overvoltage and will continue to operate
normally.
When the power supplies are present but the channel is off,
again either the p-channel MOSFET or one of the n-channel
MOSFETs will turn off when an overvoltage occurs.
Rev. E | Page 11 of 20
VSS
Figure 17. +55 V Overvoltage Input to the On Channel
–40V
OVERVOLTAGE
Q1
n-CHANNEL
MOSFET IS
ON
VSS
Q2
VDD
Q3
p-CHANNEL
MOSFET IS
OFF
Figure 18. −40 V Overvoltage on an Off Channel with
Multiplexer Power On
+55V
OVERVOLTAGE
Q1
Q2
Q3
n-CHANNEL
MOSFET IS
OFF
Figure 19. +55 V Overvoltage with Power Off
–40V
OVERVOLTAGE
Finally, when the power supplies are off, the gate of each
MOSFET will be at ground. A negative overvoltage switches
on the first n-channel MOSFET but the bias produced by the
overvoltage causes the p-channel MOSFET to remain turned
off. With a positive overvoltage, the first MOSFET in the series
will remain off since the gate to source voltage applied to this
MOSFET is negative.
Q3
00035-017
n-CHANNEL
MOSFET IS
OFF
VDD
Q2
00035-018
Figure 17 to Figure 20 show the conditions of the three MOSFETs
for the various overvoltage situations. When the analog input
applied to an ON channel approaches the positive power supply
line, the n-channel MOSFET turns OFF since the voltage on
the analog input exceeds the difference between VDD and the
n-channel threshold voltage (VTN). When a voltage more negative than VSS is applied to the multiplexer, the p-channel
MOSFET will turn off since the analog input is more negative
than the difference between VSS and the p-channel threshold
voltage (VTP). Since VTN is nominally 1.5 V and VTP is typically
3 V, the analog input range to the multiplexer is limited to
−12 V to +13.5 V when a ±15 V power supply is used.
Q1
00035-019
When an analog input of VSS + 3 V to VDD − 1.5 V is applied to
the ADG508F/ADG509F/ADG528F, the multiplexer behaves as
a standard multiplexer, with specifications similar to a standard
multiplexer, for example, the on-resistance is 400 Ω maximum.
However, when an overvoltage is applied to the device, one of
the three MOSFETs will turn off.
+55V
OVERVOLTAGE
n-CHANNEL
MOSFET IS
ON
Q1
Q2
Q3
p-CHANNEL
MOSFET IS
OFF
Figure 20. −40 V Overvoltage with Power Off
00035-020
The ADG508F/ADG509F/ADG528F multiplexers are capable of
withstanding overvoltages from −40 V to +55 V, irrespective of
whether the power supplies are present or not. Each channel of
the multiplexer consists of an n-channel MOSFET, a p-channel
MOSFET, and an n-channel MOSFET, connected in series. When
the analog input exceeds the power supplies, one of the MOSFETs
will switch off, limiting the current to submicroamp levels, thereby
preventing the overvoltage from damaging any circuitry following
the multiplexer. Figure 17 illustrates the channel architecture that
enables these multiplexers to withstand continuous overvoltages.
ADG508F/ADG509F/ADG528F
TEST CIRCUITS
IDS
S1
V1
VDD
VSS
VDD
VSS
ID (ON)
D
A
S2
VD
S8
D
EN
2.4V
00035-025
S
VS
00035-021
VS
RON = V1/IDS
Figure 24. ID (On)
Figure 21. On Resistance
VDD
VSS
A
A
S1
VDD
D
D
EN
0.8V
00035-022
EN
Figure 25. Input Leakage Current (with Overvoltage)
Figure 22. IS (Off)
VDD
0.8V
VS
VD
VSS
0V
0V
0V
VDD
VSS
A2
A1
VSS
A0
D
S2
EN
ID (OFF)
VD
GND
0.8V
00035-023
EN
VS
A
VS
S8
D
RS
A
S8
S1
ADG528F*
WR
00035-027
S1
VSS
S8
S8
VDD
VDD
S2
VSS
S2
VS
VSS
00035-026
IS (OFF)
S1
VDD
Figure 26. Input Leakage Current (with Power Supplies Off)
Figure 23. ID (Off)
Rev. E | Page 12 of 20
ADG508F/ADG509F/ADG528F
VIN
VDD
VSS
VDD
A2
VSS
A1
50Ω
3V
VS1
S1
A0
EN
RS
D
VOUT
RL
1MΩ
WR
GND
50%
50%
VS8
S8
ADG528F*
2.4V
ADDRESS
DRIVE (VIN)
S2 TO S7
CL
35pF
90%
VOUT
*SIMILAR CONNECTION FOR ADG508F/ADG509F.
tTRANSITION
00035-024
90%
tTRANSITION
Figure 27. Switching Time of Multiplexer, tTRANSITION
VDD
VSS
VSS
VDD
A2
VIN
A1
50Ω
3V
ADDRESS
DRIVE (VIN)
VS
S1
S2 TO S7
A0
ADG528F* S8
RS
EN
2.4V
D
VOUT
RL
1kΩ
WR
GND
CL
35pF
VOUT
80%
80%
00035-029
tOPEN
*SIMILAR CONNECTION FOR ADG508F/ADG509F.
Figure 28. Break-Before-Make Delay, tOPEN
VDD
VSS
VSS
VDD
A2
A1
3V
ENABLE
DRIVE (VIN)
VS
S1
tOFF (EN)
ADG528F*
RS
EN
VIN
VO
D
VOUT
RL
1kΩ
WR
GND
VRS
50%
0V
S2 TO S8
A0
50%
CL
35pF
0.9VO
OUTPUT
0V
00035-030
tON (EN)
*SIMILAR CONNECTION FOR ADG508F/ADG509F.
Figure 29. Enable Delay, tON (EN), tOFF (EN)
VSS
VDD
A2
VSS
A1
A0
2.4V
WR
VS
S1
tON (WR)
ADG528F
VO
EN
WR
D
VWR
GND
50%
0V
S2 TO S8
RS
VRS
3V
VOUT
RL
1kΩ
CL
35pF
OUTPUT
0.2VO
0V
Figure 30. Write Turn-On Time, tON (WR)
Rev. E | Page 13 of 20
00035-031
VDD
ADG508F/ADG509F/ADG528F
VDD
VSS
VDD
A2
VSS
3V
RS
VS
S1
A1
0V
S2 TO S8
A0
ADG528F*
EN
VOUT
RL
1kΩ
WR
GND
VIN
tRS
tOFF (RS)
VO
D
RS
50%
CL
35pF
0.8VO
SWITCH
OUTPUT
0V
00035-032
2.4V
50%
*SIMILAR CONNECTION FOR ADG508F/ADG509F.
Figure 31. Reset Turn-Off Time, tOFF (RS)
VDD
VSS
VDD
A2
VSS
A1
A0
RS
3V
RS
0V
D
S
VOUT
EN
VS
VIN
LOGIC
INPUT (VIN)
2.4V
ADG528F*
GND
CL
1nF
ΔVOUT
VOUT
WR
00035-033
QINJ = CL × ΔVOUT
*SIMILAR CONNECTION FOR ADG508F/ADG509F.
Figure 32. Charge Injection
VDD
VDD
A2
S1
S8
A0
VIN
ADG528F*
2.4V
RS
EN
GND
D
WR
VSS
VOUT
RL
1kΩ
VSS
*SIMILAR CONNECTION FOR ADG508F/ADG509F.
Figure 33. Off Isolation
Rev. E | Page 14 of 20
00035-034
A1
ADG508F/ADG509F/ADG528F
OUTLINE DIMENSIONS
0.800 (20.32)
0.790 (20.07)
0.780 (19.81)
16
9
1
8
0.280 (7.11)
0.250 (6.35)
0.240 (6.10)
0.325 (8.26)
0.310 (7.87)
0.300 (7.62)
0.100 (2.54)
BSC
0.060 (1.52)
MAX
0.210 (5.33)
MAX
0.195 (4.95)
0.130 (3.30)
0.115 (2.92)
0.015
(0.38)
MIN
0.150 (3.81)
0.130 (3.30)
0.115 (2.92)
0.015 (0.38)
GAUGE
PLANE
SEATING
PLANE
0.022 (0.56)
0.018 (0.46)
0.014 (0.36)
0.430 (10.92)
MAX
0.005 (0.13)
MIN
0.014 (0.36)
0.010 (0.25)
0.008 (0.20)
0.070 (1.78)
0.060 (1.52)
0.045 (1.14)
073106-B
COMPLIANT TO JEDEC STANDARDS MS-001-AB
CONTROLLING DIMENSIONS ARE IN INCHES; MILLIMETER DIMENSIONS
(IN PARENTHESES) ARE ROUNDED-OFF INCH EQUIVALENTS FOR
REFERENCE ONLY AND ARE NOT APPROPRIATE FOR USE IN DESIGN.
CORNER LEADS MAY BE CONFIGURED AS WHOLE OR HALF LEADS.
Figure 34. 16-Lead Plastic Dual In-Line Package [PDIP] Narrow Body
(N-16)
Dimensions shown in inches and (millimeters)
10.00 (0.3937)
9.80 (0.3858)
4.00 (0.1575)
3.80 (0.1496)
9
16
1
8
1.27 (0.0500)
BSC
0.25 (0.0098)
0.10 (0.0039)
COPLANARITY
0.10
0.51 (0.0201)
0.31 (0.0122)
6.20 (0.2441)
5.80 (0.2283)
1.75 (0.0689)
1.35 (0.0531)
SEATING
PLANE
0.50 (0.0197)
0.25 (0.0098)
45°
8°
0°
0.25 (0.0098)
0.17 (0.0067)
1.27 (0.0500)
0.40 (0.0157)
Figure 35. 16-Lead Standard Small Outline Package [SOIC-N] Narrow Body
(R-16)
Dimensions shown in millimeters and (inches)
Rev. E | Page 15 of 20
060606-A
COMPLIANT TO JEDEC STANDARDS MS-012-AC
CONTROLLING DIMENSIONS ARE IN MILLIMETERS; INCH DIMENSIONS
(IN PARENTHESES) ARE ROUNDED-OFF MILLIMETER EQUIVALENTS FOR
REFERENCE ONLY AND ARE NOT APPROPRIATE FOR USE IN DESIGN.
ADG508F/ADG509F/ADG528F
10.50 (0.4134)
10.10 (0.3976)
9
16
7.60 (0.2992)
7.40 (0.2913)
1
8
1.27 (0.0500)
BSC
0.75 (0.0295)
0.25 (0.0098)
2.65 (0.1043)
2.35 (0.0925)
0.30 (0.0118)
0.10 (0.0039)
COPLANARITY
0.10
10.65 (0.4193)
10.00 (0.3937)
SEATING
PLANE
0.51 (0.0201)
0.31 (0.0122)
45°
8°
0°
1.27 (0.0500)
0.40 (0.0157)
0.33 (0.0130)
0.20 (0.0079)
032707-B
COMPLIANT TO JEDEC STANDARDS MS-013- AA
CONTROLLING DIMENSIONS ARE IN MILLIMETERS; INCH DIMENSIONS
(IN PARENTHESES) ARE ROUNDED-OFF MILLIMETER EQUIVALENTS FOR
REFERENCE ONLY AND ARE NOT APPROPRIATE FOR USE IN DESIGN.
Figure 36. 16-Lead Standard Small Outline Package [SOIC-W] Wide Body
(RW-16)
Dimensions shown in millimeters and (inches)
0.920 (23.37)
0.900 (22.86)
0.880 (22.35)
18
10
1
9
0.280 (7.11)
0.250 (6.35)
0.240 (6.10)
0.325 (8.26)
0.310 (7.87)
0.300 (7.62)
0.100 (2.54)
BSC
0.210 (5.33)
MAX
0.060 (1.52)
MAX
0.195 (4.95)
0.130 (3.30)
0.115 (2.92)
0.015
(0.38)
MIN
0.150 (3.81)
0.130 (3.30)
0.115 (2.92)
0.015 (0.38)
GAUGE
PLANE
SEATING
PLANE
0.005 (0.13)
MIN
0.430 (10.92)
MAX
0.070 (1.78)
0.060 (1.52)
0.045 (1.14)
COMPLIANT TO JEDEC STANDARDS MS-001
CONTROLLING DIMENSIONS ARE IN INCHES; MILLIMETER DIMENSIONS
(IN PARENTHESES) ARE ROUNDED-OFF INCH EQUIVALENTS FOR
REFERENCE ONLY AND ARE NOT APPROPRIATE FOR USE IN DESIGN.
CORNER LEADS MAY BE CONFIGURED AS WHOLE OR HALF LEADS.
Figure 37. 18-Lead Plastic Dual In-Line Package [PDIP] Narrow Body
(N-18)
Dimensions shown in inches and (millimeters)
Rev. E | Page 16 of 20
070706-A
0.022 (0.56)
0.018 (0.46)
0.014 (0.36)
0.014 (0.36)
0.010 (0.25)
0.008 (0.20)
ADG508F/ADG509F/ADG528F
0.180 (4.57)
0.165 (4.19)
0.048 (1.22 )
0.042 (1.07)
0.056 (1.42)
0.042 (1.07)
3
0.048 (1.22)
0.042 (1.07)
4
18
PIN 1
IDENTIFIER
TOP VIEW
(PINS DOWN)
9
0.020 (0.50)
R
0.021 (0.53)
0.013 (0.33)
0.050
(1.27)
BSC
0.330 (8.38)
0.032 (0.81) 0.290 (7.37)
0.026 (0.66)
14
8
0.020
(0.51)
R
0.20 (0.51)
MIN
19
13
BOTTOM
VIEW
(PINS UP)
0.045 (1.14)
R
0.025 (0.64)
0.356 (9.04)
SQ
0.350 (8.89)
0.120 (3.04)
0.090 (2.29)
0.395 (10.03)
SQ
0.385 (9.78)
COMPLIANT TO JEDEC STANDARDS MO-047-AA
CONTROLLING DIMENSIONS ARE IN INCHES; MILLIMETER DIMENSIONS
(IN PARENTHESES) ARE ROUNDED-OFF INCH EQUIVALENTS FOR
REFERENCE ONLY AND ARE NOT APPROPRIATE FOR USE IN DESIGN.
Figure 38. 20-Lead Plastic Leaded Chip Carrier [PLCC]
(P-20)
Dimensions shown in inches and (millimeters)
5.10
5.00
4.90
16
9
4.50
4.40
4.30
6.40
BSC
1
8
PIN 1
1.20
MAX
0.15
0.05
0.65
BSC
0.30
0.19
COPLANARITY
0.10
0.20
0.09
SEATING
PLANE
8°
0°
COMPLIANT TO JEDEC STANDARDS MO-153-AB
Figure 39. 16-Lead Thin Shrink Small Outline Package [TSSOP]
(RU-16)
Dimensions shown in millimeters
Rev. E | Page 17 of 20
0.75
0.60
0.45
ADG508F/ADG509F/ADG528F
ORDERING GUIDE
Model
ADG508FBN
ADG508FBNZ
ADG508FBRN
ADG508FBRN–REEL7
ADG508FBRNZ
ADG508FBRNZ–REEL7
ADG508FBRW
ADG508FBRWZ
ADG508FBRWZ-REEL
ADG508FBRUZ
ADG508FBRUZ-REEL7
ADG509FBN
ADG509FBNZ
ADG509FBRN
ADG509FBRN–REEL7
ADG509FBRNZ
ADG509FBRNZ–REEL7
ADG509FBRW
ADG509FBRW-REEL
ADG509FBRWZ
ADG509FBRWZ-REEL
ADG509FBRUZ
ADG509FBRUZ-REEL7
ADG528FBN
ADG528FBNZ
ADG528FBP
ADG528FBP-REEL
ADG528FBPZ
Temperature Range
−40°C to +85°C
−40°C to +85°C
−40°C to +85°C
−40°C to +85°C
−40°C to +85°C
−40°C to +85°C
−40°C to +85°C
−40°C to +85°C
−40°C to +85°C
−40°C to +85°C
−40°C to +85°C
−40°C to +85°C
−40°C to +85°C
−40°C to +85°C
−40°C to +85°C
−40°C to +85°C
−40°C to +85°C
−40°C to +85°C
−40°C to +85°C
−40°C to +85°C
−40°C to +85°C
−40°C to +85°C
−40°C to +85°C
−40°C to +85°C
−40°C to +85°C
−40°C to +85°C
−40°C to +85°C
−40°C to +85°C
Package Description
16-Lead PDIP
16-Lead PDIP
16-Lead SOIC_N
16-Lead SOIC_N
16-Lead SOIC_N
16-Lead SOIC_N
16-Lead SOIC_W
16-Lead SOIC_W
16-Lead SOIC_W
16-Lead TSSOP
16-Lead TSSOP
16-Lead PDIP
16-Lead PDIP
16-Lead SOIC_N
16-Lead SOIC_N
16-Lead SOIC_N
16-Lead SOIC_N
16-Lead SOIC_W
16-Lead SOIC_W
16-Lead SOIC_W
16-Lead SOIC_W
16-Lead TSSOP
16-Lead TSSOP
18-Lead PDIP
18-Lead PDIP
20-Lead PLCC
20-Lead PLCC
20-Lead PLCC
Rev. E | Page 18 of 20
Package Option
N-16
N-16
R-16
R-16
R-16
R-16
RW-16
RW-16
RW-16
RU-16
RU-16
N-16
N-16
R-16
R-16
R-16
R-16
RW-16
RW-16
RW-16
RW-16
RU-16
RU-16
N-18
N-18
P-20
P-20
P-20
ADG508F/ADG509F/ADG528F
NOTES
Rev. E | Page 19 of 20
ADG508F/ADG509F/ADG528F
NOTES
©2001–2009 Analog Devices, Inc. All rights reserved. Trademarks and
registered trademarks are the property of their respective owners.
D00035-0-7/09(E)
Rev. E | Page 20 of 20