8-Channel/4-Channel
Fault-Protected Analog Multiplexers
ADG508F/ADG509F
FEATURES
FUNCTIONAL BLOCK DIAGRAMS
All switches off with power supply off
Analog output of on channel clamped within power
supplies if an overvoltage occurs
Latch-up proof construction
Low on resistance (270 Ω typical)
Fast switching times
tON: 230 ns maximum
tOFF: 130 ns maximum
Low power dissipation (3.3 mW maximum)
Fault and overvoltage protection (−40 V to +55 V)
Break-before-make construction
TTL and CMOS compatible inputs
ADG508F
S1
D
S8
APPLICATIONS
A0 A1 A2 EN
Figure 1.
Existing multiplexer applications (both fault-protected and
nonfault-protected)
New designs requiring multiplexer functions
ADG509F
GENERAL DESCRIPTION
S1A
The ADG508F and ADG509F are CMOS analog multiplexers, with the ADG508F comprising eight single channels
and the ADG509F comprising four differential channels. These
multiplexers provide fault protection. Using a series n-channel,
p-channel, n-channel MOSFET structure, both device and signal
source protection is provided in the event of an overvoltage or
power loss. The multiplexer can withstand continuous overvoltage inputs from −40 V to +55 V. During fault conditions with
power supplies off, the multiplexer input (or output) appears as
an open circuit and only a few nanoamperes of leakage current
will flow. This protects not only the multiplexer and the circuitry
driven by the multiplexer, but also protects the sensors or signal
sources that drive the multiplexer.
S4A
The ADG508F switches one of eight inputs to a common output
as determined by the 3-bit binary address lines A0, A1, and A2.
The ADG509F switches one of four differential inputs to a
common differential output as determined by the 2-bit binary
address lines A0 and A1. An EN input on each device is used
to enable or disable the device. When disabled, all channels are
switched off.
00035-001
1 OF 8
DECODER
DA
S1B
DB
S4B
A0 A1 EN
00035-101
1 OF 4
DECODER
Figure 2.
PRODUCT HIGHLIGHTS
1.
2.
3.
4.
5.
6.
Fault protection. The ADG508F/ADG509F can withstand
continuous voltage inputs from −40 V to +55 V. When a
fault occurs due to the power supplies being turned off, all
the channels are turned off and only a leakage current of a
few nanoamperes flows.
On channel saturates while fault exists.
Low RON.
Fast switching times.
Break-before-make switching. Switches are guaranteed
break-before-make so that input signals are protected
against momentary shorting.
Trench isolation eliminates latch-up. A dielectric trench
separates the p and n-channel MOSFETs thereby
preventing latch-up.
Rev. F
Information furnished by Analog Devices is believed to be accurate and reliable. However, no
responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other
rights of third parties that may result from its use. Specifications subject to change without notice. No
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
Trademarks and registered trademarks are the property of their respective owners.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700
www.analog.com
Fax: 781.461.3113 ©2001–2011 Analog Devices, Inc. All rights reserved.
ADG508F/ADG509F
TABLE OF CONTENTS
Features .............................................................................................. 1
Absolute Maximum Ratings ............................................................5
Applications....................................................................................... 1
ESD Caution...................................................................................5
General Description ......................................................................... 1
Pin Configuration and Function Descriptions..............................6
Functional Block Diagrams............................................................. 1
Typical Performance Characteristics ..............................................8
Product Highlights ........................................................................... 1
Terminology .................................................................................... 10
Revision History ............................................................................... 2
Theory of Operation ...................................................................... 11
Specifications..................................................................................... 3
Test Circuits..................................................................................... 12
Dual Supply ................................................................................... 3
Outline Dimensions ....................................................................... 15
Truth Tables................................................................................... 4
Ordering Guide .......................................................................... 17
REVISION HISTORY
7/11—Rev. E to Rev. F
Deleted ADG528F ..............................................................Universal
Changes to Features Section and General Description Section . 1
Changes to Specifications Section.................................................. 3
Deleted Timing Diagrams Section ................................................. 4
Changes to Table 4............................................................................ 5
Added Table 5.................................................................................... 6
Added Table 6.................................................................................... 7
Replaced Typical Performance Characteristics Section .............. 8
Changes to Terminology Section.................................................. 10
Changes to Figure 27 and Figure 28............................................. 13
Changes to Figure 31...................................................................... 14
Changes to Theory of Operation Section.................................... 11
Updated Outline Dimensions ....................................................... 15
Changes to Ordering Guide .......................................................... 17
7/09—Rev. D: Rev. E
Updated Format..................................................................Universal
Added TSSOP .....................................................................Universal
Updated Outline Dimensions ....................................................... 15
Changes to Ordering Guide .......................................................... 18
4/01—Data Sheet Changed from Rev. C to Rev. D.
Changes to Ordering Guide ............................................................ 1
Changes to Specifications Table...................................................... 2
Max Ratings Changed ...................................................................... 4
Deleted 16-Lead Cerdip from Outline Dimensions .................. 11
Deleted 18-Lead Cerdip from Outline Dimensions .................. 12
Rev. F | Page 2 of 20
ADG508F/ADG509F
SPECIFICATIONS
DUAL SUPPLY
VDD = +15 V ± 10%, VSS = −15 V ± 10%, GND = 0 V, unless otherwise noted.
Table 1.
Parameter
ANALOG SWITCH
Analog Signal Range
RON
RON Drift
On-Resistance Match Between
Channels, ∆RON
LEAKAGE CURRENTS
Source Off Leakage IS (Off )
Drain Off Leakage ID (Off )
ADG508F
ADG509F
Channel On Leakage ID, IS (On)
ADG508F
ADG509F
FAULT
Source Leakage Current IS (Fault)
(With Overvoltage)
Drain Leakage Current ID (Fault)
(With Overvoltage)
Source Leakage Current IS (Fault)
(Power Supplies Off )
DIGITAL INPUTS
Input High Voltage, VINH
Input Low Voltage, VINL
Input Current, IINL or IINH
CIN, Digital Input Capacitance
DYNAMIC CHARACTERISTICS 1
tTRANSITION
tOPEN
tON (EN)
tOFF (EN)
tSETT, Settling Time
0.1%
0.01%
+25°C
VSS + 1.4
VDD − 1.4
VSS + 2.2
VDD – 2.2
270
B Version
−40°C to +85°C
Test Conditions/Comments
V typ
V typ
V typ
V typ
Ω typ
Ω max
Output open circuit
Output loaded, 1 mA
0.6
%/°C typ
−10 V ≤ VS ≤ +10 V, IS = 1 mA;
VDD = +15 V ± 10%, VSS = −15 V ± 10%
See Figure 21
VS = 0 V, IS = 1 mA
3
% max
VS = ±10 V, IS = −1 mA
nA typ
nA max
nA typ
nA max
nA max
nA typ
nA max
nA max
VD = ±10 V, VS = +10 V;
See Figure 22
VD = ±10 V, VS = +10 V;
See Figure 23
nA typ
μA max
nA typ
μA max
VS = +55 V or −40 V, VD = 0 V, see Figure 25
nA typ
μA max
VS = ±25 V, VD = VEN = A0, A1, A2 = 0 V
See Figure 26
±0.02
±1
±0.04
±1
±1
±0.04
±1
±1
±0.02
±2
±5
±2
350
390
Unit
±50
±60
±30
±60
±30
±2
±1
±2
2.4
0.8
±1
5
175
220
90
60
180
230
100
130
300
40
300
V min
V max
μA max
pF typ
VS = VD = ± 10 V;
See Figure 24
VS = ±25 V, VD = +10 V, see Figure 23
VIN = 0 or VDD
ns typ
ns max
ns typ
ns min
ns typ
ns max
ns typ
RL = 1 MΩ, CL = 35 pF;
VS1 = ±10 V, VS8 = +10 V; see Figure 27
RL = 1 kΩ, CL = 35 pF;
VS = 5 V; see Figure 28
RL = 1 kΩ, CL = 35 pF;
VS = 5 V; see Figure 29
RL = 1 kΩ, CL = 35 pF
ns max
μs typ
μs typ
VS = 5 V; see Figure 29
RL = 1 kΩ, CL = 35 pF;
VS = 5 V
150
1
2.5
Rev. F | Page 3 of 20
ADG508F/ADG509F
B Version
−40°C to +85°C
Parameter
Charge Injection
Off Isolation
+25°C
15
93
CS (Off )
CD (Off )
ADG508F
ADG509F
POWER REQUIREMENTS
IDD
ISS
3
pF typ
22
12
pF typ
pF typ
1
0.05
0.1
0.2
1
Unit
pC typ
dB typ
mA max
μA max
Test Conditions/Comments
VS = 0 V, RS = 0 Ω, CL= 1 nF; see Figure 30
RL = 1 kΩ, CL = 15 pF, f = 100 kHz; VS = 7 V rms;
see Figure 31
VIN = 0 V or 5 V
Guaranteed by design, not subject to production test.
TRUTH TABLES
Table 2. ADG508F Truth Table 1
A2
X
0
0
0
0
1
1
1
1
1
A1
X
0
0
1
1
0
0
1
1
A0
X
0
1
0
1
0
1
0
1
EN
0
1
1
1
1
1
1
1
1
On Switch
None
1
2
3
4
5
6
7
8
X = don’t care.
Table 3. ADG509F Truth Table 1
A1
X
0
0
1
1
1
A0
X
0
1
0
1
EN
0
1
1
1
1
On Switch Pair
None
1
2
3
4
X = don’t care.
Rev. F | Page 4 of 20
ADG508F/ADG509F
ABSOLUTE MAXIMUM RATINGS
TA = 25°C unless otherwise noted.
Table 4.
Parameter
VDD to VSS
VDD to GND
VSS to GND
Digital Input, EN, Ax
VS, Analog Input Overvoltage with
Power On (VDD = +15 V, VSS = −15 V)
VS, Analog Input Overvoltage with
Power Off (VDD = 0 V, VSS = 0 V)
Continuous Current, S or D
Peak Current, S or D
(Pulsed at 1 ms, 10% Duty Cycle Max)
Operating Temperature Range
Industrial (B Version)
Storage Temperature Range
Junction Temperature
TSSOP
θJA, Thermal Impedance
Plastic DIP Package
θJA, Thermal Impedance
16-Lead
SOIC Package
θJA, Thermal Impedance
Narrow Body
Wide Body
Rating
48 V
−0.3 V to +48 V
+0.3 V to −48 V
−0.3 V to VDD + 0.3 V or
20 mA, whichever occurs first
VSS − 25 V to VDD + 40 V
Stresses above those listed under Absolute Maximum Ratings
may cause permanent damage to the device. This is a stress
rating only; functional operation of the device at these or any
other conditions above those indicated in the operational
section of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect
device reliability.
ESD CAUTION
−40 V to +55 V
20 mA
40 mA
−40°C to +85°C
−65°C to +150°C
150°C
112°C/W
117°C/W
77°C/W
75°C/W
Rev. F | Page 5 of 20
ADG508F/ADG509F
PIN CONFIGURATION AND FUNCTION DESCRIPTIONS
A0 1
16 A1
EN 2
VSS 3
15 A2
ADG508F
14 GND
TOP VIEW 13 VDD
S2 5 (Not to Scale) 12 S5
S3 6
11 S6
S4 7
10 S7
D 8
9
S8
00035-004
S1 4
Figure 3. ADG508F Pin Configuration
Table 5. ADG508F Pin Function Descriptions
Pin No.
1
2
Mnemonic
A0
EN
3
VSS
4
5
6
7
8
9
10
11
12
13
14
15
16
S1
S2
S3
S4
D
S8
S7
S6
S5
VDD
GND
A2
A1
Description
Logic Control Input.
Active High Digital Input. When low, the device is disabled and all switches are off. When high,
Ax logic inputs determine on switches.
Most Negative Power Supply Potential. In single-supply applications, this pin can be connected
to ground.
Source Terminal 1. This pin can be an input or an output.
Source Terminal 2. This pin can be an input or an output.
Source Terminal 3. This pin can be an input or an output.
Source Terminal 4. This pin can be an input or an output.
Drain Terminal. This pin can be an input or an output.
Source Terminal 8. This pin can be an input or an output.
Source Terminal 7. This pin can be an input or an output.
Source Terminal 6. This pin can be an input or an output.
Source Terminal 5. This pin can be an input or an output.
Most Positive Power Supply Potential.
Ground (0 V) Reference.
Logic Control Input.
Logic Control Input.
Rev. F | Page 6 of 20
ADG508F/ADG509F
A0 1
16 A1
EN 2
VSS 3
15 GND
ADG509F
14 VDD
TOP VIEW 13 S1B
S2A 5 (Not to Scale) 12 S2B
S3A 6
11 S3B
S4A 7
10 S4B
DA 8
9
DB
00035-005
S1A 4
Figure 4. ADG509F Pin Configuration
Table 6. ADG509F Pin Function Descriptions
Pin No.
1
2
Mnemonic
A0
EN
3
VSS
4
5
6
7
8
9
10
11
12
13
14
15
16
S1A
S2A
S3A
S4A
DA
DB
S4B
S3B
S2B
S1B
VDD
GND
A1
Description
Logic Control Input.
Active High Digital Input. When low, the device is disabled and all switches are off. When high,
Ax logic inputs determine on switches.
Most Negative Power Supply Potential. In single-supply applications, this pin can be connected
to ground.
Source Terminal 1A. This pin can be an input or an output.
Source Terminal 2A. This pin can be an input or an output.
Source Terminal 3A. This pin can be an input or an output.
Source Terminal 4A. This pin can be an input or an output.
Drain Terminal A. This pin can be an input or an output.
Drain Terminal B. This pin can be an input or an output.
Source Terminal 4B. This pin can be an input or an output.
Source Terminal 3B. This pin can be an input or an output.
Source Terminal 2B. This pin can be an input or an output.
Source Terminal 1B. This pin can be an input or an output.
Most Positive Power Supply Potential.
Ground (0 V) Reference.
Logic Control Input.
Rev. F | Page 7 of 20
ADG508F/ADG509F
TYPICAL PERFORMANCE CHARACTERISTICS
2000
2000
TA = 25°C
1750
VDD = +5V
VSS = –5V
1250
VDD = +10V
VSS = –10V
RON (Ω)
1000
VDD = +15V
VSS = –15V
750
750
500
250
250
00035-008
500
0
–15
–10
–5
0
VD, VS (V)
5
10
0
–15
15
Figure 5. On Resistance as a Function of VD (VS)
0
VD, VS (V)
100µ
VDD = 0V
VSS = 0V
VD = 0V
5
10
15
OPERATING RANGE
100n
10n
1n
1µ
100n
10n
100p
10p
10p
00035-009
100p
–30
–20
–10
0
10
20
30
VS SOURCE VOLTAGE (V)
40
50
OPERATING RANGE
1n
1p
–50
60
Figure 6. Source Input Leakage Current as a Function of VS (Power Supplies
Off) During Overvoltage Conditions
00035-012
1µ
–40
VDD = +15V
VSS = –15V
VD = 0V
10µ
IS INPUT LEAKAGE (A)
10µ
–40
–30
–20
–10
0
10
20
30
VS SOURCE VOLTAGE (V)
40
50
60
Figure 9. Source Input Leakage Current as a Function of VS (Power Supplies
On) During Overvoltage Conditions
0.3
1m
100µ
VDD = +15V
VSS = –15V
VD = 0V
1µ
100n
10n
1n
VDD = +15V
VSS = –15V
VS (VD) = ±10V
TA = 25°C
0.2
LEAKAGE CURRENTS (nA)
10µ
OPERATING RANGE
100p
0.1
ID (OFF)
0.0
IS (OFF)
–0.1
–0.2
00035-010
10p
1p
–50
–5
1m
100µ
IS INPUT LEAKAGE (A)
–10
Figure 8. On Resistance as a Function of VD (VS) for Different Temperatures
1m
ID INPUT LEAKAGE (A)
1000
–40
–30
–20
–10
0
10
20
30
VS SOURCE VOLTAGE (V)
40
50
ID, IS (ON)
–0.3
–14
60
Figure 7. Drain Output Leakage Current as a Function of VS (Power Supplies
On) During Overvoltage Conditions
Rev. F | Page 8 of 20
–10
–6
00035-013
RON (Ω)
1250
TA = 125°C
TA = 105°C
TA = 85°C
TA = 25°C
1500
00035-011
1500
1p
–50
VDD = +15V
VSS = –15V
1750
–2
2
VS, VD (V)
6
10
Figure 10. Leakage Currents as a Function of VD (VS)
14
ADG508F/ADG509F
0
VDD = +15V
VSS = –15V
VD = +10V
VS = –10V
10
–20
OFF ISOLATION (dB)
LEAKAGE CURRENTS (nA)
100
ID (OFF)
1
ID (ON)
TA = 25°C
VDD = +15V
VSS = –15V
–40
–60
–80
IS (OFF)
0.1
0.01
45
55
65
75
85
95
TEMPERATURE (°C)
105
115
–120
1k
125
40
240
35
tTRANSITION
PIN CAPACITANCE (pF)
SWITCHING TIME (ns)
220
tON (EN)
180
160
140
tOFF (EN)
10
11
12
13
POWER SUPPLY (V)
14
25
1G
DRAIN OFF
20
15
10
0
–15
15
SOURCE OFF
–10
–5
0
5
10
15
VS (V)
Figure 15. Capacitance vs. Source Voltage
30
300
VDD = +15V
VSS = –15V
tON (EN)
250
200
20
QINJ (pC)
150
tOFF (EN)
100
VDD = +15V
VSS = –15V
TA = 25°C
10
tTRANSITION
0
–10
–20
50
00035-016
SWITCHING TIME (ns)
100M
30
Figure 12. Switching Time vs. Dual Power Supply
0
–40
10M
TA = 25°C
VDD = +15V
VSS = –15V
5
00035-015
100
1M
Figure 14. Off Isolation vs. Frequency, ±15 V Dual Supply
260
120
100k
FREQUENCY (Hz)
Figure 11. Leakage Currents as a Function of Temperature
200
10k
00035-114
35
–20
0
20
40
60
TEMPERATURE (°C)
80
100
–30
–15
120
–10
–5
0
VS (V)
5
10
Figure 16. Charge Injection vs. Source Voltage
Figure 13. Switching Time vs. Temperature
Rev. F | Page 9 of 20
15
00035-115
25
000354-113
00035-014
–100
ADG508F/ADG509F
TERMINOLOGY
VDD
Most positive power supply potential.
CD (Off)
Channel output capacitance for off condition.
VSS
Most negative power supply potential.
CIN
Digital input capacitance.
GND
Ground (0 V) reference.
tON (EN)
Delay time between the 50% and 90% points of the digital input
and switch on condition.
RON
Ohmic resistance between D and S.
RON Drift
Percentage change in RON when temperature changes by one
degree Celsius.
ΔRON
ΔRON represents the difference between the RON of any two
channels as a percentage of the maximum RON of those two
channels.
IS (Off)
Source leakage current when the switch is off.
ID (Off)
Drain leakage current when the switch is off.
ID, IS (On)
Channel leakage current when the switch is on.
IS (Fault—Power Supplies On)
Source leakage current when exposed to an overvoltage
condition.
ID (Fault—Power Supplies On)
Drain leakage current when exposed to an overvoltage
condition.
IS (Fault—Power Supplies Off)
Source leakage current with power supplies off.
VD (VS)
Analog Voltage on Terminals D, S.
CS (Off)
Channel input capacitance for off condition.
tOFF (EN)
Delay time between the 50% and 90% points of the digital input
and switch off condition.
tTRANSITION
Delay time between the 50% and 90% points of the digital
inputs and the switch on condition when switching from
one address state to another.
tOPEN
Off time measured between 80% points of both switches when
switching from one address state to another.
VINL
Maximum input voltage for Logic 0.
VINH
Minimum input voltage for Logic 1.
IINL (IINH)
Input current of the digital input.
Off Isolation
A measure of unwanted signal coupling through an off channel.
Charge Injection
A measure of the glitch impulse transferred from the digital
input to the analog output during switching.
IDD
Positive supply current.
ISS
Negative supply current.
Rev. F | Page 10 of 20
ADG508F/ADG509F
THEORY OF OPERATION
During fault conditions (power supplies off), the leakage
current into and out of the ADG508F/ADG509F is limited to
a few microamps. This protects the multiplexer and succeeding
circuitry from over stresses as well as protecting the signal
sources which drive the multiplexer. Also, the other channels
of the multiplexer will be undisturbed by the overvoltage and
will continue to operate normally.
When an analog input of VSS + 2.2 V to VDD − 2.2 V (output
loaded, 1 mA) is applied to the ADG508F/ADG509F, the
multiplexer behaves as a standard multiplexer, with specifications similar to a standard multiplexer, for example,
the on-resistance is 390 Ω maximum. However, when an
overvoltage is applied to the device, one of the three
MOSFETs saturate.
+55V
OVERVOLTAGE
Q1
n-CHANNEL
MOSFET
SATURATES
VDD
Q2
Q3
00035-017
The ADG508F/ADG509F multiplexers are capable of withstanding overvoltages from −40 V to +55 V, irrespective of whether the
power supplies are present or not. Each channel of the multiplexer
consists of an n-channel MOSFET, a p-channel MOSFET, and an
n-channel MOSFET, connected in series. When the analog input
exceeds the power supplies, one of the MOSFETs will saturate
limiting the current. The current during a fault condition is
determined by the load on the output. Figure 17 illustrates
the channel architecture that enables these multiplexers to
withstand continuous overvoltages.
VSS
Figure 17. +55 V Overvoltage Input to the On Channel
When the power supplies are present but the channel is off,
again either the p-channel MOSFET or one of the n-channel
MOSFETs will remain off when an overvoltage occurs.
n-CHANNEL
MOSFET
IS ON
VSS
Rev. F | Page 11 of 20
VDD
Q3
p-CHANNEL
MOSFET
SATURATES
Figure 18. −40 V Overvoltage on an Off Channel with
Multiplexer Power On
+55V
OVERVOLTAGE
Q1
Q2
Q3
00035-019
n-CHANNEL
MOSFET IS
OFF
Figure 19. +55 V Overvoltage with Power Off
–40V
OVERVOLTAGE
n-CHANNEL
MOSFET IS
ON
Finally, when the power supplies are off, the gate of each
MOSFET will be at ground. A negative overvoltage switches
on the first n-channel MOSFET but the bias produced by the
overvoltage causes the p-channel MOSFET to remain turned
off. With a positive overvoltage, the first MOSFET in the series
will remain off because the gate to source voltage applied to this
MOSFET is negative.
Q2
Q1
Q2
Q3
p-CHANNEL
MOSFET IS
OFF
Figure 20. −40 V Overvoltage with Power Off
00035-020
Figure 17 to Figure 20 show the conditions of the three MOSFETs
for the various overvoltage situations. When the analog input
applied to an on channel approaches the positive power supply
line, the n-channel MOSFET saturates because the voltage on
the analog input exceeds the difference between VDD and the
n-channel threshold voltage (VTN). When a voltage more negative than VSS is applied to the multiplexer, the p-channel
MOSFET will saturate because the analog input is more
negative than the difference between VSS and the p-channel
threshold voltage (VTP). Because VTN is nominally 1.4 V and
VTP −1.4 V, the analog input range to the multiplexer is limited
to VSS + 1.4 V to VDD – 1.4 V (output open circuit) when a
±15 V power supply is used.
Q1
00035-018
–40V
OVERVOLTAGE
ADG508F/ADG509F
TEST CIRCUITS
IDS
V1
ID (ON)
D
S
S
NC
D
A
RON = V1/IDS
Figure 24. ID (On)
Figure 21. On Resistance
A
S1
VSS
VDD
VSS
S2
VS
A
D
D
EN
00035-022
VDD
0V
VSS
VD
0V
0V
VDD
VSS
A2
A1
D
S1
A0
A
EN
VS
S8
D
VD
0.8V
GND
00035-027
00035-023
VS
A
ADG508F
ID (OFF)
S8
EN
0.8V
Figure 25. Input Leakage Current (with Overvoltage)
VSS
S2
VSS
VS
Figure 22. IS (Off)
S1
VDD
S8
0.8V
VD
VDD
VSS
S2
S8
EN
S1
VDD
00035-026
IS (OFF)
VDD
VD
NC = NO CONNECT
00035-025
00035-021
VS
Figure 23. ID (Off)
Figure 26. Input Leakage Current (with Power Supplies Off)
Rev. F | Page 12 of 20
ADG508F/ADG509F
VIN
VDD
VSS
VDD
A2
VSS
A1
50Ω
3V
VS1
S1
A0
EN
50%
50%
VS8
S8
ADG508F*
2.4V
ADDRESS
DRIVE (VIN)
S2 TO S7
D
VOUT
RL
1MΩ
GND
CL
35pF
90%
VOUT
90%
tTRANSITION
00035-024
*SIMILAR CONNECTION FOR ADG509F.
tTRANSITION
Figure 27. Switching Time of Multiplexer, tTRANSITION
VIN
VDD
VSS
VDD
A2
VSS
A1
50Ω
3V
ADDRESS
DRIVE (VIN)
VS
S1
S2 TO S7
A0
ADG508F* S8
D
EN
2.4V
VOUT
RL
1kΩ
GND
CL
35pF
VOUT
80%
80%
00035-029
tOPEN
*SIMILAR CONNECTION FOR ADG509F.
Figure 28. Break-Before-Make Delay, tOPEN
VDD
VSS
3V
VDD
A2
VSS
ENABLE
DRIVE (VIN)
ADG508F*
EN
VIN
50Ω
GND
VOUT
D
VOUT
RL
1kΩ
50%
0V
S2 TO S8
A0
50%
CL
35pF
0.9VOUT
OUTPUT
0.1VOUT
0V
tON (EN)
*SIMILAR CONNECTION FOR ADG509F.
Figure 29. Enable Delay, tON (EN), tOFF (EN)
Rev. F | Page 13 of 20
tOFF (EN)
00035-030
A1
VS
S1
ADG508F/ADG509F
VDD
VSS
VDD
A2
VSS
A1
A0
RS
3V
LOGIC
INPUT (VIN)
ADG508F*
0V
D
S
VOUT
EN
VS
VIN
CL
1nF
∆VOUT
VOUT
GND
00035-033
QINJ = CL × ∆VOUT
*SIMILAR CONNECTION FOR ADG509F.
Figure 30. Charge Injection
VDD
VSS
0.1µF
0.1µF
VDD
IN
NETWORK
ANALYZER
VSS
SA
NC
SB
50Ω
50Ω
VS
D
RL
50Ω
GND
OFF ISOLATION = 20 log
VOUT
VS
Figure 31. Off Isolation
Rev. F | Page 14 of 20
VOUT
00035-034
VIN
ADG508F/ADG509F
OUTLINE DIMENSIONS
0.800 (20.32)
0.790 (20.07)
0.780 (19.81)
16
9
1
8
0.280 (7.11)
0.250 (6.35)
0.240 (6.10)
0.325 (8.26)
0.310 (7.87)
0.300 (7.62)
0.100 (2.54)
BSC
0.060 (1.52)
MAX
0.210 (5.33)
MAX
0.195 (4.95)
0.130 (3.30)
0.115 (2.92)
0.015
(0.38)
MIN
0.150 (3.81)
0.130 (3.30)
0.115 (2.92)
0.015 (0.38)
GAUGE
PLANE
SEATING
PLANE
0.022 (0.56)
0.018 (0.46)
0.014 (0.36)
0.430 (10.92)
MAX
0.005 (0.13)
MIN
0.014 (0.36)
0.010 (0.25)
0.008 (0.20)
0.070 (1.78)
0.060 (1.52)
0.045 (1.14)
073106-B
COMPLIANT TO JEDEC STANDARDS MS-001-AB
CONTROLLING DIMENSIONS ARE IN INCHES; MILLIMETER DIMENSIONS
(IN PARENTHESES) ARE ROUNDED-OFF INCH EQUIVALENTS FOR
REFERENCE ONLY AND ARE NOT APPROPRIATE FOR USE IN DESIGN.
CORNER LEADS MAY BE CONFIGURED AS WHOLE OR HALF LEADS.
Figure 32. 16-Lead Plastic Dual In-Line Package [PDIP] Narrow Body
(N-16)
Dimensions shown in inches and (millimeters)
10.00 (0.3937)
9.80 (0.3858)
4.00 (0.1575)
3.80 (0.1496)
9
16
1
8
1.27 (0.0500)
BSC
0.25 (0.0098)
0.10 (0.0039)
COPLANARITY
0.10
0.51 (0.0201)
0.31 (0.0122)
6.20 (0.2441)
5.80 (0.2283)
1.75 (0.0689)
1.35 (0.0531)
SEATING
PLANE
0.50 (0.0197)
0.25 (0.0098)
45°
8°
0°
0.25 (0.0098)
0.17 (0.0067)
1.27 (0.0500)
0.40 (0.0157)
Figure 33. 16-Lead Standard Small Outline Package [SOIC_N] Narrow Body
(R-16)
Dimensions shown in millimeters and (inches)
Rev. F | Page 15 of 20
060606-A
COMPLIANT TO JEDEC STANDARDS MS-012-AC
CONTROLLING DIMENSIONS ARE IN MILLIMETERS; INCH DIMENSIONS
(IN PARENTHESES) ARE ROUNDED-OFF MILLIMETER EQUIVALENTS FOR
REFERENCE ONLY AND ARE NOT APPROPRIATE FOR USE IN DESIGN.
ADG508F/ADG509F
10.50 (0.4134)
10.10 (0.3976)
9
16
7.60 (0.2992)
7.40 (0.2913)
1
10.65 (0.4193)
10.00 (0.3937)
8
1.27 (0.0500)
BSC
0.30 (0.0118)
0.10 (0.0039)
COPLANARITY
0.10
0.75 (0.0295)
45°
0.25 (0.0098)
2.65 (0.1043)
2.35 (0.0925)
SEATING
PLANE
0.51 (0.0201)
0.31 (0.0122)
8°
0°
0.33 (0.0130)
0.20 (0.0079)
1.27 (0.0500)
0.40 (0.0157)
03-27-2007-B
COMPLIANT TO JEDEC STANDARDS MS-013-AA
CONTROLLING DIMENSIONS ARE IN MILLIMETERS; INCH DIMENSIONS
(IN PARENTHESES) ARE ROUNDED-OFF MILLIMETER EQUIVALENTS FOR
REFERENCE ONLY AND ARE NOT APPROPRIATE FOR USE IN DESIGN.
Figure 34. 16-Lead Standard Small Outline Package [SOIC_W] Wide Body
(RW-16)
Dimensions shown in millimeters and (inches)
5.10
5.00
4.90
16
9
4.50
4.40
4.30
6.40
BSC
1
8
PIN 1
1.20
MAX
0.15
0.05
0.65
BSC
0.30
0.19
COPLANARITY
0.10
0.20
0.09
SEATING
PLANE
8°
0°
COMPLIANT TO JEDEC STANDARDS MO-153-AB
Figure 35. 16-Lead Thin Shrink Small Outline Package [TSSOP]
(RU-16)
Dimensions shown in millimeters
Rev. F | Page 16 of 20
0.75
0.60
0.45
ADG508F/ADG509F
ORDERING GUIDE
Model 1
ADG508FBNZ
ADG508FBRN
ADG508FBRNZ
ADG508FBRNZ–REEL7
ADG508FBRWZ
ADG508FBRWZ-REEL
ADG508FBRUZ
ADG508FBRUZ-REEL7
ADG509FBNZ
ADG509FBRN
ADG509FBRNZ
ADG509FBRNZ–REEL7
ADG509FBRWZ
ADG509FBRWZ-REEL
ADG509FBRUZ
ADG509FBRUZ-REEL7
1
Temperature Range
−40°C to +85°C
−40°C to +85°C
−40°C to +85°C
−40°C to +85°C
−40°C to +85°C
−40°C to +85°C
−40°C to +85°C
−40°C to +85°C
−40°C to +85°C
−40°C to +85°C
−40°C to +85°C
−40°C to +85°C
−40°C to +85°C
−40°C to +85°C
−40°C to +85°C
−40°C to +85°C
Package Description
16-Lead PDIP
16-Lead SOIC_N
16-Lead SOIC_N
16-Lead SOIC_N
16-Lead SOIC_W
16-Lead SOIC_W
16-Lead TSSOP
16-Lead TSSOP
16-Lead PDIP
16-Lead SOIC_N
16-Lead SOIC_N
16-Lead SOIC_N
16-Lead SOIC_W
16-Lead SOIC_W
16-Lead TSSOP
16-Lead TSSOP
Z = RoHS Compliant Part.
Rev. F | Page 17 of 20
Package Option
N-16
R-16
R-16
R-16
RW-16
RW-16
RU-16
RU-16
N-16
R-16
R-16
R-16
RW-16
RW-16
RU-16
RU-16
ADG508F/ADG509F
NOTES
Rev. F | Page 18 of 20
ADG508F/ADG509F
NOTES
Rev. F | Page 19 of 20
ADG508F/ADG509F
NOTES
©2001–2011 Analog Devices, Inc. All rights reserved. Trademarks and
registered trademarks are the property of their respective owners.
D00035-0-7/11(F)
Rev. F | Page 20 of 20
工商网监
湘ICP备2023018690号
