Fault Protection, −0.4 pC QINJ,
8:1/Dual 4:1 Multiplexers
ADG5208F/ADG5209F
Data Sheet
FEATURES
FUNCTIONAL BLOCK DIAGRAMS
Overvoltage protection up to −55 V and +55 V
Power-off protection up to −55 V and +55 V
Overvoltage detection on source pins
Low charge injection (QINJ): −0.4 pC
Low on capacitance
ADG5208F: 20 pF
ADG5209F: 14 pF
Latch-up immune under any circumstance
Known state without digital inputs present
VSS to VDD analog signal range
±5 V to ±22 V dual-supply operation
8 V to 44 V single-supply operation
Fully specified at ±15 V, ±20 V, +12 V, and +36 V
ADG5208F
S1
D
S8
13035-001
1-OF-8
DECODER
A0 A1 A2 EN
Figure 1. ADG5208F Functional Block Diagram
APPLICATIONS
ADG5209F
Analog input/output modules
Process control/distributed control systems
Data acquisition
Instrumentation
Avionics
Automatic test equipment
Communication systems
Relay replacement
S1A
DA
S4A
S1B
DB
S4B
A0
A1
EN
13035-002
1-OF-4
DECODER
Figure 2. ADG5209F Functional Block Diagram
GENERAL DESCRIPTION
The ADG5208F and ADG5209F are 8:1 and dual 4:1 analog
multiplexers. The ADG5208F switches one of eight inputs to a
common output, and the ADG5209F switches one of four
differential inputs to a common differential output. An EN input
on both devices enables or disables the device. Each channel
conducts equally well in both directions when on, and each
channel has an input signal range that extends to the supplies.
The digital inputs are compatible with 3 V logic inputs over the
full operating supply range.
When no power supplies are present, the channel remains in the off
condition, and the switch inputs are high impedance. Under normal
operating conditions, if the analog input signal levels on any Sx pin
exceed positive fault voltage (VDD) or negative fault voltage (VSS)
by a threshold voltage (VT), the channel turns off and that Sx pin
becomes high impedance. If the fault channel is selected, the drain
pin is pulled to the secondary supply voltage that was exceeded.
Rev. A
Input signal levels of up to −55 V or +55 V relative to ground are
blocked, in both the powered and unpowered conditions.
The low capacitance and charge injection of these switches make
them ideal solutions for data acquisition and sample-and-hold
applications, where low glitch switching and fast settling times
are required.
PRODUCT HIGHLIGHTS
1.
2.
3.
4.
5.
The source pins are protected against voltages greater than
the supply rails, up to −55 V and +55 V.
The source pins are protected against voltages between
−55 V and +55 V in an unpowered state.
Trench isolation guards against latch-up.
Optimized for low charge injection and on capacitance.
The ADG5208F/ADG5209F can be operated from a dual
supply of ±5 V up to ±22 V or a single power supply of 8 V
up to 44 V.
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ADG5208F/ADG5209F
Data Sheet
TABLE OF CONTENTS
Features .............................................................................................. 1
Test Circuits ..................................................................................... 20
Applications ....................................................................................... 1
Terminology .................................................................................... 23
Functional Block Diagrams ............................................................. 1
Theory of Operation ...................................................................... 24
General Description ......................................................................... 1
Switch Architecture .................................................................... 24
Product Highlights ........................................................................... 1
Fault Protection .......................................................................... 25
Revision History ............................................................................... 2
Applications Information .............................................................. 26
Specifications..................................................................................... 3
Power Supply Rails ..................................................................... 26
±15 V Dual Supply ....................................................................... 3
Power Supply Sequencing Protection ...................................... 26
±20 V Dual Supply ....................................................................... 5
Signal Range ................................................................................ 26
12 V Single Supply ........................................................................ 7
Power Supply Recommendations............................................. 26
36 V Single Supply ........................................................................ 9
High Voltage Surge Suppression .............................................. 26
Continuous Current per Channel, Sx, D, or Dx ..................... 11
Large Voltage, High Frequency Signals ................................... 26
Absolute Maximum Ratings.......................................................... 12
Outline Dimensions ....................................................................... 27
ESD Caution ................................................................................ 12
Ordering Guide .......................................................................... 27
Pin Configurations and Function Descriptions ......................... 13
Typical Performance Characteristics ........................................... 15
REVISION HISTORY
3/16—Rev. 0 to Rev. A
Added 16-Lead LFCSP....................................................... Universal
Changes to General Description Section ...................................... 1
Changes to Table 5 .......................................................................... 11
Changes to Table 6 .......................................................................... 12
Added Figure 4; Renumbered Sequentially ................................ 13
Changes to Table 7 .......................................................................... 13
Added Figure 6 ................................................................................ 14
Changes to Table 9 .......................................................................... 14
Updated Outline Dimensions ....................................................... 27
Changes to Ordering Guide .......................................................... 27
4/15—Revision 0: Initial Version
Rev. A | Page 2 of 27
Data Sheet
ADG5208F/ADG5209F
SPECIFICATIONS
±15 V DUAL SUPPLY
VDD = 15 V ± 10%, VSS = −15 V ± 10%, GND = 0 V, CDECOUPLING = 0.1 µF, unless otherwise noted.
Table 1.
Parameter
ANALOG SWITCH
Analog Signal Range
On Resistance, RON
On-Resistance Match Between Channels,
∆RON
On-Resistance Flatness, RFLAT(ON)
Threshold Voltage, VT
LEAKAGE CURRENTS
Source Off Leakage, IS (Off )
Drain Off Leakage, ID (Off )
Channel On Leakage, ID (On), S (On)
FAULT
Source Leakage Current, IS
With Overvoltage
Power Supplies Grounded or
Floating
Drain Leakage Current, ID
With Overvoltage
+25°C
−40°C to
+85°C
VDD to VSS
250
270
250
270
2.5
6
2.5
6
6.5
8
1.5
3.5
0.7
±0.1
±1
±0.1
±1
±0.3
±1.5
335
395
335
395
12
13
12
13
9
9
4
4
V
Ω typ
Ω max
Ω typ
Ω max
Ω typ
Ω max
Ω typ
Ω max
Ω typ
Ω max
Ω typ
Ω max
V typ
±5
±5
±10
±20
±25
nA typ
nA max
nA typ
nA max
nA typ
nA max
±66
±78
µA typ
±25
±40
µA typ
±10
nA typ
±70
Power Supplies Grounded
Power Supplies Floating
±700
±50
±700
±50
Digital Input Capacitance, CIN
Unit
±2
±50
±500
DIGITAL INPUTS
Input Voltage
High, VINH
Low, VINL
Input Current, IINL or IINH
−40°C to
+125°C
±0.7
±1.1
5.0
±90
nA max
nA typ
±700
±50
nA max
µA typ
2.0
0.8
V min
V max
µA typ
µA max
pF typ
±1.2
Rev. A | Page 3 of 27
Test Conditions/Comments
VDD = +13.5 V, VSS = −13.5 V, see Figure 38
VS = ±10 V, IS = −1 mA
VS = ±9 V, IS = −1 mA
VS = ±10 V, IS = −1 mA
VS = ±9 V, IS = −1 mA
VS = ±10 V, IS = −1 mA
VS = ±9 V, IS = −1 mA
See Figure 30
VDD = +16.5 V, VSS = −16.5 V
VS = ±10 V, VD = ∓10 V, see Figure 36
VS = ±10 V, VD = ∓10 V, see Figure 36
VS = VD = ±10 V, see Figure 37
VDD = +16.5 V, VSS = −16.5 V, GND = 0 V, VS =
±55 V, see Figure 35
VDD = 0 V or floating, VSS = 0 V or floating, GND =
0 V, Ax = 0 V or floating, VS = ±55 V, see Figure 34
VDD = +16.5 V, VSS = −16.5 V, GND = 0 V, VS =
±55 V, see Figure 35
VDD = 0 V, VSS = 0 V, GND = 0 V, VS = ±55 V, Ax = 0 V,
see Figure 34
VDD = floating, VSS = floating, GND = 0 V,
VS = ±55 V, Ax = 0 V, see Figure 34
VIN = VGND or VDD
ADG5208F/ADG5209F
Parameter
DYNAMIC CHARACTERISTICS 1
Transition Time, tTRANSITION
tON (EN)
tOFF (EN)
Break-Before-Make Time Delay, tD
Data Sheet
+25°C
180
230
180
235
95
125
130
−40°C to
+85°C
−40°C to
+125°C
245
260
250
260
145
145
90
Overvoltage Response Time, tRESPONSE
Overvoltage Recovery Time, tRECOVERY
Charge Injection, QINJ
Off Isolation
Channel-to-Channel Crosstalk
Adjacent Channels
Nonadjacent Channels
Total Harmonic Distortion Plus Noise,
THD + N
−3 dB Bandwidth
ADG5208F
ADG5209F
Insertion Loss
CS (Off )
CD (Off )
ADG5208F
ADG5209F
CD (On), CS (On)
ADG5208F
ADG5209F
POWER REQUIREMENTS
Normal Mode
IDD
IGND
ISS
Fault Mode
IDD
IGND
ISS
90
115
745
945
−0.4
−76
130
965
970
Test Conditions/Comments
ns typ
ns max
ns typ
ns max
ns typ
ns max
ns typ
ns min
ns typ
ns max
ns typ
ns max
pC typ
dB typ
RL = 1 kΩ, CL = 35 pF
VS = 8 V, see Figure 47
RL = 1 kΩ, CL = 35 pF
VS = 10 V, see Figure 46
RL = 1 kΩ, CL = 35 pF
VS = 10 V, see Figure 46
RL = 1 kΩ, CL = 35 pF
VS = 10 V, see Figure 45
RL = 1 kΩ, CL = 5 pF, see Figure 43
−75
−88
0.005
dB typ
dB typ
% typ
190
290
10.5
4
MHz typ
MHz typ
dB typ
pF typ
13
8
pF typ
pF typ
20
14
pF typ
pF typ
RL = 1 kΩ, CL = 5 pF, see Figure 44
VS = 0 V, RS = 0 Ω, CL = 1 nF, see Figure 48
RL = 50 Ω, CL = 5 pF, f = 1 MHz, see Figure 40
RL = 50 Ω, CL = 5 pF, f = 1 MHz, see Figure 42
RL = 10 kΩ, VS = 15 V p-p, f = 20 Hz to 20 kHz, see
Figure 39
RL = 50 Ω, CL = 5 pF, see Figure 41
RL = 50 Ω, CL = 5 pF, f = 1 MHz, see Figure 41
VS = 0 V, f = 1 MHz
VS = 0 V, f = 1 MHz
VS = 0 V, f = 1 MHz
VDD = +16.5 V; VSS = −16.5 V; GND = 0 V;
digital inputs = 0 V, 5 V, or VDD
1.3
2
0.75
1.25
0.65
0.8
2
1.25
0.85
mA typ
mA max
mA typ
mA max
mA typ
mA max
VS = ±55 V
1.6
2.2
0.9
1.6
0.65
1.0
VDD/VSS
1
130
Unit
2.3
1.7
1.1
±5
±22
Guaranteed by design; not subject to production test.
Rev. A | Page 4 of 27
mA typ
mA max
mA typ
mA max
mA typ
mA max
V min
V max
GND = 0 V
GND = 0 V
Data Sheet
ADG5208F/ADG5209F
±20 V DUAL SUPPLY
VDD = 20 V ± 10%, VSS = −20 V ± 10%, GND = 0 V, CDECOUPLING = 0.1 µF, unless otherwise noted.
Table 2.
Parameter
ANALOG SWITCH
Analog Signal Range
On Resistance, RON
On-Resistance Match Between
Channels, ∆RON
On-Resistance Flatness, RFLAT(ON)
Threshold Voltage, VT
LEAKAGE CURRENTS
Source Off Leakage, IS (Off )
Drain Off Leakage, ID (Off )
Channel On Leakage, ID (On), IS (On)
FAULT
Source Leakage Current, IS
With Overvoltage
Power Supplies Grounded or Floating
Drain Leakage Current, ID
With Overvoltage
+25°C
−40°C to
+85°C
VDD to VSS
260
280
250
270
2.5
6
2.5
6
12.5
14
1.5
3.5
0.7
±0.1
±1
±0.1
±1
±0.3
±1.5
345
405
335
395
12
13
15
15
4
4
±2
±5
±5
±10
±20
±25
Unit
V
Ω typ
Ω max
Ω typ
Ω max
Ω typ
Ω max
Ω typ
Ω max
Ω typ
Ω max
Ω typ
Ω max
V typ
nA typ
nA max
nA typ
nA max
nA typ
nA max
±66
µA typ
±25
µA typ
±10
nA typ
±2
±500
±2
Power Supplies Floating
±700
±50
±700
±50
Digital Input Capacitance, CIN
13
12
Power Supplies Grounded
DIGITAL INPUTS
Input Voltage
High, VINH
Low, VINL
Input Current, IINL or IINH
−40°C to
+125°C
±0.7
±1.1
5.0
±2
µA max
nA typ
±700
±50
nA max
µA typ
2.0
0.8
V min
V max
µA typ
µA max
pF typ
±1.2
Rev. A | Page 5 of 27
Test Conditions/Comments
VDD = +18 V, VSS = −18 V, see Figure 38
VS = ±15 V, IS = −1 mA
VS = ±13.5 V, IS = −1 mA
VS = ±15 V, IS = −1 mA
VS = ±13.5 V, IS = −1 mA
VS = ±15 V, IS = −1 mA
VS = ±13.5 V, IS = −1 mA
See Figure 30
VDD = +22 V, VSS = −22 V
VS = ±15 V, VD = ∓15 V, see Figure 36
VS = ±15 V, VD = ∓15 V, see Figure 36
VS = VD = ±15 V, see Figure 37
VDD = +22 V, VSS = −22 V, GND = 0 V, VS = ±55 V,
see Figure 35
VDD = 0 V or floating, VSS = 0 V or floating, GND =
0 V, Ax = 0 V or floating, VS = ±55 V, see Figure 34
VDD = +22 V, VSS = −22 V, GND = 0 V, VS = ±55 V,
see Figure 35
VDD = 0 V, VSS = 0 V, GND = 0 V, VS = ±55 V, Ax =
0 V, see Figure 34
VDD = floating, VSS = floating, GND = 0 V, VS =
±55 V, Ax = 0 V, see Figure 34
VIN = VGND or VDD
ADG5208F/ADG5209F
Parameter
DYNAMIC CHARACTERISTICS 1
Transition Time, tTRANSITION
tON (EN)
tOFF (EN)
Break-Before-Make Time Delay, tD
Data Sheet
+25°C
190
245
185
250
95
120
140
−40°C to
+85°C
−40°C to
+125°C
270
285
270
280
145
145
90
Overvoltage Response Time, tRESPONSE
Overvoltage Recovery Time, tRECOVERY
Charge Injection, QINJ
Off Isolation
Channel-to-Channel Crosstalk
Adjacent Channels
Nonadjacent Channels
Total Harmonic Distortion Plus Noise,
THD + N
−3 dB Bandwidth
ADG5208F
ADG5209F
Insertion Loss
CS (Off )
CD (Off )
ADG5208F
ADG5209F
CD (On), CS (On)
ADG5208F
ADG5209F
POWER REQUIREMENTS
Normal Mode
IDD
IGND
ISS
Fault Mode
IDD
IGND
ISS
75
105
820
1100
−0.8
−76
105
1250
1400
Test Conditions/Comments
ns typ
ns max
ns typ
ns max
ns typ
ns max
ns typ
ns min
ns typ
ns max
ns typ
ns max
pC typ
dB typ
RL = 1 kΩ, CL = 35 pF
VS = 10 V, see Figure 47
RL = 1 kΩ, CL = 35 pF
VS = 10 V, see Figure 46
RL = 1 kΩ, CL = 35 pF
VS = 10 V, see Figure 46
RL = 1 kΩ, CL = 35 pF
VS = 10 V, see Figure 45
RL = 1 kΩ, CL = 5 pF, see Figure 43
−75
−88
0.005
dB typ
dB typ
% typ
190
290
10.5
4
MHz typ
MHz typ
dB typ
pF typ
12
8
pF typ
pF typ
19
14
pF typ
pF typ
RL = 1 kΩ, CL = 5 pF, see Figure 44
VS = 0 V, RS = 0 Ω, CL = 1 nF, see Figure 48
RL = 50 Ω, CL = 5 pF, f = 1 MHz, see Figure 40
RL = 50 Ω, CL = 5 pF, f = 1 MHz, see Figure 42
RL = 10 kΩ, VS = 20 V p-p, f = 20 Hz to 20 kHz,
see Figure 39
RL = 50 Ω, CL = 5 pF, see Figure 41
RL = 50 Ω, CL = 5 pF, f = 1 MHz, see Figure 41
VS = 0 V, f = 1 MHz
VS = 0 V, f = 1 MHz
VS = 0 V, f = 1 MHz
VDD = +22 V; VSS = −22 V; GND = 0 V; digital
inputs = 0 V, 5 V, or VDD
1.3
2
0.75
1.25
0.65
0.8
2
1.25
0.85
mA typ
mA max
mA typ
mA max
mA typ
mA max
VS = ±55 V
1.6
2.2
0.9
1.6
0.65
1.0
VDD/VSS
1
105
Unit
2.3
1.7
1.1
±5
±22
Guaranteed by design; not subject to production test.
Rev. A | Page 6 of 27
mA typ
mA max
mA typ
mA max
mA typ
mA max
V min
V max
GND = 0 V
GND = 0 V
Data Sheet
ADG5208F/ADG5209F
12 V SINGLE SUPPLY
VDD = 12 V ± 10%, VSS = 0 V, GND = 0 V, CDECOUPLING = 0.1 µF, unless otherwise noted.
Table 3.
Parameter
ANALOG SWITCH
Analog Signal Range
On Resistance, RON
On-Resistance Match Between
Channels, ∆RON
On-Resistance Flatness, RFLAT(ON)
Threshold Voltage, VT
LEAKAGE CURRENTS
Source Off Leakage, IS (Off )
Drain Off Leakage, ID (Off )
Channel On Leakage, ID (On), IS (On)
FAULT
Source Leakage Current, IS
With Overvoltage
Power Supplies Grounded or Floating
Drain Leakage Current, ID
With Overvoltage
+25°C
−40°C to
+85°C
0 V to VDD
630
690
270
290
6
17
3
6.5
380
440
25
27
0.7
±0.1
±1
±0.1
±1
±0.3
±1.5
710
730
355
410
19
12
460
460
28
28
±2
±5
±5
±10
±20
±25
Unit
V
Ω typ
Ω max
Ω typ
Ω max
Ω typ
Ω max
Ω typ
Ω max
Ω typ
Ω max
Ω typ
Ω max
V typ
nA typ
nA max
nA typ
nA max
nA typ
nA max
±63
µA typ
±25
µA typ
±10
nA typ
±50
±500
±70
Power Supplies Floating
±700
±50
±700
±50
Digital Input Capacitance, CIN
19
11
Power Supplies Grounded
DIGITAL INPUTS
Input Voltage
High, VINH
Low, VINL
Input Current, IINL or IINH
−40°C to
+125°C
±0.7
±1.1
5.0
±90
nA max
nA typ
±700
±50
nA max
µA typ
2.0
0.8
V min
V max
µA typ
µA max
pF typ
±1.2
Rev. A | Page 7 of 27
Test Conditions/Comments
VDD = 10.8 V, VSS = 0 V, see Figure 38
VS = 0 V to 10 V, IS = −1 mA
VS = 3.5 V to 8.5 V, IS = −1 mA
VS = 0 V to 10 V, IS = −1 mA
VS = 3.5 V to 8.5 V, IS = −1 mA
VS = 0 V to 10 V, IS = −1 mA
VS = 3.5 V to 8.5 V, IS = −1 mA
See Figure 30
VDD = 13.2 V, VSS = 0 V
VS = 1 V/10 V, VD = 10 V/1 V, see Figure 36
VS = 1 V/10 V, VD = 10 V/1 V, see Figure 36
VS = VD = 1 V/10 V, see Figure 37
VDD = 13.2 V, VSS = 0 V, GND = 0 V, VS = ±55 V,
see Figure 35
VDD = 0 V or floating, VSS = 0 V or floating, GND =
0 V, Ax = 0 V or floating, VS = ±55 V, see Figure 34
VDD = 13.2 V, VSS = 0 V, GND = 0 V, VS = ±55 V,
see Figure 35
VDD = 0 V, VSS = 0 V, GND = 0 V, VS = ±55 V, Ax =
0 V, see Figure 34
VDD = floating, VSS = floating, GND = 0 V, VS =
±55 V, Ax = 0 V, see Figure 34
VIN = VGND or VDD
ADG5208F/ADG5209F
Parameter
DYNAMIC CHARACTERISTICS 1
Transition Time, tTRANSITION
tON (EN)
tOFF (EN)
Break-Before-Make Time Delay, tD
Data Sheet
+25°C
160
200
160
200
130
155
95
−40°C to
+85°C
−40°C to
+125°C
215
230
220
235
160
160
65
Overvoltage Response Time, tRESPONSE
Overvoltage Recovery Time, tRECOVERY
Charge Injection, QINJ
Off Isolation
Channel-to-Channel Crosstalk
Adjacent Channels
Nonadjacent Channels
Total Harmonic Distortion Plus Noise,
THD + N
−3 dB Bandwidth
ADG5208F
ADG5209F
Insertion Loss
CS (Off )
CD (Off )
ADG5208F
ADG5209F
CD (On), CS (On)
ADG5208F
ADG5209F
POWER REQUIREMENTS
Normal Mode
IDD
IGND
ISS
Fault Mode
IDD
IGND
ISS
110
145
500
655
0.9
−74
145
720
765
Test Conditions/Comments
ns typ
ns max
ns typ
ns max
ns typ
ns max
ns typ
ns min
ns typ
ns max
ns typ
ns max
pC typ
dB typ
RL = 1 kΩ, CL = 35 pF
VS = 8 V, see Figure 47
RL = 1 kΩ, CL = 35 pF
VS = 8 V, see Figure 46
RL = 1 kΩ, CL = 35 pF
VS = 8 V, see Figure 46
RL = 1 kΩ, CL = 35 pF
VS = 8 V, see Figure 45
RL = 1 kΩ, CL = 5 pF, see Figure 43
−75
−88
0.044
dB typ
dB typ
% typ
175
270
10.5
4
MHz typ
MHz typ
dB typ
pF typ
14
8
pF typ
pF typ
21
14
pF typ
pF typ
RL = 1 kΩ, CL = 5 pF, see Figure 44
VS = 6 V, RS = 0 Ω, CL = 1 nF, see Figure 48
RL = 50 Ω, CL = 5 pF, f = 1 MHz, see Figure 40
RL = 50 Ω, CL = 5 pF, f = 1 MHz, see Figure 42
RL = 10 kΩ, VS = 6 V p-p, f = 20 Hz to 20 kHz,
see Figure 39
RL = 50 Ω, CL = 5 pF, see Figure 41
RL = 50 Ω, CL = 5 pF, f = 1 MHz, see Figure 41
VS = 6 V, f = 1 MHz
VS = 6 V, f = 1 MHz
VS = 6 V, f = 1 MHz
VDD = 13.2 V; VSS = 0 V; GND = 0 V; digital
inputs = 0 V, 5 V, or VDD
1.3
2
0.75
1.4
0.5
0.65
2
1.4
0.7
mA typ
mA max
mA typ
mA max
mA typ
mA max
VS = ±55 V
1.6
2.2
0.9
1.6
0.65
1.0
VDD
1
145
Unit
2.3
1.7
1.1
8
44
Guaranteed by design; not subject to production test.
Rev. A | Page 8 of 27
mA typ
mA max
mA typ
mA max
mA typ
mA max
V min
V max
Digital inputs = 5 V
VS = ±55 V, VD = 0 V
GND = 0 V
GND = 0 V
Data Sheet
ADG5208F/ADG5209F
36 V SINGLE SUPPLY
VDD = 36 V ± 10%, VSS = 0 V, GND = 0 V, CDECOUPLING = 0.1 µF, unless otherwise noted.
Table 4.
Parameter
ANALOG SWITCH
Analog Signal Range
On Resistance, RON
On-Resistance Match Between
Channels, ∆RON
On-Resistance Flatness, RFLAT(ON)
Threshold Voltage, VT
LEAKAGE CURRENTS
Source Off Leakage, IS (Off )
Drain Off Leakage, ID (Off )
Channel On Leakage, ID (On), IS (On)
FAULT
Source Leakage Current, IS
With Overvoltage
Power Supplies Grounded or
Floating
Drain Leakage Current, ID
With Overvoltage
+25°C
−40°C to
+85°C
0 V to VDD
310
335
250
270
3
7
3
6.5
62
70
1.5
3.5
0.7
±0.1
±1
±0.1
±1
±0.3
±1.5
415
480
335
395
16
12
85
100
4
4
±2
±5
±5
±10
±20
±25
Unit
V
Ω typ
Ω max
Ω typ
Ω max
Ω typ
Ω max
Ω typ
Ω max
Ω typ
Ω max
Ω typ
Ω max
V typ
nA typ
nA max
nA typ
nA max
nA typ
nA max
±58
µA typ
±25
µA typ
±10
nA typ
±50
±500
±70
Power Supplies Floating
±700
±50
±700
±50
Digital Input Capacitance, CIN
18
11
Power Supplies Grounded
DIGITAL INPUTS
Input Voltage
High, VINH
Low, VINL
Input Current, IINL or IINH
−40°C to
+125°C
±0.7
±1.1
5.0
±90
nA max
nA typ
±700
±50
nA max
µA typ
2.0
0.8
V min
V max
µA typ
µA max
pF typ
±1.2
Rev. A | Page 9 of 27
Test Conditions/Comments
VDD = 32.4 V, VSS = 0 V, see Figure 38
VS = 0 V to 30 V, IS = −1 mA
VS = 4.5 V to 28 V, IS = −1 mA
VS = 0 V to 30 V, IS = −1 mA
VS = 4.5 V to 28 V, IS = −1 mA
VS = 0 V to 30 V, IS = −1 mA
VS = 4.5 V to 28 V, IS = −1 mA
See Figure 30
VDD = 39.6 V, VSS = 0 V
VS = 1 V/ 30 V, VD = 30 V/1 V, see Figure 36
VS = 1 V/ 30 V, VD = 30 V/1 V, see Figure 36
VS = VD = 1 V/30 V, see Figure 37
VDD = +39.6 V, VSS = 0 V, GND = 0 V, VS = +55 V,
−40 V, see Figure 35
VDD = 0 V or floating, VSS = 0 V or floating, GND =
0 V, Ax = 0 V or floating, VS = ±55 V, see Figure 34
VDD = 39.6 V, VSS = 0 V, GND = 0 V, VS = ±55 V, see
Figure 35
VDD = 0 V, VSS = 0 V, GND = 0 V, VS = +55 V, −40 V,
Ax = 0 V, see Figure 34
VDD = floating, VSS = floating, GND = 0 V, VS = ±55 V,
Ax = 0 V, see Figure 34
VIN = VGND or VDD
ADG5208F/ADG5209F
Parameter
DYNAMIC CHARACTERISTICS 1
Transition Time, tTRANSITION
tON (EN)
tOFF (EN)
Break-Before-Make Time Delay, tD
Data Sheet
+25°C
180
230
175
225
105
135
105
−40°C to
+85°C
−40°C to
+125°C
245
255
245
260
150
150
65
Overvoltage Response Time, tRESPONSE
Overvoltage Recovery Time, tRECOVERY
Charge Injection, QINJ
Off Isolation
Channel-to-Channel Crosstalk
Adjacent Channels
Nonadjacent Channels
Total Harmonic Distortion Plus Noise,
THD + N
−3 dB Bandwidth
ADG5208F
ADG5209F
Insertion Loss
CS (Off )
CD (Off )
ADG5208F
ADG5209F
CD (On), CS (On)
ADG5208F
ADG5209F
POWER REQUIREMENTS
Normal Mode
IDD
IGND
ISS
Fault Mode
IDD
IGND
ISS
60
80
1400
1900
−0.9
−75
85
2100
2200
Test Conditions/Comments
ns typ
ns max
ns typ
ns max
ns typ
ns max
ns typ
ns min
ns typ
ns max
ns typ
ns max
pC typ
dB typ
RL = 1 kΩ, CL = 35 pF
VS = 18 V, see Figure 47
RL = 1 kΩ, CL = 35 pF
VS = 18 V, see Figure 46
RL = 1 kΩ, CL = 35 pF
VS = 18 V, see Figure 46
RL = 1 kΩ, CL = 35 pF
VS = 18 V, see Figure 45
RL = 1 kΩ, CL = 5 pF, see Figure 43
−75
−88
0.007
dB typ
dB typ
% typ
200
300
10.5
3
MHz typ
MHz typ
dB typ
pF typ
12
7
pF typ
pF typ
19
12
pF typ
pF typ
RL = 1 kΩ, CL = 5 pF, see Figure 44
VS = 18 V, RS = 0 Ω, CL = 1 nF, see Figure 48
RL = 50 Ω, CL = 5 pF, f = 1 MHz, see Figure 40
RL = 50 Ω, CL = 5 pF, f = 1 MHz, see Figure 42
RL = 10 kΩ, VS = 18 V p-p, f = 20 Hz to 20 kHz,
see Figure 39
RL = 50 Ω, CL = 5 pF, see Figure 41
RL = 50 Ω, CL = 5 pF, f = 1 MHz, see Figure 41
VS = 18 V, f = 1 MHz
VS = 18 V, f = 1 MHz
VS = 18 V, f = 1 MHz
VDD = 39.6 V; VSS = 0 V; GND = 0 V; digital inputs =
0 V, 5 V, or VDD
1.3
2
0.75
1.4
0.5
0.65
2
1.4
0.7
mA typ
mA max
mA typ
mA max
mA typ
mA max
VS = +55 V, −40 V
1.6
2.2
0.9
1.6
0.65
1.0
VDD
1
85
Unit
2.3
1.7
1.1
8
44
Guaranteed by design; not subject to production test.
Rev. A | Page 10 of 27
mA typ
mA max
mA typ
mA max
mA typ
mA max
V min
V max
GND = 0 V
GND = 0 V
Data Sheet
ADG5208F/ADG5209F
CONTINUOUS CURRENT PER CHANNEL, Sx, D, OR Dx
Table 5.
Parameter
ADG5208F
16-Lead TSSOP, θJA = 112.6°C/W
16-Lead LFCSP, θJA = 30.4°C/W
ADG5209F
16-Lead TSSOP, θJA = 112.6°C/W
16-Lead LFCSP, θJA = 30.4°C/W
25°C
85°C
125°C
Unit
Test Conditions/Comments
27
16
48
27
16
11
25
17
8
7
11
9
mA max
mA max
mA max
mA max
VS = VSS to VDD − 4.5 V
VS = VSS to VDD
VS = VSS to VDD − 4.5 V
VS = VSS to VDD
20
12
36
21
13
8
20
13
8
6
10
8
mA max
mA max
mA max
mA max
VS = VSS to VDD − 4.5 V
VS = VSS to VDD
VS = VSS to VDD − 4.5 V
VS = VSS to VDD
Rev. A | Page 11 of 27
ADG5208F/ADG5209F
Data Sheet
ABSOLUTE MAXIMUM RATINGS
TA = 25°C, unless otherwise noted.
Table 6.
Parameter
VDD to VSS
VDD to GND
VSS to GND
Sx Pins
Sx to VDD or VSS
VS to VD
D or Dx Pins1
Digital Inputs2
Peak Current, Sx, D, or Dx Pins
Continuous Current, Sx, D, or Dx
Pins
D or Dx Pins, Overvoltage State,
Load Current
Operating Temperature Range
Storage Temperature Range
Junction Temperature
Thermal Impedance, θJA (4-Layer
Board)
16-Lead TSSOP
16-Lead LFCSP
Reflow Soldering Peak
Temperature, Pb-Free
Rating
48 V
−0.3 V to +48 V
−48 V to +0.3 V
−55 V to +55 V
80 V
80 V
VSS − 0.7 V to VDD + 0.7 V or
30 mA, whichever occurs first
GND − 0.7 V to 48 V or
30 mA, whichever occurs first
72.5 mA (pulsed at 1 ms,
10% duty cycle maximum)
Data3 + 15%
Stresses at or above those listed under Absolute Maximum
Ratings may cause permanent damage to the product. This is a
stress rating only; functional operation of the product at these
or any other conditions above those indicated in the operational
section of this specification is not implied. Operation beyond
the maximum operating conditions for extended periods may
affect product reliability.
Only one absolute maximum rating can be applied at any
one time.
ESD CAUTION
1 mA
−40°C to +125°C
−65°C to +150°C
150°C
112.6°C/W
30.4°C/W
As per JEDEC J-STD-020
Overvoltages at the D or Dx pins are clamped by internal diodes. Limit the
current to the maximum ratings given.
2
The digital inputs are the EN and Ax pins.
3
See Table 5.
1
Rev. A | Page 12 of 27
Data Sheet
ADG5208F/ADG5209F
11 S6
S4 7
10 S7
D 8
9
S8
13 A2
12 GND
S1 2
ADG5208F
11 VDD
S2 3
TOP VIEW
(Not to Scale)
10 S5
9
S3 4
S8 7
S3 6
14 A1
VSS 1
S6
NOTES
1. THE EXPOSED PAD IS CONNECTED INTERNALLY. FOR
INCREASED RELIABILITY OF THE SOLDER JOINTS AND
MAXIMUM THERMAL CAPABILITY, IT IS RECOMMENDED
THAT THE PAD BE SOLDERED TO THE SUBSTRATE, VSS.
13035-004
14 GND
13 VDD
TOP VIEW
(Not to Scale) 12 S5
S4 5
S2 5
ADG5208F
13035-003
S1 4
S7 8
15 A2
VSS 3
16 EN
16 A1
D 6
A0 1
EN 2
15 A0
PIN CONFIGURATIONS AND FUNCTION DESCRIPTIONS
Figure 4. ADG5208F Pin Configuration (LFCSP)
Figure 3. ADG5208F Pin Configuration (TSSOP)
Table 7. ADG5208F Pin Function Descriptions
Pin No.
TSSOP
1
2
LFCSP
15
16
Mnemonic
A0
EN
3
4
5
6
7
8
9
10
11
12
13
14
15
16
N/A1
1
2
3
4
5
6
7
8
9
10
11
12
13
14
0
VSS
S1
S2
S3
S4
D
S8
S7
S6
S5
VDD
GND
A2
A1
EPAD
1
Description
Logic Control Input.
Active High Digital Input. When this pin is low, the device is disabled and all switches are off. When
this pin is high, the Ax logic inputs determine the on switches.
Most Negative Power Supply Potential.
Overvoltage Protected Source Terminal 1. This pin can be an input or an output.
Overvoltage Protected Source Terminal 2. This pin can be an input or an output.
Overvoltage Protected Source Terminal 3. This pin can be an input or an output.
Overvoltage Protected Source Terminal 4. This pin can be an input or an output.
Drain Terminal. This pin can be an input or an output.
Overvoltage Protected Source Terminal 8. This pin can be an input or an output.
Overvoltage Protected Source Terminal 7. This pin can be an input or an output.
Overvoltage Protected Source Terminal 6. This pin can be an input or an output.
Overvoltage Protected Source Terminal 5. This pin can be an input or an output.
Most Positive Power Supply Potential.
Ground (0 V) Reference.
Logic Control Input.
Logic Control Input.
Exposed Pad. The exposed pad is connected internally. For increased reliability of the solder joints
and maximum thermal capability, it is recommended that the pad be soldered to the substrate, VSS.
N/A means not applicable.
Table 8. ADG5208F Truth Table
A2
X1
0
0
0
0
1
1
1
1
1
A1
X1
0
0
1
1
0
0
1
1
A0
X1
0
1
0
1
0
1
0
1
EN
0
1
1
1
1
1
1
1
1
X is don’t care.
Rev. A | Page 13 of 27
On Switch
None
S1
S2
S3
S4
S5
S6
S7
S8
2
16 A1
VSS
3
S1A
4
S2A
5
13 S1B
TOP VIEW
(Not to Scale) 12 S2B
S3A
6
11 S3B
S4A
7
10 S4B
DA
8
9
15 GND
14 VDD
12 VDD
S1A 2
ADG5209F
11 S1B
S2A 3
TOP VIEW
(Not to Scale)
10 S2B
9
NOTES
1. THE EXPOSED PAD IS CONNECTED INTERNALLY. FOR
INCREASED RELIABILITY OF THE SOLDER JOINTS AND
MAXIMUM THERMAL CAPABILITY, IT IS RECOMMENDED
THAT THE PAD BE SOLDERED TO THE SUBSTRATE, VSS.
Figure 5. ADG5209F Pin Configuration (TSSOP)
13035-006
DB 7
S3B
S4B 8
DA 6
S3A 4
S4A 5
DB
VSS 1
13035-005
ADG5209F
13 GND
1
14 A1
A0
EN
16 EN
Data Sheet
15 A0
ADG5208F/ADG5209F
Figure 6. ADG5209F Pin Configuration (LFCSP)
Table 9. ADG5209F Pin Function Descriptions
Pin No.
TSSOP LFCSP
1
15
2
16
Mnemonic
A0
EN
3
4
5
6
7
8
9
10
11
12
13
14
15
16
N/A1
VSS
S1A
S2A
S3A
S4A
DA
DB
S4B
S3B
S2B
S1B
VDD
GND
A1
EPAD
1
1
2
3
4
5
6
7
8
9
10
11
12
13
14
0
Description
Logic Control Input.
Active High Digital Input. When this pin is low, the device is disabled and all switches are off. When this
pin is high, the Ax logic inputs determine the on switches.
Most Negative Power Supply Potential.
Overvoltage Protected Source Terminal 1A. This pin can be an input or an output.
Overvoltage Protected Source Terminal 2A. This pin can be an input or an output.
Overvoltage Protected Source Terminal 3A. This pin can be an input or an output.
Overvoltage Protected Source Terminal 4A. This pin can be an input or an output.
Drain Terminal A. This pin can be an input or an output.
Drain Terminal B. This pin can be an input or an output.
Overvoltage Protected Source Terminal 4B. This pin can be an input or an output.
Overvoltage Protected Source Terminal 3B. This pin can be an input or an output.
Overvoltage Protected Source Terminal 2B. This pin can be an input or an output.
Overvoltage Protected Source Terminal 1B. This pin can be an input or an output.
Most Positive Power Supply Potential.
Ground (0 V) Reference.
Logic Control Input.
Exposed Pad. The exposed pad is connected internally. For increased reliability of the solder joints and
maximum thermal capability, it is recommended that the pad be soldered to the substrate, VSS.
N/A means not applicable.
Table 10. ADG5209F Truth Table
A1
X1
0
0
1
1
1
A0
X1
0
1
0
1
EN
0
1
1
1
1
On Switch Pair
None
S1x
S2x
S3x
S4x
X is don’t care.
Rev. A | Page 14 of 27
Data Sheet
ADG5208F/ADG5209F
TYPICAL PERFORMANCE CHARACTERISTICS
1200
1400
TA = 25°C
±22V
±20V
±18V
±16.5V
±15.0V
±13.5V
800
ON RESISTANCE (Ω)
600
400
200
600
400
–10
–5
0
5
10
15
20
25
0
–15
–12
–3
–6
–9
0
6
3
9
12
15
VS, VD (V)
Figure 7. RON as a Function of VS, VD, Dual Supply
13035-108
–15
13035-105
–20
VS, VD (V)
Figure 10. RON as a Function of VS, VD for Different Temperatures,
±15 V Dual Supply
1200
1400
TA = 25°C
13.2V
12.0V
10.8V
VDD = +20V
VSS = –20V
+125°C
+85°C
+25°C
–40°C
1200
ON RESISTANCE (Ω)
1000
800
600
400
200
1000
800
600
400
200
0
2
4
6
8
10
12
14
VS, VD (V)
0
–20
13035-106
0
–15
–5
–10
0
5
10
15
20
VS, VD (V)
Figure 8. RON as a Function of VS, VD, 12 V Single Supply
13035-109
ON RESISTANCE (Ω)
800
200
0
–25
Figure 11. RON as a Function of VS, VD for Different Temperatures,
±20 V Dual Supply
1200
1400
TA = 25°C
39.6V
36.0V
32.4V
VDD = 12V
VSS = 0V
+125°C
+85°C
+25°C
–40°C
1200
ON RESISTANCE (Ω)
1000
800
600
400
200
1000
800
600
400
200
0
0
5
10
15
20
25
30
35
VS, VD (V)
40
13035-107
ON RESISTANCE (Ω)
1000
Figure 9. RON as a Function of VS, VD, 36 V Single Supply
0
0
2
4
6
8
10
12
VS, VD (V)
Figure 12. RON as a Function of VS, VD for Different Temperatures,
12 V Single Supply
Rev. A | Page 15 of 27
13035-110
ON RESISTANCE (Ω)
1000
VDD = +15V
VSS = –15V
+125°C
+85°C
+25°C
–40°C
1200
ADG5208F/ADG5209F
Data Sheet
1400
1.5
1000
1.0
LEAKAGE CURRENT (nA)
1200
ON RESISTANCE (Ω)
VDD = 12V
VSS = 0V
VBIAS = 1V, 10V
VDD = 36V
VSS = 0V
+125°C
+85°C
+25°C
–40°C
800
600
400
0.5
0
–0.5
4
8
12
16
20
24
28
32
36
VS, VD (V)
–1.0
0
60
80
100
120
Figure 16. Leakage Current vs. Temperature, 12 V Single Supply
2.5
3
VDD = +15V
VSS = –15V
VBIAS = ±10V
VDD = 36V
VSS = 0V
VBIAS = 1V, 30V
2
1.5
1.0
0.5
0
–0.5
–1.0
IS (OFF) + –
IS (OFF) – +
IS, ID (ON) + +
ID (OFF) + –
ID (OFF) – +
IS, ID (ON) – –
–2.0
20
40
60
80
100
120
TEMPERATURE (°C)
40
60
80
100
120
Figure 17. Leakage Current vs. Temperature, 36 V Single Supply
6
VDD = +15V
VSS = –15V
LEAKAGE CURRENT (nA)
5
1
0
–1
60
80
100
120
3
2
VS = –30V
VS = +30V
VS = –55V
VS = +55V
TEMPERATURE (°C)
Figure 15. Leakage Current vs. Temperature, ±20 V Dual Supply
0
13035-113
–3
40
4
1
ID (OFF) + –
ID (OFF) – +
IS, ID (ON) – –
IS (OFF) + –
IS (OFF) – +
IS, ID (ON) + +
20
20
TEMPERATURE (°C)
VDD = +20V
VSS = –20V
VBIAS = ±15V
0
ID (OFF) + –
ID (OFF) – +
IS, ID (ON) – –
IS (OFF) + –
IS (OFF) – +
IS, ID (ON) + +
0
3
–2
–2
–4
Figure 14. Leakage Current vs. Temperature, ±15 V Dual Supply
2
–1
0
20
40
60
80
TEMPERATURE (°C)
100
120
13035-116
0
0
–3
13035-112
–1.5
1
13035-115
LEAKAGE CURRENT (nA)
LEAKAGE CURRENT (nA)
40
TEMPERATURE (°C)
Figure 13. RON as a Function of VS, VD for Different Temperatures,
36 V Single Supply
2.0
20
13035-114
0
13035-111
0
LEAKAGE CURRENT (nA)
ID (OFF) + –
ID (OFF) – +
IS, ID (ON) – –
IS (OFF) + –
IS (OFF) – +
IS, ID (ON) + +
200
Figure 18. Overvoltage Leakage Current vs. Temperature, ±15 V Dual Supply
Rev. A | Page 16 of 27
Data Sheet
ADG5208F/ADG5209F
0
6
VDD = +20V
VSS = –20V
OFF ISOLATION (dB)
5
4
3
2
VS = –30V
VS = +30V
VS = –55V
VS = +55V
20
–60
–80
–100
–120
0
0
–40
40
60
80
100
120
TEMPERATURE (°C)
–140
1k
0
–20
5
VDD = +15V
VSS = –15V
TA = 25°C
–40
CROSSTALK (dB)
–60
–80
–100
VS = –30V
VS = +30V
VS = –55V
VS = +55V
–120
0
0
20
40
60
80
100
120
TEMPERATURE (°C)
–140
10k
100k
1M
10M
100M
1G
FREQUENCY (Hz)
13035-121
1
13035-118
LEAKAGE CURRENT (nA)
1G
ADJACENT CHANNELS
NONADJACENT CHANNELS, COMMON DRAIN
NONADJACENT CHANNELS, SEPARATE DRAIN
VDD = 12V
VSS = 0V
2
100M
Figure 22. Off Isolation vs. Frequency, ±15 V Dual Supply
6
3
10M
FREQUENCY (Hz)
Figure 19. Overvoltage Leakage Current vs. Temperature, ±20 V Dual Supply
4
1M
100k
10k
13035-120
1
13035-117
LEAKAGE CURRENT (nA)
VDD = +15V
VSS = –15V
TA = 25°C
–20
Figure 23. Crosstalk vs. Frequency, ±15 V Dual Supply
Figure 20. Overvoltage Leakage Current vs. Temperature, 12 V Single Supply
6
6
VDD = 36V
VSS = 0V
4
CHARGE INJECTION (pC)
4
3
2
VS = –30V
VS = +40V
VS = –40V
VS = +55V
20
0
–2
–4
–6
TA = 25°C
–8
0
0
2
40
60
80
TEMPERATURE (°C)
100
120
Figure 21. Overvoltage Leakage Current vs. Temperature, 36 V Single Supply
Rev. A | Page 17 of 27
VDD = 36V, VSS = 0V
VDD = 12V, VSS = 0V
–10
0
5
10
15
20
25
30
35
40
VS (V)
Figure 24. Charge Injection vs. Source Voltage (VS), Single Supply
13035-122
1
13035-119
LEAKAGE CURRENT (nA)
5
Data Sheet
8
–9
6
–10
ADG5209F
ADG5208F
–11
4
–12
2
BANDWIDTH (dB)
CHARGE INJECTION (pC)
ADG5208F/ADG5209F
0
–2
–4
–13
–14
–15
–16
–17
–6
–8
–18
VDD = +20V, VSS = –20V
–15
–10
–5
0
5
10
15
20
VS (V)
VDD = +15V
VSS = –15V
TA = 25°C
–20
10k
13035-123
–10
–20
–19
VDD = +15V, VSS = –15V
100k
Figure 25. Charge Injection vs. Source Voltage (VS), Dual Supply
10M
100M
1G
Figure 28. Bandwidth vs. Frequency
0
220
VDD = +15V
VSS = –15V
TA = 25°C
–20
1M
FREQUENCY (Hz)
13035-126
TA = 25°C
VDD
VDD
VDD
VDD
210
= +12V,
= +36V,
= +15V,
= +20V,
VSS
VSS
VSS
VSS
= 0V
= 0V
= –15V
= –20V
200
tTRANSITION (ns)
ACPSRR (dB)
–40
–60
–80
190
180
170
160
–100
100k
1M
10M
100M
1G
FREQUENCY (Hz)
140
–40
13035-124
–120
10k
–20
20
40
60
80
100
120
100
120
TEMPERATURE (°C)
Figure 26. ACPSRR vs. Frequency, ±15 V Dual Supply
0.06
0
13035-127
150
Figure 29. tTRANSITION vs. Temperature
0.9
LOAD = 10kΩ
TA = 25°C
0.8
THRESHOLD VOLTAGE, VT (V)
0.05
0.03
VDD
VDD
VDD
VDD
0.02
= +12V,
= +36V,
= +15V,
= +20V,
VSS
VSS
VSS
VSS
= 0V, VS = +6V p-p
= 0V, VS = +18V p-p
= –15V, VS = +15V p-p
= –20V, VS = +20V p-p
0.6
0.5
0.4
0.3
0.2
0.01
0
0
5
10
15
FREQUENCY (kHz)
20
0
–40
–20
0
20
40
60
80
TEMPERATURE (°C)
Figure 30. Threshold Voltage (VT) vs. Temperature
Figure 27. THD + N vs. Frequency
Rev. A | Page 18 of 27
13035-128
0.1
13035-125
THD + N (%)
0.04
0.7
Data Sheet
ADG5208F/ADG5209F
TA = 25°C
VDD = +10V
VSS = –10V
T
20
SIGNAL VOLTAGE (V p-p)
VS
VDD
DRAIN
2
VSS
16
12
8
DISTORTIONLESS
OPERATING REGION
CH2 10V
CH4 10V
1µs
T
2.5GS/s A CH1
–10.0ns 100k POINTS
15.2V
0
1
10
FREQUENCY (MHz)
Figure 31. Drain Output Response to Positive Overvoltage
Figure 33. Large Voltage Signal Tracking vs. Frequency
T
VDD
DRAIN
2
VSS
CH1 10V
CH3 10V
CH2 10V
CH4 10V
1µs
T
2.5GS/s A CH1
–10.0ns 100k POINTS
–15.6V
13035-130
VS
Figure 32. Drain Output Response to Negative Overvoltage
Rev. A | Page 19 of 27
100
13035-131
CH1 10V
CH3 10V
13035-129
4
ADG5208F/ADG5209F
Data Sheet
TEST CIRCUITS
VDD
VSS
0.1µF
0.1µF
VDD = VSS = GND = 0V
ID
IS
D/Dx
NETWORK
ANALYZER
A
VDD
13035-040
RL
10kΩ
VS
VSS
Sx
Figure 34. Switch Unpowered Leakage
50Ω
50Ω
Ax
VS
D/Dx
VIN
IS
ID
D/Dx
GND
OFF ISOLATION = 20 log
Figure 35. Switch Overvoltage Leakage
IS (OFF)
ADG5208F*
S1
A
VSS
VDD
0.1µF
0.1µF
A
VDD
Ax
*SIMILAR CONNECTION FOR ADG5209F.
13035-035
VD
ADG5208F*
S1
VS
D/Dx
VIN
ID (ON)
D
RL
50Ω
GND
Figure 36. Off Leakage
INSERTION LOSS = 20 log
A
VOUT
VOUT WITH SWITCH
VOUT WITHOUT SWITCH
Figure 41. Bandwidth
S2
VDD
S8
A
50Ω
Sx
VS
NC
NETWORK
ANALYZER
VSS
S8
A
VS
Figure 40. Off Isolation
ID (OFF)
D
VOUT
13035-037
RL
10kΩ
|VS| > |VDD| OR |VSS|
VOUT
A
13035-039
Sx
A
RL
50Ω
13035-041
Sx
A
VSS
0.1µF
0.1µF
VD
*SIMILAR CONNECTION FOR ADG5209F.
VDD
RL
50Ω
V
13035-034
RON = V/IDS
VDD
0.1µF
VDD
AUDIO
PRECISION
VSS
RS
Sx
VS
V p-p
Ax
D/Dx
GND
RL
10kΩ
VOUT
13035-042
VIN
VS
VOUT
VS
Figure 42. Channel-to-Channel Crosstalk
VSS
Figure 39. THD + N
Rev. A | Page 20 of 27
VOUT
S2/S2x
CHANNEL-TO-CHANNEL CROSSTALK = 20 log
Figure 38. On Resistance
0.1µF
RL
50Ω
D/Dx
GND
D/Dx
IDS
VS
NETWORK
ANALYZER
S1/S1x
Figure 37. On Leakage
Sx
VSS
13035-038
NC = NO CONNECT
13035-036
VS
Data Sheet
ADG5208F/ADG5209F
VDD
VSS
0.1µF
0.1µF
VDD + 0.5V
VDD
SOURCE
VOLTAGE
(VS)
VSS
Sx
VD
D/Dx
CL
5pF
VS
0V
tRESPONSE
ADG5208F/
ADG5209F
VDD
OTHER SOURCE/
DRAIN PINS
GND
OUTPUT × 0.5
OUTPUT
(VD)
RL
1kΩ
0V
13035-043
NOTES
1. THE OUTPUT PULLS TO VDD WITHOUT A 1kΩ RESISTOR (INTERNAL 40kΩ
PULL-UP RESISTOR TO THE SUPPLY RAIL DURING A FAULT).
Figure 43. Overvoltage Response Time, tRESPONSE
VDD
VSS
0.1µF
0.1µF
VDD + 0.5V
VDD
SOURCE
VOLTAGE
(VS)
VSS
Sx
VD
D/Dx
CL
5pF
VS
0V
ADG5208F/
ADG5209F
tRECOVERY
OUTPUT
(VD)
RL
1kΩ
OTHER SOURCE/
DRAIN PINS
OUTPUT × 0.5
GND
13035-044
0V
NOTES
1. THE OUTPUT STARTS FROM THE VDD CLAMP LEVEL WITHOUT A 1kΩ RESISTOR
(INTERNAL 40kΩ PULL-UP RESISTOR TO THE SUPPLY RAIL DURING A FAULT).
Figure 44. Overvoltage Recovery Time, tRECOVERY
VSS
VDD
0.1µF
0.1µF
3V
VDD
ADDRESS
DRIVE (VIN)
VSS
A0
S1
VS
A1
VIN
0V
S2 TO S7
A2
S8
ADG5208F*
80%
80%
OUTPUT
2.0V
OUTPUT
D
EN
GND
1kΩ
35pF
*SIMILAR CONNECTION FOR ADG5209F.
Figure 45. Break-Before-Make Time Delay, tD
Rev. A | Page 21 of 27
13035-045
tD
ADG5208F/ADG5209F
Data Sheet
VDD
VSS
0.1µF
0.1µF
3V
VDD
ENABLE
DRIVE (VIN)
50%
VSS
A0
50%
S1
VS
A1
S2 TO S8
0V
A2
tON (EN)
ADG5208F*
tOFF (EN)
OUTPUT
0.9VOUT
D
EN
OUTPUT
VIN
35pF
1kΩ
GND
13035-046
0.1VOUT
*SIMILAR CONNECTION FOR ADG5209F.
Figure 46. Enable Delay, tON (EN), tOFF (EN)
VSS
VDD
0.1µF
3V
ADDRESS
DRIVE (VIN)
0.1µF
tr < 20ns
tf < 20ns
50%
VSS
VDD
50%
A0
S1
0V
VS1
A1
VIN
S2 TO S7
A2
tTRANSITION
tTRANSITION
VS8
S8
90%
ADG5208F*
2.0V
OUTPUT
OUTPUT
D
EN
GND
1kΩ
35pF
13035-047
90%
*SIMILAR CONNECTION FOR ADG5209F.
Figure 47.Address to Output Switching Time, tTRANSITION
VDD
VSS
0.1µF
0.1µF
VDD
3V
VSS
A0
A1
VIN
A2
ADG5208F*
QINJ = CL × ΔVOUT
ΔVOUT
S1
D
EN
GND
VS
VOUT
CL
1nF
VIN
*SIMILAR CONNECTION FOR ADG5209F.
Figure 48. Charge Injection, QINJ
Rev. A | Page 22 of 27
13035-048
VOUT
RS
Data Sheet
ADG5208F/ADG5209F
TERMINOLOGY
IDD
IDD represents the positive supply current.
tTRANSITION
tTRANSITION represents the delay time between the 50% and 90%
points of the digital inputs and the switch on condition when
switching from one address state to another.
ISS
ISS represents the negative supply current.
VD, VS
VD and VS represent the analog voltage on the D or Dx pins and
the Sx pins, respectively.
RON
RON represents the ohmic resistance between the D or Dx pins
and the Sx pins.
tD
tD represents the off time measured between the 90% points of
both switches when switching from one address state to
another.
∆RON
∆RON represents the difference between the RON of any two channels.
tRESPONSE
tRESPONSE represents the delay between the source voltage
exceeding the supply voltage by 0.5 V and the drain voltage
falling to 50% of its peak voltage.
RFLAT(ON)
RFLAT(ON) is the flatness that is defined as the difference between
the maximum and minimum value of on resistance measured
over the specified analog signal range.
tRECOVERY
tRECOVERY represents the delay between an overvoltage on the Sx pin
falling below the supply voltage plus 0.5 V and the drain voltage
rising from 0 V to 50% of its peak voltage.
IS (Off)
IS (off) is the source leakage current with the switch off.
Off Isolation
Off isolation is a measure of unwanted signal coupling through
an off switch.
ID (Off)
ID (off) is the drain leakage current with the switch off.
ID (On), IS (On)
ID (on) and IS (on) represent the channel leakage currents with
the switch on.
VINL
VINL is the maximum input voltage for Logic 0.
VINH
VINH is the minimum input voltage for Logic 1.
CD (Off)
CD (off) represents the off switch drain capacitance, which is
measured with reference to ground.
CS (Off)
CS (off) represents the off switch source capacitance, which is
measured with reference to ground.
CD (On), CS (On)
CD (on) and CS (on) represent the on switch capacitances, which
are measured with reference to ground.
tON (EN)
tON (EN) represents the delay between applying the digital
control input and the output switching on (see Figure 46).
tOFF (EN)
tOFF (EN) represents the delay between applying the digital
control input and the output switching off (see Figure 46).
Channel-to-Channel Crosstalk
Crosstalk is a measure of unwanted signal that is coupled
through from one channel to another as a result of parasitic
capacitance.
Insertion Loss
Insertion loss is the loss due to the on resistance of the switch.
IINL, IINH
IINL and IINH represent the low and high input currents of the
digital inputs.
CIN
CIN is the digital input capacitance.
Charge Injection
Charge injection is a measure of the glitch impulse transferred
from the digital input to the analog output during switching.
−3 dB Bandwidth
Bandwidth is the frequency at which the output is attenuated
by 3 dB.
AC Power Supply Rejection Ratio (ACPSRR)
ACPSRR is the ratio of the amplitude of signal on the output to
the amplitude of the modulation. ACPSRR is a measure of the
ability of the device to avoid coupling noise and spurious signals
that appear on the supply voltage pin to the output of the switch.
The dc voltage on the device is modulated by a sine wave of
0.62 V p-p.
On Response
On response is the frequency response of the on switch.
VT
VT is the voltage threshold at which the overvoltage protection
circuitry engages (see Figure 30).
Total Harmonic Distortion Plus Noise (THD + N)
THD + N is the ratio of the harmonic amplitude plus noise of
the signal to the fundamental.
Rev. A | Page 23 of 27
ADG5208F/ADG5209F
Data Sheet
THEORY OF OPERATION
SWITCH ARCHITECTURE
Each channel of the ADG5208F/ADG5209F consists of a
parallel pair of NDMOS and PDMOS transistors. This construction
provides excellent performance across the signal range. The
ADG5208F/ADG5209F channels operate as standard switches
when input signals with a voltage between VSS and VDD are applied.
For example, the on resistance is 250 Ω typically and opening or
closing the switch is controlled using the appropriate address pins.
Additional internal circuitry enables the switch to detect
overvoltage inputs by comparing the voltage on a source pin
with VDD and VSS. A signal is considered overvoltage if it
exceeds the supply voltages by the voltage threshold, VT. The
threshold voltage is typically 0.7 V, but can range from 0.8 V at
−40°C down to 0.6 V at +125°C. See Figure 30 to see the change
in VT with operating temperature.
The voltage range that can be applied to any source input is +55 V
to −55 V. When the device is powered using a single supply of
25 V or greater, the minimum signal level increases from −55 V
to −40 V at VDD = +40 V to remain within the 80 V maximum
rating. Construction of the process allows the channel to
withstand 80 V across the switch when it is opened. These
overvoltage limits apply whether the power supplies are present
or not.
VDD
ESD
PROTECTION
ESD
Sx
D/Dx
During overvoltage conditions, the leakage current into and out
of the source pins is limited to tens of microamperes. If the source
pin is unselected, only nanoamperes of leakage appear on the
drain pin. However, if the source is selected, the pin is pulled to
the supply rail. The device that pulls the drain pin to the rail has
an impedance of approximately 40 kΩ; thus, the D or Dx pin
current is limited to approximately 1 mA during a shorted load
condition. This internal impedance also determines the minimum
external load resistance required to ensure that the drain pin is
pulled to the desired voltage level during a fault. When an
overvoltage event occurs, the channels undisturbed by the
overvoltage input continue to operate normally without
additional crosstalk.
ESD Performance
The drain pins have ESD protection diodes to the rails and the
voltage at these pins must not exceed the supply voltage. The
source pins have specialized ESD protection that allows the signal
voltage to reach ±55 V regardless of supply voltage level. See
Figure 49 for an overview of the switch channel function.
Trench Isolation
In the ADG5208F and ADG5209F, an insulating oxide layer
(trench) is placed between the NDMOS and the PDMOS
transistors of each switch. Parasitic junctions, which occur
between the transistors in junction isolated switches, are
eliminated, and the result is a switch that is latch-up immune
under all circumstances.
NDMOS
PDMOS
P-WELL
N-WELL
ESD
Ax
SWITCH
DRIVER
LOGIC
BLOCK
VSS
13035-049
FAULT
DETECTOR
Figure 49. Switch Channel and Control Function
Overvoltage Reaction
Rev. A | Page 24 of 27
TRENCH
BURIED OXIDE LAYER
HANDLE WAFER
Figure 50. Trench Isolation
13035-050
When an overvoltage condition is detected on a source pin, the
switch automatically opens regardless of the digital logic state.
The source pin becomes high impedance and, if that source pin
is selected, the drain pin is pulled to the supply that was exceeded.
For example, if the source voltage exceeds VDD, then the drain
output pulls to VDD, similarly for VSS. In Figure 31, the voltage
on the drain pin can be seen to follow the voltage on the source
pin until the switch turns off completely. The drain pin then
pulls to GND due to the 1 kΩ load resistor; otherwise, it pulls to
the VDD supply. The maximum voltage on the drain is limited by
the internal ESD diodes and the rate at which the output voltage
discharges is dependent on the load at the pin.
Data Sheet
ADG5208F/ADG5209F
FAULT PROTECTION
When the voltages at the source inputs exceed VDD or VSS by VT,
the switch turns off or, if the device is unpowered, the switch
remains off. The switch input remains high impedance regardless
of the digital input state and if it is selected, the drain pulls to
either VDD or VSS. Signal levels up to +55 V and −55 V are
blocked in both the powered and unpowered condition as long as
the 80 V limitation between the source and supply pins is met.
These calculations are all within device specifications: a 55 V
maximum fault on the source inputs and a maximum of 80 V
across the off switch channel.
+22V
‒55V
+55V
–22V
VDD
GND
VSS
S1
S2
S3
D
The following three conditions must be satisfied for the switch
to be in the on condition:
S8
1-OF-8
DECODER
A0
0V
+5V
The switch responds to an analog input that exceeds VDD or VSS
by a threshold voltage, VT, by turning off. The absolute input
voltage limits are −55 V and +55 V, while maintaining an 80 V
limit between the source pin and the supply rails. The switch
remains off until the voltage at the source pin returns to
between VDD and VSS.
The fault response time (tRESPONSE) when powered by a ±15 V
dual supply is typically 90 ns and the fault recovery time (tRECOVERY)
is 745 ns. These vary with supply voltages and output load
conditions.
Exceeding ±55 V on any source input may damage the ESD
protection circuitry on the device.
The maximum stress across the switch channel is 80 V, therefore,
the user must pay close attention to this limit under a fault
condition.
For example, consider the case where the device is set up as
shown in Figure 51.
VDD/VSS = ±22 V, S1 = +22 V, S1 is selected
S2 has a −55 V fault and S3 has a +55 V fault
The voltage between S2 and D = +22 V − (−55 V) = +77 V
The voltage between S3 and D = 55 V− 22 V = 33 V
A1
A2
EN
13035-051
VDD to VSS ≥ 8 V
The input signal is between VSS − VT and VDD + VT
The digital logic control input is active
When the switch is turned on, signal levels up to the supply rails
are passed.
•
•
•
•
0V
ADG5208F
Power-On Protection
•
•
•
+22V
Figure 51. ADG5208F in an Overvoltage Condition
Power-Off Protection
When no power supplies are present, the switch remains in the
off condition, and the switch inputs are high impedance. This
state ensures that no current flows and prevents damage to the
switch or downstream circuitry. The switch output is a virtual
open circuit.
The switch remains off regardless of whether the VDD and VSS
supplies are 0 V or floating. A GND reference must always be
present to ensure proper operation. Signal levels of up to ±55 V
are blocked in the unpowered condition.
Digital Input Protection
The ADG5208F and the ADG5209F can tolerate digital input
signals being present on the device without power. When the
device is unpowered, the switch is guaranteed to be in the off
state, regardless of the state of the digital logic signals.
The digital inputs are protected against positive faults of up to
44 V. The digital inputs do not offer protection against negative
overvoltages. ESD protection diodes connected to GND are
present on the digital inputs.
Rev. A | Page 25 of 27
ADG5208F/ADG5209F
Data Sheet
APPLICATIONS INFORMATION
POWER SUPPLY RAILS
To guarantee correct operation of the device, 0.1 µF decoupling
capacitors are required.
The ADG5208F and the ADG5209F can operate with bipolar
supplies between ±5 V and ±22 V. The supplies on VDD and VSS
need not be symmetrical, but the VDD to VSS range must not
exceed 44 V. The ADG5208F and the ADG5209F can also
operate with single supplies between 8 V and 44 V with VSS
connected to GND.
These devices are fully specified at ±15 V, ±20 V, +12 V, and
+36 V supply ranges.
POWER SUPPLY RECOMMENDATIONS
Analog Devices, Inc., has a wide range of power management
products to meet the requirements of most high performance
signal chains.
An example of a bipolar power solution is shown in Figure 52.
The ADP7118 and ADP7182 can be used to generate clean
positive and negative rails from the ADP5070 (dual switching
regulator) output. These rails can be used to power the ADG5208F/
ADG5209F amplifier, and/or a precision converter in a typical
signal chain.
+16V
ADP7118
LDO
12V
INPUT
+15V
ADP5070
–16V
ADP7182
LDO
–15V
13035-052
The overvoltage protected family of switches and multiplexers
provides robust solutions for instrumentation, industrial,
automotive, aerospace, and other harsh environments where
overvoltage signals can be present and the system must remain
operational both during and after the overvoltage has occurred.
Figure 52. Bipolar Power Solution
Table 11. Recommended Power Management Devices
POWER SUPPLY SEQUENCING PROTECTION
The switch channel remains open when the devices are
unpowered and signals from −55 V to +55 V can be applied
without damaging the devices. The switch channel closes only
when the supplies are connected, a suitable digital control signal
is placed on the address pins, and the signal is within normal
operating range. Placing the ADG5208F/ADG5209F between
external connectors and sensitive components offers protection
in systems where a signal is presented to the source pins before
the supply voltages are available.
SIGNAL RANGE
The ADG5208F/ADG5209F switches have overvoltage detection
circuitry on their inputs that compares the voltage levels at the
source terminals with VDD and VSS. To protect downstream
circuitry from overvoltages, supply the ADG5208F/ADG5209F
with voltages that match the intended signal range. The additional
protection architecture allows the signals up to the supply rails
to be passed and only a signal that exceeds the supply rail by the
threshold voltage is then blocked. This signal block offers
protection to both the device and any downstream circuitry.
Product
ADP5070
ADP7118
ADP7142
ADP7182
Description
1 A/0.6 A, dc-to-dc switching regulator with
independent positive and negative outputs
20 V, 200 mA, low noise, CMOS LDO
40 V, 200 mA, low noise, CMOS LDO
−28 V, −200 mA, low noise, linear regulator
HIGH VOLTAGE SURGE SUPPRESSION
The ADG5208F/ADG5209F are not intended for use in very
high voltage applications. The maximum operating voltage of
the transistor is 80 V. In applications where the inputs are likely
to be subject to overvoltages exceeding the breakdown voltage,
use transient voltage suppressors (TVSs) or similar devices.
LARGE VOLTAGE, HIGH FREQUENCY SIGNALS
Figure 33 illustrates the voltage range and frequencies that the
ADG5208F/ADG5209F can reliably convey. For signals that
extend across the full signal range from VSS to VDD, keep the
frequency below 1 MHz. If the required frequency is greater
than 1 MHz, decrease the signal range appropriately to ensure
signal integrity.
Rev. A | Page 26 of 27
Data Sheet
ADG5208F/ADG5209F
OUTLINE DIMENSIONS
5.10
5.00
4.90
16
9
4.50
4.40
4.30
6.40
BSC
1
8
PIN 1
1.20
MAX
0.15
0.05
0.20
0.09
0.30
0.19
0.65
BSC
COPLANARITY
0.10
0.75
0.60
0.45
8°
0°
SEATING
PLANE
COMPLIANT TO JEDEC STANDARDS MO-153-AB
Figure 53. 16-Lead Thin Shrink Small Outline Package [TSSOP]
(RU-16)
Dimensions shown in millimeters
PIN 1
INDICATOR
4.10
4.00 SQ
3.90
0.35
0.30
0.25
0.65
BSC
16
13
PIN 1
INDICATOR
12
1
EXPOSED
PAD
4
2.70
2.60 SQ
2.50
9
0.80
0.75
0.70
0.45
0.40
0.35
8
0.05 MAX
0.02 NOM
COPLANARITY
0.08
0.20 REF
SEATING
PLANE
5
0.20 MIN
BOTTOM VIEW
FOR PROPER CONNECTION OF
THE EXPOSED PAD, REFER TO
THE PIN CONFIGURATION AND
FUNCTION DESCRIPTIONS
SECTION OF THIS DATA SHEET.
COMPLIANT TO JEDEC STANDARDS MO-220-WGGC.
08-16-2010-C
TOP VIEW
Figure 54. 16-Lead Lead Frame Chip Scale Package [LFCSP]
4 mm × 4 mm Body and 0.75 mm Package Height
(CP-16-17)
Dimensions shown in millimeters
ORDERING GUIDE
Model 1
ADG5208FBCPZ-RL7
ADG5208FBRUZ
ADG5208FBRUZ-RL7
ADG5209FBCPZ-RL7
ADG5209FBRUZ
ADG5209FBRUZ-RL7
1
Temperature Range
−40°C to +125°C
−40°C to +125°C
−40°C to +125°C
−40°C to +125°C
−40°C to +125°C
−40°C to +125°C
Package Description
16-Lead Lead Frame Chip Scale Package [LFCSP]
16-Lead Thin Shrink Small Outline Package [TSSOP]
16-Lead Thin Shrink Small Outline Package [TSSOP]
16-Lead Lead Frame Chip Scale Package [LFCSP]
16-Lead Thin Shrink Small Outline Package [TSSOP]
16-Lead Thin Shrink Small Outline Package [TSSOP]
Z = RoHS Compliant Part.
©2015–2016 Analog Devices, Inc. All rights reserved. Trademarks and
registered trademarks are the property of their respective owners.
D13035-0-3/16(A)
Rev. A | Page 27 of 27
Package Option
CP-16-17
RU-16
RU-16
CP-16-17
RU-16
RU-16
工商网监
湘ICP备2023018690号
