CMOS Latched 8-/16-Channel Analog Multiplexers ADG526A/ADG527A
FEATURES
44 V supply maximum rating VSS to VDD analog signal range Single- or dual-supply specifications Wide supply ranges (10.8 V to 16.5 V) Microprocessor compatible (100 ns WR pulse) Extended plastic temperature range (−40°C to +85°C) Low leakage (20 pA typical) Low power dissipation (28 mW maximum) Available in PDIP, CERDIP, SOIC, and PLCC packages Superior alternative to DG526 and DG527
FUNCTIONAL BLOCK DIAGRAMS
ADG526A
S1
D S16 DECODER/ LATCHES
01532-001
WR
A0 A1 A2 A3 EN RS
Figure 1. ADG526A
APPLICATIONS
Data acquisition systems Communication systems Automatic test equipment Microprocessor controlled systems
ADG527A
S1A DA S8A S1B DB S8B WR DECODER/ LATCHES
01532-002
GENERAL DESCRIPTION
The ADG526A and ADG527A are CMOS monolithic analog multiplexers with 16 single channels and dual 8 channels, respectively. On-chip latches facilitate microprocessor interfacing. The ADG526A switches one of 16 inputs to a common output, depending on the state of four binary addresses and an enable input. The ADG527A switches one of eight differential inputs to a common differential output, depending on the state of three binary addresses and an enable input. Both devices have TTL and 5 V CMOS logic-compatible digital inputs. The ADG526A and ADG527A are designed on an enhanced LC2MOS process that gives an increased signal capability of VSS to VDD and enables operation over a wide range of supply voltages. The devices can comfortably operate anywhere in the 10.8 V to 16.5 V single- or dual-supply range. These multiplexers also feature high switching speeds and low RON.
A0 A1 A2 EN RS
Figure 2. ADG527A
PRODUCT HIGHLIGHTS
1. Single- or Dual-Supply Specifications with a Wide Tolerance. The devices are specified in the 10.8 V to 16.5 V range for both single and dual supplies. Easily Interfaced. The ADG526A and ADG527A can be easily interfaced with microprocessors. The WR signal latches the state of the address control lines and the enable line. The RS signal clears both the address and enable data in the latches, resulting in no output (all switches off). RS can be tied to the microprocessor reset pin. Extended Signal Range. The enhanced LC2MOS processing results in a high breakdown and an increased analog signal range from VSS to VDD. Break-Before-Make Switching. Switches are guaranteed break-before-make so that input signals are protected against momentary shorting. Low Leakage. Leakage currents in the range of 20 pA make these multiplexers suitable for high precision circuits.
2.
3.
4.
5.
Rev. C
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ADG526A/ADG527A TABLE OF CONTENTS
Features .............................................................................................. 1 Applications ....................................................................................... 1 General Description ......................................................................... 1 Functional Block Diagrams ............................................................. 1 Product Highlights ........................................................................... 1 Revision History ............................................................................... 2 Specifications..................................................................................... 3 Dual Supply ................................................................................... 3 Single Supply ................................................................................. 5 Absolute Maximum Ratings............................................................ 7 ESD Caution...................................................................................7 Pin Configurations and Function Descriptions ............................8 Typical Performance Characteristics ........................................... 11 Terminology .................................................................................... 12 Timing .............................................................................................. 13 Test Circuits ..................................................................................... 14 Outline Dimensions ....................................................................... 17 Ordering Guide .......................................................................... 19
REVISION HISTORY
6/08—Rev. B to Rev. C. Updated Format .................................................................. Universal ADG526A LCCC Package Removed ............................... Universal Changes to Features.......................................................................... 1 Added Applications Section ............................................................ 1 Changes to Absolute Maximum Ratings ....................................... 7 Added Table 4, Renumbered Sequentially .................................... 8 Added Table 5.................................................................................... 9 Changes to Figure 7 and Figure 8 ................................................. 11 Updated Outline Dimensions ....................................................... 17 Changes to Ordering Guide .......................................................... 19 2/02—Rev. A to Rev. B. Edits to Specifications Table, Dual Supply .....................................2 Edits to Specifications Table, Single Supply ...................................3 Edits to Ordering Guide ...................................................................4 Removal of one Pin Configuration and Diagram .........................6
Rev. C | Page 2 of 20
ADG526A/ADG527A SPECIFICATIONS
DUAL SUPPLY
VDD = 10.8 V to 16.5 V, VSS = −10.8 V to −16.5 V, unless otherwise noted. Table 1.
ADG526A/ADG527A K Version B Version 25°C −40°C to +85°C 25°C −40°C to +85°C VSS VDD 280 450 300 VSS VDD VSS VDD 280 450 300 VSS VDD ADG526A T Version 25°C −55°C to +125°C Unit VSS VDD 280 450 VSS VDD V min V max Ω typ Ω max Ω max Ω max %/°C typ % typ nA typ 50 nA max nA typ nA max nA max nA typ nA max nA max nA max
Parameter ANALOG SWITCH Analog Signal Range RON
Comments
−10 V ≤ VS ≤ +10 V, IDS = 1 mA; see Figure 15 VDD = +15 V (±10%), VSS = −15 V (±10%) VDD = +15 V (±5%), VSS = −15 V (±5%) −10 V ≤ VS ≤ +10 V, IDS = 1 mA −10 V ≤ VS ≤ +10 V, IDS = 1 mA V1 = ±10 V, V2 = 10 V; see Figure 16 V1 = ±10 V, V2 = 10 V; see Figure 17
600 400
600 400
600
300 RON Drift RON Match IS (Off), Off Input Leakage 0.6 5 0.02 1 0.04 1 1 0.04 1 1 50 0.6 5 0.02 1 0.04 1 1 0.04 1 1 50 0.6 5 0.02 1 0.04 1 0.04 200 100 25 1
400
ID (Off), Off Output Leakage ADG526A ADG527A ID (On), On Channel Leakage ADG526A ADG527A IDIFF, Differential Off Output Leakage (ADG527A Only) DIGITAL CONTROL VINH, Input High Voltage VINL, Input Low Voltage IINL or IINH CIN, Digital Input Capacitance DYNAMIC CHARACTERISTICS 1 tTRANSITION
200 100
200 100
200
V1 = ±10 V, V2 = 10 V; see Figure 18
200 100 25
200
V1 = ±10 V, V2 = 10 V; see Figure 19
2.4 0.8 1 8 8
2.4 0.8 1 8
2.4 0.8 1
V min V max μA max pF max
VIN = 0 to VDD
200 300 50 25 200 300 200 300 100 400 10 400 400 120 100 10 100
200 300 50 25 200 300 200 300 100 400 10 400 400 120 100 10 100
200 300 50 25 200 300 200 300 100 400 10 400 400 130 100 10 100
ns typ ns max ns typ ns min ns typ ns max ns typ ns max ns min ns min ns min ns min
V1 = ±10 V, V2 = 10 V; see Figure 20 See Figure 21 See Figure 22 and Figure 23 See Figure 22 and Figure 24 See Figure 13 See Figure 13 See Figure 13 See Figure 14
tOPEN tON (EN, WR) tOFF (EN, RS) tW , Write Pulse Width tS, Address Enable Setup Time tH, Address Enable Hold Time tRS, Reset Pulse Width
Rev. C | Page 3 of 20
ADG526A/ADG527A
ADG526A/ADG527A K Version B Version 25°C −40°C to +85°C 25°C −40°C to +85°C 68 68 ADG526A T Version 25°C −55°C to +125°C Unit 68 dB typ
Parameter Off Isolation
Comments VEN = 0.8 V, RL = 1 kΩ, CL = 15 pF,VS = 7 V rms, f = 100 kHz VS = 7 V rms, f = 100 kHz VEN = 0.8 V VEN = 0.8 V RS = 0 Ω, VS = 0 V; see Figure 25 VIN = VINL or VINH VIN = VINL or VINH
CS (Off) CD (Off) ADG526A ADG527A QINJ, Charge Injection POWER SUPPLY IDD ISS Power Dissipation
50 5 44 22 4
50 5 44 22 4
50 5 44 4
dB min pF typ pF typ pF typ pC typ
0.6 1.5 20 0.2 10 28
0.6 1.5 20 0.2 10 28
0.6 1.5 20 0.2 10 28
mA typ mA max μA typ mA max mW typ mW max
1
Sample tested at 25°C to ensure compliance.
Rev. C | Page 4 of 20
ADG526A/ADG527A
SINGLE SUPPLY
VDD = 10.8 V to 16.5 V, VSS = GND to 0 V, unless otherwise noted. Table 2.
ADG526A/ADG527A K Version B Version 25°C −40°C to +85°C 25°C −40°C to +85°C VSS VDD 500 700 0.6 5 0.02 1 0.04 1 1 0.04 1 1 50 VSS VDD VSS VDD 500 700 0.6 5 0.02 1 0.04 1 1 0.04 1 1 50 VSS VDD ADG526A T Version −55°C to +125°C VSS VDD
Parameter ANALOG SWITCH Analog Signal Range RON
25°C VSS VDD 500 700 0.6 5 0.02 1 0.04 1 0.04
Unit V min V max Ω typ Ω max %/°C typ % typ nA typ
Comments
0 V ≤ VS ≤ 10 V, IDS = 0.5 mA; see Figure 15 0 V ≤ VS ≤ 10 V, IDS = 0.5 mA 0 V ≤ VS ≤ 10 V, IDS = 0.5 mA V1 = 10 V/0 V, V2 = 0 V/ 10 V; see Figure 16 V1 = 10 V/0 V, V2 = 0 V/ 10 V; see Figure 17
1000
1000
1000
RON Drift RON Match IS (Off), Off Input Leakage ID (Off), Off Output Leakage ADG526A ADG527A ID (On), On Channel Leakage ADG526A ADG527A IDIFF, Differential Off Output Leakage (ADG527A Only) DIGITAL CONTROL VINH, Input High Voltage VINL, Input Low Voltage IINL or IINH CIN, Digital Input Capacitance DYNAMIC CHARACTERISTICS 1 tTRANSITION
50
nA max nA typ nA max nA max nA typ nA max nA max nA max
200 100
200 100
200
V1 = 10 V/0 V, V2 = 0 V/ 10 V; see Figure 18
200 100 25
200 100 25
1
200
V1 = 10 V/0 V, V2 = 0 V/ 10 V; see Figure 19
2.4 0.8 1 8 8
2.4 0.8 1 8
2.4 0.8 1
V min V max μA max pF max
VIN = 0 to VDD
300 450 50 25 250 450 250 450 100 600 10 600 600 120 100 10 100 68 50
300 450 50 25 250 450 250 450 100 600 10 600 600 120 100 10 100 68 50
300 450 50 25 250 450 250 450 100 600 10 600 600 130 100 10 100 68 50
ns typ ns max ns typ ns min ns typ ns max ns typ ns max ns min ns min ns min ns min dB typ dB min
V1 = 10 V/0 V, V2 = 0 V/ 10 V; see Figure 20 See Figure 21 See Figure 22 and Figure 23 See Figure 22 and Figure 24 See Figure 13 See Figure 13 See Figure 13 See Figure 14 VEN = 0.8 V, RL = 1 kΩ, CL = 15 pF VS = 3.5 V rms, f = 100 kHz
tOPEN tON (EN, WR) tOFF (EN, RS) tW Write Pulse Width tS Address Enable Setup Time tH Address Enable Hold Time tRS Reset Pulse Width Off Isolation
Rev. C | Page 5 of 20
ADG526A/ADG527A
ADG526A/ADG527A K Version B Version 25°C −40°C to +85°C 25°C −40°C to +85°C 5 5 44 22 4 44 22 4 ADG526A T Version −55°C to +125°C
Parameter CS (Off) CD (Off) ADG526A ADG527A QINJ, Charge Injection POWER SUPPLY IDD Power Dissipation
25°C 5 44 4
Unit pF typ pF typ pF typ pC typ
Comments VEN = 0.8 V VEN = 0.8 V RS = 0 Ω, VS = 0 V; see Figure 25 VIN = VINL or VINH
0.6 1.5 11 25
0.6 1.5 11 25
0.6 1.5 11 25
mA typ mA max mW typ mW max
1
Sample tested at 25°C to ensure compliance.
Rev. C | Page 6 of 20
ADG526A/ADG527A ABSOLUTE MAXIMUM RATINGS
TA = 25°C, unless otherwise noted. Table 3.
Parameter VDD to VSS VDD to GND VSS to GND Analog Inputs1 Voltage at Sx or Dx Pins Rating 44 V 25 V −25 V VSS − 2 V to VDD + 2 V or 20 mA, whichever occurs first 20 mA 40 mA VSS − 4 V to VDD + 4 V or 20 mA, whichever occurs first 470 mW 6 mW/°C −40°C to +85°C −40°C to +85°C −65°C to +150°C 300°C
Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.
ESD CAUTION
Continuous Current, Sx or Dx Pins Pulsed Current, Sx or Dx Pins 1 ms Duration, 10% Duty Cycle Digital Inputs1 Voltage at A, EN, WR, RS
Power Dissipation (Any Package) Up to 75°C Derates Above 75°C Operating Temperature Range Commercial (K Version) Industrial (B Version) Storage Temperature Range Lead Temperature (Soldering, 10 sec)
1
Overvoltage at A, EN, WR, RS, Sx, or Dx pins are clamped by diodes. Limit current to the maximum rating in Table 3.
Rev. C | Page 7 of 20
ADG526A/ADG527A PIN CONFIGURATIONS AND FUNCTION DESCRIPTIONS
VDD S16 VSS
27
NC
RS
VDD 1 NC 2 RS 3 S16 4 S15 5
28 D 27 VSS 26 S8
4
3
2
1
28
26 25 24
S15 5 S14 6 S13 7 S12 8 S11 9 S10 10 S09 11
12
24 S6 TOP VIEW S14 6 (Not to Scale) 23 S5 S13 7 22 S4
ADG526A
25 S7
PIN 1 IDENTFIER
S8
D
S7 S6 S5 S4 S3 S2 S1
ADG526A
TOP VIEW (Not to Scale)
23 22 21 20 19
S12 8 S11 9 S10 10 S9 11 GND 12 WR 13 A3 14
21 S3 20 S2 19 S1 18 EN 17 A0 16 A1
01532-005
13
14
15
16
17
18
GND
WR
EN
A3
A2
A1
A0
NC = NO CONNECT
15 A2
NC = NO CONNECT
Figure 3. ADG526A PDIP, SOIC, and CERDIP Pin Configuration
Figure 4. ADG526A PLCC Pin Configuration
Table 4. ADG526A Pin Function Descriptions
Pin No. 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 Mnemonic VDD NC RS S16 S15 S14 S13 S12 S11 S10 S9 GND WR A3 A2 A1 A0 EN S1 S2 S3 S4 S5 S6 S7 S8 VSS D Description Most Positive Power Supply Potential. No Connect. Reset. The RS signal clears both the address and enable data in the latches resulting in no output (all switches off ). Source Terminal. This pin can be an input or output. Source Terminal. This pin can be an input or output. Source Terminal. This pin can be an input or output. Source Terminal. This pin can be an input or output. Source Terminal. This pin can be an input or output. Source Terminal. This pin can be an input or output. Source Terminal. This pin can be an input or output. Source Terminal. This pin can be an input or output. Ground (0 V) Reference. Write. The WR signal latches the state of the address control lines and the enable line. Logic Control Inputs. Selects which source terminal is connected to the drain (D). Logic Control Inputs. Selects which source terminal is connected to the drain (D). Logic Control Inputs. Selects which source terminal is connected to the drain (D). Logic control inputs. Selects which source terminal is connected to the drain (D). Enable. Active high logic control input. Source Terminal. This pin can be an input or output. Source Terminal. This pin can be an input or output. Source Terminal. This pin can be an input or output. Source Terminal. This pin can be an input or output. Source Terminal. This pin can be an input or output. Source Terminal. This pin can be an input or output. Source Terminal. This pin can be an input or output. Source Terminal. This pin can be an input or output. Most Negative Power Supply Potential. Drain Terminal. This pin can be an input or output.
Rev. C | Page 8 of 20
01532-007
ADG526A/ADG527A
S8B
VDD 1 DB 2 RS 3 S8B 4 S7B 5 S6B 6 S5B 7 S4B 8 S3B 9 S2B 10 S1B 11 GND 12 WR 13 NC 14
28 DA 27 VSS 26 S8A 25 S7A
4 3 2 1 28 27 26 25 24
S7B 5 S6B 6 S5B 7 S4B 8 S3B 9 S2B 10 S1B 11
12
PIN 1 IDENTFIER
S8A
VDD
VSS
DB
DA
RS
S7A S6A S5A S4A S3A S2A S1A
ADG527A
TOP VIEW (Not to Scale)
24 S6A 23 S5A 22 S4A 21 S3A 20 S2A 19 S1A 18 EN 17 A0 16 A1 15 A2
01532-006
ADG527A
TOP VIEW (Not to Scale)
23 22 21 20 19
13
14
15
16
17
18
GND
WR
NC
EN
A2
A1
A0
NC = NO CONNECT
NC = NO CONNECT
Figure 5. ADG527A PDIP, SOIC Pin Configuration
Figure 6. ADG527A PLCC Pin Configuration
Table 5. ADG527A Pin Function Descriptions
Pin No. 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 Mnemonic VDD DB RS S8B S7B S6B S5B S4B S3B S2B S1B GND WR NC A2 A1 A0 EN S1A S2A S3A S4A S5A S6A S7A S8A VSS DA Description Most Positive Power Supply Potential. Drain Terminal. This pin can be an input or output. Reset. The RS signal clears both the address and enable data in the latches resulting in no output (all switches off). Source Terminal. This pin can be an input or output. Source Terminal. This pin can be an input or output. Source Terminal. This pin can be an input or output. Source Terminal. This pin can be an input or output. Source Terminal. This pin can be an input or output. Source Terminal. This pin can be an input or output. Source Terminal. This pin can be an input or output. Source Terminal. This pin can be an input or output. Ground (0 V) Reference. Write. The WR signal latches the state of the address control lines and the enable line. No Connect. Logic Control Inputs. Selects which source terminal is connected to the drain (D). Logic Control Inputs. Selects which source terminal is connected to the drain (D). Logic Control Inputs. Selects which source terminal is connected to the drain (D). Enable. Active high logic control input. Source Terminal. This pin can be an input or output. Source Terminal. This pin can be an input or output. Source Terminal. This pin can be an input or output. Source Terminal. This pin can be an input or output. Source Terminal. This pin can be an input or output. Source Terminal. This pin can be an input or output. Source Terminal. This pin can be an input or output. Source Terminal. This pin can be an input or output. Most Negative Power Supply Potential. Drain Terminal. This pin can be an input or output.
Rev. C | Page 9 of 20
01532-008
ADG526A/ADG527A
Table 6. ADG526A Truth Table1
A3 X X X 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1
1
A2 X X X 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1
A1 X X X 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1
A0 X X X 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1
EN X X 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1
WR X 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
RS 1 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1
ON SWITCH Retains previous switch condition None (address and enable latches cleared) None 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16
X = don’t care.
Table 7. ADG527A Truth Table1
A2 X X X 0 0 0 0 1 1 1 1
1
A1 X X X 0 0 1 1 0 0 1 1
A0 X X X 0 1 0 1 0 1 0 1
EN X X 0 1 1 1 1 1 1 1 1
WR X 0 0 0 0 0 0 0 0 0
RS 1 0 1 1 1 1 1 1 1 1 1
ON SWITCH PAIR Retains previous switch condition None (address and enable latches cleared) None 1 2 3 4 5 6 7 8
X = don’t care.
Rev. C | Page 10 of 20
ADG526A/ADG527A TYPICAL PERFORMANCE CHARACTERISTICS
The multiplexers are guaranteed functional with reduced single or dual supplies down to 4.5 V.
700 600 500 400 300 200 100 0 –20
1.5
01532-009
1.9
VDD = 10.8V VSS = 0V
TRIGGER LEVEL (V)
1.8
RON (Ω)
VDD = 15V VSS = 0V
1.7
1.6
–15
–10
–5
0 VD (VS) (V)
5
10
15
20
5
6
7
8
9
10
11
12
13
14
15
SUPPLY VOLTAGE (V)
Figure 7. RON as a Function of VD (VS): Single-Supply Voltage, TA = 25°C
Figure 10. Trigger Levels vs. Power Supply Voltage, Dual or Single Supply, TA = 25°C
800 700 600
700 600 500 400 300 200 100 0 –20 VDD = +15V VSS = –15V
VDD = +5V VSS = –5V
tTRANSITION (ns)
RON (Ω)
500 400 300 200 100 5 6 7
SINGLE SUPPLY
VDD = +10.8V VSS = –10.8V
DUAL SUPPLY
01532-010
–15
–10
–5
0 VD (VS) (V)
5
10
15
20
8
9
10
11
12
13
14
15
SUPPLY VOLTAGE (V)
Figure 8. RON as a Function of VD (VS): Dual-Supply Voltage, TA = 25°C
Figure 11. tTRANSITION vs. Supply Voltage: Dual and Single Supplies, TA = 25°C (Note: For VDD and VSS