CMOS Latched
4-/8-Channel Analog Multiplexers
ADG528A
FEATURES
44 V Supply Maximum Rating
VSS to VDD Analog Signal Range
Single-/Dual-Supply Specifications
Wide Supply Ranges (10.8 V to 16.5 V)
Microprocessor Compatible (100 ns WR Pulse)
Extended Plastic Temperature Range
(–40°C to +85°C)
Low Leakage (20 pA typ)
Low Power Dissipation (28 mW max)
Available in 18-Lead DIP/SOIC and 20-Lead PLCC Packages
Superior Alternative to:
DG528
DG529
FUNCTIONAL BLOCK DIAGRAMS
ADG529A is obsolete
GENERAL DESCRIPTION
PRODUCT HIGHLIGHTS
The ADG528A and ADG529A are CMOS monolithic analog
multiplexers with eight channels and four dual channels, respectively. On-chip latches facilitate microprocessor interfacing. The
ADG528A switches one of eight inputs to a common output,
depending on the state of three binary addresses and an enable
input. The ADG529A switches one of four differential inputs to
a common differential output, depending on the state of two
binary addresses and an enable input. Both devices have TTL
and 5 V CMOS logic-compatible digital inputs.
1. Single-/dual-supply specifications with a wide tolerance.
The devices are specified in the 10.8 V to 16.5 V range for
both single- and dual-supplies.
The ADG528A and ADG529A are designed on an enhanced
LC2MOS process, which gives an increased signal capability of
VSS to VDD and enables operation over a wide range of supply
voltages. The devices can comfortably operate anywhere in the
10.8 V to 16.5 V single- or dual-supply range. These
multiplex-ers also feature high switching and low RON.
The ADG529A is no longer available.
2. Easily Interfaced
The ADG528A and ADG529A can be easily interfaced with
microprocessors. The WR signal latches the state of the
address control lines and the enable line. The RS signal
clears both the address and enable data in the latches resulting in no output (all switches off). RS can be tied to the
microprocessor reset pin.
3. Extended Signal Range
The enhanced LC2MOS processing results in a high breakdown
and an increased analog signal range of VSS to VDD.
4. Break-Before-Make Switching
Switches are guaranteed break-before-make so that input
signals are protected against momentary shorting.
5. Low Leakage
Leakage currents in the range of 20 pA make these multiplexers
suitable for high precision circuits.
ADG528A–SPECIFICATIONS
DUAL SUPPLY
(VDD = +10.8 V to +16.5 V, VSS = –10.8 V to –16.5 V, unless otherwise noted.)
Parameter
ANALOG SWITCH
Analog Signal Range
RON
RON Drift
RON Match
IS (OFF), Off Input
Leakage
ID (OFF), Off Input
Leakage
ADG528A
ADG529A
ID (ON), On Channel
Leakage
ADG528A
ADG529A
IDIFF, Differential Off
Output Leakage
(ADG529A only)
ADG528A
ADG529A
K Version
–40°C to
+25°C +85°C
ADG528A
ADG528A
ADG529A
ADG529A
B Version
T Version
–40°C to
–55°C to
+25°C +85°C
+25°C +125°C
Units
VSS
VDD
280
VSS
VDD
VSS
VDD
280
VSS
VDD
VSS
VDD
280
VSS
VDD
V min
V max
Ω typ
450
300
600
400
450
300
600
400
450
600
300
0.6
5
400
Ω max
Ω max
Ω max
%/°C typ
% typ
0.6
5
0.6
5
Comments
–10 V ≤ VS ≤ +10 V, IDS = 1 mA;
Test Circuit 1
VDD = 15 V (± 10%), VSS = –15 V (±10%)
VDD = 15 V (± 5%), VSS = –15 V (± 5%)
–10 V ≤ VS ≤ +10 V, IDS = 1 mA
–10 V ≤ VS ≤ +10 V, IDS = 1 mA
0.02
1
0.02
1
50
0.02
1
50
nA typ
nA max
V1 = ± 10 V, V2 = ⫿10 V; Test Circuit 2
50
0.04
1
1
0.04
1
1
100
50
0.04
1
1
100
50
nA typ
nA max
nA max
V1 = ± 10 V, V2 = ⫿10 V; Test Circuit 3
100
50
0.04
1
1
0.04
1
1
100
50
0.04
1
1
100
50
nA typ
nA max
nA max
V1 = ± 10 V, V2 = ⫿10 V; Test Circuit 4
100
50
DIGITAL CONTROL
VINH, Input High Voltage
VINL, Input Low Voltage
IINL or IINH
CIN Digital Input
Capacitance
8
25
25
25
nA max
V1 = ± 10 V, V2 = ⫿10 V; Test Circuit 5
2.4
0.8
1
2.4
0.8
1
2.4
0.8
1
V min
V max
µA max
VIN = 0 to VDD
DYNAMIC CHARACTERISTICS 1
tTRANSITION
200
300
400
tOPEN
50
25
10
tON (EN, WR)
200
300
400
tOFF (EN, RS)
200
300
400
tW Write Pulse Width
100
120
tS Address,
Enable Setup Time
100
tH, Address,
Enable Hold Time
10
tRS Reset Pulse Width
100
OFF Isolation
68
50
5
CS (OFF)
CD (OFF)
ADG528A
22
ADG529A
11
QINJ, Charge Injection
4
8
200
300
50
25
200
300
200
300
100
8
V1 = ± 10 V, V2 = ⫿10 V; Test Circuit 6
400
130
ns typ
ns max
ns typ
ns min
ns typ
ns max
ns typ
ns max
ns min
See Figure 1
100
100
ns min
See Figure 1
10
100
10
100
See Figure 1
See Figure 2
VEN = 0.8 V, RL = 1 kΩ, CL = 15 pF,
VS = 7 V rms, f = 100 kHz
VEN = 0.8 V
VEN = 0.8 V
400
10
400
400
120
200
300
50
25
200
300
200
300
100
pF max
400
10
400
68
50
5
68
50
5
ns min
ns min
dB typ
dB min
pF typ
22
11
4
22
11
4
pF typ
pF typ
pC typ
–2–
Test Circuit 7
Test Circuits 8 and 9
Test Circuits 8 and 10
RS = 0 Ω, VS = 0 V; Test Circuit 11
REV. C
ADG528A
Parameter
ADG528A
ADG529A
K Version
–40°C to
+25°C +85°C
ADG528A
ADG528A
ADG529A
ADG529A
B Version
T Version
–40°C to
–55°C to
+25°C +85°C
+25°C +125°C
POWER SUPPLY
IDD
0.6
0.6
1.5
ISS
20
20
0.2
Power Dissipation
0.6
1.5
10
1.5
20
0.2
10
2.8
0.2
10
2.8
2.8
Units
Comments
mA typ VIN = VINL or VINH
mA max
µA typ
VIN = VINL or VINH
mA max
mW typ
mW max
NOTE
1
Sample tested at +25°C to ensure compliance.
Specifications subject to change without notice.
SINGLE SUPPLY
Parameter
ANALOG SWITCH
Analog Signal Range
(VDD = +10.8 V to +16.5 V, VSS = GND = 0 V, unless otherwise noted.)
ADG528A
ADG529A
K Version
–40°C to
+25°C +85°C
ADG528A
ADG528A
ADG529A
ADG529A
B Version
T Version
–40°C to
–55°C to
+25°C +85°C
+25°C +125°C
Units
GND GND
VDD
VDD
GND GND
VDD
VDD
GND GND
VDD
VDD
V min
V max
500
500
500
Ω typ
RON
RON Drift
RON Match
IS (OFF), Off Input
Leakage
ID (OFF), Off Input
Leakage
ADG528A
ADG529A
ID (ON), On Channel
Leakage
ADG528A
ADG529A
IDIFF, Differential Off
Output Leakage
(ADG529A only)
700
0.6
5
1000
tOFF (EN, RS)
tW Write Pulse Width
REV. C
700
0.6
5
Ω max
%/°C typ GND ≤ VS ≤ +10 V, IDS = 0.5 mA
% typ
GND ≤ VS ≤ +10 V, IDS = 0.5 mA
1000
50
0.02
1
50
0.02
1
50
nA typ
nA max
V1 = +10 V/GND, V2 = GND/+10 V;
Test Circuit 2
0.04
1
1
100
50
0.04
1
1
100
50
0.04
1
1
100
50
nA typ
nA max
nA max
V1 = +10 V/GND, V2 = GND/+10 V;
Test Circuit 3
0.04
1
1
100
50
0.04
1
1
100
50
0.04
1
1
100
50
nA typ
nA max
nA max
V1 = +10 V/GND, V2 = GND/+10 V;
Test Circuit 4
V1 = +10 V/GND, V2 = GND/+10 V;
Test Circuit 5
DYNAMIC CHARACTERISTICS
tTRANSITION
300
tON (EN, WR)
1000
GND ≤ VS ≤ +10 V, IDS = 0.5 mA;
Test Circuit 1
0.02
1
DIGITAL CONTROL
VINH, Input High Voltage
VINL, Input Low Voltage
IINL or IINH
CIN Digital Input
Capacitance
8
tOPEN
700
0.6
5
Comments
450
50
25
250
450
250
450
100
25
25
25
nA max
2.4
0.8
1
2.4
0.8
1
2.4
0.8
1
V min
V max
µA max
8
8
pF max
300
300
ns typ
VIN = 0 to VDD
1
600
10
600
600
120
450
50
25
250
450
250
450
100
600
10
600
600
120
450
50
25
250
450
250
450
100
–3–
600
10
600
600
130
ns max
ns typ
ns min
ns typ
ns max
ns typ
ns max
ns min
V1 = +10 V/GND, V2 = GND/+10 V;
Test Circuit 6
Test Circuit 7
Test Circuits 8 and 9
Test Circuits 8 and 10
See Figure 1
ADG528A
Parameter
ADG528A
ADG529A
K Version
–40°C to
+25°C +85°C
DYNAMIC CHARACTERISTICS
tS Address,
Enable Setup Time
tH Address,
Enable Hold Time
tRS Reset Pulse Width
OFF Isolation
68
50
5
CS (OFF)
CD (OFF)
ADG528A
22
ADG529A
11
QINJ, Charge Injection
4
POWER SUPPLY
IDD
0.6
1
ADG528A
ADG528A
ADG529A
ADG529A
B Version
T Version
–40°C to
–55°C to
+25°C +85°C
+25°C +125°C
Comments
(Cont’d)
100
100
100
ns min
See Figure 1
10
100
10
100
10
100
See Figure 1
See Figure 2
VEN = 0.8 V, RL = 1 kΩ, CL = 15 pF,
VS = 3.5 V rms, f = 100 kHz
VEN = 0.8 V
VEN = 0.8 V
68
50
5
68
50
5
ns min
ns min
dB typ
dB min
pF typ
22
11
4
22
11
4
pF typ
pF typ
pC typ
0.6
1.5
Power Dissipation
Units
11
0.6
1.5
10
25
1.5
10
25
25
RS = 0 Ω, VS = 0 V; Test Circuit 11
mA typ VIN = VINL or VINH
mA max
mW typ
mW max
NOTE
1
Sample tested at +25°C to ensure compliance.
Specifications subject to change without notice.
–4–
REV. C
ADG528A
ABSOLUTE MAXIMUM RATINGS 1
PIN CONFIGURATIONS
DIP/SOIC
(TA = +25°C, unless otherwise noted)
VDD to VSS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44 V
VDD to GND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 V
VSS to GND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –25 V
Analog Inputs2
Voltage at S, D . . . . . . . . . VSS – 2 V to VDD + 2 V or 20 mA,
whichever Occurs First
Continuous Current, S or D . . . . . . . . . . . . . . . . . . . 20 mA
Pulsed Current, S or D
1 ms duration, 10% Duty Cycle . . . . . . . . . . . . . . . 40 mA
Digital Inputs1
Voltage at A, EN, WR, RS . . . . . . VSS – 4 V to VDD + 4 V or
20 mA, whichever Occurs First
Power Dissipation (Any Package)
Up to +75°C . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 470 mW
Derates above +75°C . . . . . . . . . . . . . . . . . . . . . . . 6 mW/°C
Operating Temperature
Commercial (K Version) . . . . . . . . . . . . . . . –40°C to +85°C
Industrial (B Version) . . . . . . . . . . . . . . . . . –40°C to +85°C
Extended (T Version) . . . . . . . . . . . . . . . . –55°C to +125°C
Storage Temperature Range . . . . . . . . . . . . . –65°C to +150°C
Lead Temperature (Soldering, 10 sec) . . . . . . . . . . . . +300°C
PLCC
NOTES
1
Stresses above those listed under “Absolute Maximum Ratings” may cause permanent
damage to the device. This is a stress rating only and functional operation of the device
at these or any other conditions above those indicated in the operational sections of this
specification is not implied. Exposure to absolute maximum rating conditions for
extended periods may affect device reliability.
2
Overvoltage at A, EN, WR, RS, S or D will be clamped by diodes. Current should
be limited to the maximum rating above.
ESD CAUTION
REV. C
–5–
ADG528A
TRUTH TABLES
TIMING DIAGRAMS
A2 A1 A0 EN WR RS ON SWITCH PAIR
X
X
X
X
X
X
X
X
X
1
0
X
0
0
0
0
1
1
1
1
X
0
0
1
1
0
0
1
1
X
0
1
0
1
0
1
0
1
0
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
1
X = Don’t Care
Retains Previous Switch Condition
NONE (Address and Enable
Latches Cleared)
NONE
1
2
3
4
5
6
7
8
Figure 1.
ADG528A
A1 A0 EN WR RS ON SWITCH PAIR
X
X
X
X
X
X
X
1
0
X
0
0
1
1
X
0
1
0
1
0
1
1
1
1
0
0
0
0
0
1
1
1
1
1
X = Don’t Care
Retains Previous Switch Condition
NONE (Address and Enable Latches
Cleared)
NONE
1
2
3
4
Figure 2.
Figure 1 shows the timing sequence for latching the switch
address and enable inputs. The latches are level sensitive; therefore, while WR is held low, the latches are transparent and the
switches respond to the address and enable inputs. This input
data is latched on the rising edge of WR.
Figure 2 shows the Reset Pulse Width, tRS, and Reset Turn-off
Time, tOFF (RS).
ADG529A
Note: All digital input signals rise and fall times measured from
10% to 90% of 3 V. tR = tF = 20 ns.
–6–
REV. C
Typical Performance Characteristics–ADG528A
The multiplexers are guaranteed functional with reduced single or dual supplies down to 4.5 V.
TPC 1. RON as a Function of VD(VS): Dual Supply
Voltage, TA = +25°C
TPC 4. Trigger Levels vs. Power Supply Voltage,
Dual or Single Supply, TA = +25°C
TPC 2. Leakage Current as a Function of Temperature
(Note: Leakage Currents Reduce as the Supply
Voltages Reduce)
TPC 5. tTRANSITION vs. Supply Voltage: Dual and
Single Supplies, TA = +25°C
(Note: For VDD and |VSS| < 10 V; V1 = VDD/VSS, V2 =
VSS/VDD. See Test Circuit 6)
TPC 6. IDD vs. Supply Voltage: Dual or Single
Supply, TA = +25°C
TPC 3. RON as a Function of VD(VS): Single Supply
Voltage, TA = +25°C
REV. C
–7–
ADG528A
Test Circuits
Test Circuit 1. RON
Test Circuit 4. ID (ON)
Test Circuit 2. IS (OFF)
Test Circuit 5. IDIFF
Test Circuit 3. ID (OFF)
Test Circuit 6. Switching Time of Multiplexer, tTRANSITION
Test Circuit 7. Break-Before-Make Delay, tOPEN
–8–
REV. C
ADG528A
Test Circuit 8. Enable Delay, tON (EN), tOFF (EN)
Test Circuit 9. Write Turn-On Time, tON (WR)
Test Circuit 10. Reset Turn-Off Time, tOFF (RS)
Test Circuit 11. Charge Injection
REV. C
–9–
ADG528A
TERMINOLOGY
RON
RON Match
RON Drift
IS (OFF)
ID (OFF)
ID (ON)
VS (VD)
CS (OFF)
CD (OFF)
CIN
tON (EN)
Ohmic resistance between terminals D and S
Difference between the RON of any two channels
Change in RON versus temperature
Source terminal leakage current when the switch
is off.
Drain terminal leakage current when the switch is
off.
Leakage current that flows from the closed switch
into the body.
Analog voltage on terminal S or D
Channel input capacitance for “OFF” condition
Channel output capacitance for “OFF” condition
Digital input capacitance
Delay time between the 50% and 90% points of
the digital input and switch “ON” condition.
tOFF (EN)
tTRANSITION
tOPEN
VINL
VINH
IINL (IINH)
VDD
VSS
IDD
ISS
–10–
Delay time between the 50% and 10% points of
the digital input and switch “OFF” condition
Delay time between the 50% and 90% points of
the digital inputs and switch “ON” condition
when switching from one address state to another.
“OFF” time measured between 50% points of
both switches when switching from one address
state to another
Maximum input voltage for Logic “0”
Minimum input voltage for Logic “1”
Input current of the digital input
Most positive voltage supply
Most negative voltage supply
Positive supply current
Negative supply current
REV. C
Data Sheet
ADG528A
OUTLINE DIMENSIONS
0.920 (23.37)
0.900 (22.86)
0.880 (22.35)
18
10
1
9
0.280 (7.11)
0.250 (6.35)
0.240 (6.10)
0.325 (8.26)
0.310 (7.87)
0.300 (7.62)
0.100 (2.54)
BSC
0.060 (1.52)
MAX
0.210 (5.33)
MAX
0.195 (4.95)
0.130 (3.30)
0.115 (2.92)
0.015
(0.38)
MIN
0.150 (3.81)
0.130 (3.30)
0.115 (2.92)
0.015 (0.38)
GAUGE
PLANE
SEATING
PLANE
0.022 (0.56)
0.018 (0.46)
0.014 (0.36)
0.014 (0.36)
0.010 (0.25)
0.008 (0.20)
0.430 (10.92)
MAX
0.005 (0.13)
MIN
0.070 (1.78)
0.060 (1.52)
0.045 (1.14)
070706-A
COMPLIANT TO JEDEC STANDARDS MS-001
CONTROLLING DIMENSIONS ARE IN INCHES; MILLIMETER DIMENSIONS
(IN PARENTHESES) ARE ROUNDED-OFF INCH EQUIVALENTS FOR
REFERENCE ONLY AND ARE NOT APPROPRIATE FOR USE IN DESIGN.
CORNER LEADS MAY BE CONFIGURED AS WHOLE OR HALF LEADS.
Figure 1. 18-Lead Plastic Dual In-Line Package [PDIP]
Narrow Body
(N-18)
Dimensions Shown in inches and (millimeters)
0.180 (4.57)
0.165 (4.19)
0.048 (1.22 )
0.042 (1.07)
3
0.048 (1.22)
0.042 (1.07)
4
0.056 (1.42)
0.042 (1.07)
0.20 (0.51)
MIN
19
PIN 1
IDENTIFIER
18
TOP VIEW
0.021 (0.53)
0.013 (0.33)
0.050
(1.27)
BSC
0.330 (8.38)
0.032 (0.81) 0.290 (7.37)
0.026 (0.66)
(PINS DOWN)
14
8
0.020
(0.51)
R
9
0.020 (0.50)
R
13
0.356 (9.04)
SQ
0.350 (8.89)
0.395 (10.03)
SQ
0.385 (9.78)
0.045 (1.14)
R
0.025 (0.64)
0.120 (3.04)
0.090 (2.29)
COMPLIANT TO JEDEC STANDARDS MO-047-AA
CONTROLLING DIMENSIONS ARE IN INCHES; MILLIMETER DIMENSIONS
(IN PARENTHESES) ARE ROUNDED-OFF INCH EQUIVALENTS FOR
REFERENCE ONLY AND ARE NOT APPROPRIATE FOR USE IN DESIGN.
Figure 2. 20-Lead Plastic Leaded Chip Carrier [PLCC]
(P-20)
Dimensions shown in inches and (millimeters)
Rev. C | Page 11 of 13
BOTTOM
VIEW
(PINS UP)
ADG528A
Data Sheet
0.005
(0.13)
MIN
0.098 (2.49)
MAX
18
10
1
9
PIN 1
0.200 (5.08)
MAX
0.960 (24.38) MAX
0.310 (7.87)
0.220 (5.59)
0.060 (1.52)
0.015 (0.38)
0.320 (8.13)
0.290 (7.37)
0.150 (3.81)
MIN
0.200 (5.08)
0.125 (3.18)
0.100
(2.54)
BSC
0.023 (0.58)
0.014 (0.36)
0.070 (1.78) SEATING
PLANE
0.030 (0.76)
15°
0°
0.015 (0.38)
0.008 (0.20)
CONTROLLING DIMENSIONS ARE IN INCHES; MILLIMETERS DIMENSIONS
(IN PARENTHESES) ARE ROUNDED-OFF INCH EQUIVALENTS FOR
REFERENCE ONLY AND ARE NOT APPROPRIATE FOR USE IN DESIGN.
Figure 3. 18-Lead Ceramic Dual In-Line Package [CERDIP]
(Q-18)
Dimensions shown in inches and (millimeters)
ORDERING GUIDE
Model1
ADG528AKN
ADG528AKNZ
ADG528AKP
ADG528AKP-REEL
ADG528AKPZ
Temperature Range
−40°C to +85°C
−40°C to +85°C
−40°C to +85°C
−40°C to +85°C
−40°C to +85°C
Package Description
18-Lead Plastic Dual In-Line Package [PDIP]
18-Lead Plastic Dual In-Line Package [PDIP]
20-Lead Plastic Leaded Chip Carrier [PLCC]
20-Lead Plastic Leaded Chip Carrier [PLCC]
20-Lead Plastic Leaded Chip Carrier [PLCC]
Package Option
N–18
N–18
P–20
P–20
P-20
ADG528AKPZ-REEL
ADG528ATQ
ADG528ABCHIPS
−40°C to +85°C
−55°C to +125°C
−55°C to +125°C
20-Lead Plastic Leaded Chip Carrier [PLCC]
18-Lead Ceramic Dual In-Line Package [CERDIP]
DIE
P-20
Q-18
1
Z = RoHS Compliant Part.
Rev. C | Page 12 of 13
Data Sheet
REVISION HISTORY
8/2017—Rev. B to Rev. C
Added ADG529A Obsolete Note .................................................... 1
Updated Outline Dimensions ........................................................11
Changes to Ordering Guide` .........................................................12
10/2004—Rev. A to Rev. B
Deleted 20-Lead LCC Package ......................................... Universal
Changes to Features .......................................................................... 5
Changes to Ordering Guide ............................................................. 6
SOIC added to DIP Pin Configuration .......................................... 5
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