FEATURES
FUNCTIONAL BLOCK DIAGRAM
Analog output protection and detection solution
Overvoltage protection up to ±60 V on S and SFB pins
Power off protection up to ±60 V on S and SFB pins
Integrated 0.6 kΩ secondary feedback channel
Known output under all conditions
User enabled, power-on condition pulls source to 0 V
Known state without digital inputs present
Optimized resistance for measurement channel and
feedback channel
Low on resistance of 6 Ω typical on signal channel
Ultraflat, on resistance on signal channel
Latch-up immune
3 mm × 2 mm LFCSP
VSS to VDD −2 V signal range
Fully specified at ±15 V, ±20 V, +12 V, and +36 V
±5 V to ±22 V dual-supply operation
8 V to 44 V single-supply operation
APPLICATIONS
DAC output protection
Amplifier output protection
Analog output modules
Process control/distributed control systems
Data acquisition
Instrumentation
COMPANION PRODUCTS
Current/Voltage Output DAC: AD5423
Precision Amplifier: ADA4077-1
Rail-to-Rail Output, JFET Op Amp: ADA4625-1
ADG5401F
S
D
POC
SFB
DFB
FF
IN
22052-001
Data Sheet
Fault Protection, 6 Ω RON, SPST Switch with
0.6 kΩ Feedback Channel
ADG5401F
Figure 1.
GENERAL DESCRIPTION
The ADG5401F main channel switch is a SPST, low on-resistance
switch that features overvoltage protection, power off protection,
and overvoltage detection on the source pins (S and SFB). The
ADG5401F also features a protected secondary feedback channel
for use with digital-to-analog converter (DAC) or amplifier outputs.
When no power supplies are present, the switch remains in the
off condition, and the switch inputs are high impedance.
When powered, if the analog input signal levels on the S pin
exceed VDD or VSS by a threshold voltage (VT) the switch turns
off, the open-drain FF pin pulls to a logic low and a path between
the D and DFB pins is switched on to prevent an open-loop
condition on the amplifier output. Input signal levels up to +60 V
or −60 V relative to ground are blocked, in both the powered and
unpowered condition. The selectable POC pin function allows
the protected switch terminal, S, to be connected to GND to
minimize glitches on the output. The switch turns on with a
Logic 1 input and conducts equally well in both directions. The
digital input is compatible with 1.8 V logic inputs over the full
operating supply range.
PRODUCT HIGHLIGHTS
1.
2.
3.
4.
5.
Rev. 0
Source pin is protected against voltages greater than the
supply rails, up to −60 V and +60 V in both powered and
unpowered states.
Overvoltage detection with digital output indicates
operating state of switches.
Trench isolation guards against latch-up.
The ADG5401F can operate from a dual supply range of
±5 V to ±22 V or a single-supply range of +8 V to +44 V.
Negative channel metal oxide semiconductor (NMOS)
only architecture requires 2 V headroom toward VDD and
provides low RON and ultraflat RON across the VSS to VDD −
5 V signal range.
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Technical Support
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ADG5401F
Data Sheet
TABLE OF CONTENTS
Features .............................................................................................. 1
Terminology.................................................................................... 26
Applications ...................................................................................... 1
Theory of Operation ...................................................................... 27
Companion Products ....................................................................... 1
Switch Architecture ................................................................... 27
Functional Block Diagram .............................................................. 1
Overvoltage Fault Protection ................................................... 28
General Description ......................................................................... 1
Applications Information ............................................................. 29
Product Highlights ........................................................................... 1
Power Supply Rails..................................................................... 29
Revision History ............................................................................... 2
Power Supply Recommendations ............................................ 29
Specifications .................................................................................... 3
Power Supply Sequencing Protection ..................................... 29
±15 V Dual Supply ....................................................................... 3
Signal Range ................................................................................ 29
±20 V Dual Supply ....................................................................... 6
Low Impedance Output Channel Protection ......................... 29
12 V Single Supply ....................................................................... 9
Intelligent Fault Detection ........................................................ 30
36 V Single Supply ..................................................................... 12
Large Voltage, High Frequency Signals .................................. 30
Continuous Current per Channel, S or D............................... 14
Amplifier or DAC Output Protection ..................................... 30
Absolute Maximum Ratings ......................................................... 15
Open-Loop Prevention ............................................................. 30
Thermal Resistance .................................................................... 15
Power-On Condition ................................................................. 31
Electrostatic Discharge (ESD) Ratings .................................... 15
Switches in a Known State ........................................................ 31
ESD Caution................................................................................ 15
High Voltage Surge Suppression ............................................. 31
Pin Configuration and Function Descriptions .......................... 16
Outline Dimensions ....................................................................... 32
Typical Performance Characteristics ........................................... 17
Ordering Guide .......................................................................... 32
Test Circuits .................................................................................... 22
REVISION HISTORY
8/2020—Revision 0: Initial Version
Rev. 0 | Page 2 of 32
Data Sheet
ADG5401F
SPECIFICATIONS
Table 1. Operating Supply Voltages
Parameter
SUPPLY VOLTAGE
Dual
Single
Min
Typ
±5
8
Max
Unit
±22
44
V
V
±15 V DUAL SUPPLY
VDD = 15 V ± 10%, VSS = −15 V ± 10%, and GND = 0 V, unless otherwise noted.
Table 2.
Parameter
ANALOG SWITCH
Analog Signal Range
On Resistance, RON
On-Resistance Flatness, RFLAT (ON)
Feedback On Resistance, RFEEDBACK
LEAKAGE CURRENTS
Source Off Leakage, IS (Off)
+25°C
8.5
5.5
7.5
0.35
0.5
0.02
0.04
0.6
2.6
Source Feedback Off Leakage, ISFB (Off)
12.5
9.5
11.5
0.6
0.7
0.05
0.05
3.3
3.8
±0.1
±0.3
Ω max
Ω typ
Ω max
Ω typ
Ω max
Ω typ
Ω max
kΩ typ
kΩ max
nA typ
±2.5
±35
±11.5
nA max
nA max
nA typ
±2.5
±35
±11.5
nA max
nA max
nA typ
nA max
nA max
nA typ
±3
±40
±12
±2.5
±35
±11.5
nA max
nA max
nA typ
±35
±11.5
nA max
nA max
nA typ
nA max
nA max
±0.1
±0.15
Channel On Feedback Leakage, IDFB (On), ISFB (On)
10.5
±0.1
±0.15
Drain Feedback Off Leakage, IDFB (Off)
Ω typ
±0.1
±0.1
±0.3
Unit
Test Conditions/Comments
VDD = 13.5 V, VSS = −13.5 V
V
±0.1
±0.15
Channel On Leakage, ID (On), IS (On)
−40°C to +125°C
VSS to
VDD − 2
6
±0.15
Drain Off Leakage, ID (Off)
−40°C to +85°C
±2.5
±3
Rev. 0 | Page 3 of 32
±40
±12
Source voltage (VS) = VSS
to 10 V, source current (IS) =
10 mA
VS = VSS to 9 V, IS = 10 mA
VS = VSS to 10 V, IS = 10 mA
VS = VSS to 9 V, IS = 10 mA
VS = VSS to 10 V, IS = −100 µA
VDD = 16.5 V, VSS = −16.5 V
VS = ±10 V,
drain voltage (VD) = 10 V
−40°C to +105°C
VS = ±10 V, VD = 10 V
−40°C to +105°C
VS = ±10 V, VD = ±10 V
−40°C to +105°C
SFB voltage (VSFB) = ±10 V,
DFB voltage (VDFB) = 10 V
−40°C to +105°C
VSFB = ±10 V, VDFB = 10 V
−40°C to +105°C
VSFB = ±10 V, VDFB = ±10 V
−40°C to +105°C
ADG5401F
Parameter
FAULT (ON S AND SFB PINS)
VT
Source Leakage Current, IS
With Overvoltage
Data Sheet
+25°C
−40°C to +85°C
0.7
Power Supplies Grounded
±55
µA typ
±11
µA typ
±0.1
nA typ
±0.3
±0.1
±5
±0.3
±5
±55
nA max
µA typ
1.3
0.8
5
0.4
V min
V max
µA typ
µA max
pF typ
V max
14.2
µs typ
2.5
5
Digital Input Capacitance, CIN
Output Voltage Low, VOL
DYNAMIC CHARACTERISTICS
On Time, tON
Off Time, tOFF
Overvoltage Response Time, tRESPONSE
Positive
17
185
220
17.2
17.2
220
220
240
240
1.1
1.2
Interrupt Flag Response Time, tDIGRESP
230
230
0.8
1
11.7
14.4
80
95
Interrupt Flag Recovery Time, tDIGREC
90
1.5
2.2
Charge Injection, QINJ
2
−230
Negative
Overvoltage Recovery Time, tRECOVERY
nA max
nA typ
±55
±2
Power Supplies Floating
DIGITAL INPUTS/OUTPUTS
Input Voltage High, VINH
Input Voltage Low, VINL
Input Low or High Current, IINL or IINH
Unit
Test Conditions/Comments
V typ
Power Supplies Grounded or Floating
Drain Leakage Current, ID
With Overvoltage
−40°C to +125°C
14.5
Rev. 0 | Page 4 of 32
14.5
100
2.2
µs max
ns typ
ns max
ns typ
ns max
µs typ
µs max
µs typ
µs max
ns typ
ns max
µs typ
µs max
pC typ
VDD = 16.5 V, VSS = −16.5 V,
GND = 0 V, VS = ±60 V
VDD = 0 V or floating,
VSS = 0 V or floating,
GND = 0 V, IN = 0 V or
floating, VS = ±60 V
VDD = 16.5 V, VSS = −16.5 V,
GND = 0 V, VS = ±60 V
VDD = 0 V, VSS = 0 V, GND = 0 V,
VS = ±60 V, IN = 0 V
VDD = floating, VSS = floating,
GND = 0 V, VS = ±60 V,
IN = 0 V
Input voltage (VIN) = 0 V or 5 V
Fault flag current (IFF) = 2 mA
Load resistance (RL) = 300 Ω,
load capacitance (CL) = 35 pF,
VS = 10 V
RL = 300 Ω, CL = 35 pF, VS = 10 V
RL = 1 kΩ, CL = 5 pF
RL = 1 kΩ, CL = 5 pF
RL = 1 kΩ, CL = 5 pF
Pull-up resistor (RPULLUP) =
1 kΩ, CL = 12 pF,
pull-up voltage (VPULL_UP) = 5 V
RPULLUP = 1 kΩ, CL = 12 pF,
VPULL_UP = 5 V
VS = 0 V,
source resistor (RS) = 0 Ω,
CL = 1 nF
Data Sheet
Parameter
Off Isolation
ADG5401F
+25°C
−70
−40°C to +85°C
−40°C to +125°C
Unit
dB typ
Total Harmonic Distortion Plus Noise, THD + N
0.001
% typ
−3 dB Bandwidth
Insertion Loss
460
−0.5
MHz typ
dB typ
9
11
19
pF typ
pF typ
pF typ
Source Off Capacitance, CS (Off)
Drain Off Capacitance, CD (Off)
Drain On Capacitance and Source On
Capacitance, CD (On) and CS (On)
POWER REQUIREMENTS
Normal Mode
Positive Supply Current, IDD
GND Current, IGND
Negative Supply Current, ISS
Fault Mode (on S and SFB Pins)
IDD
IGND
ISS
Test Conditions/Comments
RL = 50 Ω, CL = 5 pF,
frequency (f) = 1 MHz
RL = 10 kΩ, VS = 10 V p-p,
f = 20 Hz to 20 kHz
RL = 50 Ω, CL = 5 pF
RL = 50 Ω, CL = 5 pF,
f = 1 MHz
VS = 0 V, f = 1 MHz
VS = 0 V, f = 1 MHz
VS = 0 V, f = 1 MHz
VDD = 16.5 V, VSS = −16.5 V,
GND = 0 V,
digital inputs = 0 V or 5 V
165
240
85
120
80
120
240
120
120
µA typ
µA max
µA typ
µA max
µA typ
µA max
VS = ±60 V
140
230
100
150
65
110
230
150
110
Rev. 0 | Page 5 of 32
µA typ
µA max
µA typ
µA max
µA typ
µA max
ADG5401F
Data Sheet
±20 V DUAL SUPPLY
VDD = 20 V ± 10%, VSS = −20 V ± 10%, and GND = 0 V, unless otherwise noted.
Table 3.
Parameter
ANALOG SWITCH
Analog Signal Range
RON
RFLAT (ON)
RFEEDBACK
LEAKAGE CURRENTS
IS (Off)
+25°C
VSS to
VDD − 2
6
8.5
5.5
7.5
0.35
0.5
0.02
0.04
0.6
2.6
ISFB (Off)
±0.1
±0.3
IDFB (Off)
FAULT (ON S AND SFB PINS)
VT
12.5
9.5
11.5
0.6
0.7
0.05
0.05
3.3
3.8
±0.1
±0.3
Test Conditions/Comments
VDD = 18 V, VSS = −18 V
±2.5
±2.5
±3
±2.5
±2.5
±3
Ω typ
Ω max
Ω typ
Ω max
Ω typ
Ω max
Ω typ
Ω max
kΩ typ
kΩ max
VS = VSS to 15 V, IS = 10 mA
VS = VSS to 13.5 V, IS = 10 mA
VS = VSS to 15 V, IS = 10 mA
VS = VSS to 13.5 V, IS = 10 mA
VS = VSS to 15 V, IS = 100 µA
nA typ
VDD = 22 V, VSS = −22 V
VS = ±15 V, VD = 15 V
±35
±11.5
nA max
nA max
nA typ
−40°C to +105°C
VS = ±15 V, VD = 15 V
±35
±11.5
nA max
nA max
nA typ
nA max
nA max
nA typ
±40
±12
±35
±11.5
nA max
nA max
nA typ
±35
±11.5
nA max
nA max
nA typ
nA max
nA max
±0.1
±0.2
IDFB (On), ISFB (On)
10.5
±0.1
±0.2
Unit
V
±0.1
±0.2
ID (On), IS (On)
−40°C to +125°C
±0.1
±0.2
ID (Off)
−40°C to +85°C
±40
±12
0.7
−40°C to +105°C
VS = ±15 V, VD = ±15 V
−40°C to +105°C
VSFB = ±15 V, VDFB = 15 V
−40°C to +105°C
VSFB = ±15 V, VDFB = 15 V
−40°C to +105°C
VSFB = ±15 V, VDFB = ±15 V
−40°C to +105°C
V typ
IS
With Overvoltage
±55
µA typ
Power Supplies Grounded or Floating
±11
µA typ
Rev. 0 | Page 6 of 32
VDD = 22 V, VSS = −22 V,
GND = 0 V, VS = ±58 V
VDD = 0 V or floating,
VSS = 0 V or floating, GND = 0 V,
IN = 0 V or floating, VS = ±60 V
Data Sheet
Parameter
ID
With Overvoltage
Power Supplies Grounded
ADG5401F
+25°C
−40°C to +85°C
±0.1
±0.3
±0.1
±5
±0.3
±5
Power Supplies Floating
DIGITAL INPUTS/OUTPUTS
VINH
VINL
IINL or IINH
−40°C to +125°C
±55
tOFF
tRESPONSE
Positive
19.4
220
220
230
230
0.9
1
90
1.9
95
tDIGREC
2.4
−270
−70
0.001
2.6
QINJ
Off Isolation
THD + N
−3 dB Bandwidth
Insertion Loss
CS (Off)
CD (Off)
CD (On), CS (On)
450
−0.5
8
10
18
tRECOVERY
16.9
nA max
nA typ
V min
V max
µA typ
µA max
pF typ
V max
19.3
tDIGRESP
Negative
VDD = 22 V, VSS = −22 V,
GND = 0 V, VS = ±58 V
1.3
0.8
5
0.4
230
230
0.7
0.9
13.8
16.8
80
nA typ
nA max
µA typ
2.5
15.9
19.1
180
210
Test Conditions/Comments
±55
±2
5
CIN
VOL
DYNAMIC CHARACTERISTICS
tON
Unit
16.9
100
2.6
VDD = floating, VSS = floating,
GND = 0 V, VS = ±60 V, IN = 0 V
VIN = 0 V or 5 V
IFF = 2 mA
µs typ
µs max
ns typ
ns max
RL = 300 Ω, CL = 35 pF, VS = 10 V
ns typ
ns max
µs typ
µs max
µs typ
µs max
ns typ
RL = 1 kΩ, CL = 5 pF
ns max
µs typ
µs max
pC typ
dB typ
% typ
MHz typ
dB typ
pF typ
pF typ
pF typ
Rev. 0 | Page 7 of 32
VDD = 0 V, VSS = 0 V, GND = 0 V,
VS = ±60 V, IN = 0 V
RL = 300 Ω, CL = 35 pF, VS = 10 V
RL = 1 kΩ, CL = 5 pF
RL = 1 kΩ, CL = 5 pF
RPULLUP = 1 kΩ, CL = 12 pF,
VPULL_UP = 5 V
RPULLUP = 1 kΩ, CL = 12 pF,
VPULL_UP = 5 V
VS = 0 V, RS = 0 Ω, CL = 1 nF
RL = 50 Ω, CL = 5 pF, f = 1 MHz
RL = 10 kΩ, VS = 10 V p-p,
f = 20 Hz to 20 kHz
RL = 50 Ω, CL = 5 pF
RL = 50 Ω, CL = 5 pF, f = 1 MHz
VS = 0 V, f = 1 MHz
VS = 0 V, f = 1 MHz
VS = 0 V, f = 1 MHz
ADG5401F
Parameter
POWER REQUIREMENTS
Normal Mode
IDD
IGND
ISS
Fault Mode (on S and SFB Pins)
IDD
IGND
ISS
Data Sheet
+25°C
165
240
85
120
80
120
−40°C to +85°C
−40°C to +125°C
240
120
120
Unit
Test Conditions/Comments
VDD = 22 V, VSS = −22 V, GND = 0 V,
digital inputs = 0 V or 5 V
µA typ
µA max
µA typ
µA max
µA typ
µA max
VS = ±58 V
140
230
100
150
65
110
230
150
110
Rev. 0 | Page 8 of 32
µA typ
µA max
µA typ
µA max
µA typ
µA max
Data Sheet
ADG5401F
12 V SINGLE SUPPLY
VDD = 12 V ± 10%, VSS = 0 V ± 10%, and GND = 0 V, unless otherwise noted.
Table 4.
Parameter
ANALOG SWITCH
Analog Signal Range
RON
RFLAT (ON)
RFEEDBACK
LEAKAGE CURRENTS
IS (Off)
ID (Off)
ID (On), IS (On)
ISFB (Off)
IDFB (Off)
IDFB (On), ISFB (On)
FAULT (ON S AND SFB PINS)
VT
+25°C
VSS to
VDD − 2
6
8.5
5.5
7.5
0.6
0.8
0.01
0.04
0.6
2.7
±0.1
±0.15
±0.1
±0.15
±0.1
±0.3
±0.1
±0.15
±0.1
±0.15
±0.1
±0.3
−40°C to +85°C
−40°C to +125°C
Unit
Test Conditions/Comments
VDD = 10.8 V, VSS = 0 V
V
10.5
12.5
9.5
11.5
0.9
1.0
0.05
0.05
3.4
3.9
±2.5
±2.5
±3
±2.5
±2.5
±3
±35
±11.5
±35
±11.5
±40
±12
±35
±11.5
±35
±11.5
±40
±12
0.7
Ω typ
Ω max
Ω typ
Ω max
Ω typ
Ω max
Ω typ
Ω max
kΩ typ
kΩ max
nA typ
nA max
nA max
nA typ
nA max
nA max
nA typ
nA max
nA max
nA typ
nA max
nA max
nA typ
nA max
nA max
nA typ
nA max
nA max
VS = 0 V to 8 V, IS = 10 mA
VS = 0 V to 6 V, IS = 10 mA
VS = 0 V to 8 V, IS = 10 mA
VS = 0 V to 6 V, IS = 10 mA
VS = VSS to 8 V, IS = 100 µA
VDD = 13.2 V, VSS = 0 V
VS = 1 V to 10 V, VD = 10 V to 1 V
−40°C to +105°C
VS = 1 V to 10 V, VD = 10 V to 1 V
−40°C to +105°C
VS = 1 V to 10 V, VD = 10 V to 1 V
−40°C to +105°C
VSFB = 1 V to 10 V, VDFB = 10 V to 1 V
−40°C to +105°C
VSFB = 1 V to 10 V, VDFB = 10 V to 1 V
−40°C to +105°C
VSFB = VDFB = 1 V to 10 V
−40°C to +105°C
V typ
IS
With Overvoltage
±55
µA typ
Power Supplies Grounded or
Floating
±11
µA typ
Rev. 0 | Page 9 of 32
VDD = 13.2 V, VSS = 0 V, GND = 0 V,
VS = ±60 V
VDD = 0 V or floating, VSS = 0 V or
floating, GND = 0 V, IN = 0 V or floating,
VS = ±60 V
ADG5401F
Parameter
ID
With Overvoltage
Power Supplies Grounded
Data Sheet
+25°C
−40°C to +85°C
±0.1
±0.3
±0.1
±5
±0.3
±5
Power Supplies Floating
DIGITAL INPUTS/OUTPUTS
VINH
VINL
IINL or IINH
−40°C to +125°C
±55
tOFF
tRESPONSE
Positive
QINJ
Off Isolation
THD + N
−3 dB Bandwidth
Insertion Loss
CS (Off)
CD (Off)
CD (On), CS (On)
390
−0.5
12
14
20
Negative
tRECOVERY
tDIGRESP
tDIGREC
VDD = 13.2 V, VSS = 0 V, GND = 0 V,
VS = ±60 V
nA max
nA typ
1.3
0.8
V min
V max
µA typ
µA max
pF typ
V max
5
0.4
320
320
1.3
1.5
6.1
7.1
80
90
1.3
1.7
−120
−55
0.0017
nA typ
nA max
µA typ
2.5
6.5
7.6
285
340
Test Conditions/Comments
±55
±2
5
CIN
VOL
DYNAMIC CHARACTERISTICS
tON
Unit
7.6
7.6
350
350
330
330
1.7
1.8
7.7
8
95
100
1.9
1.9
VDD = floating, VSS = floating,
GND = 0 V, VS = ±60 V, IN = 0 V
VIN = 0 V or 5 V
IFF = 2 mA
µs typ
µs max
ns typ
ns max
RL = 300 Ω, CL = 35 pF, VS = 8 V
ns typ
ns max
µs typ
µs max
µs typ
µs max
ns typ
ns max
µs typ
µs max
pC typ
dB typ
% typ
RL = 1 kΩ, CL = 5 pF
MHz typ
dB typ
pF typ
pF typ
pF typ
Rev. 0 | Page 10 of 32
VDD = 0 V, VSS = 0 V, GND = 0 V,
VS = ±60 V, IN = 0 V
RL = 300 Ω, CL = 35 pF, VS = 8 V
RPULLUP = 1 kΩ, CL = 5 pF
RL = 1 kΩ, CL = 5 pF
RPULLUP = 1 kΩ, CL = 12 pF, VPULL_UP = 5 V
RPULLUP = 1 kΩ, CL = 12 pF, VPULL_UP = 5 V
VS = 6 V, RS = 0 Ω, CL = 1 nF
RL = 50 Ω, CL = 5 pF, f = 1 MHz
RL = 10 kΩ, VS = 6 V p-p,
f = 20 Hz to 20 kHz
RL = 50 Ω, CL = 5 pF
RL = 50 Ω, CL = 5 pF, f = 1MHz
VS = 6 V, f = 1 MHz
VS = 6 V, f = 1 MHz
VS = 6 V, f = 1 MHz
Data Sheet
Parameter
POWER REQUIREMENTS
Normal Mode
IDD
IGND
ISS
Fault Mode (on S and SFB Pins)
IDD
IGND
ISS
ADG5401F
+25°C
150
220
90
130
60
90
−40°C to +85°C
−40°C to +125°C
220
130
90
Unit
Test Conditions/Comments
VDD = 13.2 V, VSS = 0 V, GND = 0 V,
digital inputs = 0 V or 5 V
µA typ
µA max
µA typ
µA max
µA typ
µA max
VS = ±60 V
140
230
100
150
65
110
230
150
110
Rev. 0 | Page 11 of 32
µA typ
µA max
µA typ
µA max
µA typ
µA max
ADG5401F
Data Sheet
36 V SINGLE SUPPLY
VDD = 36 V ± 10%, VSS = 0 V ± 10%, and GND = 0 V, unless otherwise noted.
Table 5.
Parameter
ANALOG SWITCH
Analog Signal Range
RON
RFLAT (ON)
RFEEDBACK
LEAKAGE CURRENTS
IS (Off)
ID (Off)
ID (On), IS (On)
ISFB (Off)
IDFB (Off)
IDFB (On), ISFB (On)
FAULT (ON S AND SFB PINS)
VT
+25°C
VSS to
VDD − 2
6
8.5
5.5
7.5
0.6
0.8
0.01
0.04
0.6
2.7
±0.1
±0.15
±0.1
±0.15
±0.1
±0.3
±0.1
±0.15
±0.1
±0.15
±0.1
±0.3
−40°C to +85°C
−40°C to +125°C
Unit
Test Conditions/Comments
VDD = 32.4 V, VSS = 0 V
V
10.5
12.5
9.5
11.5
0.9
1.0
0.05
0.05
3.4
3.9
±2.5
±2.5
±3
±2.5
±2.5
±3
±35
±11.5
±35
±11.5
±40
±12
±35
±11.5
±35
±11.5
±40
±12
0.7
Ω typ
Ω max
Ω typ
Ω max
Ω typ
Ω max
Ω typ
Ω max
kΩ typ
kΩ max
nA typ
nA max
nA max
nA typ
nA max
nA max
nA typ
nA max
nA max
nA typ
nA max
nA max
nA typ
nA max
nA max
nA typ
nA max
nA max
VS = 0 V to 30 V, IS = 10 mA
VS = 0 V to 27 V, IS = 10 mA
VS = 0 V to 30 V, IS = 10 mA
VS = 0 V to 27 V, IS = 10 mA
VS = 0 V to 30 V, IS = 100 µA
VDD = 39.6 V, VSS = 0 V
VS = 1 V to 30 V, VD = 30 V to 1 V
−40°C to +105°C
VS = 1 V to 30 V, VD = 30 V to 1 V
−40°C to +105°C
VS = 1 V to 30 V, VD = 30 V to 1 V
−40°C to +105°C
VSFB = 1 V to 30 V, VDFB = 30 V to 1 V
−40°C to +105°C
VSFB = 1 V to 30 V, VDFB = 30 V to 1 V
−40°C to +105°C
VSFB = VDFB = 1 V to 30 V
−40°C to +105°C
V typ
IS
With Overvoltage
±55
µA typ
Power Supplies Grounded or
Floating
±11
µA typ
Rev. 0 | Page 12 of 32
VDD = 39.6 V, VSS = 0 V, GND = 0 V,
VS = +60 V and VS = −40 V
VDD = 0 V or floating, VSS = 0 V or
floating, GND = 0 V, IN = 0 V or floating,
VS = ±60 V
Data Sheet
Parameter
ID
With Overvoltage
Power Supplies Grounded
ADG5401F
+25°C
−40°C to +85°C
±0.1
±0.3
±0.1
±5
±0.3
±5
Power Supplies Floating
DIGITAL INPUTS/OUTPUTS
VINH
VINL
IINL or IINH
−40°C to +125°C
±55
tOFF
tRESPONSE
Positive
QINJ
Off Isolation
THD + N
−3 dB Bandwidth
Insertion Loss
CS (Off)
CD (Off)
CD (On), CS (On)
395
−0.5
9
11
18
Negative
tRECOVERY
tDIGRESP
tDIGREC
VDD = 39.6 V, VSS = 0 V, GND = 0 V,
VS = +60 V and VS = −40 V
nA max
nA typ
1.3
0.8
V min
V max
µA typ
µA max
pF typ
V max
5
0.4
330
350
1.3
1.5
6.2
9.4
80
95
3.3
6.1
−230
−60
0.0008
nA typ
nA max
µA typ
2.5
8.7
10.2
310
360
Test Conditions/Comments
±55
±2
5
CIN
VOL
DYNAMIC CHARACTERISTICS
tON
Unit
10.3
10.3
360
360
350
350
1.6
1.8
9.4
9.7
100
100
6.3
6.6
VDD = floating, VSS = floating,
GND = 0 V, VS = ±60 V, IN = 0 V
VIN = 0 V or 5 V
IFF = 2 mA
µs typ
µs max
ns typ
ns max
RL = 300 Ω, CL = 35 pF, VS = 18 V
ns typ
ns max
µs typ
µs max
µs typ
µs max
ns typ
ns max
µs typ
µs max
pC typ
dB typ
% typ
RL = 1 kΩ, CL = 5 pF
MHz typ
dB typ
pF typ
pF typ
pF typ
Rev. 0 | Page 13 of 32
VDD = 0 V, VSS = 0 V, GND = 0 V,
VS = ±60 V, IN = 0 V
RL = 300 Ω, CL = 35 pF, VS = 18 V
RPULLUP = 1 kΩ, CL = 5 pF
RL = 1 kΩ, CL = 5 pF
RPULLUP = 1 kΩ, CL = 12 pF, VPULL_UP = 5 V
RPULLUP = 1 kΩ, CL = 12 pF, VPULL_UP = 5 V
VS = 18 V, RS = 0 Ω, CL = 1 nF
RL = 50 Ω, CL = 5 pF, f = 1 MHz
RL = 10 kΩ, VS = 18 V p-p,
f = 20 Hz to 20 kHz
RL = 50 Ω, CL = 5 pF
RL = 50 Ω, CL = 5 pF, f = 1 MHz
VS = 18 V, f = 1 MHz
VS = 18 V, f = 1 MHz
VS = 18 V, f = 1 MHz
ADG5401F
Parameter
POWER REQUIREMENTS
Normal Mode
IDD
IGND
ISS
Fault Mode (on S and SFB Pins)
IDD
IGND
ISS
Data Sheet
+25°C
−40°C to +85°C
150
220
90
130
60
90
−40°C to +125°C
Unit
Test Conditions/Comments
VDD = 39.6 V, VSS = 0 V, GND = 0 V,
digital inputs = 0 V or 5 V
µA typ
µA max
µA typ
µA max
µA typ
µA max
220
130
90
VS = +60 V and VS = −40 V
140
230
100
150
65
110
µA typ
µA max
µA typ
µA max
µA typ
µA max
230
150
110
CONTINUOUS CURRENT PER CHANNEL, S OR D
Table 6.
Parameter
CONTINUOUS CURRENT, S OR D
θJA = 170°C/W
25°C
85°C
125°C
Unit
Test Conditions/Comments
163
151
105
99
63
61
mA max
mA max
VS = VSS to VDD − 5 V
VS = VSS to VDD − 2 V
Rev. 0 | Page 14 of 32
Data Sheet
ADG5401F
ABSOLUTE MAXIMUM RATINGS
THERMAL RESISTANCE
TA = 25°C, unless otherwise noted.
Table 7.
Parameter
VDD to VSS
VDD to GND
VSS to GND
S or SFB to GND
S or SFB to VDD
S or SFB to VSS
S to D
SFB to DFB
D or DFB1
Digital Inputs
Peak Current, S or D Pin
Continuous Current, S or D Pin
Digital Output
Temperature
Operating Range
Storage Range
Junction
Reflow Soldering Peak, Pb-Free
Value
60 V
−0.3 V to +48 V
−28 V to +0.3 V
−60 V to +60 V
80 V
80 V
80 V
80 V
VSS − 0.7 V to VDD + 0.7 V or
30 mA, whichever occurs first
GND − 0.7 V to 6 V or 30 mA,
whichever occurs first
515 mA (pulsed at 1 ms, 10%
duty cycle maximum)
Data + 15%2
GND − 0.7 V to 6 V or 30 mA,
whichever occurs first
−40°C to +125°C
−65°C to +150°C
150°C
As per JEDEC J-STD-020
Thermal performance is directly linked to printed circuit board
(PCB) design and operating environment. Careful attention to
PCB thermal design is required.
θJA is the natural convection, junction to ambient thermal
resistance measured in a one cubic foot sealed enclosure.
θJC is the junction to case thermal resistance.
Table 8. Thermal Resistance
Package Type1
CP-10-16
1
θJA
170
θJC
58.2
Unit
°C/W
Thermal impedance simulated values are based on a JEDEC 2S2P thermal
test board with four thermal vias. See JEDEC JESD-51.
ELECTROSTATIC DISCHARGE (ESD) RATINGS
The following ESD information is provided for handling of
ESD-sensitive devices in an ESD protected area only.
Human body model (HBM) per ANSI/ESDA/JEDEC JS-001.
ESD Ratings for ADG5401F
Table 9. ADG5401F, 10-Lead LFCSP
ESD Model
HBM1
Overvoltages at the D and DFB pins are clamped by internal diodes. Limit
current to the maximum ratings given.
2
See Table 6.
1
Stresses at or above those listed under Absolute Maximum
Ratings may cause permanent damage to the product. This is a
stress rating only; functional operation of the product at these
or any other conditions above those indicated in the
operational section of this specification is not implied.
Operation beyond the maximum operating conditions for
extended periods may affect product reliability.
1
Withstand Threshold (kV)
2
Class
2
This is the HBM for the input/output port to supplies, the input/output port
to input/output port, and for all other pins.
ESD CAUTION
Rev. 0 | Page 15 of 32
ADG5401F
Data Sheet
PIN CONFIGURATION AND FUNCTION DESCRIPTIONS
ADG5401F
TOP VIEW
(Not to Scale)
10 D
9
DFB
FF 3
8
IN
GND 4
7
POC
6
VSS
VDD
5
22052-003
S 1
SFB 2
Figure 2. Pin Configuration
Table 10. Pin Function Descriptions
Pin No.
1
2
3
Mnemonic
S
SFB
FF
4
5
6
7
8
9
10
GND
VDD
VSS
POC
IN
DFB
D
Description
Overvoltage Protected Source Terminal. The S pin can be an input or an output.
Overvoltage Protected Source Terminal of the Feedback Channel. The SFB pin can be an input or an output.
Fault Flag Digital Output. The FF pin is an open-drain output that requires an external pull-up resistor. This digital
output pulls low when a fault condition occurs on either the S or SFB input.
Ground (0 V) Reference.
Most Positive Power Supply Potential.
Most Negative Power Supply Potential.
Power-On Condition. The POC pin determines the power-on condition of the source pin (S).
Logic Control Input.
Drain Terminal of the Feedback Channel. The DFB pin can be an input or an output.
Drain Terminal. The D pin can be an input or an output.
Rev. 0 | Page 16 of 32
Data Sheet
ADG5401F
TYPICAL PERFORMANCE CHARACTERISTICS
10
6.4
TA = 25°C
VDD = +15V
VSS = –15V
VDD = +20V
VSS = –20V
9
+125°C
VDD = +18V
VSS = –18V
ON RESISTANCE (Ω)
6.0
VDD = +16.5V
VSS = –16.5V
5.8
VDD = +15V
VSS = –15V
5.6
VDD = +13.5V
VSS = –13.5V
5.4
8
+105°C
7
+85°C
6
+25°C
5
4
VDD = +22V
VSS = –22V
Figure 3. On Resistance as a Function of VS,VD (Dual Supply)
–5
0
5
10
VS, VD (V)
Figure 6. On Resistance as a Function of VS,VD for Different Temperatures,
±15 V Dual Supply
6.4
10
VDD = +20V
VSS = –20V
TA = 25°C
VDD = 10.8V
VSS = 0V
9
+125°C
ON RESISTANCE (Ω)
6.2
ON RESISTANCE (Ω)
–10
22052-007
VS, VD (V)
3
–15
22052-004
18
20
–40°C
12
14
16
–16
–14
–12
–10
–8
–6
–4
–2
0
2
4
6
8
10
–22
–20
–18
5.2
6.0
VDD = 12V
VSS = 0V
5.8
5.6
5.4
3
4
5
6
7
8
9
10
6
+25°C
5
11
VS, VD (V)
3
–20
22052-005
2
+85°C
–40°C
5.2
1
+105°C
7
4
VDD = 13.2V
VSS = 0V
0
8
Figure 4. On Resistance as a Function of VS,VD (12 V Single Supply)
–15
–10
–5
0
5
10
22052-008
ON RESISTANCE (Ω)
6.2
15
VS, VD (V)
Figure 7. On Resistance as a Function of VS,VD for Different Temperatures,
±20 V Dual Supply
6.4
10
VDD = 12V
VSS = 0V
TA = 25°C
9
6.2
6.0
5.8
ON RESISTANCE (Ω)
VDD = 36V
VSS = 0V
5.6
5.4
8
+105°C
7
+85°C
6
+25°C
5
4
VDD = 39.6V
VSS = 0V
0
5
10
15
20
25
30
–40°C
35
VS, VD (V)
Figure 5. On Resistance as a Function of VS,VD (36 V Single Supply)
3
22052-006
5.2
0
1
2
3
4
5
VS, VD (V)
6
7
8
9
10
22052-009
ON RESISTANCE (Ω)
+125°C
VDD = 32.4V
VSS = 0V
Figure 8. On Resistance as a Function of VS,VD for Different Temperatures,
12 V Single Supply
Rev. 0 | Page 17 of 32
ADG5401F
Data Sheet
7
10
VDD = 36V
VSS = 0V
LEAKAGE CURRENT (nA)
+105°C
+85°C
6
+25°C
5
4
20
15
30
25
VS, VD (V)
5
15
25
35
45
55
65
75
85
95 105 115 125
TEMPERATURE (°C)
Figure 12. Leakage Current vs. Temperature, 12 V Single Supply
10
12
VDD = +15V
VSS = –15V
VBIAS = +10V/–10V
6
IS, ID (ON) – –
IS (OFF) – +
ISFB (OFF) – +
ISFB, IDFB (ON) – –
IS (OFF) + –
IDFB (OFF) + –
4
2
VDD = +36V
VSS = 0V
VBIAS = +1V/–30V
10
LEAKAGE CURRENT (nA)
8
IS, ID (ON) + +
ID (OFF) – +
IDFB (OFF) – +
ISFB, IDFB (ON) + +
ID (OFF) + –
IDFB (OFF) + –
0
–2
8
IS, ID (ON) – –
IS (OFF) – +
ISFB (OFF) – +
ISFB, IDFB (ON) – –
IS (OFF) + –
IDFB (OFF) + –
6
4
IS, ID (ON) + +
ID (OFF) – +
IDFB (OFF) – +
ISFB, IDFB (ON) + +
ID (OFF) + –
IDFB (OFF) + –
2
0
0
5
15
25
35
45
55
65
75
85
95 105 115 125
TEMPERATURE (°C)
–2
22052-011
–4
0
14
VDD = +20V
VSS = –20V
VBIAS = +15V/–15V
4
D LEAKAGE CURRENT (nA)
6
35
45
55
65
75
85
95 105 115 125
VDD = +15V
VSS = –15V
12
IS, ID (ON) + +
ID (OFF) – +
IDFB (OFF) – +
ISFB, IDFB (ON) + +
ID (OFF) + –
IDFB (OFF) + –
IS, ID (ON) – –
IS (OFF) – +
ISFB (OFF) – +
ISFB, IDFB (ON) – –
IS (OFF) + –
IDFB (OFF) + –
25
Figure 13. Leakage Current vs. Temperature, 36 V Single Supply
12
8
15
TEMPERATURE (°C)
Figure 10. Leakage Current vs. Temperature, ±15 V Dual Supply
(VBIAS Is the Bias Voltage)
10
5
22052-014
LEAKAGE CURRENT (nA)
1
0
Figure 9. On Resistance as a Function of VS,VD for Different Temperatures,
36 V Single Supply
2
0
10
8
6
4
VS = –60V
VS = +60V
VSFB = –60V
VSFB = +60V
2
0
–2
–4
0
5
15
25
35
45
55
65
75
85
95 105 115 125
TEMPERATURE (°C)
–2
22052-012
LEAKAGE CURRENT (nA)
2
–1
22052-010
3
10
3
IS, ID (ON) + +
ID (OFF) – +
IDFB (OFF) – +
ISFB, IDFB (ON) + +
ID (OFF) + –
IDFB (OFF) + –
0
–40°C
5
IS, ID (ON) – –
IS (OFF) – +
ISFB (OFF) – +
ISFB, IDFB (ON) – –
IS (OFF) + –
IDFB (OFF) + –
4
22052-013
7
5
0
5
15
25
35
45
55
65
75
TEMPERATURE (°C)
85
95 105 115 125
22052-015
ON RESISTANCE (Ω)
+125°C
8
0
VDD = 12V
VSS = 0V
VBIAS = 1V/10V
6
9
Figure 14. D Leakage Current vs. Temperature During Overvoltage,
±15 V Dual Supply
Figure 11. Leakage Current vs. Temperature, ±20 V Dual Supply
Rev. 0 | Page 18 of 32
Data Sheet
14
ADG5401F
0
VDD = +20V
VSS = –20V
OFF ISOLATION (dB)
8
6
VS = –60V
VS = +60V
VSFB = –60V
VSFB = +60V
4
–60
–80
–100
–120
5
15
25
35
45
55
65
75
85
95 105 115 125
TEMPERATURE (°C)
–160
100
QINJ (pC)
–150
VS = –60V
VS = +60V
VSFB = –60V
VSFB = +60V
–350
–4
–400
–40
25
35
45
55
65
75
85
95 105 115 125
TEMPERATURE (°C)
22052-017
–2
VDD = +20V,
VSS = –20V
–30
–10
–20
0
10
20
30
40
VS (V)
Figure 19. QINJ vs. VS
Figure 16. D Leakage Current vs. Temperature During Overvoltage,
12 V Single Supply
0
8
VDD = 36V
VSS = 0V
–20
6
VDD = +15V
VSS = –15V
TA = 25°C
0.1µF DECOUPLING CAPACITORS
–40
AC PSRR (dB)
4
2
–60
–80
–100
0
–120
VS = –60V
VS = +60V
VSFB = –60V
VSFB = +60V
–2
–140
–4
0
5
15
25
35
45
55
65
75
TEMPERATURE (°C)
85
95 105 115 125
–160
100
22052-018
D LEAKAGE CURRENT (nA)
VDD = 36V,
VSS = 0V
VDD = +15V,
VSS = –15V
–250
–300
15
1G
VDD = 12V,
VSS = 0V
–200
0
5
100M
TA = 25°C
6
0
10M
–50
–100
2
1M
0
8
4
100k
Figure 18. Off Isolation vs. Frequency, ±15 V Dual Supply
VDD = 12V
VSS = 0V
10
10k
FREQUENCY (Hz)
Figure 15. D Leakage Current vs. Temperature During Overvoltage,
±20 V Dual Supply
12
1k
22052-020
0
22052-016
0
22052-019
–140
1k
10k
100k
1M
10M
100M
1G
FREQUENCY (Hz)
Figure 20. AC Power Supply Rejection Ratio (PSRR) vs. Frequency,
±15 V Dual Supply
Figure 17. D Leakage Current vs. Temperature During Overvoltage,
36 V Single Supply
Rev. 0 | Page 19 of 32
22052-021
D LEAKAGE CURRENT (nA)
–40
10
2
D LEAKAGE CURRENT (nA)
VDD = +15V
VSS = –15V
TA = 25°C
–20
12
ADG5401F
0.005
Data Sheet
0.80
RL = 10kΩ
TA = 25°C
VDD = +15V
VSS = –15V
0.75
0.004
0.65
0.003
VT (V)
THD + N (%)
0.70
SINGLE SUPPLY = 12V
0.002
0.60
0.55
DUAL SUPPLY = ±20V
DUAL SUPPLY = ±15V
0.50
0.001
0.45
0
2k
4k
6k
8k
10k
12k
14k
16k
18k
0.40
–40
22052-022
0
20k
FREQUENCY (Hz)
–20
0
20
40
60
80
100
22052-025
SINGLE SUPPLY = 36V
120
TEMPERATURE (°C)
Figure 21. THD + N vs. Frequency
Figure 24. VT vs. Temperature, ±15 V Dual Supply
0
40
–1
35
–2
30
S OFF
SFB OFF
D OFF
PIN CAPACITANCE (pF)
–3
–4
–5
–6
25
20
15
10
VDD = +15V
VSS = –15V
TA = 25°C
–8
100
5
1k
100k
10k
1M
10M
100M
1G
FREQUENCY (Hz)
0
–15
22052-023
–7
S TO D ON
–10
–5
0
5
10
15
VS (V)
Figure 22. Insertion Loss vs. Frequency
Figure 25. Pin Capacitance vs. VS
18
VDD = +15V
VSS = –15V
16
T
S
12
tON (±15V)
tOFF (±15V)
tON (±20V)
tON (+36V)
tOFF (+36V)
tOFF (±20V)
tON (+12V)
tOFF (+12V)
FF
3
D
10
1
2
8
6
4
0
–40
–20
0
20
40
60
80
100
120
TEMPERATURE (°C)
CH1 10.0V
CH3 5.00V
CH2 10.0V
M800ns
A CH1
T
0.000000s
3.60V
Figure 26. Drain Output Response to Positive Overvoltage
Figure 23. tON, tOFF Times vs. Temperature for Various Supplies
Rev. 0 | Page 20 of 32
22052-027
2
22052-024
tON, tOFF TIMES (µs)
14
22052-026
INSERTION LOSS (dB)
S TO D AND SFB TO DFB ON
Data Sheet
ADG5401F
20
LARGE VOLTAGE SIGNAL VOLTAGE (V p-p)
T
FF
3
1
2
D
S
VDD = +10V
VSS = –10V
16
12
8
4
0
CH2 10.0V
M2.00µs
A CH1
T
0.000000s
–10.6V
1
22052-028
CH1 10.0V
CH3 5.00V
10
FREQUENCY (MHz)
Figure 27. Drain Output Response to Negative Overvoltage
Figure 28. Large Voltage Signal Voltage vs. Frequency
Rev. 0 | Page 21 of 32
100
22052-029
VDD = +15V
VSS = –15V
ADG5401F
Data Sheet
TEST CIRCUITS
V
ID
IS
D
S
A
VS
22052-031
IDS
RON = V/IDS
D
A
RL
10kΩ
|VS| > |VDD| OR |VSS|
22052-034
S
Figure 32. Switch Overvoltage Leakage
Figure 29. On Resistance (IDS Is the Drain to Source Current.)
VDD = VSS = GND = 0V
A
A
VS
VD
ID
S
Figure 33. Switch Unpowered Leakage
ID (ON)
S
D
NC = NO CONNECT
A
22052-033
VD
Figure 31. On Leakage
VDD
VSS
0.1µF
0.1µF
VDD
NETWORK
ANALYZER
VSS
50Ω
S
IN
VS
VIN
RL
50Ω
GND
VOUT
OFF ISOLATION = 20 log
VOUT
VS
22052-044
D
Figure 34. Off Isolation (VOUT Is the Output Voltage)
VDD
VSS
0.1µF
0.1µF
VDD
NETWORK
ANALYZER
VSS
50Ω
S
IN
VS
D
VIN
RL
50Ω
GND
INSERTION LOSS = 20 log
VOUT
VOUT WITH SWITCH
VOUT WITHOUT SWITCH
Figure 35. Bandwidth
Rev. 0 | Page 22 of 32
22052-046
NC
A
RL
10kΩ
VS
Figure 30. Off Leakage
D
22052-035
IS
D
S
A
ID (OFF)
22052-032
IS (OFF)
Data Sheet
ADG5401F
VDD
VSS
0.1µF
0.1µF
VDD
AUDIO
PRECISION
VSS
RS
S
VS
V p-p
IN
D
VIN
VOUT
RL
10kΩ
22052-047
GND
Figure 36. THD + N
VDD
VSS
0.1µF
VDD + 0.5V
0.1µF
VDD
SOURCE
VOLTAGE
(+VS)
VSS
S
VD
D
CL*
5pF
VS
0V
ADG5401F
OUTPUT
(VD)
VDD
VDD × 0.5
GND
22052-138
+tRESPONSE
RL
1kΩ
0V
*INCLUDES TRACK CAPACITANCE
Figure 37. Overvoltage Response Time, tRESPONSE
VDD
SOURCE
VOLTAGE
(VS)
0V
VSS
0.1µF
0.1µF
5V
VSS – 0.5V
VDD
RPULLUP
1kΩ
VSS
S
VD
D
VS
ADG5401F
CL*
5pF
tRESPONSE
5V
*INCLUDES TRACK CAPACITANCE
Figure 38. Negative Overvoltage Response Time, Single-Supply, tRESPONSE
Rev. 0 | Page 23 of 32
22052-150
GND
OUTPUT
(VD) + 1V
ADG5401F
Data Sheet
VDD
VSS
0.1µF
0.1µF
VDD + 0.5V
VDD
SOURCE
VOLTAGE
(VS)
VSS
S
VD
D
CL*
5pF
VS
0V
ADG5401F
RL
1kΩ
tRECOVERY
OUTPUT
(VD)
1V
0V
22052-139
GND
*INCLUDES TRACK CAPACITANCE
Figure 39. Overvoltage Recovery Time, tRECOVERY
VDD
VSS
0.1µF
0.1µF
VDD + 0.5V
VSS
VDD
SOURCE
VOLTAGE
(VS)
S
D
VS
0V
5V
ADG5401F
RPULLUP
1kΩ
tDIGRESP
OUTPUT
FF
CL*
12pF
OUTPUT
(VFF)
GND
0V
22052-140
0.1VOUT
*INCLUDES TRACK CAPACITANCE
Figure 40. Interrupt Flag Response Time, tDIGRESP (VFF Is the Fault Flag Voltage)
VDD
VSS
0.1µF
VDD + 0.5V
0.1µF
VSS
VDD
SOURCE
VOLTAGE
(VS)
S
D
VS
5V
0V
ADG5401F
RPULLUP
1kΩ
tDIGREC
CL*
12pF
3V
GND
0V
*INCLUDES TRACK CAPACITANCE
Figure 41. Interrupt Flag Recovery Time, tDIGREC
Rev. 0 | Page 24 of 32
22052-141
OUTPUT
(VFF)
OUTPUT
FF
5V
Data Sheet
ADG5401F
VDD
VSS
0.1µF
0.1µF
ADG5401F
VIN
VOUT
D
CL
35pF
RL
300Ω
IN
90%
VOUT
10%
GND
22052-042
S
VS
50%
50%
VSS
VDD
tOFF
tON
Figure 42. Switching Times, tON and tOFF
RS
VS
VDD
VSS
VDD
VSS
S
D
0.1µF
ADG5401F
VOUT
VIN
OFF
ON
CL
1nF
IN
VOUT
GND
QINJ = CL × ΔVOUT
ΔVOUT
22052-043
0.1µF
Figure 43. Charge Injection, QINJ
Rev. 0 | Page 25 of 32
ADG5401F
Data Sheet
TERMINOLOGY
tOFF
tOFF represents the delay between applying the digital control
input and the output switching off (see Figure 42).
IDD
IDD represents the positive supply current.
ISS
ISS represents the negative supply current.
VD, VS
VD and VS represent the analog voltage on the D and DFB pins
and the S and SFB pins, respectively.
RON
RON represents the ohmic resistance between the D and DFB
pins and the S and SFB pins.
RFLAT (ON)
RFLAT (ON) is the flatness that is defined as the difference between
the maximum and minimum value of on resistance measured
over the specified analog signal range.
IS (Off)
IS (Off) is the source leakage current with the switch off.
tDIGRESP
tDIGRESP is the time required for the FF pin to go low (0.3 V),
measured with respect to voltage on the source pin exceeding
the supply voltage by 0.5 V.
tDIGREC
tDIGREC is the time required for the FF pin to return high,
measured with respect to voltage on the S pin falling below the
supply voltage plus 0.5 V.
tRESPONSE
tRESPONSE represents the delay between the source voltage
exceeding the supply voltage by 0.5 V and the drain voltage
falling to 90% of the supply voltage.
ID (Off)
ID (Off) is the drain leakage current with the switch off.
tRECOVERY
tRECOVERY represents the delay between an overvoltage on the
S pin falling below the supply voltage plus 0.5 V and the drain
voltage rising from 0 V to 10% of the supply voltage.
ID (On), IS (On)
ID (On) and IS (On) represent the channel leakage currents with
the switch on.
Off Isolation
Off isolation is a measure of unwanted signal coupling through
an off switch.
VINL
VINL is the maximum input voltage for Logic 0.
Charge Injection
Charge injection is a measure of the glitch impulse transferred
from the digital input to the analog output during switching.
VINH
VINH is the minimum input voltage for Logic 1.
IINL, IINH
IINL and IINH represent the low and high input currents of the
digital inputs.
−3 dB Bandwidth
Bandwidth is the frequency at which the output is attenuated
by 3 dB.
On Response
On response is the frequency response of the on switch.
CD (Off)
CD (Off) represents the off switch D pin capacitance, which is
measured with reference to ground.
Insertion Loss
Insertion loss is the loss due to the on resistance of the switch.
CS (Off)
CS (Off) represents the off switch S pin capacitance, which is
measured with reference to ground.
THD + N
THD + N is the ratio of the harmonic amplitude plus noise of
the signal to the fundamental.
CD (On), CS (On)
CD (On) and CS (On) represent on switch capacitances, which
are measured with reference to ground.
AC Power Supply Rejection Ratio (AC PSRR)
AC PSRR is the ratio of the amplitude of signal on the output to
the amplitude of the modulation. AC PSRR is a measure of the
ability of the device to avoid coupling noise and spurious
signals that appear on the supply voltage pin to the output of the
switch. The dc voltage on the device is modulated by a sine wave
of 0.62 V p-p.
CIN
CIN is the digital input capacitance.
tON
tON represents the delay between applying the digital control
input and the output switching on (see Figure 42).
VT
VT is the voltage threshold at which the overvoltage protection
circuitry engages (see Figure 24).
Rev. 0 | Page 26 of 32
Data Sheet
ADG5401F
THEORY OF OPERATION
The ADG5401F consists of two switch channels of N channel
diffused metal-oxide semiconductor (NDMOS) transistors, a
main channel switch and a secondary feedback channel switch.
This construction provides excellent RON performance in a
small area. The ADG5401F main channel operates as a standard
switch when input signals with a voltage between VSS and
VDD − 2 V are applied. For example, the on resistance is 6 Ω
typically, and the IN pin controls when the switch opens or
closes. The secondary switch channel on resistance is 0.6 kΩ.
The IN pin controls when both switches open or close.
Additional internal circuitry enables the switches to detect
overvoltage inputs by comparing the voltage on both the S
and SFB pins with the VDD and VSS pins. A signal is considered
overvoltage when the signal exceeds the supply voltages by VT.
VT is typically 0.7 V but can range from 0.76 V at −40°C down
to 0.5 V at +125°C. See Figure 24 to see the change in VT with
the operating temperature.
When an overvoltage condition is detected on either the S or
SFB pin, both switches automatically open regardless of the
digital logic state (IN). The S to D and SFB to DFB pins become
high impedance and ensure that no current flows through
the switches. In Figure 26, the voltage on the D pin follows the
voltage on the S pin until the main channel switch turns off
completely and the drain voltage discharges through the load.
The maximum voltage on the drain is limited by the internal
ESD diodes, and the rate at which the output voltage discharges
is dependent on the load at the D pin.
The maximum voltage that can be applied to any source input
is +60 V or −60 V. When the ADG5401F is powered using a
single supply of 25 V or greater, the maximum negative signal
level reduces to remain within the 80 V maximum rating. For
example, at VDD = +40 V, the maximum negative signal drops
from −60 V to −40 V. Construction of the process allows the
channel to withstand 80 V across either switch when the
switches are open. Note that these overvoltage limits apply
whether the power supplies are present or not.
During overvoltage conditions, the leakage current into and out
of the S and SFB pins is limited to tens of microamperes and
only nanoamperes for the D and DFB pins. This limit protects
the switches and connected circuitry from overstresses and
restricts the current drawn from the signal source.
ESD Performance
The ADG5401F has an ESD rating of 2 kV for the HBM.
The D and DFB pins have ESD protection diodes to the rails
and the voltage at these pins must not exceed the supply
voltage. The S and SFB pins have specialized ESD protection
that allow the signal voltage to reach ±60 V regardless of the
supply voltage level. See Figure 44 for the switch channel
overview.
VDD
ESD
PROTECTION
ESD
DIODE
S
D
ESD
DIODE
FAULT
DETECTOR
SWITCH
DRIVER
VSS
22052-002
SWITCH ARCHITECTURE
AND
IN
Figure 44. Switch Channel and Control Function
Trench Isolation
In the ADG5401F, an insulating oxide layer (trench) is placed
between the N channel DMOS and the P channel DMOS
(PDMOS) transistors in the circuit. Parasitic junctions that
occur between the transistors in the junction isolated switches
are eliminated, and the result is a switch that is latch-up
immune under all circumstances. These devices pass the
JESD78D latch-up test.
NDMOS
PDMOS
P WELL
N WELL
TRENCH
HANDLE WAFER
Figure 45. Trench Isolation
Rev. 0 | Page 27 of 32
22052-049
BURIED OXIDE LAYER
ADG5401F
Data Sheet
OVERVOLTAGE FAULT PROTECTION
When the voltage at the S or SFB input exceeds VDD or VSS
by VT, the switches turn off or, if the device is unpowered, the
switches remain off. Both switch inputs remain high impedance
regardless of the digital input state or the load resistance, and
the output acts as a virtual open circuit. Signal levels up to +60 V
and −60 V are blocked in both the powered and unpowered
condition as long as the +80 V absolute maximum rating
limitation between the S or SFB pin and VDD or VSS pin is
met. For example with a +40 V single supply, the overvoltage
protection is +60 V and −40 V (see Figure 46).
VDD
The switches respond to a voltage on either the S pin or the SFB
pin that exceeds VDD or VSS by VT by turning off. The absolute
input voltage limits are −60 V and +60 V, while maintaining an
80 V limit between the S or SFB pin and the supply rails. The
switches remain off until the voltage at the S and SFB pins
return to between VDD and VSS.
When powered by the ±15 V dual supply, the positive overvoltage
response time (tRESPONSE) is typically 230 ns, and tRECOVERY is 11.7 µs.
These values vary with different supply voltage and output load
conditions.
Exceeding ±60 V on either the S or SFB input may damage the
ESD protection circuitry on the ADG5401F.
Power Off Protection
When no power supplies are present, the switches remain in an
off state and the switch inputs are high impedance. This state
ensures that no current flows and prevents damage to the
switches or downstream circuitry. The switch outputs are a
virtual open circuit.
80V
ADG5401F
S
D
80V
22052-151
The switches remain off regardless of whether the VDD and VSS
supplies are 0 V or floating. A GND reference must always be
present to ensure proper operation. Signal levels of up to ±60 V
are blocked when powered off.
VSS
Figure 46. S or SFB to VDD or VSS Maximum Rating
Power-On Protection
Overvoltage Interrupt Flag
To activate the switches, the three following conditions must be
meet:
The voltages on the S and SFB inputs of the ADG5401F are
continuously monitored, and the active low digital output pin,
FF, indicates the fault state.
•
•
•
The minimum supply operating conditions in Table 1.
The input signal must be between VSS − VT and VDD + VT.
The digital logic control input, IN, is on.
When the switches are on, signal levels from VSS up to VDD − 2 V
are passed.
The voltage on the FF pin indicates if either the S or SFB input
pin is experiencing a fault condition. The FF pin is an opendrain output that requires an external pull-up resistor. The
output of the FF pin is high when both the S and SFB pins are
within the normal operating range. If either the S or SFB pin
voltage exceeds the supply voltage (VDD or VSS) by VT, the FF
output provides a low impedance path to GND.
Rev. 0 | Page 28 of 32
Data Sheet
ADG5401F
APPLICATIONS INFORMATION
The ADG5401F overvoltage protected switches provide a
robust solution for instrumentation, industrial, aerospace, and
other harsh environments where overvoltage signals can be
present, and the system must remain operational both during
and after an overvoltage occurs.
POWER SUPPLY RAILS
To guarantee correct operation of the device, 0.1 µF decoupling
capacitors are required on both VDD and VSS to GND.
The ADG5401F can operate with bipolar supplies between ±5 V
and ±22 V. Note that the VDD and VSS supplies do not have to be
symmetrical, but the supply range must not exceed 44 V. The
ADG5401F can also operate with single supplies between 8 V
and 44 V with VSS connected to GND.
The ADG5401F is fully specified at the ±15 V, ±20 V, +12 V,
and +36 V supply ranges.
POWER SUPPLY RECOMMENDATIONS
Analog Devices, Inc., has a wide range of power management
products to meet the requirements of most high performance
signal chains.
An example of a bipolar power solution is shown in Figure 47.
The ADP5070 (dual switching regulator) generates a positive and
negative supply rail for the ADG5401F amplifier and/or a
precision converter in a typical signal chain. Also shown in
Figure 47 are two optional LDOs, ADP7118 and ADP7182,
positive and negative low dropout regulators (LDOs), respectively,
that can be used to reduce the output ripple of the ADP5070 in
ultralow noise sensitive applications.
+5V
INPUT
ADP7118
LDO
+15V
ADP5070
–16.5V
ADP7182
LDO
–15V
22052-147
+16.5V
Figure 47. Bipolar Power Solution
Table 11. Recommended Power Management Devices
Product
ADP5070
ADP7118
ADP7182
Description
1 A/0.6 A, dc-to-dc switching regulator with
independent positive and negative outputs
20 V, 200 mA, low noise, CMOS LDO linear regulator
−28 V, −200 mA, low noise, LDO linear regulator
POWER SUPPLY SEQUENCING PROTECTION
When the device is off, the switch channels remain open and the
signals from −60 V to +60 V can be applied without damaging the
device. The switch channels only close when the supplies are
connected, a suitable digital control signal is placed on the IN
pin, and the signal is within the normal operating range. Note
that placing the ADG5401F between external connectors and
sensitive components offers protection in systems where a signal
is presented to the S or SFB pin before the supply voltages are
available.
SIGNAL RANGE
The ADG5401F switches have overvoltage detection circuitry on
the S and SFB pins that compares the voltage levels with VDD
and VSS. To protect downstream circuitry from overvoltages,
supply the ADG5401F with voltages that match the intended
signal range. The NDMOS only architecture used in the
switches allows signals up to VDD − 2 V to be passed with little
distortion. A signal that exceeds the supply rail by VT is then
blocked. This signal block offers protection to both the device
and any downstream circuitry.
LOW IMPEDANCE OUTPUT CHANNEL
PROTECTION
The ADG5401F can be used as a protective element in signal
chain outputs that are sensitive to both channel impedance and
overvoltage signals. Traditionally, series resistors are used to
limit the current during an overvoltage condition to protect
susceptible components.
These series resistors affect the performance of the signal chain
and reduce the precision that can be reached. A compromise
must be reached on the value of the series resistance that is high
enough to sufficiently protect sensitive components but low
enough that the precision performance of the signal chain is
not sacrificed.
The ADG5401F enables the designer to remove these resistors
and retain the precision performance without compromising
the protection of the circuit.
Rev. 0 | Page 29 of 32
ADG5401F
Data Sheet
INTELLIGENT FAULT DETECTION
The ADG5401F digital output pin (FF) can interface with a
microprocessor or control system and be used as an interrupt
flag. This feature provides real-time diagnostic information on
the state of the device and the system to which the device connects.
The control system can use the digital interrupt to start a
variety of actions, such as the following:
•
•
•
Initiating investigation into the source of the overvoltage fault
Shutting down critical systems in response to the overvoltage
Data recorders marking data during these events as
unreliable or out of specification
For systems that are sensitive during a start-up sequence, the
active low operation of the flag allows the system to ensure that
the ADG5401F powers on and that all input voltages are within
the normal operating range before initiating operation.
The FF pin is an open drain that requires an external pull-up
resistor, which allows signals to be combined into a single
interrupt for larger modules that contain multiple devices.
LARGE VOLTAGE, HIGH FREQUENCY SIGNALS
Figure 28 illustrates the voltage range and frequencies that the
ADG5401F can reliably convey. For signals that extend across
the full signal range from VSS to VDD − 2 V, keep the frequency
below 2.5 MHz. If the required frequency is greater than
2.5 MHz, decrease the signal range appropriately to ensure
signal integrity.
The secondary feedback channel is also protected from overvoltages to ±60 V and is controlled by the same switch driver
as the main switch channel. If a fault is detected on either the
source (S) or source feedback (SFB) pin, both the main switch
channel and the feedback channel open, protecting both the
amplifier output node and the negative input of the amplifier.
For optimal performance, it is recommended to keep the
maximum voltage differential between the S and SFB pins
to less than 1 V.
If the secondary feedback channel is not required, it is recommended to short the S pin to the SFB pin and the D pin to the
DFB pin.
OPEN-LOOP PREVENTION
The open-loop prevention feature is an internal switch in the
ADG5401F. When the main switch is disabled, this switch
connects the drain (D) of the main switch and the drain of the
feedback switch (DFB) (see Figure 49). This internal open-loop
prevention switch opens and closes automatically when the
main channel switch toggles. This feature stabilizes an amplifier
output by preventing the amplifier from going into an openloop configuration. When the main switch disables in normal
operation or in a fault condition, the open-loop prevention
switch activates. Note that the open-loop prevention switch is
identical to the feedback channel switch.
ADG5401F
AD5423
VIOUT
D
S
VOUT/IOUT
AMPLIFIER OR DAC OUTPUT PROTECTION
ADG5401F
ADA4625-1
D
S
VOUT/IOUT
POC
IN
SFB
FF
SECONDARY FEEDBACK CHANNEL
22052-149
DFB
Figure 48. Amplifier Output Protection
Rev. 0 | Page 30 of 32
+VSENSE
DFB
SFB
OPEN-LOOP
PREVENTION SWITCH
1kΩ FEEDBACK CHANNEL
FOR DAC/AMP APPLICATIONS
Figure 49. Open-Loop Prevention Feature
22052-050
The ADG5401F has a secondary feedback channel for protecting
the amplifier outputs or DAC outputs. The feedback channel
is connected between the drain feedback pin (DFB) and the
source feedback pin (SFB). This feedback channel has a typical
resistance of 0.6 kΩ and can close the feedback loop of an
amplifier output or a DAC output (see Figure 48). This
feedback loop removes any output error caused by the
main channel on resistance.
Data Sheet
ADG5401F
POWER-ON CONDITION
HIGH VOLTAGE SURGE SUPPRESSION
The power-on condition feature is a user configurable switch
that pulls the source (S) of the switch to ground through a
30 kΩ resistor when the switch is disabled and no fault is
present. This feature is enabled with a Logic 0 on the POC pin
and disabled with either 5 V on the POC pin or by floating the
POC pin.
To achieve protection from high voltage transients, such as
IEC 61000-4-2 ESD, IEC 61000-4-4 electrical fast transient
(EFT), and IEC 61000-4-5 surge, implement the circuit shown
in Figure 51 by using discrete resistors and a transient voltage
suppression (TVS) device. Place the resistors inside the
feedback loop of the system so that the resistors do not add any
error to the system output.
ADG5401F
AD5423
D
VIOUT
S
ADG5401F
VOUT/IOUT
D
40Ω
FF
EN
DFB
VOUT/IOUT
47pF
4.7nF
60V
TVS
POC
SFB
22052-051
+VSENSE
S
DFB
SFB
1kΩ
FF
IN
22052-052
Figure 50. DAC Output Protection
Table 12 details the switch source state when the POC pin is
enabled.
Figure 51. High Voltage Transient Protection
Table 12. Switch Source (S) State with POC Enabled
Condition
Switch Disabled, EN = 0
Switch Enabled, EN = 1
Fault On the Output
Switch Powering Up
Switch Source (S)
S connected to GND through POC
switch (30 kΩ)
Connected to D, switch closed
Switch open, fault flag asserted
S connected to GND through POC
switch (30 kΩ)
SWITCHES IN A KNOWN STATE
If no digital inputs are present on the switch control line (IN),
the switches remain in an off state, which prevents unwanted
signals passing through the switches.
Table 13 details the results achieved by using the discrete
protection circuit shown in Figure 51. To replicate the harshest
environments , the surge test was performed by zapping the
S pin directly through a 40 Ω resistor and a 0.5 µF capacitor
coupling network. The EFT test was performed by zapping the
S pin directly without any capacitive coupling through cables.
Table 13. High Voltage Transient Protection
IEC 61000-4 Transient
ESD (Contact)
EFT
Surge
Rev. 0 | Page 31 of 32
Protection Level (kV)
±6
±4
±4
ADG5401F
Data Sheet
OUTLINE DIMENSIONS
3.10
3.00
2.90
0.30
0.25
0.20
0.50 BSC
6
2.10
2.00
1.90
0.45
0.40
0.35
1
5
BOTTOM VIEW
TOP VIEW
PKG-005693
0.80
0.75
0.70
SIDE VIEW
SEATING
PLANE
0.55
BSC
PIN 1
INDICATOR
0.050 MAX
0.035 NOM
COPLANARITY
0.08
0.203 REF
01-15-2018-A
PIN 1
CORNER
10
Figure 52. 10-Lead Lead Frame Chip Scale Package [LFCSP]
3 mm × 2 mm Body and 0.75 mm Package Height
(CP-10-16)
Dimensions shown in millimeters
ORDERING GUIDE
Model1
ADG5401FBCPZ-RL7
EVAL-ADG5401FEBZ
1
Temperature Range
−40°C to +125°C
Package Description
10-Lead Lead Frame Chip Scale Package [LFCSP]
Evaluation Board
Z = RoHS Compliant Part.
©2020 Analog Devices, Inc. All rights reserved. Trademarks and
registered trademarks are the property of their respective owners.
D22052-8/20(0)
Rev. 0 | Page 32 of 32
Package Option
CP-10-16
