FEATURES
FUNCTIONAL BLOCK DIAGRAMS
Overvoltage protection up to −55 V and +55 V
Power-off protection up to −55 V and +55 V
Overvoltage detection on source and drain pins
Low on resistance: 10 Ω
On-resistance flatness of 0.5 Ω
3 kV human body model (HBM) ESD rating
Latch-up immune under any circumstance
Known state without digital inputs present
VSS to VDD analog signal range
±5 V to ±22 V dual-supply operation
8 V to 44 V single-supply operation
Fully specified at ±15 V, ±20 V, +12 V, and +36 V
ADG5412BF
S1
D1
S2
D2
S3
D3
S4
D4
FAULT
DETECTION
+ SWITCH
DRIVER
FF
IN1 IN2 IN3 IN4
NOTES
1. SWITCHES SHOWN FOR A LOGIC 1 INPUT.
12473-001
Data Sheet
Bidirectional Fault Protection and
Detection, 10 Ω RON, Quad SPST Switches
ADG5412BF/ADG5413BF
Figure 1. ADG5412BF
APPLICATIONS
ADG5413BF
S1
D1
S2
D2
S3
D3
S4
D4
FAULT
DETECTION
+ SWITCH
DRIVER
FF
IN1 IN2 IN3 IN4
NOTES
1. SWITCHES SHOWN FOR A LOGIC 1 INPUT.
12473-200
Analog input/output modules
Process control/distributed control systems
Data acquisition
Instrumentation
Avionics
Automatic test equipment
Communication systems
Relay replacement
Figure 2. ADG5413BF
GENERAL DESCRIPTION
The ADG5412BF and ADG5413BF contain four independently
controlled single-pole/single-throw (SPST) switches. The
ADG5412BF has four switches that turn on with Logic 1 inputs.
The ADG5413BF has two switches that turn on and two switches
that turn off with Logic 1 inputs. Each switch conducts equally
well in both directions when on, and each switch has an input
signal range that extends to the supplies. The digital inputs are
compatible with 3 V logic inputs over the full operating supply
range.
The low on resistance of these switches, combined with onresistance flatness over a significant portion of the signal range
make them an ideal solution for data acquisition and gain switching
applications where excellent linearity and low distortion are critical.
When no power supplies are present, the switch remains in the
off condition, and the switch inputs are high impedance. Under
normal operating conditions, if the analog input signal levels on
any switch pin exceed VDD or VSS by a threshold voltage, VT, the
switch turns off. Input signal levels up to +55 V and −55 V relative
to ground are blocked, in both the powered and unpowered
condition.
3.
Rev. B
PRODUCT HIGHLIGHTS
1.
2.
4.
5.
6.
Switch pins are protected against voltages greater than the
supply rails, up to −55 V and +55 V.
Switch pins are protected against voltages between −55 V
and +55 V, in an unpowered state.
Overvoltage detection with digital output indicates
operating state of switches.
Trench isolation guards against latch-up.
Optimized for low on resistance and on-resistance flatness.
The ADG5412BF/ADG5413BF can be operated from a
dual-supply of ±5 V up to ±22 V or a single power supply
of 8 V up to 44 V.
Document Feedback
Information furnished by Analog Devices is believed to be accurate and reliable. However, no
responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other
rights of third parties that may result from its use. Specifications subject to change without notice. No
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
Trademarks and registered trademarks are the property of their respective owners.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700 ©2014–2016 Analog Devices, Inc. All rights reserved.
Technical Support
www.analog.com
ADG5412BF/ADG5413BF
Data Sheet
TABLE OF CONTENTS
Features .............................................................................................. 1
Test Circuits ..................................................................................... 19
Applications ....................................................................................... 1
Terminology .................................................................................... 23
Functional Block Diagrams ............................................................. 1
Theory of Operation ...................................................................... 25
General Description ......................................................................... 1
Switch Architecture .................................................................... 25
Product Highlights ........................................................................... 1
Fault Protection .......................................................................... 26
Revision History ............................................................................... 2
Applications Information .............................................................. 27
Specifications..................................................................................... 3
Power Supply Rails ..................................................................... 27
±15 V Dual-Supply ....................................................................... 3
Power Supply Sequencing Protection ...................................... 27
±20 V Dual-Supply ....................................................................... 5
Signal Range ................................................................................ 27
12 V Single-Supply ....................................................................... 7
Low Impedance Channel Protection ....................................... 27
36 V Single-Supply ....................................................................... 9
High Voltage Surge Suppression .............................................. 27
Continuous Current per Channel, Sx or Dx ........................... 11
Intelligent Fault Detection ........................................................ 27
Absolute Maximum Ratings.......................................................... 12
Large Voltage, High Frequency Signals ................................... 27
ESD Caution ................................................................................ 12
Outline Dimensions ....................................................................... 28
Pin Configuration and Function Descriptions ........................... 13
Ordering Guide .......................................................................... 28
Typical Performance Characteristics ........................................... 14
REVISION HISTORY
1/16—Rev. A to Rev. B
Changes to Table 1 ............................................................................ 3
Changes to Table 2 ............................................................................ 5
Changes to Table 3 ............................................................................ 7
Changes to Table 4 ............................................................................ 9
Changes to Switch Architecture Section ..................................... 25
3/15—Rev. 0 to Rev. A
Added LFCSP Package ....................................................... Universal
Changes to Output Leakage Current, IS or ID/With Overvoltage
Parameter, Table 3............................................................................. 7
Changes to Output Leakage Current, IS or ID/With Overvoltage
Parameter, Table 4............................................................................. 9
Changes to Table 6.......................................................................... 12
Added Figure 4, Renumbered Sequentially ................................ 13
Changes to Table 7.......................................................................... 13
Changes to Figure 35...................................................................... 19
Changes to Figure 50...................................................................... 25
Changes to Applications Information Section ........................... 27
Updated Outline Dimensions ....................................................... 28
Changes to Ordering Guide .......................................................... 28
7/14—Revision 0: Initial Version
Rev. B | Page 2 of 28
Data Sheet
ADG5412BF/ADG5413BF
SPECIFICATIONS
±15 V DUAL-SUPPLY
VDD = 15 V ± 10%, VSS = −15 V ± 10%, GND = 0 V, CDECOUPLING = 0.1 μF, unless otherwise noted.
Table 1.
Parameter
ANALOG SWITCH
Analog Signal Range
On Resistance, RON
On-Resistance Match Between Channels, ∆RON
On-Resistance Flatness, RFLAT(ON)
Threshold Voltage, VT
LEAKAGE CURRENTS
Source Off Leakage, IS (Off )
Drain Off Leakage, ID (Off )
Channel On Leakage, ID (On), IS (On)
+25°C
−40°C to
+85°C
VDD to VSS
10
11.2
9.5
10.7
0.05
0.5
0.05
0.35
0.6
0.9
0.1
0.4
0.7
±0.1
±1.5
±0.1
±1.5
±0.3
±2.0
14
16.5
13.5
16
0.6
0.7
0.5
0.5
1.1
1.1
0.5
0.5
V
Ω typ
Ω max
Ω typ
Ω max
Ω typ
Ω max
Ω typ
Ω max
Ω typ
Ω max
Ω typ
Ω max
V typ
±24
±5.5
±20
±2.5
±5.5
nA typ
nA max
nA typ
nA max
nA typ
nA max
±78
μA typ
±40
μA typ
Power Supplies Grounded or Floating
Output Leakage Current, IS or ID
With Overvoltage
±20
±200
±10
±250
Power Supplies Grounded
Power Supplies Floating
±30
±10
±50
±10
nA typ
±250
nA max
nA typ
±100
±10
nA max
μA typ
2.0
0.8
V min
V max
μA typ
μA max
pF typ
±0.7
±1.2
Digital Input Capacitance, CIN
Unit
±5.5
FAULT
Input Leakage Current, IS or ID
With Overvoltage
DIGITAL INPUTS/OUTPUTS
Input Voltage
High, VINH
Low, VINL
Input Current, IINL or IINH
−40°C to
+125°C
5.0
Rev. B | Page 3 of 28
Test Conditions/Comments
VDD = 13.5 V, VSS = −13.5 V, see Figure 32
VS = ±10 V, IS = −10 mA
VS = ±9 V, IS = −10 mA
VS = ±10 V, IS = −10 mA
VS = ±9 V, IS = −10 mA
VS = ±10 V, IS = −10 mA
VS = ±9 V, IS = −10 mA
See Figure 28
VDD = 16.5 V, VSS = −16.5 V
VS = ±10 V, VD = ∓10 V, see Figure 33
VS = ±10 V, VD = ∓10 V, see Figure 33
VS = VD = ±10 V, see Figure 34
VDD = 16.5 V, VSS = 16.5 V, GND = 0 V, VS
or VD = ±55 V, see Figure 37
VDD = 0 V or floating, VSS = 0 V or
floating, GND = 0 V, INx = 0 V or
floating, VS or VD = ±55 V, see Figure 38
VDD = 16.5 V, VSS = 16.5 V, GND = 0 V, VS
or VD = ±55 V, see Figure 37
VDD = 0 V, VSS = 0 V, GND = 0 V, VS or VD =
±55 V, INx = 0 V, see Figure 38
VDD = floating, VSS = floating, GND = 0 V,
VS or VD = ±55 V, INx = 0 V, see Figure 38
VIN = VGND or VDD
ADG5412BF/ADG5413BF
Parameter
Output Voltage
High, VOH
Low, VOL
DYNAMIC CHARACTERISTICS1
tON
tOFF
Break-Before-Make Time Delay, tD
(ADG5413BF Only)
Data Sheet
+25°C
−40°C to
+85°C
−40°C to
+125°C
525
550
545
555
2.0
0.8
400
495
410
510
285
185
Overvoltage Response Time, tRESPONSE
Overvoltage Recovery Time, tRECOVERY
Interrupt Flag Response Time, tDIGRESP
Interrupt Flag Recovery Time, tDIGREC
615
630
1050
1100
115
85
Test Conditions/Comments
ns typ
ns max
ns typ
ns max
ns typ
RL = 300 Ω, CL = 35 pF
VS = 10 V, see Figure 47
RL = 300 Ω, CL = 35 pF
VS = 10 V, see Figure 47
RL = 300 Ω, CL = 35 pF
ns min
ns typ
ns max
ns typ
ns max
ns typ
μs typ
ns typ
VS1 = VS2 = 10 V, see Figure 46
RL = 1 kΩ, CL = 2 pF, see Figure 41
Charge Injection, QINJ
Off Isolation
−680
−70
pC typ
dB typ
Channel-to-Channel Crosstalk
−90
dB typ
Total Harmonic Distortion Plus Noise, THD + N
0.0015
% typ
−3 dB Bandwidth
Insertion Loss
270
−0.72
MHz typ
dB typ
13
12
24
pF typ
pF typ
pF typ
CS (Off )
CD (Off )
CD (On), CS (On)
POWER REQUIREMENTS
Normal Mode
IDD
IGND
ISS
Fault Mode
IDD
IGND
ISS
VDD/VSS
1
460
585
720
930
85
60
600
Unit
V min
V min
V max
0.9
1.2
0.4
0.55
0.5
0.65
1.3
0.6
0.7
RL = 1 kΩ, CL = 2 pF, see Figure 42
CL = 10 pF, see Figure 43
CL = 10 pF, see Figure 44
CL = 10 pF, RPULLUP = 1 kΩ, see
Figure 45
VS = 0 V, RS = 0 Ω, CL = 1 nF, see Figure 48
RL = 50 Ω, CL = 5 pF, f = 1 MHz, see
Figure 35
RL = 50 Ω, CL = 5 pF, f = 1 MHz, see
Figure 36
RL = 10 kΩ, VS = 15 V p-p, f = 20 Hz to
20 kHz, see Figure 40
RL = 50 Ω, CL = 5 pF, see Figure 39
RL = 50 Ω, CL = 5 pF, f = 1 MHz, see
Figure 39
VS = 0 V, f = 1 MHz
VS = 0 V, f = 1 MHz
VS = 0 V, f = 1 MHz
VDD = 16.5 V, VSS = −16.5 V, digital inputs =
0 V, 5 V, or VDD
mA typ
mA max
mA typ
mA max
mA typ
μA max
VS = ±55 V
1.2
1.6
0.8
1.0
0.5
1.0
1.8
1.1
1.8
±5
±22
Guaranteed by design; not subject to production test.
Rev. B | Page 4 of 28
mA typ
mA max
mA typ
mA max
mA typ
mA max
V min
V max
GND = 0 V
GND = 0 V
Data Sheet
ADG5412BF/ADG5413BF
±20 V DUAL-SUPPLY
VDD = 20 V ± 10%, VSS = −20 V ± 10%, GND = 0 V, CDECOUPLING = 0.1 μF, unless otherwise noted.
Table 2.
Parameter
ANALOG SWITCH
Analog Signal Range
On Resistance, RON
On-Resistance Match Between Channels, ∆RON
On-Resistance Flatness, RFLAT(ON)
Threshold Voltage, VT
LEAKAGE CURRENTS
Source Off Leakage, IS (Off )
Drain Off Leakage, ID (Off )
Channel On Leakage, ID (On), IS (On)
+25°C
−40°C to
+85°C
VDD to VSS
10
11.5
9.5
11
0.05
0.35
0.05
0.35
1.0
1.4
0.1
0.4
0.7
±0.1
±1.5
±0.1
±1.5
±0.3
±2.0
14.5
16.5
14
16.5
0.5
0.5
0.5
0.5
1.5
1.5
0.5
0.5
V
Ω typ
Ω max
Ω typ
Ω max
Ω typ
Ω max
Ω typ
Ω max
Ω typ
Ω max
Ω typ
Ω max
V typ
±24
±5.5
±20
±2.5
±5.5
nA typ
nA max
nA typ
nA max
nA typ
nA max
±78
μA typ
±40
μA typ
Power Supplies Grounded or Floating
Output Leakage Current, IS or ID
With Overvoltage
±0.4
±1.0
±10
±1.0
Power Supplies Grounded
Power Supplies Floating
±30
±10
±50
±10
μA typ
±1.0
μA max
nA typ
±100
±10
nA max
μA typ
2.0
0.8
V min
V max
μA typ
μA max
pF typ
0.7
1.2
Digital Input Capacitance, CIN
Unit
±5.5
FAULT
Input Leakage Current, IS or ID
With Overvoltage
DIGITAL INPUTS
Input Voltage
High, VINH
Low, VINL
Input Current, IINL or IINH
−40°C to
+125°C
5.0
Rev. B | Page 5 of 28
Test Conditions/Comments
VDD = 18 V, VSS = −18 V, see
Figure 32
VS = ±15 V, IS = −10 mA
VS = ±13.5 V, IS = −10 mA
VS = ±15 V, IS = −10 mA
VS = ±13.5 V, IS = −10 mA
VS = ±15 V, IS = −10 mA
VS = ±13.5 V, IS = −10 mA
See Figure 28
VDD = 22 V, VSS = −22 V
VS = ±15 V, VD = ∓15 V, see Figure 33
VS = ±15 V, VD = ∓15 V, see Figure 33
VS = VD = ±15 V, see Figure 34
VDD = 22 V, VSS = −22 V, GND = 0 V,
VS or VD = ±55 V, see Figure 37
VDD = 0 V or floating, VSS = 0 V or
floating, GND = 0 V, INx = 0 V or
floating, VS or VD = ±55 V, see
Figure 38
VDD = +22 V, VSS = −22 V, GND = 0 V,
VS or VD = ±55 V, see Figure 37
VDD = 0 V, VSS = 0 V, GND = 0 V, VS or
VD = ±55 V, INx = 0 V, see Figure 38
VDD = floating, VSS = floating, GND
= 0 V, VS or VD = ±55 V, INx = 0 V,
see Figure 38
VIN = VGND or VDD
ADG5412BF/ADG5413BF
Parameter
Output Voltage
High, VOH
Low, VOL
DYNAMIC CHARACTERISTICS1
tON
tOFF
Break-Before-Make Time Delay, tD
(ADG5413BF Only)
Data Sheet
+25°C
−40°C to
+85°C
−40°C to
+125°C
2.0
0.8
400
500
415
515
295
Overvoltage Recovery Time, tRECOVERY
Interrupt Flag Response Time, tDIGRESP
Interrupt Flag Recovery Time, tDIGREC
530
555
550
565
500
515
1400
1700
115
85
ns typ
ns max
ns typ
ns max
ns typ
RL = 300 Ω, CL = 35 pF
VS = 10 V, see Figure 47
RL = 300 Ω, CL = 35 pF
VS = 10 V, see Figure 47
RL = 300 Ω, CL = 35 pF
ns min
ns typ
ns max
ns typ
ns max
ns typ
μs typ
ns typ
VS1 = VS2 = 10 V, see Figure 46
RL = 1 kΩ, CL = 2 pF, see Figure 41
Charge Injection, QINJ
−640
pC typ
Off Isolation
−70
dB typ
Channel-to-Channel Crosstalk
−90
dB typ
Total Harmonic Distortion Plus Noise, THD + N
0.001
% typ
−3 dB Bandwidth
Insertion Loss
270
−0.73
MHz typ
dB typ
12
11
23
pF typ
pF typ
pF typ
CS (Off )
CD (Off )
CD (On), CS (On)
POWER REQUIREMENTS
Normal Mode
IDD
IGND
ISS
Fault Mode
IDD
IGND
ISS
VDD/VSS
1
370
480
840
1200
85
60
600
0.9
1.2
0.4
0.55
0.5
0.65
Test Conditions/Comments
V min
V max
200
Overvoltage Response Time, tRESPONSE
Unit
1.3
0.6
0.7
RL = 1 kΩ, CL = 2 pF, see Figure 42
CL = 10 pF, see Figure 43
CL = 10 pF, see Figure 44
CL = 10 pF, RPULLUP = 1 kΩ, see
Figure 45
VS = 0 V, RS = 0 Ω, CL = 1 nF, see
Figure 48
RL = 50 Ω, CL = 5 pF, f = 1 MHz, see
Figure 35
RL = 50 Ω, CL = 5 pF, f = 1 MHz, see
Figure 36
RL = 10 kΩ, VS = 20 V p-p, f = 20 Hz
to 20 kHz, see Figure 40
RL = 50 Ω, CL = 5 pF, see Figure 39
RL = 50 Ω, CL = 5 pF, f = 1 MHz, see
Figure 39
VS = 0 V, f = 1 MHz
VS = 0 V, f = 1 MHz
VS = 0 V, f = 1 MHz
VDD = 22 V, VSS = −22 V, digital
inputs = 0 V, 5 V, or VDD
mA typ
mA max
mA typ
mA max
mA typ
mA max
VS = ±55 V
1.2
1.6
0.8
1.0
0.5
1.0
1.8
1.1
1.8
±5
±22
Guaranteed by design; not subject to production test.
Rev. B | Page 6 of 28
mA typ
mA max
mA typ
mA max
mA typ
mA max
V min
V max
GND = 0 V
GND = 0 V
Data Sheet
ADG5412BF/ADG5413BF
12 V SINGLE-SUPPLY
VDD = 12 V ± 10%, VSS = 0 V, GND = 0 V, CDECOUPLING = 0.1 μF, unless otherwise noted.
Table 3.
Parameter
ANALOG SWITCH
Analog Signal Range
On Resistance, RON
On-Resistance Match Between Channels, ∆RON
On-Resistance Flatness, RFLAT(ON)
Threshold Voltage, VT
LEAKAGE CURRENTS
Source Off Leakage, IS (Off )
Drain Off Leakage, ID (Off )
Channel On Leakage, ID (On), IS (On)
+25°C
−40°C to
+85°C
0 V to VDD
22
24.5
10
11.2
0.05
0.5
0.05
0.5
12.5
14.5
0.6
0.9
0.7
±0.1
±1.5
±0.1
±1.5
±0.3
±2.0
31
37
14
16.5
0.6
0.7
0.6
0.7
19
23
1.1
1.3
V
Ω typ
Ω max
Ω typ
Ω max
Ω typ
Ω max
Ω typ
Ω max
Ω typ
Ω max
Ω typ
Ω max
V typ
±24
±5.5
±20
±2.5
±5.5
nA typ
nA max
nA typ
nA max
nA typ
nA max
±78
μA typ
±40
μA typ
Power Supplies Grounded or Floating
Output Leakage Current, IS or ID
With Overvoltage
±20
±200
±10
±250
Power Supplies Grounded
Power Supplies Floating
±30
±10
±50
±10
nA typ
±250
nA max
nA typ
±100
±10
nA max
μA typ
2.0
0.8
5.0
V min
V max
μA typ
μA max
pF typ
2.0
0.8
V min
V max
0.7
1.2
Digital Input Capacitance, CIN
Output Voltage
High, VOH
Low, VOL
Unit
±5.5
FAULT
Input Leakage Current, IS or ID
With Overvoltage
DIGITAL INPUTS
Input Voltage
High, VINH
Low, VINL
Input Current, IINL or IINH
−40°C to
+125°C
Rev. B | Page 7 of 28
Test Conditions/Comments
VDD = 10.8 V, VSS = 0 V, see Figure 32
VS = 0 V to 10 V, IS = −10 mA
VS = 3.5 V to 8.5 V, IS = −10 mA
VS = 0 V to 10 V, IS = −10 mA
VS = 3.5 V to 8.5 V, IS = −10 mA
VS = 0 V to 10 V, IS = −10 mA
VS = 3.5 V to 8.5 V, IS = −10 mA
See Figure 28
VDD = 13.2 V, VSS = 0 V
VS = 1 V/10 V, VD = 10 V/1 V, see Figure 33
VS = 1 V/10 V, VD = 10 V/1 V, see Figure 33
VS = VD = 1 V/10 V, see Figure 34
VDD = 13.2 V, VSS = 0 V, GND = 0 V, VS or
VD = ±55 V, see Figure 37
VDD = 0 V or floating, VSS = 0 V or floating,
GND = 0 V, INx = 0 V or floating, VS or
VD = ±55 V, see Figure 38
VDD = 13.2 V, VSS = 0 V, GND = 0 V, VS or
VD = ±55 V, see Figure 37
VDD = 0 V, VSS = 0 V, GND = 0 V, VS or VD =
±55 V, INx = 0 V, see Figure 38
VDD = floating, VSS = floating, GND = 0 V,
VS or VD = ±55 V, INx = 0 V, see Figure 38
VIN = VGND or VDD
ADG5412BF/ADG5413BF
Parameter
DYNAMIC CHARACTERISTICS1
tON
tOFF
Break-Before-Make Time Delay, tD
(ADG5413BF Only)
Data Sheet
+25°C
400
485
375
460
260
−40°C to
+85°C
−40°C to
+125°C
515
540
495
520
170
Overvoltage Response Time, tRESPONSE
Test Conditions/Comments
ns typ
ns max
ns typ
ns max
ns typ
RL = 300 Ω, CL = 35 pF
VS = 8 V, see Figure 47
RL = 300 Ω, CL = 35 pF
VS = 8 V, see Figure 47
RL = 300 Ω, CL = 35 pF
ns min
ns typ
ns max
ns typ
ns max
ns typ
μs typ
ns typ
pC typ
dB typ
VS1 = VS2 = 8 V, see Figure 46
RL = 1 kΩ, CL = 2 pF, see Figure 41
Charge Injection, QINJ
Off Isolation
560
660
640
800
85
60
600
−340
−65
Channel-to-Channel Crosstalk
−90
dB typ
Total Harmonic Distortion Plus Noise, THD + N
0.007
% typ
−3 dB Bandwidth
Insertion Loss
270
−0.74
MHz typ
dB typ
16
15
25
pF typ
pF typ
pF typ
Overvoltage Recovery Time, tRECOVERY
Interrupt Flag Response Time, tDIGRESP
Interrupt Flag Recovery Time, tDIGREC
CS (Off )
CD (Off )
CD (On), CS (On)
POWER REQUIREMENTS
Normal Mode
IDD
IGND
ISS
Fault Mode
IDD
IGND
ISS
VDD
1
Unit
0.9
1.2
0.4
0.55
0.5
0.65
700
720
865
960
115
85
1.3
0.6
0.7
RL = 1 kΩ, CL = 2 pF, see Figure 42
CL = 10 pF, see Figure 43
CL = 10 pF, see Figure 44
CL = 10 pF, RPULLUP = 1 kΩ, see Figure 45
VS = 6 V, RS = 0 Ω, CL = 1 nF, see Figure 48
RL = 50 Ω, CL = 5 pF, f = 1 MHz, see
Figure 35
RL = 50 Ω, CL = 5 pF, f = 1 MHz, see
Figure 36
RL = 10 kΩ, VS = 6 V p-p, f = 20 Hz to
20 kHz, see Figure 40
RL = 50 Ω, CL = 5 pF, see Figure 39
RL = 50 Ω, CL = 5 pF, f = 1 MHz, see
Figure 39
VS = 6 V, f = 1 MHz
VS = 6 V, f = 1 MHz
VS = 6 V, f = 1 MHz
VDD = 13.2 V, VSS = 0 V, digital inputs = 0 V,
5 V, or VDD
mA typ
mA max
mA typ
mA max
mA typ
mA max
VS = ±55 V
1.2
1.6
0.8
1.0
0.5
1.0
1.8
1.1
1.8
8
44
Guaranteed by design; not subject to production test.
Rev. B | Page 8 of 28
mA typ
mA max
mA typ
mA max
mA typ
mA max
V min
V max
VSS = GND = 0 V
VSS = GND = 0 V
Data Sheet
ADG5412BF/ADG5413BF
36 V SINGLE-SUPPLY
VDD = 36 V ± 10%, VSS = 0 V, GND = 0 V, CDECOUPLING = 0.1 μF, unless otherwise noted.
Table 4.
Parameter
ANALOG SWITCH
Analog Signal Range
On Resistance, RON
On-Resistance Match Between Channels, ∆RON
On-Resistance Flatness, RFLAT(ON)
+25°C
−40°C to
+85°C
−40°C to
+125°C
0 V to VDD
22
24.5
10
11
0.05
0.5
0.05
0.35
12.5
14.5
0.1
0.4
0.7
31
37
14
16.5
0.6
0.7
0.5
0.5
19
23
0.5
0.5
Unit
V
Ω typ
Ω max
Ω typ
Ω max
Ω typ
Ω max
Ω typ
Ω max
Ω typ
Ω max
Ω typ
Ω max
V typ
Threshold Voltage, VT
LEAKAGE CURRENTS
Source Off Leakage, IS (Off )
±0.1
±1.5
±0.1
±5.5
Drain Off Leakage, ID (Off )
±1.5
±0.3
±2.0
±5.5
±20
±2.5
±5.5
nA max
nA typ
nA max
±78
μA typ
±40
μA typ
Channel On Leakage, ID (On), IS (On)
nA typ
FAULT
Input Leakage Current, IS or ID
With Overvoltage
Power Supplies Grounded or Floating
Output Leakage Current, IS or ID
With Overvoltage
±20
±200
±10
±250
Power Supplies Grounded
Power Supplies Floating
±30
±10
±50
±10
DIGITAL INPUTS
Input Voltage
High, VINH
Low, VINL
Input Current, IINL or IINH
±24
nA typ
±250
nA max
nA typ
±100
±10
nA max
μA typ
2.0
0.8
V min
V max
μA typ
μA max
pF typ
0.7
1.2
Digital Input Capacitance, CIN
nA max
nA typ
5.0
Rev. B | Page 9 of 28
Test Conditions/Comments
VDD = 32.4 V, VSS = 0 V, see Figure 32
VS = 0 V to 30 V, IS = −10 mA
VS = 4.5 V to 28 V, IS = −10 mA
VS = 0 V to 30 V, IS = −10 mA
VS = 4.5 V to 28 V, IS = −10 mA
VS = 0 V to 30 V, IS = −10 mA
VS = 4.5 V to 28 V, IS = −10 mA
See Figure 28
VDD = 39.6 V, VSS = 0 V
VS = 1 V/30 V, VD = 30 V/1 V, see
Figure 33
VS = 1 V/30 V, VD = 30 V/1 V, see
Figure 33
VS = VD = 1 V/30 V, see Figure 34
VDD = 39.6 V, VSS = 0 V, GND = 0 V, VS or
VD = +55 V, −40 V, see Figure 37
VDD = 0 V or floating, VSS = 0 V or
floating, GND = 0 V, INx = 0 V or
floating, VS or VD = ±55 V, see Figure 38
VDD = 39.6 V, VSS = 0 V, GND = 0 V, VS or
VD = +55 V, −40 V, see Figure 37
VDD = 0 V, VSS = 0 V, GND = 0 V, VS or
VD = ±55 V, INx = 0 V, see Figure 38
VDD = floating, VSS = floating, GND =
0 V, VS or VD = ±55 V, INx = 0 V, see
Figure 38
VIN = VGND or VDD
ADG5412BF/ADG5413BF
Parameter
Output Voltage
High, VOH
Low, VOL
DYNAMIC CHARACTERISTICS1
tON
tOFF
Break-Before-Make Time Delay, tD
(ADG5413BF Only)
Data Sheet
+25°C
−40°C to
+85°C
−40°C to
+125°C
2.0
0.8
400
490
375
460
285
520
545
485
510
RL = 300 Ω, CL = 35 pF
VS = 18 V, see Figure 47
RL = 300 Ω, CL = 35 pF
VS = 18 V, see Figure 47
RL = 300 Ω, CL = 35 pF
ns min
ns typ
ns max
ns typ
ns max
ns typ
μs typ
ns typ
pC typ
VS1 = VS2 = 18 V, see Figure 46
RL = 1 kΩ, CL = 2 pF, see Figure 41
Charge Injection, QINJ
Off Isolation
−70
dB typ
Channel-to-Channel Crosstalk
−90
dB typ
Total Harmonic Distortion Plus Noise, THD + N
0.001
% typ
−3 dB Bandwidth
Insertion Loss
270
−0.75
MHz typ
dB typ
12
11
23
pF typ
pF typ
pF typ
Interrupt Flag Response Time, tDIGRESP
Interrupt Flag Recovery Time, tDIGREC
CS (Off )
CD (Off )
CD (On), CS (On)
POWER REQUIREMENTS
Normal Mode
IDD
IGND
ISS
Isolation Mode
IDD
IGND
ISS
VDD
1
ns typ
ns max
ns typ
ns max
ns typ
250
350
1500
2000
85
60
600
−610
Overvoltage Recovery Time, tRECOVERY
0.9
1.2
0.4
0.55
0.5
0.65
Test Conditions/Comments
V min
V max
195
Overvoltage Response Time, tRESPONSE
Unit
360
375
2300
2700
115
85
1.3
0.6
0.7
RL = 1 kΩ, CL = 2 pF, see Figure 42
CL = 10 pF, see Figure 43
CL = 10 pF, see Figure 44
CL = 10 pF, RPULLUP = 1 kΩ, see Figure 45
VS = 18 V, RS = 0 Ω, CL = 1 nF, see
Figure 48
RL = 50 Ω, CL = 5 pF, f = 1 MHz, see
Figure 35
RL = 50 Ω, CL = 5 pF, f = 1 MHz, see
Figure 36
RL = 10 kΩ, VS = 18 V p-p, f = 20 Hz to
20 kHz, see Figure 40
RL = 50 Ω, CL = 5 pF, see Figure 39
RL = 50 Ω, CL = 5 pF, f = 1 MHz, see
Figure 39
VS = 18 V, f = 1 MHz
VS = 18 V, f = 1 MHz
VS = 18 V, f = 1 MHz
VDD = 39.6 V, VSS = 0 V, digital inputs =
0 V, 5 V, or VDD
mA typ
mA max
mA typ
mA max
mA typ
mA max
VS = +55 V, −40 V
1.2
1.6
0.8
1.0
0.5
1.0
1.8
1.1
1.8
8
44
Guaranteed by design; not subject to production test.
Rev. B | Page 10 of 28
mA typ
mA max
mA typ
mA max
mA typ
mA max
V min
V max
VSS = GND = 0 V
VSS = GND = 0 V
Data Sheet
ADG5412BF/ADG5413BF
CONTINUOUS CURRENT PER CHANNEL, Sx OR Dx
Table 5.
Parameter
16-LEAD TSSOP
θJA = 112.6°C/W
16-LEAD LFCSP
θJA = 30.4°C/W
25°C
85°C
125°C
Unit
Test Conditions/Comments
83
64
59
48
39
29
mA max
mA max
VS = VSS + 4.5 V to VDD − 4.5 V
VS = VSS to VDD
152
118
99
80
61
52
mA max
mA max
VS = VSS + 4.5 V to VDD − 4.5 V
VS = VSS to VDD
Rev. B | Page 11 of 28
ADG5412BF/ADG5413BF
Data Sheet
ABSOLUTE MAXIMUM RATINGS
TA = 25°C, unless otherwise noted.
Table 6.
Parameter
VDD to VSS
VDD to GND
VSS to GND
Sx and Dx
Sx to VDD or VSS
VS to VD
Digital Inputs
Peak Current, Sx or Dx Pins
Continuous Current, Sx or Dx
Pins
Digital Output
Operating Temperature
Range
Storage Temperature Range
Junction Temperature
Thermal Impedance, θJA
(4-Layer Board)
16-Lead TTSOP
16-Lead LFSCP
Reflow Soldering Peak
Temperature, Pb Free
ESD (HBM: ANSI/ESD
STM5.1-2007)
I/O Port to Supplies
I/O Port to I/O Port
All Other Pins
1
Rating
48 V
−0.3 V to +48 V
−48 V to +0.3 V
−55 V to +55 V
80 V
80 V
GND − 0.7 V to +48 V or 30 mA,
whichever occurs first
288 mA (pulsed at 1 ms, 10%
duty cycle maximum)
Data1 + 15%
Stresses at or above those listed under Absolute Maximum
Ratings may cause permanent damage to the product. This is a
stress rating only; functional operation of the product at these
or any other conditions above those indicated in the operational
section of this specification is not implied. Operation beyond
the maximum operating conditions for extended periods may
affect product reliability.
Only one absolute maximum rating can be applied at any one time.
ESD CAUTION
GND − 0.7 V to 6 V or 30 mA,
whichever occurs first
−40°C to +125°C
−65°C to +150°C
150°C
112.6°C/W
30.4°C/W
As per JEDEC J-STD-020
5.5 kV
5.5 kV
3 kV
See Table 5.
Rev. B | Page 12 of 28
Data Sheet
ADG5412BF/ADG5413BF
VDD
S1 1
VSS
4
GND
5
12
FF
GND 3
S4
6
11
S3
S4 4
D4
7
10
D3
IN4
8
9
IN3
12 S2
ADG5412BF/
ADG5413BF
TOP VIEW
D4 5
12473-003
TOP VIEW
(Not to Scale)
VSS 2
11 VDD
10 FF
9
S3
NOTES
1. THE EXPOSED PAD IS INTERNALLY CONNECTED.
FOR INCREASED RELIABILITY OF THE SOLDER JOINTS
AND MAXIMUM THERMAL CAPABILITY, IT IS RECOMMENDED
THAT THE PAD BE CONNECTED TO THE LOWEST SUPPLY VOLTAGE, VSS.
12473-104
S2
13
ADG5412BF/
ADG5413BF
13 D2
14
14 IN2
D2
S1 3
D3 8
IN2
15
IN3 7
16
2
16 D1
1
D1
IN4 6
IN1
15 IN1
PIN CONFIGURATION AND FUNCTION DESCRIPTIONS
Figure 4. LFCSP Pin Configuration
Figure 3. TSSOP Pin Configuration
Table 7. Pin Function Descriptions
Pin No.
TSSOP LFCSP
1
15
2
16
3
1
4
2
5
3
6
4
7
5
8
6
9
7
10
8
11
9
12
10
13
14
15
16
11
12
13
14
EP
Mnemonic
IN1
D1
S1
VSS
GND
S4
D4
IN4
IN3
D3
S3
FF
VDD
S2
D2
IN2
Exposed
Pad
Description
Logic Control Input.
Overvoltage Protected Drain Terminal. This pin can be an input or an output.
Overvoltage Protected Source Terminal. This pin can be an input or an output.
Most Negative Power Supply Potential.
Ground (0 V) Reference.
Overvoltage Protected Source Terminal. This pin can be an input or an output.
Overvoltage Protected Drain Terminal. This pin can be an input or an output.
Logic Control Input.
Logic Control Input.
Overvoltage Protected Drain Terminal. This pin can be an input or an output.
Overvoltage Protected Source Terminal. This pin can be an input or an output.
Fault Flag Digital Output. This pin has a high output when the device is in normal operation or a low when
a fault condition occurs on any of the Sx inputs.
Most Positive Power Supply Potential.
Overvoltage Protected Source Terminal. This pin can be an input or an output.
Overvoltage Protected Drain Terminal. This pin can be an input or an output.
Logic Control Input.
The exposed pad is internally connected. For increased reliability of the solder joints and maximum
thermal capability, it is recommended that the pad be connected to the lowest supply voltage, VSS.
Table 8. ADG5412BF Truth Table
INx
1
0
Switch Condition (S1 to S4)
On
Off
Table 9. ADG5413BF Truth Table
INx
0
1
S1, S4
Off
On
Switch Condition
S2, S3
On
Off
Rev. B | Page 13 of 28
ADG5412BF/ADG5413BF
Data Sheet
TYPICAL PERFORMANCE CHARACTERISTICS
25
VDD = +15V
VSS = –15V
TA = 25°C
35
VDD = +20V
VSS = –20V
VDD = +18V
VSS = –18V
15
VDD = +16.5V
VSS = –16.5V
30
ON RESISTANCE (Ω)
20
ON RESISTANCE (Ω)
40
VDD = +22V
VSS = –22V
VDD = +13.5V
VSS = –13.5V
10
20
+125°C
15
+85°C
10
VDD = +15V
VSS = –15V
5
25
+25°C
–40°C
–10
–5
0
5
10
15
20
25
VS, VD (V)
0
–15
–12
–9
–6
–3
0
3
6
9
Figure 5. RON as a Function of VS,VD (Dual-Supply)
40
VDD = +20V
VSS = –20V
TA = 25°C
35
30
ON RESISTANCE (Ω)
ON RESISTANCE (Ω)
VDD = 12V
VSS = 0V
VDD = 10.8V
VSS = 0V
15
10
VDD = 13.2V
VSS = 0V
5
25
20
+125°C
15
+85°C
10
+25°C
5
0
2
4
6
8
10
12
14
VS, VD (V)
–40°C
0
–20
12473-005
0
–15
–10
–5
0
5
10
40
VDD = 12V
VSS = 0V
TA = 25°C
35
ON RESISTANCE (Ω)
30
VDD = 32.4V
VSS = 0V
10
25
20
+125°C
15
+85°C
10
VDD = 39.6V
VSS = 0V
+25°C
–40°C
5
0
0
5
10
15
20
25
30
35
VS, VD (V)
40
12473-006
ON RESISTANCE (Ω)
VDD = 36V
VSS = 0V
5
20
Figure 9. RON as a Function of VS,VD for Different Temperatures,
±20 V Dual-Supply
25
15
15
VS, VD (V)
Figure 6. RON as a Function of VS,VD (12 V Single-Supply)
20
15
Figure 8. RON as a Function of VS,VD for Different Temperatures,
±15 V Dual-Supply
25
20
12
VS, VD (V)
12473-008
–15
Figure 7. RON as a Function of VS,VD (36 V Single-Supply)
0
0
2
4
6
8
10
12
VS, VD (V)
Figure 10. RON as a Function of VS,VD for Different Temperatures,
12 V Single-Supply
Rev. B | Page 14 of 28
12473-009
–20
12473-004
0
–25
12473-007
5
Data Sheet
ADG5412BF/ADG5413BF
40
2
VDD = 36V
VSS = 0V
35
1
0
LEAKAGE CURRENT (nA)
25
20
+125°C
+85°C
+25°C
0
4
8
12
16
20
24
28
32
36
–8
IS (OFF) + –
IS (OFF) – +
IS, ID (ON) + +
4
1
LEAKAGE CURRENT (nA)
VDD = +15V
VSS = –15V
VBIAS = +10V/–10V
–1
–2
–3
–4
–5
IS (OFF) + –
IS (OFF) – +
IS, ID (ON) + +
–7
0
20
40
ID (OFF) + –
ID (OFF) – +
IS, ID (ON) – –
60
80
100
120
TEMPERATURE (°C)
LEAKAGE CURRENT (nA)
–8
–10
40
IS (OFF) + –
IS (OFF) – +
IS, ID (ON) + +
0
20
40
ID (OFF) + –
ID (OFF) – +
IS, ID (ON) – –
60
80
100
120
VDD = +15V
VSS = –15V
60
80
–10
–15
–20
–25
–30
–35
VS = –30V
VS = +30V
VS = –55V
VS = +55V
–40
ID (OFF) + –
ID (OFF) – +
IS, ID (ON) – –
–45
100
120
TEMPERATURE (°C)
12473-012
20
–8
0
–6
0
–6
–5
–4
–14
–4
5
–2
–12
120
Figure 15. Leakage Current vs. Temperature, 36 V Single-Supply
0
IS (OFF) + –
IS (OFF) – +
IS, ID (ON) + +
100
TEMPERATURE (°C)
VDD = +20V
VSS = –20V
VBIAS = +15V/–15V
2
80
–2
–12
Figure 12. Leakage Current vs. Temperature, ±15 V Dual-Supply
4
60
0
–10
12473-011
–6
40
VDD = 36V
VSS = 0V
VBIAS = 1V/30V
2
0
20
Figure 14. Leakage Current vs. Temperature, 12 V Single-Supply
2
–8
0
ID (OFF) + –
ID (OFF) – +
IS, ID (ON) – –
TEMPERATURE (°C)
Figure 11. RON as a Function of VS,VD for Different Temperatures,
36 V Single-Supply
LEAKAGE CURRENT (nA)
–5
–7
VS, VD (V)
LEAKAGE CURRENT (nA)
–4
Figure 13. Leakage Current vs. Temperature, ±20 V Dual-Supply
–50
0
20
40
60
80
100
120
TEMPERATURE (°C)
Figure 16. Overvoltage Drain Leakage Current vs. Temperature,
±15 V Dual-Supply
Rev. B | Page 15 of 28
12473-015
0
–3
–6
–40°C
5
–2
12473-013
10
VDD = 12V
VSS = 0V
VBIAS = 1V/10V
–1
12473-014
15
12473-010
ON RESISTANCE (Ω)
30
ADG5412BF/ADG5413BF
–20
OFF ISOLATION (dB)
–10
–20
–30
–40
VS = –30V
VS = +30V
VS = –55V
VS = +55V
0
20
–40
–60
–80
–100
40
60
80
100
120
TEMPERATURE (°C)
–120
1k
12473-016
–50
–60
VDD = +15V
VSS = –15V
TA = 25°C
0
CROSSTALK (dB)
–15
–20
–25
–30
VS = –30V
VS = +30V
VS = –55V
VS = +55V
0
20
40
60
80
100
120
TEMPERATURE (°C)
–60
–80
–120
10k
100k
1M
10M
100M
1G
FREQUENCY (Hz)
Figure 21. Crosstalk vs. Frequency, ±15 V Dual-Supply
100
VDD = 36V
VSS = 0V
0
1G
–40
Figure 18. Overvoltage Drain Leakage Current vs. Temperature,
12 V Single-Supply
5
100M
–100
12473-017
LEAKAGE CURRENT (nA)
–20
VDD = 12V
VSS = 0V
–10
–45
10M
VDD = +15V
VSS = –15V
TA = 25°C
0
–40
1M
Figure 20. Off Isolation vs. Frequency, ±15 V Dual-Supply
5
–35
100k
FREQUENCY (Hz)
Figure 17. Overvoltage Drain Leakage Current vs. Temperature,
±20 V Dual-Supply
–5
10k
12473-019
0
LEAKAGE CURRENT (nA)
0
VDD = +20V
VSS = –20V
12473-020
10
Data Sheet
TA = 25°C
0
CHARGE INJECTION (pC)
–10
–15
–20
VS = –38V
VS = +38V
VS = –40V
VS = +55V
–30
0
20
VDD = 12V
VSS = 0V
–200
–300
–400
VDD = 36V
VSS = 0V
–500
–600
–700
40
60
80
100
120
TEMPERATURE (°C)
Figure 19. Overvoltage Drain Leakage Current vs. Temperature,
36 V Single-Supply
–800
0
5
10
15
20
25
30
35
40
VS (V)
Figure 22. Charge Injection vs. Source Voltage (VS), Single-Supply
Rev. B | Page 16 of 28
12473-021
–25
12473-018
LEAKAGE CURRENT (nA)
–100
–5
Data Sheet
100
ADG5412BF/ADG5413BF
0
TA = 25°C
VDD = +15V
VSS = –15V
–100
–1.0
–1.5
BANDWIDTH (dB)
–200
–300
–400
–500
–600
–15
–10
–5
0
5
10
15
–2.5
–3.0
–3.5
–4.5
20
VS (V)
–5.0
10k
100k
Figure 23. Charge Injection vs. Source Voltage (VS), Dual-Supply
0
480
460
1G
tON (+12V)
tON (±20V)
tOFF (±15V)
tON (+36V)
tOFF (+12V)
tOFF (±20V)
tON (±15V)
tOFF (+36V)
420
–60
TIME (ns)
–80
400
380
–100
360
–120
100k
1M
10M
100M
1G
FREQUENCY (Hz)
320
–40
12473-023
–140
10k
20
40
60
80
100
120
Figure 27. tON, tOFF Times vs. Temperature
0.9
THRESHOLD VOLTAGE, VT (V)
LOAD = 10kΩ
TA = 25°C
0.015
VDD = 12V, VSS = 0V, VS = 6V p-p
0.010
VDD = 15V, VSS = –15V, VS = 15V p-p
0.005
0
TEMPERATURE (°C)
Figure 24. ACPSRR vs. Frequency, ±15 V Dual-Supply
0.020
–20
12473-026
340
VDD = 20V, VSS = –20V, VS = 20V p-p
0.8
0.7
0.6
0
0
5000
10000
15000
FREQUENCY (Hz)
20000
12473-024
VDD = 36V, VSS = 0V, VS = 18V p-p
Figure 25. THD + N vs. Frequency, ±15 V Dual-Supply
0.5
–40
–20
0
20
40
60
80
100
TEMPERATURE (°C)
Figure 28. Threshold Voltage (VT) vs. Temperature
Rev. B | Page 17 of 28
120
12473-027
ACPSRR (dB)
100M
440
–40
THD + N (%)
10M
Figure 26. Bandwidth vs. Frequency
VDD = +15V
VSS = –15V
TA = 25°C
WITH DECOUPLING CAPACITORS
–20
1M
FREQUENCY (Hz)
12473-025
–800
–20
–2.0
–4.0
VDD = +20V
VSS = –20V
–700
12473-022
CHARGE INJECTION (pC)
VDD = +15V
VSS = –15V
TA = 25°C
–0.5
0
ADG5412BF/ADG5413BF
Data Sheet
24
TA = 25°C
VDD = +10V
VSS = –10V
T
SOURCE
SIGNAL VOLTAGE (V p-p)
20
VDD
DRAIN
CH2 5.00V
M200ns
A CH2
T
–10.00ns
16.1V
0
3
DRAIN
VSS
–16.1V
12473-029
SOURCE
M200ns
A CH2
T
–10.00ns
10
Figure 31. Large Voltage Signal Tracking vs. Frequency
T
CH2 5.00V
1
FREQUENCY (MHz)
Figure 29. Drain Output Response to Positive Overvoltage
CH1 5.00V
CH3 5.00V
DISTORTIONLESS
OPERATING
REGION
8
4
12473-028
CH1 5.00V
CH3 5.00V
12
Figure 30. Drain Output Response to Negative Overvoltage
Rev. B | Page 18 of 28
100
12473-030
2
16
Data Sheet
ADG5412BF/ADG5413BF
TEST CIRCUITS
IS
Dx
A
RL
10kΩ
|VS| > |VDD| OR |VSS|
Dx
IDS
RON = V/IDS
12473-031
Sx
VS
ID
Sx
A
12473-034
V
Figure 37. Switch Overvoltage Leakage
Figure 32. On Resistance
VDD = VSS = GND = 0V
IS
Sx
Dx
ID
Sx
A
Dx
A
A
VS
VD
RL
10kΩ
VS
12473-035
A
ID (OFF)
12473-032
IS (OFF)
Figure 38. Switch Unpowered Leakage
Figure 33. Off Leakage
ID (ON)
Dx
NC = NO CONNECT
A
VD
12473-033
Sx
NC
Figure 34. On Leakage
VDD
0.1µF
VDD
VSS
0.1µF
0.1µF
NETWORK
ANALYZER
VSS
Sx
VDD
50Ω
INx
Sx
VS
VIN
RL
50Ω
GND
VS
Dx
VOUT
VIN
RL
50Ω
GND
OFF ISOLATION = 20 log
VOUT
VS
INSERTION LOSS = 20 log
VDD
VDD
VSS
VSS
NETWORK
ANALYZER
S1
0.1µF
RL
50Ω
VDD
Sx
VS
V p-p
INx
S2
CHANNEL-TO-CHANNEL CROSSTALK = 20 log
RS
VOUT
Dx
GND
AUDIO
PRECISION
VSS
Dx
VIN
VS
VOUT
VS
GND
RL
10kΩ
12473-045
RL
50Ω
VOUT WITH SWITCH
VOUT WITHOUT SWITCH
VSS
0.1µF
0.1µF
VDD
VOUT
Figure 39. Bandwidth
Figure 35. Off Isolation
0.1µF
50Ω
INx
12473-044
Dx
NETWORK
ANALYZER
VSS
12473-046
VSS
Figure 36. Channel-to-Channel Crosstalk
Figure 40. THD + N
Rev. B | Page 19 of 28
VOUT
12473-047
VDD
0.1µF
ADG5412BF/ADG5413BF
Data Sheet
VDD
VSS
0.1µF
0.1µF
VDD + 0.5V
VDD
SOURCE
VOLTAGE
(VS)
VSS
S1
VD
D1
CL*
2pF
VS
0V
ADG5412BF/
ADG5413BF
tRESPONSE
VDD – 1V
RL
1kΩ
S2 TO S4
OUTPUT
(VD)
12473-036
GND
0V
*INCLUDES TRACK CAPACITANCE
Figure 41. Overvoltage Response Time, tRESPONSE
VDD
VSS
0.1µF
0.1µF
VDD + 0.5V
VDD
SOURCE
VOLTAGE
(VS)
0V
VSS
S1
VD
D1
CL*
2pF
VS
ADG5412BF/
ADG5413BF
tRECOVERY
RL
1kΩ
S2 TO S4
OUTPUT
(VD)
1V
0V
12473-037
GND
*INCLUDES TRACK CAPACITANCE
Figure 42. Overvoltage Recovery Time, tRECOVERY
VDD
VSS
0.1µF
0.1µF
VDD + 0.5V
VDD
SOURCE
VOLTAGE
(VS)
VSS
S1
VS
0V
D1
S2 TO S4
ADG5412BF/
ADG5413BF
tDIGRESP
FF
OUTPUT
(VFF)
GND
0.1VOUT
*INCLUDES TRACK CAPACITANCE
Figure 43. Interrupt Flag Response Time, tDIGRESP
Rev. B | Page 20 of 28
12473-038
0V
CL*
12pF
Data Sheet
ADG5412BF/ADG5413BF
VDD
VSS
0.1µF
0.1µF
VDD + 0.5V
VDD
SOURCE
VOLTAGE
(VS)
VSS
S1
D1
VS
S2 TO S4
0V
ADG5412BF/
ADG5413BF
FF
tDIGREC
CL*
12pF
0.9VOUT
OUTPUT
(VFF)
0V
*INCLUDES TRACK CAPACITANCE
12473-039
GND
Figure 44. Interrupt Flag Recovery Time, tDIGREC
VDD
VSS
0.1µF
0.1µF
VDD + 0.5V
VDD
SOURCE
VOLTAGE
(VS)
VSS
S1
VS
D1
S2 TO S4
0V
5V
ADG5412BF/
ADG5413BF
tDIGREC
RPULLUP
1kΩ
OUTPUT
FF
5V
CL*
12pF
3V
GND
0V
12473-040
OUTPUT
(VFF)
*INCLUDES TRACK CAPACITANCE
Figure 45. Interrupt Flag Recovery Time, tDIGREC, with a 1 kΩ Pull-Up Resistor
VDD
VSS
VSS
D1
S2
VS2
D2
RL
300Ω
IN1,
IN2
VOUT2
RL
300Ω
CL
35pF
VOUT1
CL
35pF
VOUT1
VOUT2
ADG5413BF
50%
0V
90%
90%
0V
90%
90%
0V
GND
tD
Figure 46. Break-Before-Make Time Delay, tD
Rev. B | Page 21 of 28
50%
tD
12473-041
VDD
S1
VS1
VIN
0.1µF
0.1µF
ADG5412BF/ADG5413BF
Data Sheet
VDD
VSS
ADG5412BF/
ADG5413BF
0.1µF
0.1µF
VIN
Sx
VS
50%
50%
VSS
VOUT
Dx
RL
300Ω
INx
CL
35pF
90%
VOUT
10%
GND
12473-042
VDD
tOFF
tON
Figure 47. Switching Times, tON and tOFF
RS
VS
VDD
VSS
VDD
VSS
Sx
Dx
0.1µF
ADG5412BF/
ADG5413BF
VOUT
VIN
OFF
ON
CL
1nF
INx
VOUT
QINJ = CL × ∆VOUT
GND
Figure 48. Charge Injection, QINJ
Rev. B | Page 22 of 28
∆VOUT
12473-043
0.1µF
Data Sheet
ADG5412BF/ADG5413BF
TERMINOLOGY
tOFF
tOFF represents the delay between applying the digital control
input and the output switching off (see Figure 47).
IDD
IDD represents the positive supply current.
ISS
ISS represents the negative supply current.
VD, VS
VD and VS represent the analog voltage on the Dx pins and the
Sx pins, respectively.
RON
RON represents the ohmic resistance between the Dx pins and
the Sx pins.
ΔRON
ΔRON represents the difference between the RON of any two
channels.
RFLAT(ON)
RFLAT(ON) is the flatness that is defined as the difference between
the maximum and minimum value of on resistance measured
over the specified analog signal range.
IS (Off)
IS (Off) is the source leakage current with the switch off.
tD
tD represents the off time measured between the 90% point of both
switches when switching from one address state to another.
tDIGRESP
tDIGRESP is the time required for the FF pin to go low (0.3 V),
measured with respect to voltage on the source pin exceeding
the supply voltage by 0.5 V.
tDIGREC
tDIGREC is the time required for the FF pin to return high (3 V),
measured with respect to voltage on the Sx pin falling below the
supply voltage plus 0.5 V.
tRESPONSE
tRESPONSE represents the delay between the source voltage
exceeding the supply voltage by 0.5 V and the drain voltage
falling to 90% of the supply voltage.
ID (Off)
ID (Off) is the drain leakage current with the switch off.
tRECOVERY
tRECOVERY represents the delay between an overvoltage on the Sx
pin falling below the supply voltage plus 0.5 V and the drain
voltage rising from 0 V to 10% of the supply voltage.
ID (On), IS (On)
ID (On) and IS (On) represent the channel leakage currents with
the switch on.
Off Isolation
Off isolation is a measure of unwanted signal coupling through
an off switch.
VINL
VINL is the maximum input voltage for Logic 0.
Charge Injection
Charge injection is a measure of the glitch impulse transferred
from the digital input to the analog output during switching.
VINH
VINH is the minimum input voltage for Logic 1.
Channel-to-Channel Crosstalk
Crosstalk is a measure of unwanted signal that is coupled through
from one channel to another as a result of parasitic capacitance.
IINL, IINH
IINL and IINH represent the low and high input currents of the
digital inputs.
CD (Off)
CD (Off) represents the off switch drain capacitance, which is
measured with reference to ground.
CS (Off)
CS (Off) represents the off switch source capacitance, which is
measured with reference to ground.
CD (On), CS (On)
CD (On) and CS (On) represent on switch capacitances, which
are measured with reference to ground.
−3 dB Bandwidth
Bandwidth is the frequency at which the output is attenuated
by 3 dB.
On Response
On response is the frequency response of the on switch.
Insertion Loss
Insertion loss is the loss due to the on resistance of the switch.
Total Harmonic Distortion Plus Noise (THD + N)
THD + N is the ratio of the harmonic amplitude plus noise of
the signal to the fundamental.
CIN
CIN is the digital input capacitance.
tON
tON represents the delay between applying the digital control
input and the output switching on (see Figure 47).
Rev. B | Page 23 of 28
ADG5412BF/ADG5413BF
Data Sheet
AC Power Supply Rejection Ratio (ACPSRR)
ACPSRR is the ratio of the amplitude of signal on the output to
the amplitude of the modulation. ACPSRR is a measure of the
ability of the device to avoid coupling noise and spurious signals
that appear on the supply voltage pin to the output of the switch.
The dc voltage on the device is modulated by a sine wave of
0.62 V p-p.
VT
VT is the voltage threshold at which the overvoltage protection
circuitry engages. See Figure 28.
Rev. B | Page 24 of 28
Data Sheet
ADG5412BF/ADG5413BF
THEORY OF OPERATION
SWITCH ARCHITECTURE
Each channel of the ADG5412BF/ADG5413BF consists of a
parallel pair of N-channel diffused metal-oxide semiconductor
(NDMOS) and P-channel DMOS (PDMOS) transistors. This
construction provides excellent performance across the signal
range. The ADG5412BF/ADG5413BF channels operate as standard switches when input signals with a voltage between VSS and
VDD are applied. For example, the on resistance is 10 Ω typically
and the appropriate control pin, INx, controls the opening or
closing of the switch.
Additional internal circuitry enables the switch to detect overvoltage inputs by comparing the voltage on the source or drain
pin with VDD and VSS. A signal is considered overvoltage if it
exceeds the supply voltages by the voltage threshold, VT. The
threshold voltage is typically 0.7 V, but can range from 0.8 V
(when operating at −40°C) down to 0.6 V at +125°C. See Figure 28
to see the change in VT with operating temperature.
The maximum voltage that can be applied to any switch input is
+55 V or −55 V. When the device is powered using the singlesupply of 25 V or greater, the maximum signal level reduces
from −55 V to −40 V at VDD = 40 V to remain within the 80 V
maximum rating. Construction of the process allows the channel
to withstand 80 V across the switch when it is opened. These
overvoltage limits apply whether the power supplies are present
or not.
ESD Performance
The ADG5412BF/ADG5413BF has an ESD rating of 3 kV for
the human body model (HBM). ESD protection cells allow the
voltage at the pins to exceed the supply voltage. See Figure 49
for a switch channel overview.
Trench Isolation
In the ADG5412BF and ADG5413BF, an insulating oxide layer
(trench) is placed between the NDMOS and the PDMOS
transistors of each switch. Parasitic junctions, which occur between
the transistors in junction-isolated switches, are eliminated, and
the result is a switch that is latch-up immune under all
circumstances. These devices pass a JESD78D latch-up test of
±500 mA for 1 sec, which is the harshest test in the specification.
Dx
SWITCH
DRIVER
P-WELL
N-WELL
FAULT
DETECTOR
TRENCH
12473-048
AND
INx
PDMOS
ESD
PROTECTION
Sx
FAULT
DETECTOR
NDMOS
BURIED OXIDE LAYER
Figure 49. Switch Channel and Control Function
HANDLE WAFER
When an overvoltage condition is detected on either the source pin
or drain pin, the switch is automatically opened regardless of the
digital logic state, INx. The source and drain pins both become
high impedance and ensure that no current flows through the
switch. In Figure 29, the voltage on the drain pin can be seen to
follow the voltage on the source pin until the switch has turned off
completely and the drain voltage discharges through the load. The
maximum voltage and the rate at which the output voltage discharges is dependent on the load at the pin. The ADG5412F/
ADG5413F are pin-compatible devices that are overvoltage
protected on the source pin only, with ESD diodes on the drain
pin that limit the maximum voltage while the switch is opening.
Rev. B | Page 25 of 28
Figure 50. Trench Isolation
12473-049
ESD
PROTECTION
During overvoltage conditions, the leakage current into and out
of the switch pins is limited to tens of microamperes. This limit
protects the switch and connected circuitry from over stresses as
well as restricting the current drawn from the signal source. When
an overvoltage event occurs, the channels undisturbed by the
overvoltage input continue to operate normally without
additional crosstalk.
ADG5412BF/ADG5413BF
Data Sheet
FAULT PROTECTION
When the voltages at the switch inputs exceed VDD or VSS by VT,
the switch turns off or, if the device is unpowered, the switch
remains off. The switch input remains high impedance regardless
of the digital input state or the load resistance, and the output
acts as a virtual open circuit. Signal levels up to +55 V and
−55 V are blocked in both the powered and unpowered condition
as long as the 80 V limitation between the switch and supply
pins is met.
+22V
0V
–22V
VDD
GND
VSS
ADG5413BF
‒55V
+55V
S1
D1
S2
D2
S3
D3
S4
D4
FAULT
DETECTION
+ SWITCH
DRIVER
Power-On Protection
The following three conditions must be satisfied for the switch
to be in the on condition:
5V
VDD to VSS ≥ 8 V
Input signal is between VSS − VT and VDD + VT
Digital logic control input, INx, is turned on
IN1 IN2 IN3 IN4
FF
0V
12473-050
+22V
Figure 51. ADG5413BF in Multiplexer Configuration under Overvoltage
Conditions
When the switch is turned on, signal levels up to the supply rails
are passed.
The switch responds to an analog input that exceeds VDD or VSS
by a threshold voltage, VT, by turning off. The absolute input
voltage limits are −55 V and +55 V, while maintaining an 80 V
limit between the source pin and the supply rails. The switch
remains off until the voltage at the switch pin returns to between
VDD and VSS.
The fault response time (tRESPONSE) when powered by ±15 V
dual-supply is typically 460 ns, and the fault recovery time
(tRECOVERY) is 720 ns. These vary with supply voltages and output
load conditions.
Exceeding ±55 V on any switch input may damage the ESD
protection circuitry on the device.
The maximum stress across the switch channel is 80 V; therefore,
the user must pay close attention to this limit if using the device
in a multiplexed configuration and one channel is on while another
channel is in a fault condition.
Power-Off Protection
When no power supplies are present, the switch remains in the
off condition, and the switch inputs are high impedance. This
state ensures that no current flows and prevents damage to the
switch or downstream circuitry. The switch output is a virtual
open circuit.
The switch remains off regardless of whether the VDD and VSS
supplies are 0 V or floating. A GND reference must always be
present to ensure proper operation. Signal levels of up to ±55 V
are blocked in the unpowered condition.
Digital Input Protection
The ADG5412BF and the ADG5413BF can tolerate digital
input signals being present on the device without power. When
the device is unpowered, the switch is guaranteed to be in the
off state, regardless of the state of the digital logic signals.
The digital inputs are protected against positive faults up to 44 V.
The digital inputs do not offer protection against negative
overvoltages. ESD protection diodes connected to GND are
present on the digital inputs.
For example, consider the case where the device is set up in a
multiplexer configuration as shown in Figure 51.
Overvoltage Interrupt Flag
The voltages on the switch inputs of the ADG5412BF and the
ADG5413BF are continuously monitored and the state of the
switch is indicated by an active low digital output pin, FF.
VDD/VSS = ±22 V, S1 = 22 V, all switches are on
D1 is externally multiplexed with D2; therefore, D1 and D2
= 22 V
S2 has a −55 V fault and S3 has a +55 V fault
The voltage between S2 and D1 or between S2 and D2 =
+22 V − (−55 V) = +77 V
The voltage between S3 and D3 = 55 V− 0 V = 55 V
The voltage on the FF pin indicates if any of the switch input
pins are experiencing a fault condition. The output of the FF pin
is a nominal 3 V when all switch pins are within normal operating
range. If any switch pin voltage exceeds the supply voltage by
VT, the FF output reduces to below 0.8 V.
These calculations are all within device specifications: 55 V
maximum fault on switch inputs and a maximum of 80 V across
the off switch channel.
Rev. B | Page 26 of 28
Data Sheet
ADG5412BF/ADG5413BF
APPLICATIONS INFORMATION
The overvoltage protected family of switches and multiplexers
provide a robust solution for instrumentation, industrial,
aerospace, and other harsh environments where overvoltage
signals can be present and the system must remain operational
both during and after the overvoltage has occurred.
POWER SUPPLY RAILS
To guarantee correct operation of the device, 0.1 μF decoupling
capacitors are required.
The ADG5412BF and the ADG5413BF can operate with bipolar
supplies between ±5 V and ±22 V. The supplies on VDD and
VSS need not be symmetrical but the VDD to VSS range must
not exceed 44 V. The ADG5412BF and the ADG5413BF can
also operate with single supplies between 8 V and 44 V with
VSS connected to GND.
These devices are fully specified at ±15 V, ±20 V, +12 V, and
+36 V supply ranges.
The ADG5412BF/ADG5413BF enable the designer to remove
these resistors and retain the precision performance without
compromising the protection of the circuit.
HIGH VOLTAGE SURGE SUPPRESSION
The ADG5412BF/ADG5413BF is not intended for use in very
high voltage applications. The maximum operating voltage of
the transistor is 80 V. In applications where the inputs are likely
to be subject to overvoltages exceeding the breakdown voltage,
use transient voltage suppressors (TVSs), or similar.
INTELLIGENT FAULT DETECTION
The ADG5412BF/ADG5413BF digital output pin, FF, can
interface with a microprocessor or control system and be used
as an interrupt flag. This feature provides real-time diagnostic
information on the state of the device and the system to which it
connects.
The control system can use the digital interrupt to start a variety
of actions, such as
POWER SUPPLY SEQUENCING PROTECTION
The switch channel remains open when the device is unpowered
and signals from −55 V to +55 V can be applied without damaging
the device. Only when the supplies are connected and a suitable
digital control signal is placed on the INx pin does the switch
channel close and then allow a signal to pass. Placing the
ADG5412BF/ADG5413BF between external connectors and
sensitive components offers protection in systems where a
signal is presented to the switch pins before the supply voltages
are available.
SIGNAL RANGE
The ADG5412BF/ADG5413BF switches have fault detection
circuitry on their inputs that compares the voltage levels at the
switch terminals with VDD and VSS, relative to ground. To protect
downstream circuitry from overvoltages, supply the ADG5412BF/
ADG5413BF by voltages that match the intended signal range.
The low on-resistance switch allows signals up to the supply
rails to be passed with very little distortion. A signal that
exceeds the supply rail by the threshold voltage is then blocked.
This offers protection to both the device and any downstream
circuitry.
LOW IMPEDANCE CHANNEL PROTECTION
The ADG5412BF/ADG5413BF can be used as protective
elements in signal chains that are sensitive to both channel
impedance and overvoltage signals. Traditionally, series
resistors are used to limit the current during an overvoltage
condition to protect susceptible components. These series
resistors affect the performance of the signal chain and reduce
the precision that can be reached. A compromise must be
reached on the value of the series resistance that is high enough
to sufficiently protect sensitive components but low enough that
the precision performance of the signal chain is not sacrificed.
Initiating investigation into the source of the overvoltage fault
Shutting down critical systems in response to the overvoltage
Data recorders marking data during these events as
unreliable or out of specification
For systems that are sensitive during a start-up sequence, the
active low operation of the flag allows the system to ensure that
the ADG5412BF/ADG5413BF are powered on and that all
input voltages are within normal operating range before
initiating operation.
The FF pin is a weak pull-up, which allows the signals to be
combined into a single interrupt for larger modules that contain
multiple devices.
The recovery time, tDIGREC, can be decreased from a typical 60 μs
to 600 ns by using a 1 kΩ pull-up resistor.
LARGE VOLTAGE, HIGH FREQUENCY SIGNALS
Figure 31 illustrates the voltage range and frequencies that the
ADG5412BF/ADG5413BF can reliably convey. For signals that
extend across the full signal range from VSS to VDD, keep the
frequency below 3 MHz. If the required frequency is greater
than 3 MHz, decrease the signal voltage appropriately to ensure
signal integrity.
Rev. B | Page 27 of 28
ADG5412BF/ADG5413BF
Data Sheet
OUTLINE DIMENSIONS
5.10
5.00
4.90
16
9
4.50
4.40
4.30
6.40
BSC
1
8
PIN 1
1.20
MAX
0.15
0.05
0.30
0.19
0.65
BSC
COPLANARITY
0.10
0.20
0.09
0.75
0.60
0.45
8°
0°
SEATING
PLANE
COMPLIANT TO JEDEC STANDARDS MO-153-AB
Figure 52. 16-Lead Thin Shrink Small Outline Package [TSSOP]
(RU-16)
Dimensions shown in millimeters
4.10
4.00 SQ
3.90
PIN 1
INDICATOR
0.35
0.30
0.25
0.65
BSC
16
13
PIN 1
INDICATOR
12
1
EXPOSED
PAD
2.70
2.60 SQ
2.50
4
9
0.80
0.75
0.70
0.45
0.40
0.35
8
0.05 MAX
0.02 NOM
COPLANARITY
0.08
0.20 REF
SEATING
PLANE
5
BOTTOM VIEW
0.20 MIN
FOR PROPER CONNECTION OF
THE EXPOSED PAD, REFER TO
THE PIN CONFIGURATION AND
FUNCTION DESCRIPTIONS
SECTION OF THIS DATA SHEET.
COMPLIANT TO JEDEC STANDARDS MO-220-WGGC.
08-16-2010-C
TOP VIEW
Figure 53. 16-Lead Lead Frame Chip Scale Package [LFCSP_WQ]
4 mm × 4 mm Body, Very Very Thin Quad
(CP-16-17)
Dimensions shown in millimeters
ORDERING GUIDE
Model1
ADG5412BFBRUZ
ADG5412BFBRUZ-RL7
ADG5412BFBCPZ-RL7
EVAL-ADG5412BFEBZ
ADG5413BFBRUZ
ADG5413BFBRUZ-RL7
ADG5413BFBCPZ-RL7
1
Temperature Range
−40°C to +125°C
−40°C to +125°C
−40°C to +125°C
−40°C to +125°C
−40°C to +125°C
−40°C to +125°C
Package Description
16-Lead Thin Shrink Small Outline Package [TSSOP]
16-Lead Thin Shrink Small Outline Package [TSSOP]
16-Lead Lead Frame Chip Scale Package [LFCSP_WQ]
Evaluation Board
16-Lead Thin Shrink Small Outline Package [TSSOP]
16-Lead Thin Shrink Small Outline Package [TSSOP]
16-Lead Lead Frame Chip Scale Package [LFCSP_WQ]
Z = RoHS Compliant Part.
©2014–2016 Analog Devices, Inc. All rights reserved. Trademarks and
registered trademarks are the property of their respective owners.
D12473-0-1/16(B)
Rev. B | Page 28 of 28
Package Option
RU-16
RU-16
CP-16-17
RU-16
RU-16
CP-16-17
工商网监
湘ICP备2023018690号
