±60 V Fault Protection and Detection,
11 Ω RON, Dual SPST Switch
ADG5421F
Data Sheet
FEATURES
FUNCTIONAL BLOCK DIAGRAM
Overvoltage fault protection up to ±60 V on S1 and S2 pins
Power-off protection up to ±60 V on S1 and S2 pins
Known state without digital inputs present
Low on resistance of 11 Ω typical
Ultraflat, on resistance
Latch-up immune under any circumstance
3.5 kV human body model (HBM) ESD rating
VSS to VDD −2 V signal range
Fully specified at ±15 V, ±20 V, +12 V, and +36 V
±5 V to ±22 V dual-supply operation
8 V to 44 V single-supply operation
10-lead, 3 mm × 2 mm, LFCSP
ADG5421F
S1
D1
S2
D2
FF
25051-001
FAULT
DETECTION
AND SWITCH
DRIVER
IN1 IN2
Figure 1.
APPLICATIONS
Analog input and output modules
Process control and distributed control systems
Data acquisition
Instrumentation
Avionics
Automatic test equipment
Communication systems
Relay replacement
COMPANION PRODUCTS
Precision 24-Bit ADC: AD7768-1
Precision 16-Bit, 2 MSPS SAR ADC: AD4000
GENERAL DESCRIPTION
The ADG5421F is a dual SPST, low on resistance switch that
features overvoltage protection, power-off protection, and
overvoltage detection on the source pins.
When no power supplies are present, the switch remains in the
off condition, and the switch inputs are high impedance. When
powered, if the analog input signal levels on either of the Sx pins
exceed VDD or VSS by the threshold voltage, VT, both switches
turn off together, and the open-drain fault flag (FF) pin pulls to a
logic low. Input signal levels up to +60 V or −60 V relative to
ground are blocked in both the powered and unpowered
condition.
The switches turn on with a Logic 1 input and conduct equally
well in both directions. The digital input is compatible with
1.8 V logic inputs over the full operating supply range.
Rev. 0
PRODUCT HIGHLIGHTS
1.
2.
3.
4.
5.
Source pins are protected against voltages greater than the
supply rails, up to −60 V and +60 V in both powered and
unpowered state.
Overvoltage detection with digital output indicates
operating state of switches.
Trench isolation guards against latch-up.
The ADG5421F can operate from a dual supply of ±5 V up
to ±22 V or a single power supply of +8 V up to +44 V.
Negative channel metal oxide semiconductor (NMOS)
only architecture requires 2 V headroom towards VDD and
provides low RON and low RON flatness across the signal
range of VSS to VDD − 2 V.
Document Feedback
Information furnished by Analog Devices is believed to be accurate and reliable. However, no
responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other
rights of third parties that may result from its use. Specifications subject to change without notice.
No license is granted by implication or otherwise under any patent or patent rights of Analog
Devices. Trademarks and registered trademarks are the property of their respective owners.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700
©2020 Analog Devices, Inc. All rights reserved.
Technical Support
www.analog.com
ADG5421F
Data Sheet
TABLE OF CONTENTS
Features .............................................................................................. 1
Typical Performance Characteristics .......................................... 16
Applications ...................................................................................... 1
Test Circuits .................................................................................... 21
General Description ......................................................................... 1
Terminology.................................................................................... 25
Functional Block Diagram .............................................................. 1
Theory of Operation ...................................................................... 26
Companion Products ....................................................................... 1
Switch Architecture ................................................................... 26
Product Highlights ........................................................................... 1
Overvoltage Fault Protection ................................................... 27
Revision History ............................................................................... 2
Applications Information ............................................................. 28
Specifications .................................................................................... 3
Power Supply Rails..................................................................... 28
±15 V Dual Supply ....................................................................... 3
Power Supply Recommendations ............................................ 28
±20 V Dual Supply ....................................................................... 5
Power Supply Sequencing Protection ..................................... 28
12 V Single Supply ....................................................................... 8
Signal Range ................................................................................ 28
36 V Single Supply ..................................................................... 11
Intelligent Fault Detection ........................................................ 28
Continuous Current per Channel, S or D............................... 13
Switch in a Known State............................................................ 28
Absolute Maximum Ratings ......................................................... 14
High Voltage Surge Suppression ............................................. 29
Thermal Resistance .................................................................... 14
Related Products......................................................................... 30
Electrostatic Discharge (ESD) Ratings .................................... 14
Outline Dimensions ....................................................................... 31
ESD Caution................................................................................ 14
Ordering Guide .......................................................................... 31
Pin Configuration and Function Descriptions .......................... 15
REVISION HISTORY
10/2020—Revision 0: Initial Version
Rev. 0 | Page 2 of 31
Data Sheet
ADG5421F
SPECIFICATIONS
Table 1. Operating Supply Voltages
Parameter
SUPPLY VOLTAGE
Dual
Single
Min
Typ
±5
8
Max
Unit
±22
44
V
V
±15 V DUAL SUPPLY
VDD = 15 V ± 10%, VSS = −15 V ± 10%, and GND = 0 V, unless otherwise noted.
Table 2.
Parameter
ANALOG SWITCH
Analog Signal Range
On Resistance, RON
On-Resistance Flatness, RFLAT (ON)
On-Resistance Matching, RMATCH (ON)
LEAKAGE CURRENTS
Source Off Leakage, IS (Off)
+25°C
14
11
13.5
0.3
0.7
0.02
0.06
0.02
0.2
FAULT
Threshold Voltage, VT
Source Leakage Current, IS
With Overvoltage
Power Supplies Grounded or
Floating
Ω typ
17.5
20.5
17
20
0.8
0.9
0.1
0.1
0.35
0.45
Ω max
Ω typ
Ω max
Ω typ
Ω max
Ω typ
Ω max
Ω typ
Ω max
nA typ
±2.5
±22
nA max
±8
nA max
±0.05
±0.05
±0.3
Unit
Test Conditions/Comments
VDD = +13.5 V, VSS = −13.5 V
V
±0.05
±0.2
Channel On Leakage, ID (On), IS (On)
−40°C to +125°C
VSS to
VDD − 2
11.5
±0.2
Drain Off Leakage, ID (Off)
−40°C to +85°C
nA typ
±2.5
±3.5
±22
nA max
±8
nA max
±30
±14
nA typ
nA max
nA max
0.7
Source voltage (VS) = VSS to 10 V,
source current (IS) = 10 mA, see
Figure 31
VS = VSS to 10 V, IS = 10 mA
VS = VSS to 9 V, IS = 10 mA
VS = VSS to 9 V, IS = 10 mA
VS = VSS to 10 V, IS = 10 mA
VS = VSS to 10 V, IS = 10 mA
VS = VSS to 9 V, IS = 10 mA
VS = VSS to 9 V, IS = 10 mA
VS = VSS to 10 V, IS = 10 mA
VS = VSS to 10 V, IS = 10 mA
VDD = +16.5 V, VSS = −16.5 V
VS = ±10 V, drain voltage (VD) = 10 V,
see Figure 32
VS = ±10 V, drain voltage (VD) = 10 V
VS = ±10 V, drain voltage (VD) = 10 V,
−40°C to +105°C
VS = ±10 V, VD = 10 V, see Figure 32
VS = ±10 V, VD = 10 V
VS = ±10 V, VD = 10 V,
−40°C to +105°C
VS = ±10 V, VD = ±10 V, see Figure 33
VS = ±10 V, VD = ±10 V
VS = ±10 V, VD = ±10 V,
−40°C to +105°C
V
See Figure 25
±30
µA typ
±5.5
µA typ
VDD = +16.5 V, VSS = −16.5 V,
GND = 0 V, VS = ±60 V, see Figure 34
VDD = 0 V or floating, VSS = 0 V or
floating, GND = 0 V, IN = 0 V or
floating, VS = ±60 V, see Figure 35
Rev. 0 | Page 3 of 31
ADG5421F
Parameter
Drain Leakage Current, ID
With Overvoltage
Data Sheet
+25°C
±2
±20
±0.1
±0.2
±2
Off Time, tOFF
Break-Before-Make Time Delay, tD
Overvoltage Response Time, tRESPONSE
Positive
Negative
Overvoltage Recovery Time, tRECOVERY
Interrupt Flag Response Time, tDIGRESP
nA typ
VDD = +16.5 V, VSS = −16.5 V,
GND = 0 V, VS = ±60 V, see Figure 34
VDD = +16.5 V, VSS = −16.5 V,
GND = 0 V, VS = ±60 V
VDD = 0 V, VSS = 0 V, GND = 0 V,
VS = ±60 V, IN = 0 V, see Figure 35
VDD = 0 V, VSS = 0 V, GND = 0 V,
VS = ±60 V, IN = 0 V
VDD = floating, VSS = floating, GND =
0 V, VS = ±60 V, IN = 0 V, see Figure 35
nA max
nA max
±0.1
µA typ
1.3
0.8
5
0.4
V min
V max
µA typ
µA max
pF typ
V max
11.2
µs typ
0.7
14.1
140
14.1
14.1
µs max
ns typ
170
10
7.7
170
170
7.6
7.6
ns max
µs typ
µs min
190
190
540
570
12.8
12.8
140
140
160
180
420
510
9.8
12.8
110
130
Interrupt Flag Recovery Time, tDIGREC
Test Conditions/Comments
±20
1
Digital Input Capacitance, CIN
Output Voltage Low, VOL
DYNAMIC CHARACTERISTICS
On Time, tON
Unit
nA typ
Power Supplies Floating
DIGITAL INPUTS AND OUTPUTS
Input Voltage High, VINH
Input Voltage Low, VINL
Input Low or High Current, IINL or IINH
−40°C to +125°C
±0.1
±0.2
Power Supplies Grounded
−40°C to +85°C
1.8
2.4
ns typ
ns max
ns typ
ns max
µs typ
µs max
ns typ
ns max
µs typ
2.6
2.6
µs max
Charge Injection, QINJ
−135
pC typ
Off Isolation
−85
dB typ
Channel to Channel Crosstalk
−78
dB typ
Total Harmonic Distortion Plus Noise,
THD + N
0.001
% typ
Rev. 0 | Page 4 of 31
Input voltage (VIN) = 0 V or 5 V
VIN = 0 V or 5 V
Fault flag current (IFF) = 2 mA
Load resistance (RL) = 300 Ω,
load capacitance (CL) = 35 pF,
VS = 10 V, see Figure 45
RL = 300 Ω, CL = 35 pF, VS = 10 V
RL = 300 Ω, CL = 35 pF, VS = 10 V, see
Figure 45
RL = 300 Ω, CL = 35 pF, VS = 10 V
RL = 300 Ω, CL = 35 pF, VS = 10 V
RL = 300 Ω, CL = 35 pF, VS = 10 V
RL = 1 kΩ, CL = 5 pF, see Figure 40
RL = 1 kΩ, CL = 5 pF
RL = 1 kΩ, CL = 5 pF, see Figure 41
RL = 1 kΩ, CL = 5 pF
RL = 1 kΩ, CL = 5 pF, see Figure 42
RL = 1 kΩ, CL = 5 pF
Pull-up resistor (RPULLUP) = 1 kΩ, CL =
12 pF, pull-up voltage (VPULL_UP) = 5 V,
see Figure 43
RPULLUP = 1 kΩ, CL = 12 pF,
VPULL_UP = 5 V
RPULLUP = 1 kΩ, CL = 12 pF,
VPULL_UP = 5 V, see Figure 44
RPULLUP = 1 kΩ, CL = 12 pF,
VPULL_UP = 5 V
VS = 0 V, source resistor (RS) = 0 Ω,
CL = 1 nF, see Figure 46
RL = 50 Ω, CL = 5 pF,
frequency (f) = 1 MHz, see Figure 36
RL = 50 Ω, CL = 5 pF, f = 1 MHz, see
Figure 37
RL = 10 kΩ, VS = 10 V p-p,
f = 20 Hz to 20 kHz, see Figure 39
Data Sheet
ADG5421F
Parameter
−3 dB Bandwidth
Insertion Loss
+25°C
630
−0.95
Source Off Capacitance, CS (Off)
Drain Off Capacitance, CD (Off)
Drain On Capacitance and Source On
Capacitance, CD (On) and CS (On)
Drain On Capacitance and Source On
Capacitance Flatness, CDFLAT (On)
and CSFLAT (On)
Capacitance Matching, CMATCH (On)
POWER REQUIREMENTS
7
5
11
pF typ
pF typ
pF typ
Test Conditions/Comments
RL = 50 Ω, CL = 5 pF, see Figure 38
RL = 50 Ω, CL = 5 pF, f = 1 MHz, see
Figure 38
VS = 0 V, f = 1 MHz
VS = 0 V, f = 1 MHz
VS = 0 V, f = 1 MHz
2.5
pF typ
VS = VSS to VDD − 2 V, f = 1 MHz
0.3
pF typ
VS = VSS to VDD − 2 V, f = 1 MHz
VDD = +16.5 V, VSS = −16.5 V, GND = 0 V,
digital inputs = 0 V or +5 V
Normal Mode
Positive Supply Current, IDD
GND Current, IGND
Negative Supply Current, ISS
Fault Mode
IDD
IGND
ISS
−40°C to +85°C
130
205
55
90
75
115
−40°C to +125°C
205
90
115
Unit
MHz typ
dB typ
µA typ
µA max
µA typ
µA max
µA typ
µA max
VS = ±60 V
185
270
155
210
55
90
270
210
90
µA typ
µA max
µA typ
µA max
µA typ
µA max
±20 V DUAL SUPPLY
VDD = 20 V ± 10%, VSS = −20 V ± 10%, and GND = 0 V, unless otherwise noted.
Table 3.
Parameter
ANALOG SWITCH
Analog Signal Range
RON
RFLAT (ON)
RMATCH (ON)
+25°C
−40°C to +85°C
−40°C to +125°C
VSS to
VDD − 2
11.5
14
11
13.5
0.6
0.7
0.02
0.06
0.02
0.2
Unit
Test Conditions/Comments
VDD = +18 V, VSS = −18 V
V
Ω typ
17.5
20.5
17
20
0.8
0.9
0.1
0.1
0.35
0.45
Rev. 0 | Page 5 of 31
Ω max
Ω typ
Ω max
Ω typ
Ω max
Ω typ
Ω max
Ω typ
Ω max
VS = VSS to 15 V, IS = 10 mA,
see Figure 31
VS = VSS to 15 V, IS = 10 mA
VS = VSS to 13.5 V, IS = 10 mA
VS = VSS to 13.5 V, IS = 10 mA
VS = VSS to 15 V, IS = 10 mA
VS = VSS to 15 V, IS = 10 mA
VS = VSS to 13.5 V, IS = 10 mA
VS = VSS to 13.5 V, IS = 10 mA
VS = VSS to 15 V, IS = 10 mA
VS = VSS to 15 V, IS = 10 mA
ADG5421F
Parameter
LEAKAGE CURRENTS
IS (Off)
Data Sheet
+25°C
FAULT
VT
IS
With Overvoltage
±0.05
±0.3
Unit
nA typ
±2.5
±22
nA max
±8
nA max
±0.05
±0.2
ID (On), IS (On)
−40°C to +125°C
±0.05
±0.2
ID (Off)
−40°C to +85°C
nA typ
±2.5
±3.5
±22
nA max
±8
nA max
±30
±14
nA typ
nA max
nA max
0.7
Power Supplies Grounded or
Floating
Test Conditions/Comments
VDD = +22 V, VSS = −22 V
VS = ±15 V, VD = 15 V, see Figure 32
VS = ±15 V, VD = 15 V
VS = ±15 V, VD = 15 V,
−40°C to +105°C
VS = ±15 V, VD = 15 V, see Figure 32
VS = ±15 V, VD = 15 V
VS = ±15 V, VD = 15 V,
−40°C to +105°C
VS = ±15 V, VD = ±15 V, see Figure 33
VS = ±15 V, VD = ±15 V
VS = ±15 V, VD = ±15 V,
−40°C to +105°C
V typ
See Figure 25
±30
µA typ
±5.5
µA typ
VDD = +22 V, VSS = −22 V,
GND = 0 V, VS = ±60 V, see Figure 34
VDD = 0 V or floating, VSS = 0 V or
floating, GND = 0 V, IN = 0 V or
floating, VS = ±60 V, see Figure 35
ID
With Overvoltage
±0.1
±0.2
Power Supplies Grounded
nA typ
±2
±0.1
±0.2
±2
±20
nA max
±0.1
µA typ
1.3
0.8
5
0.4
V min
V max
µA typ
µA max
pF typ
V max
12.6
µs typ
0.7
1
CIN
VOL
DYNAMIC CHARACTERISTICS
tON
tOFF
tD
nA max
nA typ
Power Supplies Floating
DIGITAL INPUTS AND OUTPUTS
VINH
VINL
IINL or IINH
±20
15.9
140
15.9
15.9
µs max
ns typ
160
11.5
8.9
160
160
8.8
8.8
ns max
µs typ
µs min
Rev. 0 | Page 6 of 31
VDD = +22 V, VSS = −22 V,
GND = 0 V, VS = ±60 V, see Figure 34
VDD = +22 V, VSS = −22 V,
GND = 0 V, VS = ±60 V
VDD = 0 V, VSS = 0 V, GND = 0 V,
VS = ±60 V, IN = 0 V, see Figure 35
VDD = 0 V, VSS = 0 V, GND = 0 V,
VS = ±60 V, IN = 0 V
VDD = floating, VSS = floating, GND =
0 V, VS = ±60 V, IN = 0 V, see Figure 35
VIN = 0 V or 5 V
VIN = 0 V or 5 V
IFF = 2 mA
RL = 300 Ω, CL = 35 pF, VS = 10 V,
see Figure 45
RL = 300 Ω, CL = 35 pF, VS = 10 V
RL = 300 Ω, CL = 35 pF, VS = 10 V,
see Figure 45
RL = 300 Ω, CL = 35 pF, VS = 10 V
RL = 300 Ω, CL = 35 pF, VS = 10 V
RL = 300 Ω, CL = 35 pF, VS = 10 V
Data Sheet
Parameter
tRESPONSE
Positive
Negative
tRECOVERY
tDIGRESP
ADG5421F
+25°C
160
190
360
440
11.7
14.8
120
140
tDIGREC
−40°C to +85°C
−40°C to +125°C
190
190
460
490
14.8
14.9
140
140
2.2
2.8
Unit
Test Conditions/Comments
ns typ
ns max
ns typ
ns max
µs typ
µs max
ns typ
RL = 1 kΩ, CL = 5 pF, see Figure 40
RL = 1 kΩ, CL = 5 pF
RL = 1 kΩ, CL = 5 pF, see Figure 41
RL = 1 kΩ, CL = 5 pF
RL = 1 kΩ, CL = 5 pF, see Figure 42
RL = 1 kΩ, CL = 5 pF
RPULLUP = 1 kΩ, CL = 12 pF,
VPULL_UP = 5 V, see Figure 43
RPULLUP = 1 kΩ, CL = 12 pF,
VPULL_UP = 5 V
RPULLUP = 1 kΩ, CL = 12 pF,
VPULL_UP = 5 V, see Figure 44
RPULLUP = 1 kΩ, CL = 12 pF,
VPULL_UP = 5 V
VS = 0 V, RS = 0 Ω, CL = 1 nF,
see Figure 46
RL = 50 Ω, CL = 5 pF, f = 1 MHz,
see Figure 36
RL = 50 Ω, CL = 5 pF, f = 1 MHz,
see Figure 37
RL = 10 kΩ, VS = 10 V p-p,
f = 20 Hz to 20 kHz, see Figure 39
RL = 50 Ω, CL = 5 pF, see Figure 38
RL = 50 Ω, CL = 5 pF, f = 1 MHz,
see Figure 38
VS = 0 V, f = 1 MHz
VS = 0 V, f = 1 MHz
VS = 0 V, f = 1 MHz
VS = VSS to VDD − 2 V, f = 1 MHz
VS = VSS to VDD − 2 V, f = 1 MHz
VDD = +22 V, VSS = −22 V, GND = 0 V,
digital inputs = 0 V or +5 V
ns max
µs typ
3
3
µs max
QINJ
−150
pC typ
Off Isolation
−85
dB typ
Channel to Channel Crosstalk
−78
dB typ
THD + N
0.001
% typ
−3 dB Bandwidth
Insertion Loss
630
−0.95
MHz typ
dB typ
6
5
11
2.5
0.3
pF typ
pF typ
pF typ
pF typ
pF typ
130
205
55
90
75
115
µA typ
µA max
µA typ
µA max
µA typ
µA max
CS (Off)
CD (Off)
CD (On), CS (On)
CDFLAT (On), CSFLAT (On)
CMATCH (On)
POWER REQUIREMENTS
Normal Mode
IDD
IGND
ISS
Fault Mode
IDD
IGND
ISS
205
90
115
VS = ±60 V
185
270
155
210
55
90
270
210
90
Rev. 0 | Page 7 of 31
µA typ
µA max
µA typ
µA max
µA typ
µA max
ADG5421F
Data Sheet
12 V SINGLE SUPPLY
VDD = 12 V ± 10%, VSS = 0 V ± 10%, and GND = 0 V, unless otherwise noted.
Table 4.
Parameter
ANALOG SWITCH
Analog Signal Range
RON
RFLAT (ON)
RMATCH (ON)
LEAKAGE CURRENTS
IS (Off)
+25°C
14.5
11
13.5
0.7
1.25
0.01
0.04
0.02
0.2
FAULT
VT
IS
With Overvoltage
Ω typ
18
21.5
17
20
1.3
1.35
0.06
0.06
0.35
0.45
Ω max
Ω typ
Ω max
Ω typ
Ω max
Ω typ
Ω max
Ω typ
Ω max
nA typ
±2.5
±22
±8
±0.05
nA max
nA max
nA typ
±2.5
±22
±8
±0.05
±0.3
Unit
Test Conditions/Comments
VDD = 10.8 V, VSS = 0 V
V
±0.05
±0.2
ID (On), IS (On)
−40°C to +125°C
VSS to
VDD − 2
11.5
±0.2
ID (Off)
−40°C to +85°C
nA max
nA max
nA typ
±3.5
±30
±14
0.7
Power Supplies Grounded or
Floating
nA max
nA max
VS = 0 V to 7.5 V, IS = 10 mA,
see Figure 31
VS = 0 V to 7.5 V, IS = 10 mA
VS = 0 V to 6 V, IS = 10 mA
VS = 0 V to 6 V, IS = 10 mA
VS = 0 V to 7.5 V, IS = 10 mA
VS = 0 V to 7.5 V, IS = 10 mA
VS = 0 V to 6 V, IS = 10 mA
VS = 0 V to 6 V, IS = 10 mA
VS = 0 V to 7.5 V, IS = 10 mA
VS = 0 V to 7.5 V, IS = 10 mA
VDD = 13.2 V, VSS = 0 V
VS = 1 V to 10 V, VD = 10 V to 1 V,
see Figure 32
VS = 1 V to 10 V, VD = 10 V to 1 V
VS = 1 V to 10 V, VD = 10 V to 1 V,
−40°C to +105°C
VS = 1 V to 10 V, VD = 10 V to 1 V,
see Figure 32
VS = 1 V to 10 V, VD = 10 V to 1 V
VS = 1 V to 10 V, VD = 10 V to 1 V,
−40°C to +105°C
VS = 1 V to 10 V, VD = 10 V to 1 V,
see Figure 33
VS = 1 V to 10 V, VD = 10 V to 1 V
VS = 1 V to 10 V, VD = 10 V to 1 V,
−40°C to +105°C
V typ
See Figure 25
±30
µA typ
±5.5
µA typ
VDD = 13.2 V, VSS = 0 V, GND = 0 V,
VS = ±60 V, see Figure 34
VDD = 0 V or floating, VSS = 0 V or
floating, GND = 0 V, IN = 0 V or
floating, VS = ±60 V, see Figure 35
ID
With Overvoltage
±0.1
±0.2
Power Supplies Grounded
±2
±20
±0.1
±0.2
Power Supplies Floating
nA typ
nA max
nA typ
±2
±20
nA max
±0.1
µA typ
Rev. 0 | Page 8 of 31
VDD = +13.2 V, VSS = 0 V, GND = 0 V,
VS = ±60 V, see Figure 34
VDD = +13.2 V, VSS = 0 V, GND = 0 V,
VS = ±60 V
VDD = 0 V, VSS = 0 V, GND = 0 V,
VS = ±60 V, IN = 0 V, see Figure 35
VDD = 0 V, VSS = 0 V, GND = 0 V,
VS = ±60 V, IN = 0 V
VDD = floating, VSS = floating, GND = 0 V,
VS = ±60 V, IN = 0 V, see Figure 35
Data Sheet
Parameter
DIGITAL INPUTS AND OUTPUTS
VINH
VINL
IINL or IINH
ADG5421F
+25°C
−40°C to +85°C
−40°C to +125°C
Unit
Test Conditions/Comments
1.3
0.8
VIN = 0 V or 5 V
VIN = 0 V or 5 V
5
0.4
V min
V max
µA typ
µA max
pF typ
V max
5.3
µs typ
0.7
1
CIN
VOL
DYNAMIC CHARACTERISTICS
tON
tOFF
tD
tRESPONSE
Positive
6.3
200
6.3
6.3
µs max
ns typ
240
4.5
3.5
240
240
3.4
3.4
ns max
µs typ
µs min
250
250
700
700
6.5
6.6
tDIGRESP
210
250
600
700
5.3
6.2
110
130
1.6
130
130
tDIGREC
ns max
µs typ
2.1
−75
2.4
2.4
QINJ
µs max
pC typ
Off Isolation
−69
dB typ
Channel to Channel Crosstalk
−78
dB typ
THD + N
0.0018
% typ
−3 dB Bandwidth
Insertion Loss
570
−0.95
MHz typ
dB typ
CS (Off)
CD (Off)
CD (On), CS (On)
CDFLAT (On), CSFLAT (On)
CMATCH (On)
8
7
11
2
0.4
pF typ
pF typ
pF typ
pF typ
pF typ
Negative
tRECOVERY
Rev. 0 | Page 9 of 31
ns typ
ns max
ns typ
ns max
µs typ
µs max
ns typ
IFF = 2 mA
RL = 300 Ω, CL = 35 pF, VS = 8 V,
see Figure 45
RL = 300 Ω, CL = 35 pF, VS = 8 V
RL = 300 Ω, CL = 35 pF, VS = 8 V,
see Figure 45
RL = 300 Ω, CL = 35 pF, VS = 8 V
RL = 300 Ω, CL = 35 pF, VS = 8 V
RL = 300 Ω, CL = 35 pF, VS = 8 V
RL = 1 kΩ, CL = 5 pF, see Figure 40
RL = 1 kΩ, CL = 5 pF
RPULLUP = 1 kΩ, CL = 5 pF, see Figure 41
RPULLUP = 1 kΩ, CL = 5 pF
RL = 1 kΩ, CL = 5 pF, see Figure 42
RL = 1 kΩ, CL = 5 pF
RPULLUP = 1 kΩ, CL = 12 pF, VPULL_UP = 5 V,
see Figure 43
RPULLUP = 1 kΩ, CL = 12 pF, VPULL_UP = 5 V
RPULLUP = 1 kΩ, CL = 12 pF, VPULL_UP = 5 V,
see Figure 44
RPULLUP = 1 kΩ, CL = 12 pF, VPULL_UP = 5 V
VS = 6 V, RS = 0 Ω, CL = 1 nF,
see Figure 46
RL = 50 Ω, CL = 5 pF, f = 1 MHz, see
Figure 36
RL = 50 Ω, CL = 5 pF, f = 1 MHz,
see Figure 37
RL = 10 kΩ, VS = 6 V p-p,
f = 20 Hz to 20 kHz, see Figure 39
RL = 50 Ω, CL = 5 pF, see Figure 38
RL = 50 Ω, CL = 5 pF, f = 1 MHz,
see Figure 38
VS = 6 V, f = 1 MHz
VS = 6 V, f = 1 MHz
VS = 6 V, f = 1 MHz
VS = VSS to VDD − 2 V, f = 1 MHz
VS = VSS to VDD − 2 V, f = 1 MHz
ADG5421F
Parameter
POWER REQUIREMENTS
Normal Mode
IDD
IGND
ISS
Fault Mode
IDD
IGND
ISS
Data Sheet
+25°C
125
200
45
80
80
120
−40°C to +85°C
−40°C to +125°C
200
80
120
Unit
Test Conditions/Comments
VDD = 13.2 V, VSS = 0 V, GND = 0 V,
digital inputs = 0 V or 5 V
µA typ
µA max
µA typ
µA max
µA typ
µA max
VS = ±60 V
185
270
155
210
55
90
270
210
90
Rev. 0 | Page 10 of 31
µA typ
µA max
µA typ
µA max
µA typ
µA max
Data Sheet
ADG5421F
36 V SINGLE SUPPLY
VDD = 36 V ± 10%, VSS = 0 V ± 10%, and GND = 0 V, unless otherwise noted.
Table 5.
Parameter
ANALOG SWITCH
Analog Signal Range
RON
RFLAT (ON)
RMATCH (ON)
LEAKAGE CURRENTS
IS (Off)
+25°C
14.5
11
13.5
1.1
1.25
0.01
0.04
0.02
0.2
FAULT
VT
IS
With Overvoltage
Ω typ
18
21.5
17
20
1.3
1.35
0.06
0.06
0.35
0.45
Ω max
Ω typ
Ω max
Ω typ
Ω max
Ω typ
Ω max
Ω typ
Ω max
nA typ
±2.5
±22
±8
±0.05
nA max
nA max
nA typ
±2.5
±22
±8
±0.05
±0.3
Unit
Test Conditions/Comments
VDD = 32.4 V, VSS = 0 V
V
±0.05
±0.2
ID (On), IS (On)
−40°C to +125°C
VSS to
VDD − 2
12
±0.2
ID (Off)
−40°C to +85°C
nA max
nA max
nA typ
±3.5
±30
±14
0.7
Power Supplies Grounded or
Floating
nA max
nA max
VS = 0 V to 29.5 V, IS = 10 mA, see
Figure 31
VS = 0 V to 29.5 V, IS = 10 mA
VS = 0 V to 27 V, IS = 10 mA
VS = 0 V to 27 V, IS = 10 mA
VS = 0 V to 29.5 V, IS = 10 mA
VS = 0 V to 29.5 V, IS = 10 mA
VS = 0 V to 27 V, IS = 10 mA
VS = 0 V to 27 V, IS = 10 mA
VS = 0 V to 29.5 V, IS = 10 mA
VS = 0 V to 29.5 V, IS = 10 mA
VDD = 39.6 V, VSS = 0 V
VS = 1 V to 30 V, VD = 30 V to 1 V,
see Figure 32
VS = 1 V to 30 V, VD = 30 V to 1 V
VS = 1 V to 30 V, VD = 30 V to 1 V,
−40°C to +105°C
VS = 1 V to 30 V, VD = 30 V to 1 V,
see Figure 32
VS = 1 V to 30 V, VD = 30 V to 1 V
VS = 1 V to 30 V, VD = 30 V to 1 V,
−40°C to +105°C
VS = 1 V to 30 V, VD = 30 V to 1 V,
see Figure 33
VS = 1 V to 30 V, VD = 30 V to 1 V
VS = 1 V to 30 V, VD = 30 V to 1 V,
−40°C to +105°C
V typ
See Figure 25
±30
µA typ
±5.5
µA typ
VDD = +39.6 V, VSS = 0 V, GND = 0 V,
VS = +60 V, and VS = −40 V, see Figure 34
VDD = 0 V or floating, VSS = 0 V or
floating, GND = 0 V, IN = 0 V or
floating, VS = ±60 V, see Figure 35
ID
With Overvoltage
±0.1
±0.2
Power Supplies Grounded
±2
±20
±0.1
±0.2
Power Supplies Floating
nA typ
nA max
nA typ
±2
±20
nA max
±0.1
µA typ
Rev. 0 | Page 11 of 31
VDD = +39.6 V, VSS = 0 V, GND = 0 V,
VS = +60 V and VS = −40 V, see Figure 34
VDD = +39.6 V, VSS = 0 V, GND = 0 V,
VS = +60 V and VS = −40 V
VDD = 0 V, VSS = 0 V, GND = 0 V,
VS = ±60 V, IN = 0 V, see Figure 35
VDD = 0 V, VSS = 0 V, GND = 0 V,
VS = ±60 V, IN = 0 V
VDD = floating, VSS = floating, GND = 0 V,
VS = ±60 V, IN = 0 V, see Figure 35
ADG5421F
Parameter
DIGITAL INPUTS AND OUTPUTS
VINH
VINL
IINL or IINH
Data Sheet
+25°C
−40°C to +85°C
−40°C to +125°C
Unit
Test Conditions/Comments
1.3
0.8
VIN = 0 V or 5 V
VIN = 0 V or 5 V
5
0.4
V min
V max
µA typ
µA max
pF typ
V max
7.2
µs typ
0.7
1
CIN
VOL
DYNAMIC CHARACTERISTICS
tON
tOFF
tD
tRESPONSE
Positive
8.7
200
8.7
8.7
µs max
ns typ
240
6
4.7
250
250
4.6
4.6
ns max
µs typ
µs min
290
290
700
700
10.8
11.3
tDIGRESP
240
290
600
700
6.6
10.7
120
150
4.1
150
150
tDIGREC
ns max
µs typ
7.8
−115
8
8.5
QINJ
µs max
pC typ
Off Isolation
−70
dB typ
Channel to Channel Crosstalk
−78
dB typ
THD + N
0.0008
% typ
−3 dB Bandwidth
Insertion Loss
630
−0.95
MHz typ
dB typ
CS (Off)
CD (Off)
CD (On), CS (On)
CDFLAT (On), CSFLAT (On)
CMATCH (On)
6
5
10
3.3
0.3
pF typ
pF typ
pF typ
pF typ
pF typ
Negative
tRECOVERY
Rev. 0 | Page 12 of 31
ns typ
ns max
ns typ
ns max
µs typ
µs max
ns typ
IFF = 2 mA
RL = 300 Ω, CL = 35 pF, VS = 18 V,
see Figure 45
RL = 300 Ω, CL = 35 pF, VS = 18 V
RL = 300 Ω, CL = 35 pF, VS = 18 V,
see Figure 45
RL = 300 Ω, CL = 35 pF, VS = 18 V
RL = 300 Ω, CL = 35 pF, VS = 18 V
RL = 300 Ω, CL = 35 pF, VS = 18 V
RL = 1 kΩ, CL = 5 pF, see Figure 40
RL = 1 kΩ, CL = 5 pF
RPULLUP = 1 kΩ, CL = 5 pF, see Figure 41
RPULLUP = 1 kΩ, CL = 5 pF
RL = 1 kΩ, CL = 5 pF, see Figure 42
RL = 1 kΩ, CL = 5 pF
RPULLUP = 1 kΩ, CL = 12 pF, VPULL_UP = 5 V,
see Figure 43
RPULLUP = 1 kΩ, CL = 12 pF, VPULL_UP = 5 V
RPULLUP = 1 kΩ, CL = 12 pF, VPULL_UP = 5 V,
see Figure 44
RPULLUP = 1 kΩ, CL = 12 pF, VPULL_UP = 5 V
VS = 18 V, RS = 0 Ω, CL = 1 nF,
see Figure 46
RL = 50 Ω, CL = 5 pF, f = 1 MHz,
see Figure 36
RL = 50 Ω, CL = 5 pF, f = 1 MHz,
see Figure 37
RL = 10 kΩ, VS = 18 V p-p,
f = 20 Hz to 20 kHz, see Figure 39
RL = 50 Ω, CL = 5 pF, see Figure 38
RL = 50 Ω, CL = 5 pF, f = 1 MHz,
see Figure 38
VS = 18 V, f = 1 MHz
VS = 18 V, f = 1 MHz
VS = 18 V, f = 1 MHz
VS = VSS to VDD − 2 V, f = 1 MHz
VS = VSS to VDD − 2 V, f = 1 MHz
Data Sheet
Parameter
POWER REQUIREMENTS
Normal Mode
IDD
IGND
ISS
Fault Mode
IDD
IGND
ISS
ADG5421F
+25°C
−40°C to +85°C
125
200
45
80
80
120
−40°C to +125°C
Unit
Test Conditions/Comments
VDD = 39.6 V, VSS = 0 V, GND = 0 V,
digital inputs = 0 V or 5 V
µA typ
µA max
µA typ
µA max
µA typ
µA max
200
80
120
VS = +60 V and VS = −40 V
185
270
155
210
55
90
µA typ
µA max
µA typ
µA max
µA typ
µA max
270
210
90
CONTINUOUS CURRENT PER CHANNEL, S OR D
Table 6.
Parameter
CONTINUOUS CURRENT, S OR D
θJA = 170°C/W
25°C
85°C
125°C
Unit
Test Conditions/Comments
88
81
61
57
41
39
mA max
mA max
VS = VSS to VDD − 5 V
VS = VSS to VDD − 2 V
Rev. 0 | Page 13 of 31
ADG5421F
Data Sheet
ABSOLUTE MAXIMUM RATINGS
THERMAL RESISTANCE
Table 7.
Parameter
VDD to VSS
VDD to GND
VSS to GND
Sx Pins
Sx to VDD
Sx to VSS
VS to VD
Dx Pins1
Digital Inputs
Peak Current, Sx or Dx Pins
Digital Output
Temperature
Operating Range
Storage Range
Junction
Reflow Soldering Peak, Pb-Free
1
Value
60 V
−0.3 V to +48 V
−28 V to +0.3 V
−60 V to +60 V
80 V
80 V
80 V
VSS − 0.7 V to VDD + 0.7 V or
30 mA, whichever occurs first
GND − 0.7 V to 6 V or 30 mA,
whichever occurs first
278 mA (pulsed at 1 ms,
10% duty cycle maximum)
GND − 0.7 V to 6 V or 30 mA,
whichever occurs first
−40°C to +125°C
−65°C to +150°C
150°C
As per JEDEC J-STD-020
Thermal performance is directly linked to printed circuit board
(PCB) design and operating environment. Careful attention to
PCB thermal design is required.
θJA is the natural convection, junction to ambient thermal
resistance measured in a one cubic foot sealed enclosure.
θJC is the junction to case thermal resistance.
Table 8. Thermal Resistance
Package Type1
CP-10-16
1
θJA
170
θJC
58.2
Unit
°C/W
Thermal impedance simulated values are based on a JEDEC 2S2P thermal
test board with four thermal vias. See JEDEC JESD-51.
ELECTROSTATIC DISCHARGE (ESD) RATINGS
The following ESD information is provided for handling of
ESD-sensitive devices in an ESD protected area only.
Human body model (HBM) per ANSI/ESDA/JEDEC JS-001.
ESD Ratings for ADG5421F
Table 9. ADG5421F, 10-Lead LFCSP
Overvoltages at the Dx pins are clamped by the internal diodes. Limit
current to the maximum ratings given.
Stresses at or above those listed under Absolute Maximum
Ratings may cause permanent damage to the product. This is a
stress rating only; functional operation of the product at these
or any other conditions above those indicated in the operational
section of this specification is not implied. Operation beyond
the maximum operating conditions for extended periods may
affect product reliability.
ESD Model
HBM1
1
Withstand Threshold (kV)
3.5
Class
2
This is the HBM for the input and output port to supplies, the input and
output port to the input and output port, and for all other pins.
ESD CAUTION
Rev. 0 | Page 14 of 31
Data Sheet
ADG5421F
PIN CONFIGURATION AND FUNCTION DESCRIPTIONS
ADG5421F
S1 1
10
D1
S2 2
9
D2
FF 3
8
IN1
GND 4
7
IN2
VDD 5
6
VSS
25051-003
TOP VIEW
(Not to Scale)
Figure 2. Pin Configuration
Table 10. Pin Function Descriptions
Pin No.
1
2
3
Mnemonic
S1
S2
FF
4
5
6
7
8
9
10
GND
VDD
VSS
IN2
IN1
D2
D1
Description
Overvoltage Protected Source Terminal. S1 can be an input or an output.
Overvoltage Protected Source Terminal. S2 can be an input or an output.
Fault Flag Digital Output. The FF pin is an open-drain output that requires an external pull-up resistor. This digital
output pulls low when a fault condition occurs on either of the Sx inputs.
Ground (0 V) Reference.
Most Positive Power Supply Potential.
Most Negative Power Supply Potential.
Logic Control Input.
Logic Control Input.
Drain Terminal. D1 can be an input or an output.
Drain Terminal. D2 can be an input or an output.
Rev. 0 | Page 15 of 31
ADG5421F
Data Sheet
TYPICAL PERFORMANCE CHARACTERISTICS
20
12.0
TA = 25°C
VDD = +20V
VSS = –20V
11.8
18
+125°C
VDD = +18V
VSS = –18V
11.4
ON RESISTANCE (Ω)
ON RESISTANCE (Ω)
11.6
VDD = +16.5V
VSS = –16.5V
11.2
11.0
VDD = +15V
VSS = –15V
10.8
10.6
VDD = +13.5V
VSS = –13.5V
10.4
VDD = +15V
VSS = –15V
16
+105°C
14
+85°C
12
+25°C
10
8
VDD = +22V
VSS = –22V
–40°C
VS, VD (V)
6
–15
25051-004
12
14
16
18
20
–22
–20
–18
–16
–14
–12
–10
–8
–6
–4
–2
0
2
4
6
8
10
10.0
20
VDD = 10.8V
VSS = 0V
10
18
+125°C
11.4
ON RESISTANCE (Ω)
ON RESISTANCE (Ω)
5
VDD = +20V
VSS = –20V
TA = 25°C
VDD = 12V
VSS = 0V
11.2
0
VS, VD (V)
12.0
11.6
–5
Figure 6. On Resistance as a Function of VS, VD for Different Temperatures,
±15 V Dual Supply
Figure 3. On Resistance as a Function of VS, VD (Dual Supply)
11.8
–10
25051-007
10.2
11.0
10.8
10.6
16
+105°C
14
+85°C
12
+25°C
10
10.4
8
VDD = 13.2V
VSS = 0V
0
1
2
3
4
5
6
7
8
9
10
11
VS, VD (V)
6
–20
Figure 4. On Resistance as a Function of VS, VD (12 V Single Supply)
–15
–10
–5
0
5
10
25051-008
–40°C
10.0
25051-005
10.2
15
VS, VD (V)
Figure 7. On Resistance as a Function of VS, VD for Different Temperatures,
±20 V Dual Supply
12.0
20
VDD = 12V
VSS = 0V
TA = 25°C
11.8
18
+125°C
VDD = 32.4V
VSS = 0V
11.4
ON RESISTANCE (Ω)
ON RESISTANCE (Ω)
11.6
11.2
11.0
VDD = 36V
VSS = 0V
10.8
10.6
16
+105°C
14
+85°C
12
+25°C
10
10.4
8
VDD = 39.6V
VSS = 0V
0
5
10
15
20
25
30
–40°C
35
VS, VD (V)
Figure 5. On Resistance as a Function of VS, VD (36 V Single Supply)
6
25051-006
10.0
0
1
2
3
4
VS, VD (V)
5
6
7
8
25051-009
10.2
Figure 8. On Resistance as a Function of VS, VD for Different Temperatures,
12 V Single Supply
Rev. 0 | Page 16 of 31
Data Sheet
20
ADG5421F
6
VDD = 36V
VSS = 0V
VDD = 12V
VSS = 0V
5
18
LEAKAGE CURRENT (nA)
ON RESISTANCE (Ω)
+125°C
16
+105°C
14
+85°C
12
+25°C
10
IS (OFF) –+
IS(OFF) +–
IS, ID (ON) – –
4
ID (OFF) –+
ID (OFF) +–
IS, ID (ON) ++
3
2
1
0
8
–40°C
125
25051-013
115
95
85
65
75
45
55
25
TEMPERATURE (°C)
Figure 12. Leakage Current vs. Temperature, 12 V Single Supply
Figure 9. On Resistance as a Function of VS, VD for Different Temperatures,
36 V Single Supply
10
9
VDD = 36V
VSS = 0V
VDD = +15V
VSS = –15V
8
8
IS (OFF) –+
IS(OFF) +–
IS, ID (ON) – –
6
5
LEAKAGE CURRENT (nA)
7
LEAKAGE CURRENT (nA)
105
VS, VD (V)
35
–1
5
30
15
25
0
20
–20
15
–10
10
–40
5
–30
0
25051-010
6
ID (OFF) –+
ID (OFF) +–
IS, ID (ON) ++
4
3
2
1
0
IS (OFF) –+
IS(OFF) +–
IS, ID (ON) – –
6
ID (OFF) –+
ID (OFF) +–
IS, ID (ON) ++
4
2
0
–1
25051-014
125
115
105
95
85
75
65
55
45
35
25
15
5
0
–10
TEMPERATURE (°C)
Figure 13. Leakage Current vs. Temperature, 36 V Single Supply
Figure 10. Leakage Current vs. Temperature, ±15 V Dual Supply
10
10
VDD = +20V
VSS = –20V
VDD = +15V
VSS = –15V
9
8
6
Dx LEAKAGE CURRENT (nA)
8
IS (OFF) –+
IS(OFF) +–
IS, ID (ON) – –
ID (OFF) –+
ID (OFF) +–
IS, ID (ON) ++
4
2
VS = –60V
VS = +60V
7
6
5
4
3
2
1
0
0
Figure 11. Leakage Current vs. Temperature, ±20 V Dual Supply
125
115
105
95
85
25051-015
TEMPERATURE (°C)
75
65
55
45
35
25
15
5
0
–10
–20
–40
25051-012
125
115
105
95
85
75
65
55
45
35
25
15
5
0
–10
–20
–30
TEMPERATURE (°C)
–30
–1
–2
–40
LEAKAGE CURRENT (nA)
–20
–40
125
25051-011
115
95
105
85
75
65
55
45
35
25
5
15
0
–10
–20
–30
–40
TEMPERATURE (°C)
–30
–2
–2
Figure 14. Dx Leakage Current vs. Temperature During Overvoltage,
±15 V Dual Supply
Rev. 0 | Page 17 of 31
ADG5421F
Data Sheet
10
0
VDD = +20V
VSS = –20V
9
VDD = +15V
VSS = –15V
TA = 25°C
–20
–40
VS = –60V
VS = +60V
7
OFF ISOLATION (dB)
Dx LEAKAGE CURRENT (nA)
8
6
5
4
3
2
–60
–80
–100
–120
1
–160
100
TEMPERATURE (°C)
25051-016
115
125
95
105
85
65
75
45
55
25
35
5
15
0
–20
–10
–40
–30
–1
100k
1M
10M
100M
1G
Figure 18. Off Isolation vs. Frequency, ±15 V Dual Supply
8
0
VDD = 12V
VSS = 0V
TA = 25°C
–20
6
–40
VS = –60V
VS = +60V
5
VDD = 12V,
VSS = 0V
–60
QINJ (pC)
4
3
2
–80
VDD = +15V,
VSS = –15V
–100
–120
TEMPERATURE (°C)
25051-017
125
115
105
95
85
75
65
55
45
35
25
–200
–40
15
–2
5
–180
0
–1
–10
–160
–20
0
–30
–140
–40
1
VDD = 36V,
VSS = 0V
VDD = +20V,
VSS = –20V
–30
–10
0
10
20
30
40
100M
1G
VS (V)
Figure 16. Dx Leakage Current vs. Temperature During Overvoltage,
12 V Single Supply
Figure 19. QINJ vs. VS
6
0
VDD = 36V
VSS = 0V
5
–20
25051-020
7
–20
VDD = +15V
VSS = –15V
TA = 25°C
4
VS = –60V
VS = +60V
–40
2
1
0
–60
–80
–100
125
115
105
95
85
25051-018
TEMPERATURE (°C)
75
65
55
45
35
25
15
–160
100
5
–3
0
–140
–10
–2
–20
–120
–30
–1
1k
10k
100k
1M
10M
FREQUENCY (Hz)
Figure 17. Dx Leakage Current vs. Temperature During Overvoltage,
36 V Single Supply
Rev. 0 | Page 18 of 31
Figure 20. AC Power Supply Rejection Ratio (PSRR) vs. Frequency,
±15 V Dual Supply
25051-021
AC PSRR (dB)
3
–40
Dx LEAKAGE CURRENT (nA)
10k
FREQUENCY (Hz)
Figure 15. Dx Leakage Current vs. Temperature During Overvoltage,
±20 V Dual Supply
Dx LEAKAGE CURRENT (nA)
1k
25051-019
–140
0
Data Sheet
0.0030
ADG5421F
16
RL = 10kΩ
TA = 25°C
14
0.0025
SINGLE SUPPLY = 12V
tON, tOFF TIMES (µs)
12
0.0015
DUAL SUPPLY = ±20V
DUAL SUPPLY = ±15V
0.0010
10
tON (±15V)
tOFF (±15V)
tON (±20V)
tON (+36V)
tOFF (+36V)
tOFF (±20V)
tON (+12V)
tOFF (+12V)
8
6
4
SINGLE SUPPLY = 36V
0.0005
4
8
12
16
20
0
–40
FREQUENCY (kHz)
0.85
–2
0.80
–3
0.75
VT (V)
–1
–4
0.65
–6
0.60
VDD = +15V
VSS = –15V
TA = 25°C
60
80
100
120
VDD = +15V
VSS = –15V
0.55
10k
100k
1M
10M
100M
1G
FREQUENCY (Hz)
0.50
–40
0
15
125
85
TEMPERATURE (°C)
Figure 25. VT vs. Temperature, ±15 V Dual Supply
Figure 22. Insertion Loss vs. Frequency,
±15 V Dual Supply
20
0
–20
40
0.70
–5
25051-023
INSERTION LOSS (dB)
0.90
1k
20
Figure 24. tON, tOFF Times vs. Temperature for Various Supplies
0
–8
100
0
TEMPERATURE (°C)
Figure 21. THD + N vs. Frequency
–7
–20
25051-026
0
25051-022
0
25051-025
2
OFF SOURCE
OFF DRAIN
ON SOURCE DRAIN
TA = 25°C
VDD = +15V
VSS = –15V
TA = 25°C
18
PIN CAPACITANCE (pF)
16
–40
–60
–80
–100
14
12
10
8
6
4
–120
–140
100
1k
10k
100k
1M
10M
100M
FREQUENCY (Hz)
1G
0
–15
–10
–5
0
5
VS (V)
Figure 26. Pin Capacitance vs. VS
Figure 23. Crosstalk vs. Frequency, ±15 V Dual Supply
Rev. 0 | Page 19 of 31
10
15
25051-027
2
25051-024
CROSSTALK (dB)
THD + N (%)
0.0020
ADG5421F
Data Sheet
1.0
TA = 25°C
VDD
VDD
VDD
VDD
0.6
VDD = +15V
VSS = −15V
= +15V, VSS = –15V
= +20V, VSS = –20V
= 36V, VSS = 0V
= 12V, VSS = 0V
T
0.4
0.2
FF
2
0
Dx
–0.2
VSS
–0.4
–0.6
Sx
–10
0
10
20
30
VS (V)
CH1 10.0V
CH3 10.0V
Figure 27. Pin Capacitance Matching vs. VS
CH2 10.0V
CH4 10.0V
1.00µs
A CH1
T
–70.00000ns
–15.0V
25051-030
–1.0
–20
25051-028
–0.8
Figure 29. Drain Output Response to Negative Overvoltage
20
Sx
VDD
FF
2
Dx
VDD = +10V
VSS = −10V
TA = 25°C
16
12
8
4
0
CH1 10.0V
CH3 10.0V
CH2 10.0V
CH4 10.0V
1.00µs
A CH1
T
0.000000s
15.4V
1
10
FREQUENCY (MHz)
Figure 30. Large Voltage Signal Voltage vs. Frequency
Figure 28. Drain Output Response to Positive Overvoltage
Rev. 0 | Page 20 of 31
100
25051-130
T
LARGE VOLTAGE SIGNAL VOLTAGE (V p-p)
VDD = +15V
VSS = −15V
25051-029
PIN CAPACITANCE MATCHING (pF)
0.8
Data Sheet
ADG5421F
TEST CIRCUITS
V
ID
Dx
RON = V/IDS
Dx
A
RL
10kΩ
|VS| > |VDD| OR |VSS|
25051-031
IDS
VS
Sx
A
25051-034
IS
Sx
Figure 34. Switch Overvoltage Leakage
Figure 31. On Resistance (IDS Is the Drain to Source Current.)
VDD = VSS = GND = 0V
A
A
VD
VS
ID
Sx
Figure 35. Switch Unpowered Leakage
ID (ON)
Dx
NC = NO CONNECT
A
25051-033
Sx
VD
Figure 33. On Leakage
VDD
0.1µF
VSS
VDD
VSS
0.1µF
NETWORK
ANALYZER
50Ω
Sx
INx
VS
VIN
RL
50Ω
GND
VOUT
OFF ISOLATION = 20 log
VOUT
25051-044
Dx
VS
Figure 36. Off Isolation (VOUT Is the Output Voltage)
VDD
VSS
0.1µF
0.1µF
VDD
VSS
NETWORK
ANALYZER
S1
RL
50Ω
VOUT
Dx
S2
VS
GND
CHANNEL-TO-CHANNEL CROSSTALK = 20 log
VOUT
VS
Figure 37. Channel to Channel Crosstalk
Rev. 0 | Page 21 of 31
25051-045
RL
50Ω
A
RL
10kΩ
VS
Figure 32. Off Leakage
NC
Dx
25051-035
IS
Dx
Sx
A
ID (OFF)
25051-032
IS (OFF)
ADG5421F
Data Sheet
VDD
VSS
0.1µF
0.1µF
VDD
NETWORK
ANALYZER
VSS
50Ω
Sx
INx
VS
VIN
RL
50Ω
GND
VOUT
VOUT WITH SWITCH
INSERTION LOSS = 20 log
VOUT WITHOUT SWITCH
25051-046
Dx
Figure 38. Bandwidth
VDD
VSS
0.1µF
0.1µF
VDD
AUDIO
PRECISION
VSS
RS
Sx
VS
V p-p
INx
Dx
VIN
VOUT
RL
10kΩ
25051-047
GND
Figure 39. THD + N
VSS
VDD
0.1µF
VDD + 0.5V
Sx
VD
Dx
VS
0V
ADG5421F
CL*
5pF
RL
1kΩ
VDD
VDD × 0.5
GND
0V
*INCLUDES TRACK CAPACITANCE
Figure 40. Positive Overvoltage Response Time, tRESPONSE
Rev. 0 | Page 22 of 31
25051-138
OUTPUT
(VD)
VSS
VDD
SOURCE
VOLTAGE
(+VS)
+tRESPONSE
0.1µF
Data Sheet
ADG5421F
VDD
SOURCE
VOLTAGE
(VS)
0V
VSS
0.1µF
0.1µF
5V
VSS – 0.5V
VDD
RPULLUP
1kΩ
VSS
Sx
VD
Dx
CL*
5pF
VS
ADG5421F
tRESPONSE
5V
25051-150
GND
OUTPUT
(VD) + 1V
*INCLUDES TRACK CAPACITANCE
Figure 41. Negative Overvoltage Response Time, Single-Supply, tRESPONSE
VDD
VSS
0.1µF
VDD + 0.5V
0.1µF
VDD
SOURCE
VOLTAGE
(VS)
VSS
Sx
VD
Dx
CL*
5pF
VS
0V
ADG5421F
RL
1kΩ
tRECOVERY
OUTPUT
(VD)
GND
25051-139
1V
0V
*INCLUDES TRACK CAPACITANCE
Figure 42. Overvoltage Recovery Time, tRECOVERY
VDD
VSS
0.1µF
0.1µF
VDD + 0.5V
VDD
SOURCE
VOLTAGE
(VS)
VSS
Sx
Dx
VS
0V
5V
ADG5421F
RPULLUP
1kΩ
OUTPUT
tDIGRESP
FF
CL*
12pF
OUTPUT
(VFF )
GND
0.1V OUT
*INCLUDES TRACK CAPACITANCE
Figure 43. Interrupt Flag Response Time, tDIGRESP (VFF Is the Fault Flag Voltage)
Rev. 0 | Page 23 of 31
25051-140
0V
ADG5421F
Data Sheet
VSS
VDD
0.1µF
VDD + 0.5V
0.1µF
VSS
VDD
SOURCE
VOLTAGE
(VS)
Dx
Sx
VS
5V
0V
ADG5421F
RPULLUP
1kΩ
tDIGREC
OUTPUT
FF
5V
CL*
12pF
3V
OUTPUT
(VFF )
25051-141
GND
0V
*INCLUDES TRACK CAPACITANCE
Figure 44. Interrupt Flag Recovery Time, tDIGREC
VDD
0.1µF
VSS
0.1µF
ADG5421F
VIN
VDD
50%
VOUT
Dx
RL
300Ω
INx
CL
35pF
90%
VOUT
10%
GND
25051-042
Sx
VS
50%
VSS
tOFF
tON
Figure 45. Switching Times, tON and tOFF
RS
VS
VDD
VSS
VDD
VSS
Sx
Dx
0.1µF
ADG5421F
VOUT
VIN
OFF
ON
CL
1nF
INx
VOUT
GND
QINJ = CL × ΔVOUT
ΔVOUT
25051-043
0.1µF
Figure 46. Charge Injection, QINJ
Rev. 0 | Page 24 of 31
Data Sheet
ADG5421F
TERMINOLOGY
tOFF
tOFF represents the delay between applying the digital control
input and the output switching off.
IDD
IDD represents the positive supply current.
ISS
ISS represents the negative supply current.
VD, VS
VD and VS represent the analog voltage on the Dx pins and the
Sx pins, respectively.
RON
RON represents the ohmic resistance between the Dx pins and
the Sx pins.
RFLAT (ON)
RFLAT (ON) is the flatness that is defined as the difference between
the maximum and minimum value of on resistance measured
over the specified analog signal range.
IS (Off)
IS (Off) is the source leakage current with the switch off.
tDIGRESP
tDIGRESP is the time required for the FF pin to go low (0.3 V),
measured with respect to voltage on the Sx pin exceeding the
source voltage by 0.5 V.
tDIGREC
tDIGREC is the time required for the FF pin to return high,
measured with respect to voltage on the Sx pin falling below
the source voltage plus 0.5 V.
tRESPONSE
tRESPONSE represents the delay between the source voltage
exceeding the supply voltage by 0.5 V and the drain voltage
falling to 90% of the supply voltage.
ID (Off)
ID (Off) is the drain leakage current with the switch off.
tRECOVERY
tRECOVERY represents the delay between an overvoltage on the
Sx pin falling below the supply voltage plus 0.5 V and the drain
voltage rising from 0 V to 10% of the supply voltage.
ID (On), IS (On)
ID (On) and IS (On) represent the channel leakage currents with
the switch on.
Off Isolation
Off isolation is a measure of unwanted signal coupling through
an off switch.
VINL
VINL is the maximum input voltage for Logic 0.
Charge Injection
Charge injection is a measure of the glitch impulse transferred
from the digital input to the analog output during switching.
VINH
VINH is the minimum input voltage for Logic 1.
IINL, IINH
IINL and IINH represent the low and high input currents of the
digital inputs.
CD (Off)
CD (Off) represents the off switch Dx pin capacitance, which is
measured with reference to ground.
−3 dB Bandwidth
Bandwidth is the frequency at which the output is attenuated
by 3 dB.
On Response
On response is the frequency response of the on switch.
Insertion Loss
Insertion loss is the loss due to the on resistance of the switch.
CS (Off)
CS (Off) represents the off switch Sx pin capacitance, which is
measured with reference to ground.
THD + N
THD + N is the ratio of the harmonic amplitude plus noise of
the signal to the fundamental.
CD (On), CS (On)
CD (On) and CS (On) represent on switch capacitances, which
are measured with reference to ground.
AC Power Supply Rejection Ratio (AC PSRR)
AC PSRR is the ratio of the amplitude of signal on the output to
the amplitude of the modulation. AC PSRR is a measure of the
ability of the device to avoid coupling noise and spurious signals
that appear on the supply voltage pins to the output of the switch
(see Figure 20). The dc voltage on the device is modulated by a
sine wave of 0.62 V p-p.
CIN
CIN is the digital input capacitance.
tON
tON represents the delay between applying the digital control
input and the output switching on.
VT
VT is the voltage threshold at which the overvoltage protection
circuitry engages.
Rev. 0 | Page 25 of 31
ADG5421F
Data Sheet
THEORY OF OPERATION
The ADG5421F consists of two switch channels of N channel
diffused metal-oxide semiconductor (NDMOS) transistors.
This construction provides excellent performance in a small
area. The ADG5421F operates as a standard switch when input
signals with a voltage between VSS and VDD − 2 V are applied.
For example, the on resistance is 11 Ω typically, and the INx
pins controls when the switches open or close.
Additional internal circuitry enables the switches to detect
overvoltage inputs by comparing the voltage on both the S1
and S2 pins with the VDD and VSS pins. A signal is considered
overvoltage when the signal exceeds the supply voltages by VT.
VT is typically 0.7 V but can range from 0.76 V at −40°C down
to 0.5 V at +125°C. See Figure 25 to see the change in VT with
the operating temperature.
When an overvoltage condition is detected on either the S1 or
S2 pins, both switches automatically open regardless of the
digital logic state (INx). The S1 to D1 and S2 to D2 become
high impedance and ensure that no current flows through
the switches. In Figure 28, the voltage on the Dx pin follows the
voltage on the Sx pins until the main channel switch turns off
completely, and the drain voltage discharges through the load.
The maximum voltage on the drain is limited by the internal
ESD diodes and the rate at which the output voltage discharges
is dependent on the load at the Dx pins.
The maximum voltage that can be applied to any source input
is +60 V or −60 V. When the ADG5421F is powered using a
single supply of 25 V or greater, the maximum negative signal
level reduces to remain within the 80 V maximum rating. For
example, at VDD = +40 V, the maximum negative signal drops
from −60 V to −40 V. Construction of the process allows the
channel to withstand 80 V across either switch when the
switches are open. Note that these overvoltage limits apply
whether the power supplies are present or not.
During overvoltage conditions, the leakage current into and out
of the Sx pins is limited to tens of microamperes and nanoamperes
only for the Dx pins. This limit protects the switches and
connected circuitry from overstresses and restricts the
current drawn from the signal source.
ESD Performance
The ADG5421F has an ESD rating of 3.5 kV for the HBM.
The Dx pins have ESD protection diodes to the rails, and the
voltage at these pins must not exceed the supply voltage. The
Sx pins have specialized ESD protection that allow the signal
voltage to reach ±60 V regardless of the supply voltage level.
See Figure 47 for the switch channel overview.
ESD
PROTECTION
VDD
ESD
DIODE
Sx
Dx
FAULT
DETECTOR
SWITCH
DRIVER
ESD
DIODE
VSS
25051-002
SWITCH ARCHITECTURE
AND
INx
Figure 47. Switch Channel and Control Function
Trench Isolation
In the ADG5421F, an insulating oxide layer (trench) is placed
between the NDMOS and the P-channel DMOS (PDMOS)
transistors in the circuit. Parasitic junctions that occur between
the transistors in the junction isolated switches are eliminated,
and the result is a switch that is latch-up immune under all
circumstances. These devices pass the JESD78D latch-up test.
NDMOS
PDMOS
P WELL
N WELL
TRENCH
HANDLE WAFER
Figure 48. Trench Isolation
Rev. 0 | Page 26 of 31
25051-049
BURIED OXIDE LAYER
Data Sheet
ADG5421F
OVERVOLTAGE FAULT PROTECTION
When the voltage at the Sx inputs exceed VDD or VSS by VT, both
switches turn off, or, if the device is unpowered, the switches
remain off. Both switch inputs remain high impedance regardless
of the digital input state or the load resistance, and the output
acts as a virtual open circuit. Signal levels up to +60 V and −60 V
are blocked in both the powered and unpowered condition as
long as the +80 V absolute maximum rating limitation between
the Sx pins and VDD or VSS pins is met (see Figure 49). For example
with a +40 V single-supply, the overvoltage protection is +60 V
and −40 V.
VDD
When powered by the ±15 V dual supply, the positive tRESPONSE
is typically 160 ns, and tRECOVERY is 9.8 µs. These values vary with
different supply voltage and output load conditions.
Exceeding ±60 V on either Sx input may damage the ESD
protection circuitry on the ADG5421F.
Power-Off Protection
When no power supplies are present, the switches remain in an
off state, and the switch inputs are high impedance. This state
ensures that no current flows and prevents damage to the
switches or downstream circuitry. The switch outputs are a
virtual open circuit.
80V
ADG5421F
Sx
Dx
The switches remain off regardless of whether the VDD and VSS
supplies are 0 V or floating. A GND reference must always be
present to ensure proper operation. Signal levels of up to ±60 V
are blocked when powered off.
25051-151
80V
VSS
Figure 49. Sx to VDD or VSS Maximum Rating
Overvoltage Interrupt Flag
Power-On Protection
To activate the switches, the three following conditions must be
meet:
•
•
•
The switches respond to a voltage on either of the Sx pins that
exceeds VDD or VSS by VT by turning off. The absolute input
voltage limits are −60 V and +60 V, while maintaining an
+80 V limit between the Sx pins and the supply rails. The
switches remain off until the voltage at the Sx pins return to
between VDD and VSS.
The minimum supply operating conditions in Table 1.
The input signal must be between VSS − VT and VDD + VT.
The digital logic control input, INx, is on.
When the switches are on, signal levels from VSS up to VDD − 2 V
are passed.
The voltages on the Sx inputs of the ADG5421F are
continuously monitored, and the active low digital output pin,
FF, indicates the fault state.
The voltage on the FF pin indicates if either of the Sx pins are
experiencing a fault condition. The FF pin is an open-drain
output that requires an external pull-up resistor. The output of
the FF pin is high when both the Sx pins are within the normal
operating range. If either of the Sx pin voltages exceeds the
supply voltage (VDD or VSS) by VT, the FF output provides a low
impedance path to GND.
Rev. 0 | Page 27 of 31
ADG5421F
Data Sheet
APPLICATIONS INFORMATION
The ADG5421F overvoltage protected switches provide a
robust solution for instrumentation, industrial, aerospace, and
other harsh environments where overvoltage signals can be
present, and the system must remain operational both during
and after an overvoltage occurs.
POWER SUPPLY RAILS
To guarantee correct operation of the device, 0.1 µF decoupling
capacitors are required on both VDD and VSS to GND.
The ADG5421F can operate with bipolar supplies between ±5 V
and ±22 V. Note that the VDD and VSS supplies do not have to be
symmetrical, but the supply range must not exceed 44 V. The
ADG5421F can also operate with single supplies between 8 V
and 44 V with VSS connected to GND.
The ADG5421F is fully specified at the ±15 V, ±20 V, +12 V,
and +36 V supply ranges.
POWER SUPPLY RECOMMENDATIONS
Analog Devices, Inc., has a wide range of power management
products to meet the requirements of most high performance
signal chains.
An example of a bipolar power solution is shown in Figure 50.
The ADP5070 (dual switching regulator) generates a positive and
negative supply rail for the ADG5421F amplifier and/or a
precision converter in a typical signal chain. Also shown in
Figure 50 are two optional LDOs, ADP7118 and ADP7182,
positive and negative low dropout (LDOs) regulators, respectively,
that can be used to reduce the output ripple of the ADP5070 in
ultralow noise sensitive applications.
ADP7118
LDO
+15V
ADP5070
–16.5V
ADP7182
LDO
–15V
25051-147
+16.5V
+5V
INPUT
POWER SUPPLY SEQUENCING PROTECTION
When the ADG5421F is off, the switch channels remain open
and signals from −60 V to +60 V can be applied without
damaging the device. The switch channels only close when the
supplies are connected, a suitable digital control signal is placed
on the INx pins, and the signal is within the normal operating
range. Note that placing the ADG5421F between external
connectors and sensitive components offers protection in
systems where a signal is presented to the Sx pins before the
supply voltages are available.
SIGNAL RANGE
The ADG5421F switches have overvoltage detection circuitry on
the S1 and S2 pins that compares the voltage levels with VDD
and VSS. To protect downstream circuitry from overvoltages,
supply the ADG5421F with voltages that match the intended
signal range. The NDMOS only architecture used in this switch
allows signals up to VDD − 2 V to be passed with little distortion.
A signal that exceeds the supply rail by VT is then blocked. This
signal block offers protection to both the device and any
downstream circuitry.
INTELLIGENT FAULT DETECTION
The ADG5421F digital output pin (FF) can interface with a
microprocessor or control system and be used as an interrupt
flag. This feature provides real-time diagnostic information on
the state of the device and the system to which the device
connects.
The control system can use the digital interrupt to start a
variety of actions, such as the following:
•
•
•
Figure 50. Bipolar Power Solution
Table 11. Recommended Power Management Devices
Product
ADP5070
ADP7118
ADP7182
Description
1 A/0.6 A, dc-to-dc switching regulator with
independent positive and negative outputs
20 V, 200 mA, low noise, CMOS LDO linear regulator
−28 V, −200 mA, low noise, LDO linear regulator
Initiating investigation into the source of the overvoltage fault
Shutting down critical systems in response to the overvoltage
Data recorders marking data during these events as
unreliable or out of specification
For systems that are sensitive during a start-up sequence, the
active low operation of the flag allows the system to ensure that
the ADG5421F powers on and that all input voltages are within
the normal operating range before initiating operation.
The FF pin is an open drain that requires an external pull-up
resistor, which allows signals to be combined into a single
interrupt for larger modules that contain multiple devices.
SWITCH IN A KNOWN STATE
If no digital inputs are present on the switch control lines, INx,
the switches remain in an off state to prevent any unwanted
signals passing through the switch.
Rev. 0 | Page 28 of 31
Data Sheet
ADG5421F
HIGH VOLTAGE SURGE SUPPRESSION
To achieve protection from high voltage transients, such as
IEC 61000-4-2 ESD, IEC 61000-4-4 electrical fast transient
(EFT), and IEC 61000-4-5 surge, implement the circuit shown
in Figure 51 by using discrete resistor and a transient voltage
suppression (TVS) device.
82Ω
VIN
Table 12. High Voltage Transient Protection
ADG5421F
S1
IEC 61000-4 Transient
ESD (Contact)
EFT
Surge
D1
D2
S2
60V
TVS
IN1 IN2
FF
25051-052
FAULT
DETECTION
AND SWITCH
DRIVER
Table 12 details the results achieved by using the discrete
protection circuit shown in Figure 51. To replicate the harshest
environments, the surge test was performed by striking the
Sx pins directly through a 40 Ω resistor and a 0.5 µF capacitor
coupling network. The EFT test was performed by striking the
Sx pins directly without any capacitive coupling through cables.
Figure 51. High Voltage Transient Protection
Rev. 0 | Page 29 of 31
Protection Level (kV)
±8
±4
±1
ADG5421F
Data Sheet
RELATED PRODUCTS
Table 13. Related Products to the ADG5421F
Device(s)
ADG5401F
Configuration
SPST
Fault Limit
Voltage rails
Fault Indicator
General flag
Package
LFCSP
ADG5412F/ADG5413F
Quad SPST
Voltage rails
General flag
TSSOP/LFCSP
ADG5412BF/ADG5413BF
Quad SPST
Voltage rails
General flag
TSSOP/LFCSP
ADG5404F
4:1 mux
Voltage rails
General and
specific flags
TSSOP/LFCSP
ADG5436F
Dual SPDT
Voltage rails
General and
specific flags
TSSOP/LFCSP
ADG5462F
Quad channel
protector
Secondary
supplies
General flag
TSSOP/LFCSP
Rev. 0 | Page 30 of 31
Function
±60 V fault protection, 6 Ω RON,
SPST switch with 0.6 kΩ feedback
channel
±55 V fault protection and
detection, 10 Ω RON, quad SPST
switches
±55 V bidirectional fault protection
and detection, 10 Ω RON, quad SPST
switches
±55 V fault protection and
detection, 10 Ω RON, 4-channel
multiplexer
±55 V fault protection and
detection, 10 Ω RON, dual SPDT
switch
±55 V fault protection and
detection, 10 Ω RON, quad channel
protector
Data Sheet
ADG5421F
OUTLINE DIMENSIONS
3.10
3.00
2.90
0.30
0.25
0.20
0.50 BSC
10
6
2.10
2.00
1.90
0.45
0.40
0.35
1
5
BOTTOM VIEW
TOP VIEW
PKG-005693
0.80
0.75
0.70
SIDE VIEW
SEATING
PLANE
0.55
BSC
PIN 1
INDICATOR
0.050 MAX
0.035 NOM
COPLANARITY
0.08
0.203 REF
01-15-2018-A
PIN 1
CORNER
Figure 52. 10-Lead Lead Frame Chip Scale Package [LFCSP]
3 mm × 2 mm Body and 0.75 mm Package Height
(CP-10-16)
Dimensions shown in millimeters
ORDERING GUIDE
Model 1
ADG5421FBCPZ-RL7
EVAL-ADG5421FEBZ
1
Temperature Range
−40°C to +125°C
Package Description
10-Lead Lead Frame Chip Scale Package [LFCSP]
Evaluation Board
Z = RoHS Compliant Part.
©2020 Analog Devices, Inc. All rights reserved. Trademarks and
registered trademarks are the property of their respective owners.
D25051-10/20(0)
Rev. 0 | Page 31 of 31
Package Option
CP-10-16
