CMOS Low Voltage, 2 Ω SPST Switches
ADG701L/ADG702L
Data Sheet
FEATURES
FUNCTIONAL BLOCK DIAGRAMS
1.8 V to 5.5 V single supply
2 Ω (typical) on resistance
Low on resistance flatness
Guaranteed leakage specifications up to 85°C
–3 dB bandwidth > 200 MHz
Rail-to-rail operation
Fast switching times
tON 18 ns
tOFF 12 ns
Typical power consumption < 0.01 µW
Transistor/Transistor Logic (TTL)/CMOS-compatible
ADG701L
D
S
SWITCHES SHOWN
FOR A LOGIC 1 INPUT
05486-001
IN
Figure 1.
ADG702L
S
APPLICATIONS
D
Battery-powered systems
Communication systems
Sample-and-hold systems
Audio signal routing
Video switching
Mechanical reed relay replacement
PRODUCT HIGHLIGHTS
GENERAL DESCRIPTION
1.
SWITCHES SHOWN
FOR A LOGIC 1 INPUT
05486-020
IN
Figure 2.
The ADG701L/ADG702L are monolithic CMOS SPST
switches. These switches are designed using an advanced
submicron process that provides low power dissipation yet also
offers high switching speed, low on resistance, and low leakage
currents. In addition, −3 dB bandwidths greater than 200 MHz
can be achieved.
The ADG701L/ADG702L can operate from a single 1.8 V to
5.5 V supply, making it ideal for use in battery-powered
instruments and with the new generation of DACs and ADCs
from Analog Devices, Inc.
Figure 1 and Figure 2 show that with a logic input of 1, the
switch of the ADG701L is closed while the switch of the
ADG702L is open. Each switch conducts equally well in both
directions when on.
2.
3.
4.
5.
6.
1.8 V to 5.5 V Single-Supply Operation. The ADG701L/
ADG702L offer high performance, including low on
resistance and fast switching times. The ADG701L/
ADG702L are fully specified and guaranteed with 3 V
and 5 V supply rails.
Very Low RON (3 Ω Maximum at 5 V, 5 Ω Maximum at 3 V).
At 1.8 V operation, on resistance (RON) is typically 40 Ω
over the temperature range.
On Resistance Flatness, RFLAT(ON) (1 Ω Maximum).
−3 dB Bandwidth > 200 MHz.
Low Power Dissipation. CMOS construction ensures low
power dissipation.
Fast tON/tOFF.
The ADG701L/ADG702L are packaged as 5-lead SOT-23,
6-lead SOT-23, and 8-lead MSOP.
Rev. A
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Tel: 781.329.4700
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Fax: 781.461.3113 ©2006–2020 Analog Devices, Inc. All rights reserved.
ADG701L/ADG702L
Data Sheet
TABLE OF CONTENTS
Features .............................................................................................. 1
Typical Performance Characteristics .............................................7
Applications ...................................................................................... 1
Test Circuits .......................................................................................8
General Description ......................................................................... 1
Terminology.......................................................................................9
Functional Block Diagrams............................................................. 1
Applications Information ............................................................. 10
Product Highlights ........................................................................... 1
Supply Voltages .......................................................................... 10
Revision History ............................................................................... 2
Bandwidth ................................................................................... 10
Specifications .................................................................................... 3
Off Isolation ................................................................................ 10
Absolute Maximum Ratings ........................................................... 5
Outline Dimensions ....................................................................... 11
ESD Caution.................................................................................. 5
Ordering Guide .......................................................................... 12
Pin Configurations and Function Descriptions ........................... 6
REVISION HISTORY
1/2020—Rev. 0 to Rev. A
Changes to Table 1 ........................................................................... 3
Reformatted Test Circuits Section ................................................. 8
Changes to Bandwidth Section ..................................................... 10
Updated Outline Dimensions ....................................................... 11
Changes to Ordering Guide .......................................................... 12
11/2006—Revision 0: Initial Version
Rev. A | Page 2 of 12
Data Sheet
ADG701L/ADG702L
SPECIFICATIONS
VDD = 5 V ± 10% and GND = 0 V. Temperature range for the B version is −40°C to +85°C, unless otherwise noted.
Table 1.
Parameter
ANALOG SWITCH
Analog Signal Range
RON
RFLAT(ON)
+25°C
B Version
−40°C to +85°C
0 V to VDD
2
3
0.5
4
1.0
LEAKAGE CURRENTS
Source Off Leakage, IS (Off)
Drain Off Leakage, ID (Off)
Channel On Leakage, ID, IS (On)
DIGITAL INPUTS
Input High Voltage, VINH
Input Low Voltage, VINL
Input Current
IINL or IINH
DYNAMIC CHARACTERISTICS1
tON
±0.01
±0.25
±0.01
±0.25
±0.01
±0.25
±0.35
V
Ω typ
Source Voltage (VS) = 0 V to VDD and source off
leakage = −10 mA, see Figure 12
Ω max
Ω typ
Ω max
VS = 0 V to VDD and source current (IS) = −10 mA
nA typ
VDD = 5.5 V
VS = 4.5 V/1 V and drain voltage (VD) = 1 V/4.5 V,
see Figure 14
±0.35
2.4
0.8
V min
V max
μA typ
μA max
Digital input voltage (VIN) = VINL or VINH
±0.1
ns typ
Load resistance (RL) = 300 Ω and load capacitance
(CLOAD) = 35 pF
VS = 3 V, see Figure 16
RL = 300 Ω and CL = 35 pF
VS = 3 V, see Figure 16
VS = 2 V and source resistance (RS) = 0 Ω, CL = 1 nF,
see Figure 17
RL = 50 Ω, CL = 5 pF, and f = 10 MHz
RL = 50 Ω, CL = 5 pF, and f = 1 MHz, see Figure 13
RL = 50 Ω and CL = 5 pF, see Figure 15
±0.35
0.005
12
tOFF
8
Charge Injection
5
ns max
ns typ
ns max
pC typ
Off Isolation
−55
−75
200
17
17
38
dB typ
dB typ
MHz typ
pF typ
pF typ
pF typ
0.001
μA typ
μA max
12
Bandwidth −3 dB
Source Capacitance (CS) (Off)
Drain Capacitance (CD) (Off)
CD, CS (On)
POWER REQUIREMENTS
Supply Current (IDD)
Test Conditions/Comments
nA max
nA typ
nA max
nA typ
nA max
18
1.0
1
Unit
Guaranteed by design, not subject to production test.
Rev. A | Page 3 of 12
VS = 4.5 V/1 V and VD = 1 V/4.5 V, see Figure 14
VS = VD = 1 V or 4.5 V, see Figure 18
VDD = 5.5 V
Digital inputs = 0 V or 5 V
ADG701L/ADG702L
Data Sheet
VDD = 3 V ± 10% and the GND pin = 0 V. Temperature range for the B version is −40°C to +85°C, unless otherwise noted.
Table 2.
Parameter
ANALOG SWITCH
Analog Signal Range
RON
RFLAT(ON)
LEAKAGE CURRENTS
Source Off Leakage IS (Off)
Drain Off Leakage ID (Off)
Channel On Leakage ID, IS (On)
DIGITAL INPUTS
Input High Voltage, VINH
Input Low Voltage, VINL
Input Current
IINL or IINH
DYNAMIC CHARACTERISTICS1
tON
+25°C
B Version
−40°C to +85°C
0 V to VDD
3.5
5
1.5
±0.01
±0.25
±0.01
±0.25
±0.01
±0.25
6
4
−55
−75
200
17
17
38
V min
V max
μA typ
μA max
VIN = VINL or VINH
±0.1
ns typ
ns max
ns typ
ns max
pC typ
dB typ
dB typ
MHz typ
pF typ
pF typ
pF typ
RL = 300 Ω and CL = 35 pF
VS = 2 V, see Figure 16
RL = 300 Ω and CL = 35 pF
VS = 2 V, see Figure 16
VS = 1.5 V, RS = 0 Ω and CL = 1 nF, see Figure 17
RL = 50 Ω, CL = 5 pF, and f = 10 MHz
RL = 50 Ω, CL = 5 pF, and f = 1 MHz, see Figure 13
RL = 50 Ω and CL = 5 pF, see Figure 15
13
Bandwidth −3 dB
CS (Off)
CD (Off)
CD, CS (On)
POWER REQUIREMENTS
IDD
0.001
1.0
1
VS = 0 V to VDD and IS = −10 mA
VDD = 3.3 V
VS = 3 V/1 V and VD = 1 V/3 V, see Figure 14
2.0
0.4
20
Charge Injection
Off Isolation
VS = 0 V to VDD and IS = −10 mA, see Figure 12
±0.35
±0.35
14
8
V
Ω typ
Ω max
Ω typ
Test Conditions/Comments
nA typ
nA max
nA typ
nA max
nA typ
nA max
±0.35
0.005
tOFF
Unit
μA typ
μA max
Guaranteed by design, not subject to production test.
Rev. A | Page 4 of 12
VS = 3 V/1 V and VD = 1 V/3 V, see Figure 14
VS = VD = 1 V or 3 V, see Figure 18
VDD = 3.3 V
Digital inputs = 0 V or 3 V
Data Sheet
ADG701L/ADG702L
ABSOLUTE MAXIMUM RATINGS
TA = 25°C, unless otherwise noted.
Table 3.
Parameter
VDD to GND Pin
Analog, Digital Inputs 1
Continuous Current, S or D
Peak Current, S or D
Operating Temperature Range
Industrial (B Version)
Storage Temperature Range
Junction Temperature
MSOP Package, Power
Dissipation
θJA Thermal Impedance
θJC Thermal Impedance
SOT-23 Package, Power
Dissipation
θJA Thermal Impedance
θJC Thermal Impedance
Lead Temperature, Soldering
Vapor Phase (60 sec)
Infrared (15 sec)
Lead-free Reflow Soldering
Peak Temperature
Time at Peak Temperature
ESD
1
Rating
−0.3 V to +7 V
−0.3 V to VDD + 0.3 V or 30 mA,
whichever occurs first
30 mA
100 mA, pulsed at 1 ms,
10% duty cycle maximum
Stresses at or above those listed under Absolute Maximum
Ratings may cause permanent damage to the product. This is a
stress rating only; functional operation of the product at these
or any other conditions above those indicated in the operational
section of this specification is not implied. Operation beyond
the maximum operating conditions for extended periods may
affect product reliability.
ESD CAUTION
−40°C to +85°C
−65°C to +150°C
150°C
315 mW
206°C/W
44°C/W
282 mW
229.6°C/W
91.99°C/W
215°C
220°C
260 (+0/−5)°C
10 sec to 40 sec
2 kV
Overvoltages at IN, S, or D are clamped by internal diodes. Current should be
limited to the maximum ratings given.
Rev. A | Page 5 of 12
ADG701L/ADG702L
Data Sheet
D 1
NC 2
ADG701L/
ADG702L
D 1
8
S
7
GND
6 IN
NC 3
TOP VIEW
VDD 4 (Not to Scale) 5 NC
S 2
IN
VDD
5
NC
TOP VIEW
GND 3 (Not to Scale)
4
IN
05486-003
6
ADG701L/
ADG702L
NC = NO CONNECT
4
Figure 5. 5-Lead SOT-23 Pin Configuration
Figure 3. 8-Lead MSOP Pin Configuration
S 2
VDD
05486-002
TOP VIEW
GND 3 (Not to Scale)
NC = NO CONNECT
D 1
5
ADG701L/
ADG702L
Figure 4. 6-Lead SOT-23 Pin Configuration
Table 4. Pin Function Descriptions
8-Lead MSOP
1
2, 3, 5
4
6
7
8
Pin Number
6-lead SOT-23
1
5
6
4
3
2
5-lead SOT-23
1
Not applicable
5
4
3
2
Mnemonic
D
NC
VDD
IN
GND
S
Description
Drain Terminal. Can be an input or output.
No Connect.
Most Positive Power Supply Potential.
Logic Control Input.
Ground (0 V) Reference.
Source Terminal. May be an input or output.
Table 5. Truth Table
ADG701L In
0
1
05486-004
PIN CONFIGURATIONS AND FUNCTION DESCRIPTIONS
ADG702L In
1
0
Switch Condition
Off
On
Rev. A | Page 6 of 12
Data Sheet
ADG701L/ADG702L
TYPICAL PERFORMANCE CHARACTERISTICS
10m
3.5
VDD = 2.7V
TA = 25C
1m
3.0
100
2.5
VDD = 4.5V
2.0
1.5
VDD = 5.0V
10
1
100n
0.5
10n
05486-005
1.0
0
0.5
1.0
1.5
2.0
2.5
3.0
3.5
4.0
4.5
VD OR VS (DRAIN OR SOURCE VOLTAGE (V))
05486-008
ISUPPLY (A)
RON ()
VDD = 3.0V
0
VDD = 5V
1n
10
5.0
100
1k
10k
100k
FREQUENCY (Hz)
1M
10M
Figure 9. Supply Current (ISUPPLY) vs. Input Switching Frequency
Figure 6. RON as a Function of VD (VS) Single Supplies
–10
3.5
VDD = 3V
VDD = 5V, 3V
–20
3.0
–30
+85C
OFF ISOLATION (dB)
2.5
RON ()
+25C
2.0
–40C
1.5
1.0
–40
–50
–60
–70
–80
05486-006
0
0
0.5
1.0
1.5
2.0
2.5
VD OR VS (DRAIN OR SOURCE VOLTAGE (V))
05486-009
–90
0.5
–100
–110
10k
3.0
100k
1M
10M
FREQUENCY (Hz)
100M
Figure 10. Off Isolation vs. Frequency
Figure 7. RON as a Function of VD (VS) for Different Temperatures VDD = 3 V
0
3.5
VDD = 5V
VDD = 3V
3.0
RON ()
+85C
2.0
+25C
1.5
–40C
1.0
0
05486-007
0.5
0
0.5
1.0
1.5
2.0
2.5
3.0
3.5
4.0
4.5
VD OR VS (DRAIN OR SOURCE VOLTAGE (V))
–2
–4
–6
10k
5.0
Figure 8. RON as a Function of VD (VS) for Different Temperatures VDD = 5 V
Rev. A | Page 7 of 12
05486-010
ON RESPONSE (dB)
2.5
100k
1M
10M
FREQUENCY (Hz)
Figure 11. Bandwidth
100M
ADG701L/ADG702L
Data Sheet
TEST CIRCUITS
IDS
V1
D
VD
VS
Figure 12. RON
Figure 14. Off Leakage
VDD
VDD
0.1µF
0.1µF
VDD
VDD
VOUT
D
S
RL
50Ω
IN
RL
50Ω
IN
VIN
VIN
VS
05486-016
GND
VOUT
D
GND
Figure 13. Off Isolation
05486-017
S
Figure 15. Bandwidth
VDD
0.1µF
VIN
ADG701L
50%
50%
ADG702L
50%
50%
VDD
VS
VOUT
D
VIN
RL
300Ω
IN
CL
35pF
90%
VOUT
90%
GND
tON
tOFF
05486-014
S
Figure 16. Switching Times
VDD
VDD
VIN
D
S
ADG701L
ON
OFF
QINJ = CL × ∆VOUT
∆VOUT
VOUT
CL
1nF
VS
IN
VIN
ADG702L
VOUT
GND
Figure 17. Charge Injection
S
D
ID (ON)
A
VD
VS
Figure 18. On Leakage
Rev. A | Page 8 of 12
05486-015
RS
05486-013
VS
A
05486-012
S
A
RON = V1/IDS
VS
ID (OFF)
IS (OFF)
D
05486-011
S
Data Sheet
ADG701L/ADG702L
TERMINOLOGY
RON
Ohmic resistance between D and S.
RFLAT(ON)
Flatness is defined as the difference between the maximum and
minimum value of on resistance as measured over the specified
analog signal range.
tON
Delay between applying the digital control input and the output
switching on. See Figure 16.
tOFF
Delay between applying the digital control input and the output
switching off.
IS (OFF)
Source leakage current with the switch off.
Off Isolation
A measure of unwanted signal coupling through an off switch.
ID (OFF)
Drain leakage current with the switch off.
Charge Injection
ID, IS (ON)
Channel leakage current with the switch on.
VD (VS)
Analog voltage on Terminal D and Terminal S.
CS (OFF)
Off switch source capacitance.
CD (OFF)
Off switch drain capacitance.
CD, CS (ON)
On switch capacitance.
A measure of the glitch impulse transferred from the digital
input to the analog output during switching.
Bandwidth
The frequency at which the output is attenuated by −3 dB.
On Response
The frequency response of the on switch.
On Loss
The voltage drop across the on switch, seen in Figure 11 as the
number of decibels the signal is away from 0 dB at very low
frequencies.
Rev. A | Page 9 of 12
ADG701L/ADG702L
Data Sheet
APPLICATIONS INFORMATION
The ADG701L/ADG702L belong to the Analog Devices new
family of CMOS switches. This series of general-purpose switches
have improved switching times, lower RON, higher bandwidth,
low power consumption, and low leakage currents.
SUPPLY VOLTAGES
Functionality of the ADG701L/ADG702L extends from 1.8 V to
5.5 V single supply, making the parts ideal for battery-powered
instruments where power, efficiency, and performance are
important design parameters.
It is important to note that the supply voltage affects the input
signal range, the on resistance, and the switching times of the
part. The effects of the power supplies can be clearly seen in the
Typical Performance Characteristics section and the
Specifications section.
The signal transfer characteristic is dependent on the switch
channel capacitance, CDS. This capacitance creates a frequency
zero in the numerator of the transfer function, A(s). Because
the switch on resistance is small, this zero usually occurs at high
frequencies. The bandwidth is a function of the switch output
capacitance combined with CDS and the load capacitance. The
frequency pole corresponding to these capacitances appears in
the denominator of A(s).
The dominant effect of the output capacitance, CD, causes the
pole breakpoint frequency to occur first. In order to maximize
bandwidth, a switch must have a low input and output capacitance and low on resistance. The on response versus frequency
for the ADG701L/ADG702L is shown in Figure 11.
OFF ISOLATION
Off isolation is a measure of the input signal coupled through
an off switch to the switch output. The capacitance, CDS,
couples the input signal to the output load when the switch is
off (see Figure 20).
BANDWIDTH
Figure 19 illustrates the parasitic components that affect the ac
performance of CMOS switches (a box surrounds the switch).
Additional external capacitances further degrade some performance. These capacitances affect feedthrough, crosstalk, and
system bandwidth.
CDS
S
VIN
D
VIN
CD
CLOAD
VOUT
RLOAD
05486-018
RON
CD
CLOAD
VOUT
RLOAD
Figure 20. Off Isolation Is Affected by External Load Resistance and
Capacitance
CDS
S
D
05486-019
For VDD = 1.8 V operation, RON is typically 40 Ω over the
temperature range.
Figure 19. Switch Represented by Equivalent Parasitic Components
The transfer function that describes the equivalent diagram of
the switch (see Figure 19) is of the form A(s), as shown in the
following equation:
s(RON CDS ) 1
A(s) RT
s(RON CT RT ) 1
and calculate the total capacitance, CT, with the following
equation:
The larger the value of CDS, the larger the values of feedthrough
produced. Figure 10 illustrates the drop in off isolation as a
function of frequency. From dc to roughly 1 MHz, the switch
shows better than −75 dB isolation. Up to frequencies of
10 MHz, the off isolation remains better than −55 dB. As the
frequency increases, more and more of the input signal is
coupled through to the output. Off isolation can be maximized
by choosing a switch with the smallest CDS possible. The values
of load resistance and capacitance also affect off isolation, as
they contribute to the coefficients of the poles and zeros in the
transfer function of the switch when open.
s(RLOADCDS ) 1
A(s) RT
s(RLOAD )(CT ) 1
CT = CLOAD + CD + CDS
where CDS is the drain/source capacitance.
Rev. A | Page 10 of 12
Data Sheet
ADG701L/ADG702L
OUTLINE DIMENSIONS
3.20
3.00
2.80
8
3.20
3.00
2.80
5.15
4.90
4.65
5
1
4
PIN 1
IDENTIFIER
0.65 BSC
0.95
0.85
0.75
15° MAX
1.10 MAX
0.80
0.55
0.40
0.23
0.09
6°
0°
0.40
0.25
10-07-2009-B
0.15
0.05
COPLANARITY
0.10
COMPLIANT TO JEDEC STANDARDS MO-187-AA
Figure 21. 8-Lead Mini Small Outline Package [MSOP]
(RM-8)
Dimensions shown in millimeters
3.00
2.90
2.80
1.70
1.60
1.50
6
5
4
1
2
3
3.00
2.80
2.60
PIN 1
INDICATOR
0.95 BSC
1.90
BSC
1.45 MAX
0.95 MIN
0.15 MAX
0.05 MIN
0.50 MAX
0.30 MIN
0.20 MAX
0.08 MIN
SEATING
PLANE
10°
4°
0°
0.60
BSC
COMPLIANT TO JEDEC STANDARDS MO-178-AB
Figure 22. 6-Lead Small Outline Transistor Package [SOT-23]
(RJ-6)
Dimensions shown in millimeters
Rev. A | Page 11 of 12
0.55
0.45
0.35
12-16-2008-A
1.30
1.15
0.90
ADG701L/ADG702L
Data Sheet
3.00
2.90
2.80
1.70
1.60
1.50
5
1
4
2
3.00
2.80
2.60
3
0.95 BSC
1.90
BSC
1.45 MAX
0.95 MIN
0.15 MAX
0.05 MIN
0.50 MAX
0.35 MIN
0.20 MAX
0.08 MIN
SEATING
PLANE
10°
5°
0°
0.60
BSC
COMPLIANT TO JEDEC STANDARDS MO-178-AA
0.55
0.45
0.35
11-01-2010-A
1.30
1.15
0.90
Figure 23. 5-Lead Small Outline Transistor Package [SOT-23]
(RJ-5)
Dimensions shown in millimeters
ORDERING GUIDE
Model1
ADG701LBRJZ-500RL7
ADG701LBRJZ-REEL7
ADG701LBRMZ
ADG701LBRMZ-REEL7
ADG701LBRTZ-REEL7
ADG702LBRMZ
ADG702LBRTZ-REEL7
1
2
Temperature Range
−40°C to +85°C
−40°C to +85°C
−40°C to +85°C
−40°C to +85°C
−40°C to +85°C
−40°C to +85°C
−40°C to +85°C
Package Description
5-Lead Small Outline Transistor Package [SOT-23]
5-Lead Small Outline Transistor Package [SOT-23]
8-Lead Mini Small Outline Package [MSOP]
8-Lead Mini Small Outline Package [MSOP]
6-Lead Small Outline Transistor Package [SOT-23]
8-Lead Mini Small Outline Package [MSOP]
6-Lead Small Outline Transistor Package [SOT-23]
Z = RoHS Compliant Part.
Due to package size limitations, these three characters represent the part number.
©2006–2020 Analog Devices, Inc. All rights reserved. Trademarks and
registered trademarks are the property of their respective owners.
D05486-1/20(A)
Rev. A | Page 12 of 12
Package Option
RJ-5
RJ-5
RM-8
RM-8
RJ-6
RM-8
RJ-6
Marking Code2
S10
S10
S10
S10
S10
S11
S11
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湘ICP备2023018690号
