FEATURES
FUNCTIONAL BLOCK DIAGRAMS
1.8 V to 5.5 V single-supply operation
±2.5 V dual-supply operation
On resistance: 4 Ω at 25°C (+5 V single supply/±2.5 V dual
supply)
0.5 Ω on-resistance flatness at 25°C (+5 V single supply/
±2.5 V dual supply)
Rail-to-rail operation
Transition times: 23 ns typical at 25°C
Single 32-to-1 channel multiplexer
Dual/differential 16-to-1 channel multiplexer
TTL-/CMOS-compatible inputs
48-lead TQFP or 48-lead, 7 mm × 7 mm LFCSP
ADG726
S1A
DA
S16A
S1B
DB
S16B
WR
CSA
1-OF-16
DECODER
02765-001
CSB
A0 A1 A2 A3 EN
Figure 1.
APPLICATIONS
Optical applications
Data acquisition systems
Communication systems
Relay replacement
Audio and video switching
Battery-powered systems
Medical instrumentation
Automatic test equipment (ATE)
ADG732
S1
D
S32
WR
1-OF-32
DECODER
CS
A0 A1 A2 A3 A4 EN
02765-002
Data Sheet
16-/32-Channel, 4 Ω, +1.8 V to +5.5 V and
±2.5 V Analog Multiplexers
ADG726/ADG732
Figure 2.
GENERAL DESCRIPTION
The ADG726/ADG732 are monolithic, complementary metal
oxide semiconductor (CMOS) 32-channel and dual 16-channel
analog multiplexers. The ADG732 switches one of 32 inputs (S1 to
S32) to a common output, D, as determined by the 5-bit binary
address lines A0, A1, A2, A3, and A4. The ADG726 switches one
of 16 inputs as determined by the 4-bit binary address lines A0, A1,
A2, and A3.
On-chip latches facilitate microprocessor interfacing. The ADG726
may also be configured for differential operation by tying CSA
and CSB together. An EN input is used to enable or disable the
devices. When disabled, all channels are switched off.
These multiplexers are designed on an enhanced submicron
process that provides low power dissipation yet gives high
switching speed, very low on resistance, and leakage currents.
They operate from a single supply of +1.8 V to +5.5 V and a
±2.5 V dual supply, making them ideally suited to a variety of
applications. On resistance is in the region of a few ohms and is
Rev. C
closely matched between switches and very flat over the full signal
range. These devices can operate equally well as either multiplexers
or demultiplexers and have an input signal range that extends
to the supplies. In the off condition, signal levels up to the
supplies are blocked. All channels exhibit break-before-make
switching action, preventing momentary shorting when switching
channels.
The ADG726/ADG732 are available in a 48-lead LFCSP or a 48lead TQFP. For functionally equivalent devices with serial
interface, see the ADG725/ADG731.
PRODUCT HIGHLIGHTS
1.
2.
3.
4.
+1.8 V to +5.5 V single- or ±2.5 V dual-supply operation.
These devices are specified and guaranteed with +5 V ± 10%,
+3 V ± 10% single-supply, and ±2.5 V ± 10% dual-supply
rails.
An on resistance of 4 Ω.
Guaranteed break-before-make switching action.
48-lead LFCSP package or 48-lead TQFP package.
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Technical Support
www.analog.com
ADG726/ADG732
Data Sheet
TABLE OF CONTENTS
Features .............................................................................................. 1
Absolute Maximum Ratings ............................................................9
Applications ...................................................................................... 1
ESD Caution ..................................................................................9
Functional Block Diagrams............................................................. 1
Pin Configurations and Function Description .......................... 10
General Description ......................................................................... 1
48-Lead TQFP ............................................................................ 10
Product Highlights............................................................................. 1
48-Lead LFCSP ........................................................................... 12
Revision History ............................................................................... 2
Typical Performance Characteristics .......................................... 15
Specifications .................................................................................... 3
Test Circuits .................................................................................... 17
+5 V Single Supply ....................................................................... 3
Terminology.................................................................................... 20
+3 V Single Supply ....................................................................... 5
Outline Dimensions ....................................................................... 21
±2.5 V Dual Supply ...................................................................... 7
Ordering Guide .......................................................................... 21
Timing Characteristics ................................................................ 8
REVISION HISTORY
2/2021—Rev. B to Rev. C
Changed CP-48-1 to CP-48-4 ...................................... Throughout
Changes to Figure 6........................................................................ 12
Changes to Figure 7........................................................................ 13
Updated Outline Dimensions ....................................................... 21
Changes to Ordering Guide .......................................................... 21
6/2015—Rev. A to Rev. B
Changes to Figure 4 and Table 6 .................................................. 10
Added Figure 5 and Table 7; Renumbered Sequentially .......... 11
Added Figure 6 and Table 8 .......................................................... 12
Changes to Figure 7, Table 9, and Table 10 ................................ 13
Changes to Table 11 ....................................................................... 14
2/2015—Rev. 0 to Rev. A
Updated Format ................................................................ Universal
Changes to Features Section ........................................................... 1
Changes to Table 1 ........................................................................... 3
Changes to Table 2 ............................................................................5
Changes to Table 3 ............................................................................7
Changes to Table 5 ............................................................................9
Added Table 6; Renumbered Sequentially ................................. 10
Added Table 7 ................................................................................. 11
Changes to Figure 5 ....................................................................... 11
Changes to Figure 8 to Figure 11 ................................................. 13
Changes to Figure 13 and Figure 15 to Figure 17 ...................... 14
Changes to Figure 25 to Figure 28 ............................................... 16
Changes to Figure 29 ..................................................................... 17
Moved Terminology Section ........................................................ 18
Changes to Terminology Section ................................................. 18
Updated Outline Dimensions ...................................................... 19
Changes to Ordering Guide .......................................................... 19
7/2002—Revision 0: Initial Version
Rev. C | Page 2 of 21
Data Sheet
ADG726/ADG732
SPECIFICATIONS
+5 V SINGLE SUPPLY
VDD = 5 V ± 10%, VSS = 0 V, GND = 0 V, unless otherwise noted.
Table 1.
Parameter
ANALOG SWITCH
Analog Signal Range
On Resistance
Symbol
RON
On Resistance Match Between
Channels
ΔRON
On Resistance Flatness
RFLAT (ON)
ADG726/ADG732
−40°C to
+25°C +85°C
4
5.5
0 V to VDD
5
6
0.3
0.8
Drain Off Leakage
ADG726
ADG732
Channel On Leakage
ADG726
ADG732
DIGITAL INPUTS
Input High Voltage
Input Low Voltage
Input Current
Low or High
Digital Input Capacitance
DYNAMIC CHARACTERISTICS1
Transition Time
IS (Off)
ID (Off)
ID, IS (On)
5
tTRANSITION
23
34
18
tD
On Time (CS, WR)
tON (CS, WR)
Off Time (CS, WR)
tOFF (CS, WR)
On Time (EN)
tON (EN)
Charge Injection
Off Isolation
Channel-to-Channel Crosstalk
−3 dB Bandwidth
ADG726
ADG732
tOFF (EN)
QINJ
ISO
CTK
BW
1
1.2
18
25
17
23
24
32
16
22
5
−72
−72
Unit
V
Ω typ
Ω max
Ω typ
Ω max
Ω typ
Ω max
Test Conditions/Comments
VS = 0 V to VDD, IDS = 10 mA, see Figure 20
VS = 0 V to VDD, IDS = 10 mA
VS = 0 V to VDD, IDS = 10 mA
VDD = 5.5 V
VD = 4.5 V/1 V, VS = 1 V/4.5 V, see Figure 21
±2.5
±5
±10
nA typ
nA max
nA typ
nA max
nA max
nA typ
nA max
nA max
2.4
0.8
2.4
0.8
V min
V max
±0.5
μA typ
μA max
pF typ
VIN = VINL or VINH
±0.5
40
48
RL = 300 Ω, CL = 35 pF, see Figure 27
VS1 = 3 V/0 V, VS32 = 0 V/3 V
RL = 300 Ω, CL = 35 pF; VS = 3 V, see Figure 28
1
1
32
38.5
ns typ
ns max
ns typ
ns min
ns typ
ns max
ns typ
ns max
ns typ
ns max
ns typ
ns max
pC typ
dB typ
dB typ
±1
±2.5
±5
±2
±10
0.005
CIN
Break-Before-Make Time Delay
Off Time (EN)
±0.01
±0.25
±0.05
±0.5
±1
±0.05
±0.5
±1
VINH
VINL
IINL or IINH
7
0.5
1
LEAKAGE CURRENTS
Source Off Leakage
ADG732
−40°C to
+125°C
29
33
40
43
25
25
34
18
MHz typ
MHz typ
Rev. C | Page 3 of 21
VD = 4.5 V/1 V, VS = 1 V/4.5 V, see Figure 24
VD = VS = 1 V, or 4.5 V, see Figure 25
RL = 300 Ω, CL = 35 pF; VS = 3 V, see Figure 29
RL = 300 Ω, CL = 35 pF; VS = 3 V, see Figure 29
RL = 300 Ω, CL = 35 pF; VS = 3 V, see Figure 30
RL = 300 Ω, CL = 35 pF; VS = 3 V, see Figure 30
VS = 2.5 V, RS = 0 Ω, CL = 1 nF, see Figure 31
RL = 50 Ω, CL = 5 pF, f = 1 MHz, see Figure 22
RL = 50 Ω, CL = 5 pF, f = 1 MHz, see Figure 23
RL = 50 Ω, CL = 5 pF, see Figure 26
ADG726/ADG732
Parameter
Off Switch Source Capacitance
Off Switch Drain Capacitance
ADG726
ADG732
On Switch Drain, Source
Capacitance
ADG726
ADG732
POWER REQUIREMENTS
Positive Supply Current
Data Sheet
Symbol
CS (Off)
CD (Off)
ADG726/ADG732
−40°C to
+25°C +85°C
13
Unit
pF typ
Test Conditions/Comments
f = 1 MHz
170
340
pF typ
pF typ
f = 1 MHz
f = 1 MHz
175
350
pF typ
pF typ
f = 1 MHz
f = 1 MHz
VDD = 5.5 V
Digital inputs = 0 V or 5.5 V
CD, CS (On)
IDD
10
20
1
ADG732
−40°C to
+125°C
20
Guaranteed by design; not subject to production test.
Rev. C | Page 4 of 21
μA typ
μA max
Data Sheet
ADG726/ADG732
+3 V SINGLE SUPPLY
VDD = 3 V ± 10%, VSS = 0 V, GND = 0 V, unless otherwise noted.
Table 2.
Parameter
ANALOG SWITCH
Analog Signal Range
On Resistance
Symbol
ADG726/ADG732
−40°C to
+25°C +85°C
0 V to
VDD
RON
7
11
On Resistance Match Between
Channels
ΔRON
12
0.35
On Resistance Flatness
RFLAT (ON)
1
3
LEAKAGE CURRENTS
Source Off Leakage
Drain Off Leakage
ADG726
ADG732
Channel On Leakage
ADG726
ADG732
DIGITAL INPUTS
Input High Voltage
Input Low Voltage
Input Current
Low or High
Digital Input Capacitance
DYNAMIC CHARACTERISTICS1
Transition Time
IS (Off)
ID (Off)
ID, IS (On)
IINL or IINH
5
tTRANSITION
34
52
26
On Time (CS, WR)
tON (WR, CS)
tOFF (WR, CS)
On Time (EN)
tON (EN)
Off Time (EN)
tOFF (EN)
QINJ
ISO
CTK
BW
29
43
26
38
33
48
19
25
1
−72
−72
Unit
Test Conditions/Comments
V
13
1
Ω typ
Ω max
Ω typ
Ω max
Ω typ
VS = 0 V to VDD, IDS = 10 mA, see Figure 20
VS = 0 V to VDD, IDS = 10 mA
VS = 0 V to VDD, IDS = 10 mA
VDD = 3.3 V
VS = 3 V/1 V, VD = 1 V/3 V, see Figure 21
±2.5
±5
±10
nA typ
nA max
nA typ
nA max
nA max
nA typ
nA max
nA max
2.0
0.7
2.0
0.7
V min
V max
±0.5
μA typ
μA max
pF typ
VIN = VINL or VINH
±0.5
62
69
RL = 300 Ω, CL = 35 pF, see Figure 27
VS1 = 2 V/0 V, VS32 = 0 V/2 V
RL = 300 Ω, CL = 35 pF; VS = 2 V, see Figure 28
1
1
52
60
42
55.5
ns typ
ns max
ns typ
ns min
ns typ
ns max
ns typ
ns max
ns typ
ns max
ns typ
ns max
pC typ
dB typ
dB typ
±1
±2.5
±5
±2
±10
0.005
CIN
tD
Charge Injection
Off Isolation
Channel-to-Channel Crosstalk
−3 dB Bandwidth
ADG726
ADG732
±0.01
±0.25
±0.05
±0.5
±1
±0.05
±0.5
±1
VINH
VINL
Break-Before-Make Time Delay
Off Time (CS, WR)
ADG732
−40°C to
+125°C
55
63.5
28
28
34
18
MHz typ
MHz typ
Rev. C | Page 5 of 21
VS = 1 V/3 V, VD = 3 V/1 V, see Figure 24
VS = VD = 1 V or 3 V, see Figure 25
RL = 300 Ω, CL = 35 pF; VS = 2 V, see Figure 29
RL = 300 Ω, CL = 35 pF; VS = 2 V, see Figure 29
RL = 300 Ω, CL = 35 pF; VS = 2 V, see Figure 30
RL = 300 Ω, CL = 35 pF; VS = 2 V, see Figure 30
VS = 1.5 V, RS = 0 Ω, CL = 1 nF, see Figure 31
RL = 50 Ω, CL = 5 pF, f = 1 MHz, see Figure 22
RL = 50 Ω, CL = 5 pF, f = 1 MHz, see Figure 23
RL = 50 Ω, CL = 5 pF, see Figure 26
ADG726/ADG732
Parameter
Off Switch Source Capacitance
Off Switch Drain Capacitance
ADG726
ADG732
On Switch Drain, Source
Capacitance
ADG726
ADG732
POWER REQUIREMENTS
Positive Supply Current
Data Sheet
Symbol
CS (Off)
CD (Off)
ADG726/ADG732
−40°C to
+25°C +85°C
13
Unit
pF typ
Test Conditions/Comments
f = 1 MHz
170
340
pF typ
pF typ
f = 1 MHz
f = 1 MHz
175
350
pF typ
pF typ
f = 1 MHz
f = 1 MHz
VDD = 3.3 V
Digital inputs = 0 V or 3.3 V
CD, CS (On)
IDD
5
10
1
ADG732
−40°C to
+125°C
10
Guaranteed by design; not subject to production test.
Rev. C | Page 6 of 21
μA typ
μA max
Data Sheet
ADG726/ADG732
±2.5 V DUAL SUPPLY
VDD = +2.5 V ± 10%, VSS = −2.5 V ± 10%, GND = 0 V, unless otherwise noted.
Table 3.
Parameter
ANALOG SWITCH
Analog Signal Range
On Resistance
Symbol
∆RON
On Resistance Flatness
RFLAT (ON)
Drain Off Leakage
ADG726
ADG732
Channel On Leakage
ADG726
ADG732
DIGITAL INPUTS
Input High Voltage
Input Low Voltage
Input Current
7
0.8
1
1
1.2
0.5
±0.5
ID (Off)
±0.25
±0.05
±0.5
±1
±0.05
±0.5
±1
±2.5
±5
ID, IS (On)
VINH
VINL
5
tTRANSITION
33
45
15
On Time (CS, WR)
tON (WR, CS)
Off Time (CS, WR)
tOFF (WR, CS)
On Time (EN)
tON (EN)
tOFF (EN)
QINJ
ISO
CTK
BW
±1
21
30
20
29
26
37
18
26
1
−72
−72
Unit
V
Ω typ
Ω max
Ω typ
Test Conditions/Comments
VS = VSS to VDD, IDS = 10 mA, see Figure 20
VS = VSS to VDD, IDS = 10 mA
Ω max
Ω typ
Ω max
VS = VSS to VDD, IDS = 10 mA
nA typ
VDD = +2.75 V, VSS = −2.75 V
VS = +2.25 V/−1.25 V, VD = −1.25 V/+2.25 V,
see Figure 21
nA max
nA typ
VS = +2.25 V/−1.25 V, VD = −1.25 V/+2.25 V,
see Figure 24
±2.5
±5
±10
nA max
nA max
nA typ
nA max
nA max
1.7
0.7
1.7
0.7
V min
V max
±0.5
μA typ
μA max
pF typ
VIN = VINL or VINH
±0.5
51
56
RL = 300 Ω, CL = 35 pF, see Figure 27
VS1 = 1.5 V/0 V, VS32 = 0 V/1.5 V
RL = 300 Ω, CL = 35 pF; VS = 1.5 V, see Figure 28
1
1
37
43
ns typ
ns max
ns typ
ns min
ns typ
ns max
ns typ
ns max
ns typ
ns max
ns typ
ns max
pC typ
dB typ
dB typ
±10
0.005
CIN
tD
Charge Injection
Off Isolation
Channel-to-Channel Crosstalk
−3 dB Bandwidth
ADG726
ADG732
6
0.3
±0.01
Break-Before-Make Time Delay
Off Time (EN)
4
5.5
IS (Off)
IINL or IINH
Digital Input Capacitance
DYNAMIC CHARACTERISTICS1
Transition Time
ADG732
−40°C to
+125°C
VSS to VDD
RON
On Resistance Match Between
Channels
LEAKAGE CURRENTS
Source Off Leakage
ADG726/ADG732
−40°C to
+25°C +85°C
35
38
50
29
29
34
18
MHz typ
MHz typ
Rev. C | Page 7 of 21
VS = VD = +2.25 V/−1.25 V, see Figure 25
RL = 300 Ω, CL = 35 pF; VS = 1.5 V, see Figure 29
RL = 300 Ω, CL = 35 pF; VS = 1.5 V, see Figure 29
RL = 300 Ω, CL = 35 pF; VS = 1.8 V, see Figure 30
RL = 300 Ω, CL = 35 pF; VS = 1.8 V, see Figure 30
VS = 0 V, RS = 0 Ω, CL = 1 nF, see Figure 31
RL = 50 Ω, CL = 5 pF, f = 1 MHz, see Figure 22
RL = 50 Ω, CL = 5 pF, f = 1 MHz, see Figure 23
RL = 50 Ω, CL = 5 pF, see Figure 26
ADG726/ADG732
Parameter
Off Switch Source Capacitance
Off Switch Drain Capacitance
ADG726
ADG732
On Switch Drain, Source
Capacitance
ADG726
ADG732
POWER REQUIREMENTS
Positive Supply Current
Negative Supply Current
1
Data Sheet
ADG726/ADG732
−40°C to
+25°C +85°C
13
Symbol
CS (Off)
CD (Off)
ADG732
−40°C to
+125°C
Unit
pF typ
Test Conditions/Comments
137
275
pF typ
pF typ
f = 1 MHz
f = 1 MHz
150
300
pF typ
pF typ
f = 1 MHz
f = 1 MHz
μA typ
μA max
μA typ
μA max
VDD = 2.75 V
Digital inputs = 0 V or 2.75 V
VDD = −2.75 V
Digital inputs = 0 V or 2.75 V
CD, CS (On)
IDD
10
ISS
20
20
20
20
10
Guaranteed by design; not subject to production test.
TIMING CHARACTERISTICS
Table 4.
Parameter1, 2, 3
t1
t2
t3
t4
t5
t6
1
2
3
Limit at TMIN, TMAX
0
0
10
10
5
2
Unit
ns min
ns min
ns min
ns min
ns min
ns min
Test Conditions/Comments
CS to WR setup time
CS to WR hold time
WR pulse width
Time between WR cycles
Address, enable setup time
Address, enable hold time
See Figure 3.
All input signals are specified with tr = tf = 1 ns (10% to 90% of VDD).
Guaranteed by design and characterization, not production tested.
CS
t1
t2
t3
t4
WR
t6
02765-003
t5
A0, A1, A2, A3, (A4)
EN
Figure 3. Timing Diagram
Figure 3 shows the timing sequence for latching the switch
address and enable inputs. The latches are level sensitive; therefore,
while WR is held low, the latches are transparent and the switches
respond to changing the address and enable the inputs.
Input data is latched on the rising edge of WR. The ADG726
has two CS inputs. This enables the device to be used either as a
dual 16-to-1 channel multiplexer or a differential 16-channel
multiplexer. If a differential output is required, tie CSA and
CSB together.
Rev. C | Page 8 of 21
Data Sheet
ADG726/ADG732
ABSOLUTE MAXIMUM RATINGS
TA = 25°C, unless otherwise noted.
Table 5.
Parameter
VDD to VSS
VDD to GND
VSS to GND
Analog Inputs1
Digital Inputs1
Peak Current, S or D (Pulsed at 1 ms,
10% Duty Cycle Maximum)
Continuous Current, S or D
Operating Temperature Range
ADG726
ADG732
Storage Temperature Range
Junction Temperature
Thermal Impedance θJA (4-Layer Board)
48-Lead LFCSP
48-Lead TQFP
Reflow Soldering Peak Temperature,
Pb Free
1
Rating
7V
−0.3 V to +7 V
+0.3 V to −7 V
VSS − 0.3 V to VDD + 0.3 V
or 30 mA, whichever
occurs first
–0.3 V to VDD + 0.3 V or
30 mA, whichever
occurs first
60 mA
Stresses at or above those listed under Absolute Maximum
Ratings may cause permanent damage to the product. This is a
stress rating only; functional operation of the product at these
or any other conditions above those indicated in the
operational section of this specification is not implied.
Operation beyond the maximum operating conditions for
extended periods may affect product reliability.
ESD CAUTION
30 mA
−40°C to +85°C
−40°C to +125°C
−65°C to +150°C
150°C
25°C/W
54.6°C/W
As per JEDEC J-STD-020
Overvoltages at A, EN, WR, CS, S, or D will be clamped by internal diodes.
Current should be limited to the maximum ratings given.
Rev. C | Page 9 of 21
ADG726/ADG732
Data Sheet
PIN CONFIGURATIONS AND FUNCTION DESCRIPTION
S13B
S14B
S15B
S16B
DB
NIC
DA
NIC
S16A
S15A
S14A
S13A
48-LEAD TQFP
48 47 46 45 44 43 42 41 40 39 38 37
S12A 1
36
S12B
S11A 2
35
S11B
S10A 3
34
S10B
S9A 4
33
S9B
S8A 5
32
S8B
S7A 6
ADG726
31
S7B
S6A 7
TOP VIEW
(Not to Scale)
30
S6B
S5A 8
29
S5B
S4A 9
28
S4B
S3A 10
27
S3B
S2A 11
26
S2B
S1A 12
25
S1B
NOTES
1. NIC = NOT INTERNALLY CONNECTED. DO NOT CONNECT TO THIS PIN.
02765-005
GND
VSS
EN
WR
CSB
CSA
A3
A2
A1
A0
VDD
VDD
13 14 15 16 17 18 19 20 21 22 23 24
Figure 4. ADG726 Pin Configuration
Table 6. ADG726 Pin Function Description
Pin No.
1 to 12, 45 to 48
13, 14
15 to 18
19
Mnemonic
S16A to S1A
VDD
A0 to A3
CSA
20
CSB
21
WR
22
EN
23
24
GND
VSS
25 to 40
41
42, 44
43
S1B to S16B
DB
NIC
DA
Description
Source Terminal. This pin may be an input or output.
Most Positive Power Supply Potential.
Logic Control Inputs.
Chip Select Pin A. CSA is active low. If a differential output configuration is required, tie CSA and CSB
together.
Chip Select Pin B. CSB is active low. If a differential output configuration is required, tie CSB and CSA
together.
Write pin. When WR is low, the logic control inputs (A0 to A3) control which state the switches are in. On
the rising edge of WR, the logic control input data is latched.
Active Low, Digital Input. When this pin is high, the device is disabled and all switches are off. When this
pin is low, the Ax logic control inputs determine the on switches. The EN input signal is not latched by WR
.
Ground (0 V) Reference.
Most Negative Power Supply in a Dual-Supply Application. In single-supply applications, connect this pin
to GND.
Source Terminal. This pin may be an input or output.
Drain Terminal. This pin may be an input or output.
Not Internally Connected. Do not connect to this pin.
Drain Terminal. This pin may be an input or output.
Rev. C | Page 10 of 21
S29
S30
S31
S32
NIC
NIC
D
NIC
S16
S15
S14
ADG726/ADG732
S13
Data Sheet
48 47 46 45 44 43 42 41 40 39 38 37
S12 1
36 S28
S11 2
35 S27
S10 3
34 S26
S9 4
33 S25
S8 5
32 S24
S7 6
ADG732
31 S23
S6 7
TOP VIEW
(Not to Scale)
30 S22
S5 8
29 S21
S4 9
28 S20
S3 10
27 S19
S2 11
26 S18
S1 12
25 S17
NOTES
1. NIC = NOT INTERNALLY CONNECTED. DO NOT CONNECT TO THIS PIN.
02765-104
VSS
GND
EN
WR
CS
A4
A3
A2
A1
A0
VDD
VDD
13 14 15 16 17 18 19 20 21 22 23 24
Figure 5. ADG732 Pin Configuration
Table 7. ADG732 Pin Function Description
Pin No.
1 to 12, 45 to 48
13, 14
15 to 19
20
21
Mnemonic
S16 to S1
VDD
A0 to A4
CS
WR
22
EN
23
24
GND
VSS
25 to 40
41, 42, 44
43
S17 to S32
NIC
D
Description
Source Terminal. This pin may be an input or output.
Most Positive Power Supply Potential.
Logic Control Inputs.
Chip Select Pin. CS is active low.
Write Pin. When WR is low, the logic control inputs (A0 to A4) control which state the switches are in. On
the rising edge of WR, the logic control input data is latched.
Active Low, Digital Input. When this pin is high, the device is disabled and all switches are off. When this
pin is low, the Ax logic control inputs determine the on switches. The EN input signal is not latched by WR.
Ground (0 V) Reference.
Most Negative Power Supply in a Dual-Supply Application. In single-supply applications, connect this pin
to GND.
Source Terminal. This pin may be an input or output.
Not Internally Connected. Do not connect to this pin.
Drain Terminal. This pin may be an input or output.
Rev. C | Page 11 of 21
ADG726/ADG732
Data Sheet
48
47
46
45
44
43
42
41
40
39
38
37
S13A
S14A
S15A
S16A
NIC
DA
NIC
DB
S16B
S15B
S14B
S13B
48-LEAD LFCSP
1
2
3
4
5
6
7
8
9
10
11
12
TOP VIEW
(Not to Scale)
36
35
34
33
32
31
30
29
28
27
26
25
S12B
S11B
S10B
S9B
S8B
S7B
S6B
S5B
S4B
S3B
S2B
S1B
NOT INTERNALLY CONNECTED.
02765-105
VDD
VDD
A0
A1
A2
A3
CSA
CSB
WR
EN
GND
VSS
13
14
15
16
17
18
19
20
21
22
23
24
S12A
S11A
S10A
S9A
S8A
S7A
S6A
S5A
S4A
S3A
S2A
S1A
Figure 6. ADG726 Pin Configuration
Table 8. ADG726 Pin Function Description
Pin No.
1 to 12, 45 to 48
13, 14
15 to 18
19
Mnemonic
S16A to S1A
VDD
A0 to A3
CSA
20
CSB
21
WR
22
EN
23
24
GND
VSS
25 to 40
41
42, 44
43
S1B to S16B
DB
NIC
DA
EPAD
Description
Source Terminal. This pin may be an input or output.
Most Positive Power Supply Potential.
Logic Control Inputs.
Chip Select Pin A. CSA is active low. If a differential output configuration is required, tie CSA and CSB
together.
Chip Select Pin B. CSB is active low. If a differential output configuration is required, tie CSB and CSA
together.
Write pin. When WR is low, the logic control inputs (A0 to A3) control which state the switches are in. On
the rising edge of WR, the logic control input data is latched.
Active Low, Digital Input. When this pin is high, the device is disabled and all switches are off. When this pin is
low, the Ax logic control inputs determine the on switches. The EN input signal is not latched by WR.
Ground (0 V) Reference.
Most Negative Power Supply in a Dual-Supply Application. In single-supply applications, connect this pin
to GND.
Source Terminal. This pin may be an input or output.
Drain Terminal. This pin may be an input or output.
Not Internally Connected. Do not connect to this pin.
Drain Terminal. This pin may be an input or output.
Exposed Pad. The exposed pad must be connected to GND.
Rev. C | Page 12 of 21
ADG726/ADG732
48 S13
47 S14
46 S15
45 S16
44 NIC
43 D
42 NIC
41 NIC
40 S32
39 S31
38 S30
37 S29
Data Sheet
S12 1
S11 2
S10 3
S9 4
S8 5
S7 6
S6 7
S5 8
S4 9
S3 10
S2 11
S1 12
ADG732
NOTES
1. NIC = NOT INTERNALLY CONNECTED. DO NOT CONNECT TO THIS PIN.
2. THE EXPOSED PAD MUST BE CONNECTED TO GND.
02765-004
VDD 13
VDD 14
A0 15
A1 16
A2 17
A3 18
A4 19
CS 20
WR 21
EN 22
GND 23
V 24
TOP VIEW
(Not to Scale)
36 S28
35 S27
34 S26
33 S25
32 S24
31 S23
30 S22
29 S21
28 S20
27 S19
26 S18
25 S17
Figure 7. ADG732 Pin Configuration
Table 9. ADG732 Pin Function Description
Pin No.
1 to 12, 45 to 48
13, 14
15 to 19
20
21
Mnemonic
S16 to S1
VDD
A0 to A4
CS
WR
22
EN
23
24
GND
VSS
25 to 40
41, 42, 44
43
S17 to S32
NIC
D
EPAD
Description
Source Terminal. This pin may be an input or output.
Most Positive Power Supply Potential.
Logic Control Inputs.
Chip Select Pin. CS is active low.
Write Pin. When WR is low, the logic control inputs (A0 to A4) control which state the switches are in. On
the rising edge of WR, the logic control input data is latched.
Active Low, Digital Input. When this pin is high, the device is disabled and all switches are off. When this
pin is low, the Ax logic control inputs determine the on switches. The EN input signal is not latched by WR.
Ground (0 V) Reference.
Most Negative Power Supply in a Dual-Supply Application. In single-supply applications, connect this pin
to GND.
Source Terminal. This pin may be an input or output.
Not Internally Connected. Do not connect to this pin.
Drain Terminal. This pin may be an input or output.
Exposed Pad. The exposed pad must be connected to GND.
Truth Tables
Table 10. ADG726 Truth Table
A31
A21
A11
A01
EN1
CSA
CSB
WR1
On Switch
X
X
X
0
0
0
0
0
0
0
0
1
1
1
1
X
X
X
0
0
0
0
1
1
1
1
0
0
0
0
X
X
X
0
0
1
1
0
0
1
1
0
0
1
1
X
X
X
0
1
0
1
0
1
0
1
0
1
0
1
X
X
1
0
0
0
0
0
0
0
0
0
0
0
0
1
1
X
0
0
0
0
0
0
0
0
0
0
0
0
1
1
X
0
0
0
0
0
0
0
0
0
0
0
0
L→H
X
X
0
0
0
0
0
0
0
0
0
0
0
0
Latches control input data
No change in switch condition
None
S1A to DA, S1B to DB
S2A to DA, S2B to DB
S3A to DA, S3B to DB
S4A to DA, S4B to DB
S5A to DA, S5B to DB
S6A to DA, S6B to DB
S7A to DA, S7B to DB
S8A to DA, S8B to DB
S9A to DA, S9B to DB
S10A to DA, S10B to DB
S11A to DA, S11B to DB
S12A to DA, S12B to DB
Rev. C | Page 13 of 21
ADG726/ADG732
Data Sheet
A31
A21
A11
A01
EN1
CSA
CSB
WR1
On Switch
1
1
1
1
1
1
1
1
0
0
1
1
0
1
0
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
S13A to DA, S13B to DB
S14A to DA, S14B to DB
S15A to DA, S15B to DB
S16A to DA, S16B to DB
1
X is don’t care, L is low, and H is high.
Table 11. ADG732 Truth Table
A41
A31
A21
A11
A01
EN1
CS
WR1
Switch Condition
X
X
X
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
X
X
X
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
X
X
X
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
X
X
X
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
X
X
X
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
X
X
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
X
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
L→H
X
X
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Latches control input data
No change in switch condition
None
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
1
X is don’t care, L is low, and H is high.
Rev. C | Page 14 of 21
Data Sheet
ADG726/ADG732
TYPICAL PERFORMANCE CHARACTERISTICS
8
7
VDD = 3.3V
4
3
VDD = 4.5V
VDD = 5V
2
VDD = 5.5V
5
+25°C
4
–40°C
3
2
1.0
1.5
2.0
2.5
3.0
3.5
4.0
4.5
5.0
5.5
VD, VS (V)
0
0
0.5
2.5
8
TA = 25°C
VDD = +2.25V
VSS = –2.25V
ON RESISTANCE (Ω)
4
VDD = +2.75V
VSS = –2.75V
3
+85°C
5
4
3
2
2
1
1
–0.75
0.25
1.25
2.25
VD, VS (V)
+25°C
0
–2.5
02765-007
0
–1.75
+125°C
6
VDD = +2.75V
VSS = –2.75V
5
3.0
VDD = +2.5V
VSS = –2.5V
7
6
RESISTANCE (Ω)
2.0
Figure 11. On Resistance vs. VD (VS), Single Supply
7
–2.0
–1.5
–1.0
–0.5
0
–40°C
0.5
1.0
1.5
2.0
2.5
VD, VS (V)
Figure 9. On Resistance vs. VD (VS), Dual Supply
8
1.5
VD, VS (V)
Figure 8. On Resistance vs. VD (VS), Single Supply
8
1.0
02765-010
0.5
02765-006
0
02765-009
1
1
0
+125°C
+85°C
6
ON RESISTANCE (Ω)
5
VDD = +3V
7
VDD = 3.0V
6
ON RESISTANCE (Ω)
8
TA = 25°C
VSS = 0V
VDD = 2.7V
Figure 12. On Resistance vs. VD (VS), Dual Supply
2000
VDD = +5V
VDD = +5V
7
+125°C
LEAKAGE CURRENT (pA)
ON RESISTANCE (Ω)
1500
+85°C
6
5
4
+25°C
3
–40°C
2
ON (+, +)
1000
ON (–, –)
500
OFF (+, –)
0
0
0.5
1.0
1.5
2.0
2.5
3.0
VS, VD (V)
3.5
4.0
4.5
5.0
Figure 10. On Resistance vs. VD (VS) for Different Temperatures, Single Supply
Rev. C | Page 15 of 21
–500
OFF (–, +)
0
20
40
60
80
100
TEMPERATURE (°C)
Figure 13. Leakage Currents vs. Temperature
120
02765-011
0
02765-008
1
ADG726/ADG732
25
Data Sheet
0
TA = +25°C
–10
20
VDD = 5V
TA = 25°C
–20
15
–30
OFF ISOLATION (dB)
QINJ (pC)
10
5
0
–40
–50
–60
–70
–5
–80
–10
–3
–1
–2
0
1
2
3
4
5
VD, VS (V)
0
45
–10
tON, VDD = 3V
CROSSTALK (dB)
VDD = 3V, 5V
TA = 25°C
tON, VDD = 5V
25
20
tOFF, VDD = 3V
15
tOFF, VDD = 5V
–30
–40
–50
–60
–70
10
–80
5
0
20
40
60
80
100
120
TEMPERATURE (°C)
02765-013
–20
–100
0.03
0.1
1
10
100
FREQUENCY (MHz)
02765-016
–90
0
–40
Figure 18. Crosstalk vs. Frequency
Figure 15. tON/tOFF (EN) Time vs. Temperature
1.8
0
TA = +25°C
ADG726
1.6
–2
INSERTION LOSS (dB)
1.4
1.2
RISING
1.0
FALLING
0.8
0.6
–4
ADG732
–6
–8
–10
0.4
–12
0.2
VDD = 5V
TA = 25°C
0
1
2
3
4
5
6
VDD (V)
02765-014
0
Figure 16. Logic Threshold Voltage vs. Supply Voltage (VDD)
–14
0.03
0.1
1
10
FREQUENCY (MHz)
Figure 19. Insertion Loss vs. Frequency
Rev. C | Page 16 of 21
100
02765-017
TIME (ns)
100
–20
35
LOGIC THRESHOLD VOLTAGE (V)
10
Figure 17. Off Isolation vs. Frequency
50
30
1
FREQUENCY (MHz)
Figure 14. ADG732 Charge Injection (QINJ) vs. VD (VS)
40
0.1
02765-015
–90
–100
0.03
02765-012
–15
Data Sheet
ADG726/ADG732
TEST CIRCUITS
S1
V1
VDD
VSS
VDD
VSS
D
S2
D
VS
RON = V1/IDS
GND
S1
A
VDD
VSS
D
S2
VS
VDD
VSS
VDD
VSS
D
S1
EN
GND
LOGIC 1
VS
02765-019
VS
VD
GND
Figure 21. IS (Off)
VDD
VSS
50Ω
A0
ADG732*
NETWORK
ANALYZER
50Ω
S
VS
D
VOUT
RL
50Ω
EN
LOGIC 1
VSS
A4
VS
D
0.1µF
VDD
NETWORK
ANALYZER
50Ω
A4
S
VD
LOGIC 0
VSS
0.1µF
0.1µF
A0
EN
Figure 25. ID (On)
VSS
0.1µF
VDD
A
S32
S32
VDD
ID (ON)
VOUT
RL
50Ω
EN
ADG732*
GND
OFF ISOLATION = 20 LOG
VOUT
VS
*SIMILAR CONNECTION FOR ADG726.
02765-027
GND
INSERTION LOSS = 20 LOG
VOUT WITH SWITCH
VOUT WITHOUT SWITCH
*SIMILAR CONNECTION FOR ADG726.
Figure 26. Bandwidth
Figure 22. Off Isolation
VDD
VSS
VDD
VSS
S1
A4
A0
S2
S32
ADG732*
D
50Ω
NETWORK
ANALYZER
50Ω
VS
VOUT
RL
50Ω
*SIMILAR CONNECTION FOR ADG726.
CHANNEL-TO-CHANNEL CROSSTALK = 20LOG10 (VOUT/VS)
02765-028
EN CS GND WR
Figure 23. Channel-to-Channel Crosstalk
Rev. C | Page 17 of 21
02765-029
IS (OFF)
VSS
VD
LOGIC 1
Figure 24. ID (Off)
Figure 20. On Resistance
VDD
EN
02765-021
VS
A
S32
02765-018
S
ID(OFF)
02765-020
IDS
ADG726/ADG732
Data Sheet
VSS
VDD
VSS
A4
VIN
VIN
50Ω
ADDRESS
DRIVE (VIN)
VS1
S1
VS1
VS32
S32
ADG732*
50%
0V
S2 THRU S31
A0
50%
D
CL
35pF
RL
300Ω
EN CS GND WR
90%
VOUT
VOUT
90%
VS32
tTRANSITION
tTRANSITION
02765-022
VDD
*SIMILAR CONNECTION FOR ADG726.
Figure 27. Switching Time of Multiplexer, tTRANSITION
VSS
VDD
VSS
A4
VIN
50Ω
A0
VIN
VS
S1
ADDRESS
DRIVE (VIN)
S2 THRU S31
0V
S32
ADG732*
VS
D
RL
300Ω
EN CS GND WR
CL
35pF
VOUT
VOUT
80%
80%
02765-023
VDD
tOPEN
*SIMILAR CONNECTION FOR ADG726.
Figure 28. Break-Before-Make Delay, tOPEN
VDD
VSS
VDD
VSS
VIN
A4
VWR
S1
50%
0V
VS
S2 THRU S32
A0
ADG732*
WR
VWR
EN
D
RL
300Ω
GND
CL
35pF
VOUT
SWITCH
VOUT OUTPUT
0V
tON (WR)
20%
tOFF (WR)
20%
*SIMILAR CONNECTION FOR ADG726.
02765-024
CS
VCS
Figure 29. Write Turn-On and Turn-Off Time, tON, tOFF (WR)
VDD
VSS
VDD
VSS
A4
VIN
S1
VS
VEN
50%
A0
tON (EN)
EN
ADG732*
CS
GND
D
WR
RL
300Ω
CL
35pF
VOUT
SWITCH
OUTPUT
VOUT
90%
tOFF (EN)
10%
0V
02765-025
VEN
50%
0V
S2 THRU S32
*SIMILAR CONNECTION FOR ADG726.
Figure 30. Enable Delay, tON (EN), tOFF (EN)
Rev. C | Page 18 of 21
Data Sheet
ADG726/ADG732
A4
VDD
VSS
VDD
VSS
VIN
A0
LOGIC
INPUT (VIN)
ADG732*
S
VS
EN
VIN
CS
D
CL
1nF
GND WR
VOUT
0V
VOUT
QINJ = CL × ΔVOUT
ΔVOUT
02765-026
RS
*SIMILAR CONNECTION FOR ADG726.
Figure 31. Charge Injection
Rev. C | Page 19 of 21
ADG726/ADG732
Data Sheet
TERMINOLOGY
CD (Off)
CD (Off) represents the off switch drain capacitance. It is
measured with reference to ground.
IDD
IDD represents the positive supply current.
ISS
ISS represents the negative supply current.
CD (On), CS (On)
CD (On) and CS (On) represent the on switch capacitances,
which are measured with reference to ground.
IN
IN represents the logic control input.
VD (VS)
VD and VS represent the analog voltage on the Dx pins and the
Sx pins, respectively.
CIN
CIN is the digital input capacitance.
RON
RON represents the ohmic resistance between the Dx pins and
the Sx pins.
tTRANSITION
tTRANSITION is the delay time measured between the 50% and 90%
points of the digital inputs and the switch on condition when
switching from one address state to another.
ΔRON
ΔRON represents the difference between the RON of any two
channels.
tON (EN)
tON (EN) is the delay time between the 50% and 90% points of
the EN digital input and the switch on condition.
RFLAT(ON)
RFLAT(ON) is the flatness that is defined as the difference between
the maximum and minimum value of on resistance measured
over the specified analog signal range.
tOFF (EN)
tOFF (EN) is the delay time between the 50% and 90% points of
the EN digital input and the switch off condition.
IS (Off)
IS (Off) represents the source leakage current with the switch off.
ID (Off)
ID (Off) represents the drain leakage current with the switch off.
ID (On), IS (On)
ID (On) and IS (On) represent the channel leakage currents with
the switch on.
VINL
VINL is the maximum input voltage for Logic 0.
VINH
VINH is the minimum input voltage for Logic 1.
IINL, IINH
IINL and IINH represent the low and high input currents of the
digital inputs.
tOPEN
tOPEN is the off time measured between the 80% points of both
switches when switching from one address state to another
Charge Injection
Charge injection is a measure of the glitch impulse transferred
from the digital input to the analog output during switching.
Off Isolation
Off isolation is a measure of the unwanted signal coupling
through an off switch.
Channel-to-Channel Crosstalk
Crosstalk is a measure of unwanted signal that is coupled
through from one channel to another as a result of parasitic
capacitance.
Insertion Loss
Insertion loss is the loss due to the on resistance of the switch.
CS (Off)
CS (Off) represents the off switch source capacitance. It is
measured with a reference to ground.
Rev. C | Page 20 of 21
Data Sheet
ADG726/ADG732
OUTLINE DIMENSIONS
7.10
7.00 SQ
6.90
PIN 1
INDICATOR
AREA
DETAIL A
(JEDEC 95)
0.30
0.23
0.18
37
36
48
1
0.50
BSC
P IN 1
IN D IC ATO R AR E A OP T IO N S
(SEE DETAIL A)
5.20
5.10 SQ
5.00
EXPOSED
PAD
12
0.80
0.75
0.70
END VIEW
13
BOTTOM VIEW
0.20 MIN
5.50 REF
FOR PROPER CONNECTION OF
THE EXPOSED PAD, REFER TO
THE PIN CONFIGURATION AND
FUNCTION DESCRIPTIONS
SECTION OF THIS DATA SHEET.
0.05 MAX
0.02 NOM
COPLANARITY
0.08
0.203 REF
SEATING
PLANE
PKG-004509
24
10-10-2018-C
0.45
0.40
0.35
TOP VIEW
COMPLIANT TO JEDEC STANDARDS MO-220-WKKD-4
Figure 32. 48-Lead Frame Chip Scale Package [LFCSP]
7 mm × 7 mm Body and 0.75 mm Package Height
(CP-48-4)
Dimensions shown in millimeters
0.75
0.60
0.45
1.20
MAX
9.00
BSC SQ
37
36
48
1
PIN 1
0° MIN
1.05
1.00
0.95
0.15
0.05
SEATING
PLANE
0.20
0.09
7°
3.5°
0°
0.08 MAX
COPLANARITY
7.00
BSC SQ
TOP VIEW
(PINS DOWN)
12
13
25
24
VIEW A
VIEW A
0.50
0.27
BSC
0.22
LEAD PITCH
0.17
ROTATED 90° CCW
COMPLIANT TO JEDEC STANDARDS MS-026ABC
Figure 33. 48-Lead Thin Plastic Quad Flat Package [TQFP]
(SU-48)
Dimensions shown in millimeters
ORDERING GUIDE
Model1
ADG726BCPZ
ADG726BCPZ-REEL
ADG726BSUZ
ADG726BSUZ-REEL
ADG732BCPZ
ADG732BCPZ-REEL
ADG732BSUZ
ADG732BSUZ-REEL
1
Temperature Range
–40°C to +85°C
–40°C to +85°C
–40°C to +85°C
–40°C to +85°C
–40°C to +125°C
–40°C to +125°C
–40°C to +125°C
–40°C to +125°C
Package Description
48-Lead Frame Chip Scale Package [LFCSP]
48-Lead Frame Chip Scale Package [LFCSP]
48-Lead Thin Plastic Quad Flat Package [TQFP]
48-Lead Thin Plastic Quad Flat Package [TQFP]
48-Lead Frame Chip Scale Package [LFCSP]
48-Lead Frame Chip Scale Package [LFCSP]
48-Lead Thin Plastic Quad Flat Package [TQFP]
48-Lead Thin Plastic Quad Flat Package [TQFP]
Z = RoHS-Compliant Part
©2002–2021 Analog Devices, Inc. All rights reserved. Trademarks and
registered trademarks are the property of their respective owners.
D02765-2/21(C)
Rev. C | Page 21 of 21
Package Option
CP-48-4
CP-48-4
SU-48
SU-48
CP-48-4
CP-48-4
SU-48
SU-48
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