ADG728BRU-REEL

a CMOS, Low Voltage, 2-Wire Serially Controlled, Matrix Switches ADG728/ADG729 FEATURES 2-Wire Serial Interface 2.7 V to 5.5 V Single Supply 2.5 Ω On Resistance 0.75 Ω On-Resistance Flatness 100 pA Leakage Currents Single 8-to-1 Matrix Switch ADG728 Dual 4-to-1 Matrix Switch ADG729 Power-On Reset Small 16-Lead TSSOP Package Qualified for Automotive Applications APPLICATIONS Data Acquisition Systems Communications Systems Relay Placement Audio and Video Switching Automatic Test Equipment FUNCTIONAL BLOCK DIAGRAMS ADG728 ADG729 S1 S1A DA S4A D S1B DB S4B S8 INPUT SHIFT REGISTER INPUT SHIFT REGISTER RESET SDA SCL A0 A1 GENERAL DESCRIPTION PRODUCT HIGHLIGHTS The ADG728 and ADG729 are CMOS analog matrix switches with a serially controlled 2-wire interface. The ADG728 is an 8-channel matrix switch, while the ADG729 is a dual 4-channel matrix switch. On resistance is closely matched between switches and very flat over the full signal range. These parts can operate equally well as either multiplexers, demultiplexers or switch arrays and the input signal range extends to the supplies. 1. 2-Wire Serial Interface. The ADG728 and ADG729 utilize a 2-wire serial interface that is compatible with the I2C™ interface standard. Both have two external address pins (A0 and A1). This allows the 2 LSBs of the 7-bit slave address to be set by the user. Four of each of the devices can be connected to the one bus. The ADG728 also has a RESET pin that should be tied high if not in use. SDA SCL A0 A1 2. Single Supply Operation. The ADG728 and ADG729 are fully specified and guaranteed with 3 V and 5 V supply rails. 3. Low On Resistance 2.5 Ω typical. 4. Any configuration of switches may be on at any one time. 5. Guaranteed Break-Before-Make Switching Action. 6. Small 16-Lead TSSOP Package. Each channel is controlled by one bit of an 8-bit word. This means that these devices may be used in a number of different configurations; all, any, or none of the channels may be on at any one time. On power-up of the device, all switches will be in the OFF condition and the internal shift register will contain all zeros. All channels exhibit break-before-make switching action preventing momentary shorting when switching channels. The ADG728 and ADG729 are available in 16-lead TSSOP packages. REV. C Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. Tel: 781/329-4700 www.analog.com Fax: 781/461-3113 © Analog Devices, Inc., 2012 ADG728/ADG729–SPECIFICATIONS1 (V Parameter ANALOG SWITCH Analog Signal Range On Resistance (RON) On-Resistance Match Between Channels (∆RON) On-Resistance Flatness (RFLAT(ON)) B Version –40ⴗC 25ⴗC to +85ⴗC 0 V to VDD 2.5 4.5 5 0.4 0.8 0.75 1.2 LEAKAGE CURRENTS Source OFF Leakage IS (OFF) Drain OFF Leakage ID (OFF) Channel ON Leakage ID, IS (ON) LOGIC INPUTS (A0, A1)2 Input High Voltage, VINH Input Low Voltage, VINL Input Current IINL or IINH CIN, Input Capacitance ± 0.01 ± 0.1 ± 0.01 ± 0.1 ± 0.01 ± 0.1 0.005 IIN, Input Leakage Current 0.005 VHYST, Input Hysteresis CIN, Input Capacitance 0.05 VDD 6 LOGIC OUTPUT (SDA)2 VOL, Output Low Voltage DYNAMIC CHARACTERISTICS2 tON Unit V Ω typ Ω max Ω typ Ω max Ω typ Ω max ±1 2.4 0.8 V min V max ± 0.1 µA typ µA max pF typ ± 0.3 ±1 0.7 VDD VDD + 0.3 –0.3 0.3 VDD Input Low Voltage, VINL = 5 V ⴞ 10%, GND = 0 V, unless otherwise noted.) nA typ nA max nA typ nA max nA typ nA max 6 LOGIC INPUTS (SCL, SDA)2 Input High Voltage, VINH DD ± 1.0 0.4 0.6 95 140 V min V max V min V max µA typ µA max V min pF typ Charge Injection ±3 Off Isolation –55 –75 dB typ dB typ Channel-to-Channel Crosstalk –55 –75 dB typ dB typ 65 100 13 MHz typ MHz typ pF typ 85 42 pF typ pF typ 96 48 pF typ pF typ 10 µA typ µA max 20 VD = 4.5 V/1 V, VD = 1 V/4.5 V, Test Circuit 3 VD = VS = 4.5 V/1 V, Test Circuit 4 VIN = 0 V to VDD RL = 300 Ω, CL = 35 pF, Test Circuit 5; VS1 = 3 V VS1 = 3 V, RL = 300 Ω, CL = 35 pF; Test Circuit 5 RL = 300 Ω, CL = 35 pF; VS1 = VS2 = 3 V, Test Circuit 5 VS = 2.5 V, RS = 0 Ω, CL = 1 nF; Test Circuit 6 RL = 50 Ω, CL = 5 pF, f = 10 MHz; RL = 50 Ω, CL = 5 pF, f = 1 MHz; Test Circuit 8 RL = 50 Ω, CL = 5 pF, f = 10 MHz; RL = 50 Ω, CL = 5 pF, f = 1 MHz; Test Circuit 7 8 POWER REQUIREMENTS IDD VDD = 5.5 V VD = 4.5 V/1 V, VS = 1 V/4.5 V, Test Circuit 2 ns typ ns max ns typ ns max ns typ ns min pC typ Break-Before-Make Time Delay, tD –3 dB Bandwidth ADG728 ADG729 CS (OFF) CD (OFF) ADG728 ADG729 CD, CS (ON) ADG728 ADG729 VS = 0 V to VDD, IS = 10 mA ISINK = 3 mA ISINK = 6 mA 85 1 VS = 0 V to VDD, IS = 10 mA; Test Circuit 1 VS = 0 V to VDD, IS = 10 mA V max V max tOFF 130 Test Conditions/Comments RL = 50 Ω, CL = 5 pF, Test Circuit 8 VDD = 5.5 V Digital Inputs = 0 V or 5.5 V NOTES 1 Temperature range is as follows: B Version: –40°C to +85°C. Guaranteed by design, not subject to production test. 2 –2– REV. C 1 SPECIFICATIONS ADG728/ADG729 (VDD = 3 V ⴞ 10%, GND = 0 V, unless otherwise noted.) B Version Parameter ANALOG SWITCH Analog Signal Range On Resistance (RON) 25ⴗC 0 V to VDD 6 11 On-Resistance Match Between Channels (∆RON) On-Resistance Flatness (RFLAT(ON)) LEAKAGE CURRENTS Source OFF Leakage IS (OFF) Drain OFF Leakage ID (OFF) Channel ON Leakage ID, IS (ON) LOGIC INPUTS (A0, A1)2 Input High Voltage, VINH Input Low Voltage, VINL Input Current IINL or IINH CIN, Input Capacitance LOGIC INPUTS (SCL, SDA)2 Input High Voltage, VINH ± 0.01 ± 0.1 ± 0.01 ± 0.1 ± 0.01 ± 0.1 0.005 VHYST, Input Hysteresis CIN, Input Capacitance LOGIC OUTPUT (SDA)2 VOL, Output Low Voltage DYNAMIC CHARACTERISTICS2 tON 12 0.4 1.2 3.5 V Ω typ Ω max Ω typ Ω max Ω typ ±1 2.0 0.4 V min V max ± 0.1 µA typ µA max pF typ ± 0.3 ±1 0.7 VDD VDD + 0.3 –0.3 0.3 VDD 0.005 Unit nA typ nA max nA typ nA max nA typ nA max 3 Input Low Voltage, VINL IIN, Input Leakage Current –40ⴗC to +85ⴗC ± 1.0 0.05 VDD 3 0.4 0.6 130 200 V min V max V min V max µA typ µA max V min pF typ Charge Injection ±3 Off Isolation –55 –75 dB typ dB typ Crosstalk –55 –75 dB typ dB typ 65 100 13 MHz typ MHz typ pF typ 85 42 pF typ pF typ 96 48 pF typ pF typ 10 µA typ µA max NOTES 1 Temperature ranges are as follows: B Versions: –40°C to +85°C. 2 Guaranteed by design, not subject to production test. REV. C –3– VD = 3 V/1 V, VD = 1 V/3 V, Test Circuit 3 VD = VS = 3 V/1 V, Test Circuit 4 VIN = 0 V to VDD RL = 300 Ω, CL = 35 pF, Test Circuit 5; VS1 = 2 V RL = 300 Ω, CL = 35 pF; VS = 2 V, Test Circuit 5 RL = 300 Ω, CL = 35 pF; VS1 = VS8 = 2 V, Test Circuit 5 VS = 1.5 V, RS = 0 Ω, CL = 1 nF; Test Circuit 6 RL = 50 Ω, CL = 5 pF, f = 10 MHz; RL = 50 Ω, CL = 5 pF, f = 1 MHz; Test Circuit 8 RL = 50 Ω, CL = 5 pF, f = 10 MHz; RL = 50 Ω, CL = 5 pF, f = 1 MHz; Test Circuit 7 8 20 VDD = 3.3 V VS = 3 V/1 V, VD = 1 V/3 V, Test Circuit 2 ns typ ns max ns typ ns max ns typ ns min pC typ Break-Before-Make Time Delay, tD –3 dB Bandwidth ADG728 ADG729 CS (OFF) CD (OFF) ADG728 ADG729 CD, CS (ON) ADG728 ADG729 POWER REQUIREMENTS IDD VS = 0 V to VDD, IS = 10 mA ISINK = 3 mA ISINK = 6 mA 115 1 VS = 0 V to VDD, IS = 10 mA; Test Circuit 1 VS = 0 V to VDD, IS = 10 mA V max V max tOFF 180 Test Conditions/Comments RL = 50 Ω, CL = 5 pF, Test Circuit 8 VDD = 3.3 V Digital Inputs = 0 V or 3.3 V ADG728/ADG729 TIMING CHARACTERISTICS VDD = 2.7 V to 5.5 V. All specifications −40°C to +85°C, unless otherwise noted. See Figure 1. Parameter fSCL t1 t2 t3 t4 t5 t6 1 Limit at TMIN, TMAX 400 2.5 0.6 1.3 0.6 100 0.9 0 0.6 0.6 1.3 300 20 + 0.1Cb 2 250 300 0.1Cb2 400 50 t7 t8 t9 t10 t11 Cb2 tSP 3 Unit kHz max µs min µs min µs min µs min ns min µs max µs min µs min µs min µs min ns max ns min ns max ns max ns min pF max ns max Test Conditions/Comments SCL clock frequency SCL cycle time SCL high time, tHIGH SCL low time, tLOW Start/repeated start condition hold time, tHD, STA Data setup time, tSU, DAT Data hold time, tHD, DAT Setup time for repeated start, tSU, STA Stop condition setup time, tSU, STO Bus free time between a stop condition and a start condition, tBUF Rise time of both SCL and SDA when receiving, tR Fall time of SDA when receiving, tF Fall time of SDA when transmitting, tF Capacitive load for each bus line Pulse width of spike suppressed A master device must provide a hold time of at least 300 ns for the SDA signal (referred to the VIH min of the SCL signal) to bridge the undefined region of the falling edge of SCL. 2 Cb is the total capacitance of one bus line in pF. tR and tF measured between 0.3 VDD and 0.7 VDD. 3 Input filtering on both the SCL and SDA inputs suppress noise spikes that are less than 50 ns. 1 SDA t3 t9 t4 t 11 t 10 SCL START CONDITION t6 t2 START CONDITION t5 t7 REPEATED START CONDITION t1 t8 STOP CONDITION 01002-002 t4 Figure 1. 2-Wire Serial Interface Timing Diagram –4– REV. C ADG728/ADG729 PIN FUNCTION DESCRIPTIONS ADG728 ADG729 Mnemonic Function 1 1 SCL Serial Clock Line. This is used in conjunction with the SDA line to clock data into the 8-bit input shift register. Clock rates of up to 400 kbit/s can be accommodated with this 2-wire serial interface. Active low control input that clears the input register and turns all switches to the OFF condition. Serial Data Line. This is used in conjunction with the SCL line to clock data into the 8-bit input shift register during the write cycle and used to read back 1 byte of data during the read cycle. It is a bidirectional open-drain data line which should be pulled to the supply with an external pull-up resistor. Source. May be an input or output. Drain. May be an input or output. Source. May be an input or output. Power Supply Input. These parts can be operated from a supply of 2.7 V to 5.5 V. Ground Reference. Address Input. Sets the second least significant bit of the 7-bit slave address. Address Input. Sets the least significant bit of the 7-bit slave address. RESET 2 3 3 SDA 4, 5, 6, 7 8 9, 10, 11, 12 13 14 15 16 4, 5, 6, 7 8, 9 10, 11, 12, 13 14 15 2 16 Sxx Dx Sxx VDD GND A1 A0 PIN CONFIGURATIONS ADG729 ADG728 SCL 1 16 A0 SCL 1 RESET 2 15 A1 A1 2 SDA 3 ADG728 S1 4 S2 5 15 GND 14 VDD 14 GND SDA 3 13 VDD S1A 4 12 S5 S2A 5 11 S3B ADG729 13 S1B TOP VIEW (Not to Scale) 12 S2B 11 S6 S3A 6 S4 7 10 S7 S4A 7 10 S4B D 8 9 S8 DA 8 9 DB S3 6 REV. C TOP VIEW (Not to Scale) 16 A0 –5– ADG728/ADG729 ABSOLUTE MAXIMUM RATINGS 1 (TA = 25°C unless otherwise noted.) VDD to GND . . . . . . . . . . . . . . . . . . . . . . . . . . –0.3 V to +7 V Analog, Digital Inputs2 . . . . . . . . . . –0.3 V to VDD + 0.3 V or 30 mA, Whichever Occurs First Peak Current, S or D . . . . . . . . . . . . . . . . . . . . . . . . . . 100 mA (Pulsed at 1 ms, 10% Duty Cycle max) Continuous Current, Each S . . . . . . . . . . . . . . . . . . . . . 30 mA Continuous Current D, ADG729 . . . . . . . . . . . . . . . . . 80 mA Continuous Current D, ADG728 . . . . . . . . . . . . . . . . 120 mA Operating Temperature Range Industrial (B Version) . . . . . . . . . . . . . . . . –40°C to +85°C Storage Temperature Range . . . . . . . . . . . . –65°C to +150°C Junction Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . 150°C TSSOP Package θJA Thermal Impedance . . . . . . . . . . . . . . . . . . . 150.4°C/W θJC Thermal Impedance . . . . . . . . . . . . . . . . . . . . 27.6°C/W Lead Temperature, Soldering . . . . . As per JEDEC J-STD-020 NOTES 1 Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only; functional operation of the device at these or any other conditions above those listed in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. Only one absolute maximum rating may be applied at any one time. 2 Overvoltages at IN, S or D will be clamped by internal diodes. Current should be limited to the maximum ratings given. CAUTION ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on the human body and test equipment and can discharge without detection. Although the ADG728/ADG729 features proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high-energy electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance degradation or loss of functionality. WARNING! ESD SENSITIVE DEVICE TERMINOLOGY VDD Most Positive Power Supply Potential. CD, CS (ON) “ON” Switch Capacitance. Measured with reference to ground. IDD Positive Supply Current. GND Ground (0 V) Reference. CIN Digital Input Capacitance. S Source Terminal. May be an input or output. tON D Drain Terminal. May be an input or output. Delay time between the 50% and 90% points of the STOP condition and the switch “ON” condition. VD (VS) Analog Voltage on Terminals D, S. tOFF RON Ohmic Resistance between D and S. ∆RON On Resistance Match Between any Two Channels, i.e., RONmax – RONmin. Delay time between the 50% and 90% points of the STOP condition and the switch “OFF” condition. tD “OFF” time measured between the 80% points of both switches when switching from one switch to another. Charge Injection A measure of the glitch impulse transferred from the digital input to the analog output during switching. Off Isolation A measure of unwanted signal coupling through an “OFF” switch. Crosstalk A measure of unwanted signal which is coupled through from one channel to another as a result of parasitic capacitance. Bandwidth The frequency at which the output is attenuated by 3 dBs. RFLAT(ON) Flatness is defined as the difference between the maximum and minimum value of on resistance as measured over the specified analog signal range. IS (OFF) Source Leakage Current with the Switch “OFF.” ID (OFF) Drain Leakage Current with the Switch “OFF.” ID, IS (ON) Channel Leakage Current with the Switch “ON.” VINL Maximum Input Voltage for Logic “0.” VINH Minimum Input Voltage for Logic “1.” IINL (IINH) Input Current of the Digital Input. CS (OFF) “OFF” Switch Source Capacitance. Measured with reference to ground. CD (OFF) “OFF” Switch Drain Capacitance. Measured with reference to ground. On Response The frequency response of the “ON” switch. Insertion Loss –6– The loss due to the ON resistance of the switch. REV. C Typical Performance Characteristics–ADG728/ADG729 8 8 ON RESISTANCE – ⍀ VDD = 3.3V 5 4 VDD = 4.5V VDD = 5.5V 3 2 1 5 +25ⴗC +85ⴗC 3 2 –40ⴗC 1 0 1 2 3 4 5 0 VD OR VS – DRAIN OR SOURCE VOLTAGE – V Figure 3. On Resistance as a Function of VD (VS) for Different Temperatures, Single Supply VDD = 5V VSS = 0V TA = 25ⴗC 0.08 CURRENT – nA 0.00 IS (OFF) –0.04 4 –40ⴗC 3 +25ⴗC 2 Figure 4. On Resistance as a Function of VD (VS) for Different Temperatures, Single Supply 0.35 VDD = 3V VSS = 0V TA = 25ⴗC 0.08 ID (ON) 0.04 +85ⴗC 5 0 0.5 1.0 1.5 2.0 2.5 3.0 0 VD OR VS – DRAIN OR SOURCE VOLTAGE – V 0.12 0.12 6 1 0 1 0 2 3 4 5 VD OR VS – DRAIN OR SOURCE VOLTAGE – V Figure 2. On Resistance as a Function of VD (VS) for Single Supply CURRENT – nA 6 4 VDD = 3V VSS = 0V 7 0.25 ID (ON) 0.04 0.00 IS (OFF) –0.04 VDD = 5V VSS = 0V 0.30 CURRENT – nA ON RESISTANCE – ⍀ 7 VDD = 2.7V 6 8 VDD = 5V VSS = 0V ON RESISTANCE – ⍀ TA = 25ⴗC VSS = 0V 7 ID (OFF) 0.20 0.15 ID (OFF) 0.10 ID (ON) 0.05 ID (OFF) –0.08 –0.08 0.00 IS (OFF) –0.12 –0.12 0 1 2 3 VD (VS) – Volts 4 5 Figure 5. Leakage Currents as a Function of VD (VS) 0 0.5 1.0 1.5 2.0 VD (VS) – Volts 2.5 3.0 Figure 6. Leakage Currents as a Function of VD (VS) –0.05 15 VDD = 5V VSS = 0V 0.10 ID (OFF) 100␮ 0 QINJ – pC CURRENT – A CURRENT – nA 0.25 0.15 VDD = 5V 10␮ –20 –30 0.00 IS (OFF) 25 35 45 55 65 TEMPERATURE – ⴗC ID (ON) 75 85 Figure 8. Leakage Currents as a Function of Temperature REV. C VDD = 3V VSS = 0V –10 VDD = 3V 0.05 –0.05 15 85 TA = 25ⴗC 10 0.20 75 20 TA = 25ⴗC VDD = 3V VSS = 0V 0.30 35 45 55 65 TEMPERATURE – ⴗC Figure 7. Leakage Currents as a Function of Temperature 1m 0.35 25 1␮ 10k 100k FREQUENCY – Hz 1M Figure 9. Input Current vs. Switching Frequency –7– –40 0 1 2 3 VOLTAGE – Volts 4 Figure 10. Charge Injection vs. Source Voltage 5 ADG728/ADG729 140 –20 100 80 TON, VDD = 5V TOFF, VDD = 5V 60 ATTENUATION – dB TOFF, VDD = 3V 120 VDD = 5V TA = 25ⴗC –20 ATTENUATION – dB TON, VDD = 3V TIME – ns 0 0 160 –40 –60 –80 VDD = 5V TA = 25ⴗC –40 –60 –80 40 –100 –100 20 0 –40 –20 0 20 40 60 TEMPERATURE – ⴗC 80 Figure 11. TON /TOFF Times vs. Temperature –120 30k 100k 1M 10M FREQUENCY – Hz 100M Figure 12. Off Isolation vs. Frequency –120 30k 100k 1M 10M FREQUENCY – Hz 100M Figure 13. Crosstalk vs. Frequency 0 ATTENUATION – dB VDD = 5V TA = 25ⴗC –5 ADG728 ADG729 –10 –15 –20 30k 100k 1M 10M FREQUENCY – Hz 100M Figure 14. On Response vs. Frequency –8– REV. C ADG728/ADG729 GENERAL DESCRIPTION The ADG728 and ADG729 are serially controlled, 8-channel and dual 4-channel matrix switches respectively. While providing the normal multiplexing and demultiplexing functions, these devices also provide the user with more flexibility as to where their signal may be routed. Each bit of the serial word corresponds to one switch of the device. A Logic 1 in the particular bit position turns on the switch, while a Logic 0 turns the switch off. Because each switch is independently controlled by an individual bit, this provides the option of having any, all, or none of the switches ON. This feature may be particularly useful in the demultiplexing application where the user may wish to direct one signal from the drain to a number of outputs (sources). Care must be taken, however, in the multiplexing situation where a number of inputs may be shorted together (separated only by the small on resistance of the switch). The slave whose address corresponds to the transmitted address responds by pulling the SDA line low during the ninth clock pulse (this is termed the Acknowledge bit). At this stage, all other devices on the bus remain idle while the selected device waits for data to be written to or read from its serial register. If the R/W bit is high, the master will read from the slave device. However, if the R/W bit is low, the master will write to the slave device. 2. Data is transmitted over the serial bus in sequences of nine clock pulses (eight data bits followed by an acknowledge bit). The transitions on the SDA line must occur during the low period of SCL and remain stable during the high period of SCL. When changing the switch conditions, a new 8-bit word is written to the input shift register. Some of the bits may be the same as the previous write cycle, as the user may not wish to change the state of some switches. In order to minimize glitches on the output of these switches, the part cleverly compares the state of switches from the previous write cycle. If the switch is already in the ON condition, and is required to stay ON, there will be minimal glitches on the output of the switch. 3. When all data bits have been read or written, a STOP condition is established by the master. A STOP condition is defined as a low-to-high transition on the SDA line while SCL is high. In Write mode, the master will pull the SDA line high during the 10th clock pulse to establish a STOP condition. In Read mode, the master will issue a No Acknowledge for the ninth clock pulse (i.e., the SDA line remains high). The master will then bring the SDA line low before the tenth clock pulse and then high during the tenth clock pulse to establish a STOP condition. POWER-ON RESET See Figures 18 to 21 below for a graphical explanation of the serial interface. On power-up of the device, all switches will be in the OFF condition and the internal shift register is filled with zeros and will remain so until a valid write takes place. SERIAL INTERFACE 2-Wire Serial Bus The ADG728/ADG729 are controlled via an I2C compatible serial bus. These parts are connected to this bus as a slave device (no clock is generated by the multiplexer). The ADG728/ADG729 have different 7-bit slave addresses. The five MSBs of the ADG728 are 10011, while the MSBs of the ADG729 are 10001 and the two LSBs are determined by the state of the A0 and A1 pins. The 2-wire serial bus protocol operates as follows: 1. The master initiates data transfer by establishing a START condition which is when a high-to-low transition on the SDA line occurs while SCL is high. The following byte is the address byte, which consists of the 7-bit slave address followed by a R/W bit (this bit determines whether data will be read from or written to the slave device). A repeated write function gives the user flexibility to update the matrix switch a number of times after addressing the part only once. During the write cycle, each data byte will update the configuration of the switches. For example, after the matrix switch has acknowledged its address byte, and receives one data byte, the switches will update after the data byte, if another data byte is written to the matrix switch while it is still the addressed slave device, this data byte will also cause an switch configuration update. Repeat read of the matrix switch is also allowed. INPUT SHIFT REGISTER The input shift register is eight bits wide. Figure 15 illustrates the contents of the input shift register. Data is loaded into the device as an 8-bit word under the control of a serial clock input, SCL. The timing diagram for this operation is shown in Figure 1. The 8-bit word consists of eight data bits each controlling one switch. MSB (Bit 7) is loaded first. DB0 (LSB) DB7 (MSB) S8 S7 S6 S5 S4 S3 S2 S1 DATA BITS Figure 15. ADG728/ADG729 Input Shift Register Contents REV. C –9– ADG728/ADG729 WRITE OPERATION When writing to the ADG728/ADG729, the user must begin with an address byte and R/W bit, after which the switch will acknowledge that it is prepared to receive data by pulling SDA low. This address byte is followed by the 8-bit word. The write operations for each matrix switch are shown in the figures below. SCL 1 SDA 0 START COND BY MASTER 0 1 1 A1 A0 R/W S8 S7 S6 ACK BY ADG728 ADDRESS BYTE S5 S4 S3 S2 S1 STOP ACK COND BY BY ADG728 MASTER DATA BYTE Figure 16. ADG728 Write Sequence SCL 1 SDA 0 START COND BY MASTER 0 0 1 A1 A0 R/W S8 S7 S6 ACK BY ADG729 ADDRESS BYTE S5 S4 S3 S2 S1 STOP ACK COND BY BY ADG729 MASTER DATA BYTE Figure 17. ADG729 Write Sequence READ OPERATION When reading data back from the ADG728/ADG729, the user must begin with an address byte and R/W bit, after which the matrix switch will acknowledge that it is prepared to transmit data by pulling SDA low. The readback operation is a single byte that consists of the eight data bits in the input register. The read operations for each part are shown in Figures 18 and 19. SCL 1 SDA 0 START COND BY MASTER 0 1 1 A1 A0 R/W S8 S7 S6 ACK BY ADG728 ADDRESS BYTE S5 S4 S3 S2 S1 NO ACK STOP COND BY BY MASTER MASTER DATA BYTE Figure 18. ADG728 Readback Sequence SCL 1 SDA START COND BY MASTER 0 0 0 ADDRESS BYTE 1 A1 A0 R/W S8 ACK BY ADG729 S7 S6 S5 S4 DATA BYTE S3 S2 S1 NO ACK STOP COND BY BY MASTER MASTER Figure 19. ADG729 Readback Sequence –10– REV. C ADG728/ADG729 MULTIPLE DEVICES ON ONE BUS Figure 20 shows four ADG728s devices on the same serial bus. Each has a different slave address since the state of their A0 and A1 pins is different. This allows each Matrix Switch to be written to or read from independently. Because the ADG729 has a different address to the ADG728, it would be possible for four of each of these devices to be connected to the same bus. +5V RP RP SDA MASTER SCL VDD VDD SDA SCL SDA A1 SCL A1 A0 SCL SDA A1 A0 ADG728 VDD SDA A0 ADG728 SCL A1 A0 ADG728 ADG728 Figure 20. Multiple ADG728s on the Same Bus TEST CIRCUITS IDS VDD VDD V1 S1 S2 S D D ID (OFF) A S8 VD GND VS VS RON = V1/IDS Test Circuit 1. On Resistance Test Circuit 3. IS (OFF) VDD VDD VDD VDD IS (OFF) S1 S1 A D S8 S2 VS ID (ON) A VD D S8 VD GND VS GND Test Circuit 2. ID (OFF) Test Circuit 4. ID (ON) VDD VDD SCL 50% 50% ADG728* S1 VS1 S2 THRU S7 S8 D GND VS1 VS8 RL 300⍀ 90% CL 35pF VOUT VOUT VS1 = VS8 VOUT 80% 80% 90% tOPEN * SIMILAR CONNECTION FOR ADG729 tOFF tON Test Circuit 5. Switching Times and Break-Before-Make Times REV. C –11– ADG728/ADG729 VDD VDD ADG728* SWITCH ON RS VS D S CL 1nF INPUT LOGIC VOUT ⌬VOUT SWITCH OFF QINJ = CL x ⌬VOUT GND SDA SCL * SIMILAR CONNECTION FOR ADG729 Test Circuit 6. Charge Injection VDD VDD VDD VDD ADG728* 50⍀ S1 D RL S2 VS S8 S1 S8 VS ADG728* VOUT 50⍀ D GND GND RL VOUT 50⍀ * SIMILAR CONNECTION FOR ADG729 *SIMILAR CONNECTION FOR ADG729 CHANNEL-TO-CHANNEL CROSSTALK = 20LOG10(VOUT/VS) S1 IS SWITCHED OFF FOR OFF ISOLATION MEASUREMENTS AND ON FOR BANDWIDTH MEASUREMENTS OFF ISOLATION = 20LOG10(VOUT/VS) Test Circuit 7. Channel-to-Channel Crosstalk INSERTION LOSS = 20LOG10 VOUT WITH SWITCH VOUT WITHOUT SWITCH Test Circuit 8. Off Isolation and Bandwidth –12– REV. C ADG728/ADG729 OUTLINE DIMENSIONS 5.10 5.00 4.90 16 9 4.50 4.40 4.30 6.40 BSC 1 8 PIN 1 1.20 MAX 0.15 0.05 0.20 0.09 0.30 0.19 0.65 BSC COPLANARITY 0.10 8° 0° SEATING PLANE 0.75 0.60 0.45 COMPLIANT TO JEDEC STANDARDS MO-153-AB Figure 1. 16-Lead Thin Shrink Small Outline Package [TSSOP] (RU-16) Dimensions shown in millimeters ORDERING GUIDE Model 1, 2 ADG728BRU ADG728BRU-REEL ADG728BRU-REEL7 ADG728BRUZ ADG728BRUZ-REEL ADG728BRUZ-REEL7 ADG728WBRUZ-REEL7 ADG729BRU ADG729BRU-REEL ADG729BRU-REEL7 ADG729BRUZ ADG729BRUZ-REEL7 1 2 Temperature Range −40°C to +85°C −40°C to +85°C −40°C to +85°C −40°C to +85°C −40°C to +85°C −40°C to +85°C −40°C to +85°C −40°C to +85°C −40°C to +85°C −40°C to +85°C −40°C to +85°C −40°C to +85°C Package Description 16-Lead Thin Shrink Small Outline Package [TSSOP] 16-Lead Thin Shrink Small Outline Package [TSSOP] 16-Lead Thin Shrink Small Outline Package [TSSOP] 16-Lead Thin Shrink Small Outline Package [TSSOP] 16-Lead Thin Shrink Small Outline Package [TSSOP] 16-Lead Thin Shrink Small Outline Package [TSSOP] 16-Lead Thin Shrink Small Outline Package [TSSOP] 16-Lead Thin Shrink Small Outline Package [TSSOP] 16-Lead Thin Shrink Small Outline Package [TSSOP] 16-Lead Thin Shrink Small Outline Package [TSSOP] 16-Lead Thin Shrink Small Outline Package [TSSOP] 16-Lead Thin Shrink Small Outline Package [TSSOP] Package Option RU-16 RU-16 RU-16 RU-16 RU-16 RU-16 RU-16 RU-16 RU-16 RU-16 RU-16 RU-16 Z = RoHS Compliant Part. W = Qualified for Automotive Applications. AUTOMOTIVE PRODUCTS The ADG728W model is available with controlled manufacturing to support the quality and reliability requirements of automotive applications. Note that this automotive model may have specifications that differ from the commercial models; therefore, designers should review the Specifications section of this data sheet carefully. Only the automotive grade product shown is available for use in automotive applications. Contact your local Analog Devices account representative for specific product ordering information and to obtain the specific Automotive Reliability reports for this model. REVISION HISTORY 6/12—Rev. B to Rev. C Changes to Timing Characteristics Section .................................. 4 10/11—Rev. A to Rev. B Change to Features Section ..............................................................1 Changes to Absolute Maximum Ratings Section ..........................6 Updated Outline Dimensions ....................................................... 13 Changes to Ordering Guide .......................................................... 13 Added Automotive Products Section .......................................... 13 ©2012 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. D01002-0-6/12(C) REV. C –13–