I2C®-Compatible, Wide Bandwidth, Hex 2:1 Multiplexer ADG796A
FEATURES
Bandwidth: 325 MHz Low insertion loss and on resistance: 2.6 Ω typical On resistance flatness: 0.3 Ω typical Single 3 V/5 V supply operation 3.3 V analog signal range (5 V supply, 75 Ω load) Low quiescent supply current: 1 nA typical Fast switching times: tON = 186 ns, tOFF = 177 ns I2C-compatible interface Compact 24-lead LFCSP ESD protection 4 kV human body model 200 V machine model 1 kV field-induced charged device model
FUNCTIONAL BLOCK DIAGRAM
VDD GND
ADG796A
S1A D1 S1B S2A D2 S2B S3A D3 S3B S4A D4 S4B S5A D5 S5B S6A D6 S6B I2C SERIAL INTERFACE
06036-001
APPLICATIONS
S-Video RGB/YPbPr video switches HDTV Projection TV DVD-R/RW AV receivers
A0
A1 SDA SCL
Figure 1.
GENERAL DESCRIPTION
The ADG796A is a monolithic CMOS device comprising six 2:1 multiplexer/demultiplexers controlled by a standard I2C serial interface. The CMOS process provides ultralow power dissipation, yet offers high switching speed and low on resistance. The on resistance profile is very flat over the full analog input range, and wide bandwidth ensures excellent linearity and low distortion. These features, combined with a wide input signal range, make the ADG796A the ideal switching solution for a wide range of TV applications including S-Video, YPbPr, and RGB video switches. The switches conduct equally well in both directions when on. In the off condition, signal levels up to the supplies are blocked. The ADG796A switches exhibit break-before-make switching action. The integrated I2C interface provides a large degree of flexibility in the system design. It has two user adjustable I2C address pins that allow up to four devices on the same bus. This allows the user to expand the capability of the device by increasing the size of the switching array. The ADG796A operates from a single 3 V or 5 V supply voltage and is available in a compact 4 mm × 4 mm body, 24-lead, Pb-free LFCSP.
PRODUCT HIGHLIGHTS
1. 2. 3. 4. 5. 6. Wide bandwidth: 325 MHz. Ultralow power dissipation. Extended input signal range. Integrated I2C serial interface. Compact 4 mm × 4 mm, 24-lead, Pb-free LFCSP. ESD protection tested as per ESD Association standards: • • • 4 kV HBM (ANSI/ESD STM5.1-2001) 200 V MM (ANSI/ESD STM5.2-1999) 1 kV FICDM (ANSI/ESD STM5.3.1-1999)
Rev. 0
Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective owners.
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ADG796A TABLE OF CONTENTS
Features .............................................................................................. 1 Applications....................................................................................... 1 Functional Block Diagram .............................................................. 1 General Description ......................................................................... 1 Product Highlights ........................................................................... 1 Revision History ............................................................................... 2 Specifications..................................................................................... 3 I2C Timing Specifications............................................................ 7 Absolute Maximum Ratings............................................................ 9 ESD Caution.................................................................................. 9 Pin Configuration and Function Descriptions........................... 10 Typical Performance Characteristics ........................................... 11 Test Circuits..................................................................................... 14 Terminology .................................................................................... 16 Theory of Operation ...................................................................... 17 I2C Serial Interface ..................................................................... 17 I2C Address.................................................................................. 17 Write Operation.......................................................................... 17 LDSW Bit..................................................................................... 19 Power On/Software Reset.......................................................... 19 Read Operation........................................................................... 19 Evaluation Board ............................................................................ 20 Using the ADG796A Evaluation Board .................................. 20 Outline Dimensions ....................................................................... 23 Ordering Guide .......................................................................... 23
REVISION HISTORY
7/06—Revision 0: Initial Version
Rev. 0 | Page 2 of 24
ADG796A SPECIFICATIONS
VDD = 5 V ± 10%, GND = 0 V, TA = −40°C to +85°C, unless otherwise noted. Table 1.
Parameter ANALOG SWITCH Analog Signal Range 2 On Resistance, RON On Resistance Matching Between Channels, ∆RON On Resistance Flatness, RFLAT(ON) LEAKAGE CURRENTS Source Off Leakage (IS(OFF)) Drain Off Leakage (ID(OFF)) Channel On Leakage (ID(ON), IS(ON)) DYNAMIC CHARACTERISTICS 3 tON, tENABLE tOFF, tDISABLE Break-Before-Make Time Delay, tD Off Isolation Channel-to-Channel Crosstalk Same Multiplexer Different Multiplexer −3 dB Bandwidth THD + N Charge Injection CS(OFF) CD(OFF) CD(ON), CS(ON) Power Supply Rejection Ratio, PSRR Differential Gain Error Differential Phase Error LOGIC INPUTS (A0, A1, A2)3 Input High Voltage, VINH Input Low Voltage, VINL Input Current, IINL or IINH Input Capacitance, CIN LOGIC INPUTS (SCL, SDA)3 Input High Voltage, VINH Input Low Voltage, VINL Input Leakage Current, IIN Input Hysteresis Input Capacitance, CIN LOGIC OUTPUTS3 SDA Pin Output Low Voltage, VOL Floating State Leakage Current Floating State Output Capacitance Conditions VS = VDD, RL = 1 MΩ VS = VDD, RL = 75 Ω VD = 0 V, IDS = −10 mA, see Figure 18 VD = 0 V to 1 V, IDS = −10 mA, see Figure 18 VD = 0 V IDS = −10 mA VD = 1 V IDS = −10 mA VD = 0 V to 1 V, IDS = −10 mA VD = 4 V/1 V, VS = 1 V/4 V, see Figure 19 VD = 4 V/1 V, VS = 1 V/4 V, see Figure 19 VD = VS = 4 V/1 V, see Figure 20 CL = 35 pF, RL = 50 Ω, VS = 2 V, see Figure 24 CL = 35 pF, RL = 50 Ω, VS = 2 V, see Figure 24 CL = 35 pF, RL = 50 Ω, VS1 = VS2 = 2 V, see Figure 25 f = 10 MHz, RL = 50 Ω, see Figure 22 f = 10 MHz, RL = 50 Ω, see Figure 23 Min 0 0 2.2 0.15 0.3 ±0.25 ±0.25 ±0.25 186 177 3 −60 −55 −70 325 0.14 5 10 13 27 70 0.32 0.44 2.0 VIN = 0 V to VDD 0.005 3 0.7 × VDD −0.3 VIN = 0 V to VDD +0.005 0.05 × VDD 3 0.8 ±1 250 240 Typ 1 Max 4 3.3 3.5 4 0.5 0.6 0.55 Unit V V Ω Ω Ω Ω Ω nA nA nA ns ns ns dB dB dB MHz % pC pF pF pF dB % Degrees V V μA pF V V μA V pF
1
RL = 50 Ω, see Figure 21 RL = 100 Ω CL = 1 nF, VS = 0 V, see Figure 26
f = 20 kHz CCIR330 test signal CCIR330 test signal
VDD + 0.3 +0.3 × VDD ±1
ISINK = 3 mA ISINK = 6 mA
0.4 0.6 ±1 10
V V μA pF
Rev. 0 | Page 3 of 24
ADG796A
Parameter POWER REQUIREMENTS IDD Conditions Digital inputs = 0 V or VDD, I2C interface inactive I2C interface active, fSCL = 400 kHz I2C interface active, fSCL = 3.4 MHz Min Typ 1 0.001 Max 1 0.2 0.7 Unit μA mA mA
1 2
All typical values are at TA = +25°C, unless otherwise stated. Guaranteed by initial characterization, not subject to production test. 3 Guaranteed by design, not subject to production test.
Rev. 0 | Page 4 of 24
ADG796A
VDD = 3 V ± 10%, GND = 0 V, TA = −40°C to +85°C, unless otherwise noted. Table 2.
Parameter ANALOG SWITCH Analog Signal Range 2 On Resistance, RON On Resistance Matching Between Channels, ∆RON On Resistance Flatness, RFLAT(ON) LEAKAGE CURRENTS Source Off Leakage (IS(OFF)) Drain Off Leakage (ID(OFF)) Channel On Leakage (ID(ON), IS(ON)) DYNAMIC CHARACTERISTICS 3 tON, tENABLE tOFF, tDISABLE Break-Before-Make Time Delay, tD Off Isolation Channel-to-Channel Crosstalk Same Multiplexer Different Multiplexer −3 dB Bandwidth THD + N Charge Injection CS(OFF) CD(OFF) CD(ON), CS(ON) Power Supply Rejection Ratio, PSRR Differential Gain Error Differential Phase Error LOGIC INPUTS (A0, A1, A2)3 Input High Voltage, VINH Input Low Voltage, VINL Input Current, IINL or IINH Input Capacitance, CIN LOGIC INPUTS (SCL, SDA)3 Input High Voltage, VINH Input Low Voltage, VINL Input Leakage Current, IIN Input Hysteresis Input Capacitance, CIN LOGIC OUTPUTS 3 SDA Pin Output Low Voltage, VOL Floating State Leakage Current Floating State Output Capacitance Conditions VS = VDD, RL = 1 MΩ VS = VDD, RL = 75 Ω VD = 0 V, IDS = −10 mA, see Figure 18 VD = 0 V to 1 V, IDS = −10 mA, see Figure 18 VD = 0 V IDS = −10 mA VD = 1 V IDS = −10 mA VD = 0 V to 1 V, IDS = −10 mA VD = 2 V/1 V, VS = 1 V/2 V, see Figure 19 VD = 2 V/1 V, VS = 1 V/2 V, see Figure 19 VD = VS = 2 V/1 V, see Figure 20 CL = 35 pF, RL = 50 Ω, VS = 2 V, see Figure 24 CL = 35 pF, RL = 50 Ω, VS = 2 V, see Figure 24 CL = 35 pF, RL = 50 Ω, VS1 = VS2 = 2 V, see Figure 25 f = 10 MHz, RL = 50 Ω, see Figure 22 f = 10 MHz, RL = 50 Ω, see Figure 23 Min 0 0 2.2 0.15 0.3 ±0.25 ±0.25 ±0.25 198 195 3 −60 −55 −70 310 0.14 2.5 10 13 27 70 0.28 0.28 2.0 VIN = 0 V to VDD 0.005 3 0.7 × VDD −0.3 VIN = 0 V to VDD +0.005 0.05 × VDD 3 0.8 ±1 270 260 Typ 1 Max 2.2 1.7 4 6 0.6 1.1 2.8 Unit V V Ω Ω Ω Ω Ω nA nA nA ns ns ns dB dB dB MHz % pC pF pF pF dB % Degrees V V μA pF V V μA V pF
1
RL = 50 Ω, see Figure 21 RL = 100 Ω CL = 1 nF, VS = 0 V, see Figure 26
f = 20 kHz CCIR330 test signal CCIR330 test signal
VDD + 0.3 +0.3 × VDD ±1
ISINK = 3 mA ISINK = 6 mA 3
0.4 0.6 ±1
V V μA pF
Rev. 0 | Page 5 of 24
ADG796A
Parameter POWER REQUIREMENTS IDD Conditions Digital inputs = 0 V or VDD, I2C interface inactive I2C interface active, fSCL = 400kHz I2C interface active, fSCL = 3.4MHz Min Typ 1 0.001 Max 1 0.1 0.2 Unit μA mA mA
1 2
All typical values are at TA = +25°C, unless otherwise stated. Guaranteed by initial characterization, not subject to production test. 3 Guaranteed by design, not subject to production test.
Rev. 0 | Page 6 of 24
ADG796A
I2C TIMING SPECIFICATIONS
VDD = 2.7 V to 5.5 V; GND = 0 V; TA = −40°C to +85°C, unless otherwise noted (see Figure 2 for timing diagram). Table 3.
Parameter 1 fSCL Conditions Standard mode Fast mode High speed mode CB = 100 pF max CB = 400 pF max Standard mode Fast mode High speed mode CB = 100 pF max CB = 400 pF max Standard mode Fast mode High speed mode CB = 100 pF max CB = 400 pF max Standard mode Fast mode High speed mode Standard mode Fast mode High speed mode CB = 100 pF max CB = 400 pF max Standard mode Fast mode High speed mode Standard mode Fast mode High speed mode Standard mode Fast mode Standard mode Fast mode High speed mode Standard mode Fast mode High speed mode CB = 100 pF max CB = 400 pF max Standard mode Fast mode High speed mode CB = 100 pF max CB = 400 pF max Standard mode Fast mode High speed mode CB = 100 pF max CB = 400 pF max Min Max 100 400 3.4 1.7 4 0.6 60 120 4.7 1.3 160 320 250 100 10 0 0 0 0 4.7 0.6 160 4 0.6 160 4.7 1.3 4 0.6 160 20 + 0.1 CB 10 20 20 + 0.1 CB 10 20 20 + 0.1 CB 10 20 Unit kHz kHz MHz MHz μs μs ns ns μs μs ns ns ns ns ns μs μs ns ns μs μs ns μs μs ns μs μs μs μs ns ns ns ns ns ns ns ns ns ns ns ns ns
Rev. 0 | Page 7 of 24
Description Serial clock frequency
t1
tHIGH, SCL high time
t2
tLOW, SCL low time
t3
tSU;DAT, data setup time
t4 2
3.45 0.9 703 150
tHD;DAT, data hold time
t5
tSU;STA, setup time for a repeated start condition
t6
tHD;STA, hold time (repeated) start condition
t7 t8
tBUF, bus free time between a stop and a start condition tSU;STO, setup time for stop condition
t9
1000 300 80 160 300 300 80 160 1000 300 40 80
tRDA, rise time of SDA signal
t10
tFDA, fall time of SDA signal
t11
tRCL, rise time of SCL signal
ADG796A
Parameter 1 t11A Conditions Standard mode Fast mode High speed mode CB = 100 pF max CB = 400 pF max Standard mode Fast mode High speed mode CB = 100 pF max CB = 400 pF max Fast mode High speed mode Min 20 + 0.1 CB 10 20 20 + 0.1 CB 10 20 0 0 Max 1000 300 80 160 300 300 40 80 50 10 Unit ns ns ns ns ns ns ns ns ns ns Description tRCL1, rise time of SCL signal after a repeated start condition and after an acknowledge bit
t12
tFCL, fall time of SCL signal
tSP
Pulse width of suppressed spike
1 2
Guaranteed by initial characterization. CB refers to capacitive load on the bus line, tr and tf measured between 0.3 VDD and 0.7 VDD. A device must provide a data hold time for SDA in order to bridge the undefined region of the SCL falling edge.
Timing Diagram
t11
SCL
t12
t2 t6 t4 t1 t3 t5 t10
t6
t8 t9
06036-002
SDA
t7
P S S P
Figure 2. Timing Diagram for 2-Wire Serial Interface
Rev. 0 | Page 8 of 24
ADG796A ABSOLUTE MAXIMUM RATINGS
TA = 25°C, unless otherwise noted. Table 4.
Parameter VDD to GND Analog, Digital Inputs Continuous Current, S or D Pins Peak Current, S or D Pins Operating Temperature Range Industrial (B Version) Storage Temperature Range Junction Temperature θJA Thermal Impedance 24-Lead LFCSP Lead Temperature, Soldering (10 sec) IR Reflow, Peak Temperature (
