Data Sheet
0 Hz/DC to 13 GHz, 2.5 kV HBM ESD,
SP4T, MEMS Switch with Integrated Driver
ADGM1004
FEATURES
APPLICATIONS
Fully operational down to 0 Hz/dc
On resistance: 2.9 Ω (maximum)
Off leakage: 0.5 nA (maximum)
−3 dB bandwidth
10.8 GHz (typical) for RF1, RF4
13 GHz (typical) for RF2, RF3
RF performance characteristics
Insertion loss: 0.45 dB (typical) at 2.5 GHz
Isolation: 24 dB (typical) at 2.5 GHz
IP3: 67 dBm (typical)
RF input power: 32 dBm (maximum)
Actuation lifetime: 1 billion cycles (minimum)
Hermetically sealed switch contacts
On switching time: 75 µs (maximum)
ESD HBM rating
5 kV for RF1 to RF4 and RFC pins
2.5 kV for all other pins
Integrated driver removes the need for an external driver
Supply voltage: 3.0 V to 3.6 V
CMOS/LVTTL compatible
Parallel and SPI Interface
Independently controllable switches
Switch is in an open state with no power supply present
Requirement to avoid floating nodes on all RFx pins (see the
Floating Node section)
5 mm × 4 mm × 1.45 mm, 24-lead LFCSP
Operating temperature range: 0°C to +85°C
Relay replacements
Automatic test equipment (ATE): RF, digital, and mixed signals
Load and probe boards: RF, digital, and mixed signals
RF test instrumentation
Reconfigurable filters and attenuators
High performance RF switching
COMPANION PRODUCTS
Quad PMU: AD5522
SP4T MEMS Switch: ADGM1304
Low Noise, LDO: ADP7142, LT1962, LT3045-1
GENERAL DESCRIPTION
The ADGM1004 is a wideband, single-pole, four-throw (SP4T)
switch fabricated using Analog Devices, Inc., microelectromechanical system (MEMS) switch technology. This technology
enables a small form factor, wide RF bandwidth, highly linear,
low insertion loss switch that is operational from 0 Hz/dc to
13 GHz, making it an ideal solution for a wide range of RF and
precision equipment switching needs.
An integrated driver chip generates a high voltage to
electrostatically actuate switch that can be controlled by a parallel
interface and a serial peripheral interface (SPI). All four switches
are independently controllable.
The device is packaged in a 24-lead, 5 mm × 4 mm × 1.45 mm,
lead frame chip-scale package (LFCSP).
To ensure optimum operation of the ADGM1004, follow the
Critical Operational Requirements section exactly.
The on resistance (RON) performance of the ADGM1004 is
affected by part to part variation, channel to channel variation,
cycle actuations, settling time post turn on, bias voltage, and
temperature changes.
Note that throughout this data sheet, multifunction pins, such
as IN1/SDI, are referred to either by the entire pin name or by a
single function of the pin, for example, SDI, when only that
function is relevant.
Rev. E
Document Feedback
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rights of third parties that may result from its use. Specifications subject to change without notice.
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Tel: 781.329.4700 ©2017–2020 Analog Devices, Inc. All rights reserved.
Technical Support
www.analog.com
ADGM1004
Data Sheet
TABLE OF CONTENTS
Features .............................................................................................. 1
Low Power Mode ....................................................................... 25
Applications ...................................................................................... 1
Typical Operating Circuit ......................................................... 26
Companion Products ....................................................................... 1
Applications Information ............................................................. 27
General Description ......................................................................... 1
Power Supply Rails..................................................................... 27
Revision History ............................................................................... 2
Power Supply Recommendations ............................................ 27
Functional Block Diagram .............................................................. 4
Switchable RF Attenuator ......................................................... 27
Specifications .................................................................................... 5
Reconfigurable RF Filter ........................................................... 27
Timing Characteristics ................................................................ 7
Critical Operational Requirements.............................................. 29
Absolute Maximum Ratings ........................................................... 9
System Error Considerations Due to On-Resistance Drift .. 29
Thermal Resistance ...................................................................... 9
ESD Caution.................................................................................. 9
On Resistance Shift Due to Temperature Shock Post
Actuations ................................................................................... 29
Pin Configuration and Function Descriptions .......................... 10
Floating Node ............................................................................. 29
Typical Performance Characteristics ........................................... 12
Cumulative On Switch Lifetime............................................... 30
Test Circuits .................................................................................... 17
Handling Precautions ................................................................ 30
Terminology .................................................................................... 20
Register Details ............................................................................... 32
Theory of Operation ...................................................................... 22
Switch Data Register .................................................................. 32
Parallel Digital Interface ............................................................ 22
Outline Dimensions ....................................................................... 33
SPI Digital Interface ................................................................... 23
Ordering Guide .......................................................................... 33
Internal Oscillator Feedthrough .............................................. 25
Internal Oscillator Feedthrough Mitigation ........................... 25
REVISION HISTORY
11/2020—Rev. D to Rev. E
Added Companions Products Section .......................................... 1
Added Endnote 3, Table 1; Renumbered Sequentially ............... 5
Changes to Figure 11 ..................................................................... 12
Changes to Figure 43 ..................................................................... 19
Changes to Addressable Mode Section and Figure 45 Caption .....23
Added Figure 46; Renumbered Sequentially .............................. 23
Changes to Typical Operating Circuit Section........................... 26
Added Power Supply Rails Section, Power Supply
Recommendations Section, Figure 51, and Table 7;
Renumbered Sequentially ............................................................. 27
Changes to System Error Considerations Due to On Resistance
Drift Section .................................................................................... 29
Added On Resistance Shift Due to Temperature Shock Post
Actuations Section.......................................................................... 29
Moved Figure 6; Renumbered Sequentially................................ 29
11/2019—Rev. C to Rev. D
Change to Features Section and General
Applications Section ........................................................................ 1
Moved Functional Block Diagram Section ................................... 4
Changes to Figure 1.......................................................................... 4
Changes to Specifications Section and Table 1 ............................ 5
Added Timing Characteristics Section and Table 2;
Renumbered Sequentially ............................................................... 7
Added Timing Diagrams Section, Figure 2, Figure 3, and
Figure 4; Renumbered Sequentially ................................................8
Changes to Absolute Maximum Rating Section
and Table 3 .........................................................................................9
Changes to Figure 5 and Table 5 .................................................. 10
Changes to Typical Performance Characteristics Section ........ 12
Changes to Terminology Section ................................................. 20
Changes to Parallel Digital Interface Section and
Table 6 Title .................................................................................... 22
Added SPI Digital Interface Section, Addressable Mode
Section, and Figure 45 ................................................................... 23
Added Daisy-Chain Mode Section, Figure 46, Figure 47, and
Figure 48 .......................................................................................... 24
Added Hardware Reset Section and Internal Error Status
Section .............................................................................................. 25
Changes to Internal Oscillator Feedthrough Section and
Internal Oscillator Feedthrough Mitigation Section ................. 25
Changes to Typical Operating Circuit Section and
Figure 49 .......................................................................................... 26
Deleted Handling Guidelines Section, DC Voltage Range
Section, and Voltage Standoff Limit Section .............................. 27
Added Critical Operational Requirements Section, System
Error Considerations Due to On-Resistance Drift Section,
Rev. E | Page 2 of 33
Data Sheet
ADGM1004
Figure 52, Table 7, Floating Node Section, Figure 53, Figure 54,
Figure 55, Figure 56, and Figure 57 ..............................................28
Added Figure 58, Figure 59, Cumulative On Switch Lifetime
Section, Handling Precautions Section, and Figure 61..............29
Moved Figure 60 and Electrical Overstress (EOS)
Precautions Section .........................................................................29
Added Mechanical Shock Precautions Section and Table 8 .....30
Changes to Figure 62 ......................................................................30
Added Register Details Section, Switch Data Register Section,
and Table 9 .......................................................................................31
Change to Ordering Guide ............................................................32
3/2019—Rev. B to Rev. C
Change to Features Section and Figure 1 ...................................... 1
Changes to Specifications Section and Table 1 ............................. 3
Deleted Endnote 1, Endnote 3, and Endnote 6 in Table 1;
Renumbered Sequentially ................................................................ 4
Changes to Table 2 ............................................................................ 5
Changes to Table 4 ............................................................................ 6
Updated Typical Performance Characteristics Section
Format ................................................................................................ 7
Changes to Figure 6 to Figure 8 Captions ..................................... 7
Added Figure 9 to Figure 12; Renumbered Sequentially............. 8
Deleted Figure 15 .............................................................................. 9
Added Figure 19 and Figure 20 ....................................................... 9
Added Figure 24 to Figure 26 ........................................................10
Added Figure 27 to Figure 30 ........................................................11
Changes to Figure 32 Caption .......................................................12
Added Figure 33 ..............................................................................12
Deleted Figure 27 to Figure 29 ......................................................12
Changes to Figure 35 ......................................................................13
Changes to Figure 37 Caption .......................................................13
Added Figure 39, Figure 40, and Figure 42 ................................. 14
Changes to Terminology Section.................................................. 15
Changes to Theory of Operation Section .................................... 17
Changed Internal Oscillator/EXTD_EN Section to Internal
Oscillator Section ............................................................................ 18
Changes to Internal Oscillator Section, Typical Operating
Circuit Section ................................................................................. 18
Replaced Figure 44 .......................................................................... 18
Added Oscillator Feedthrough Mitigation Section and Low
Power Mode Section ....................................................................... 18
Changes to Figure 50 and Figure 51 ............................................. 19
Added Voltage Standoff Limit Section ........................................ 22
3/2018—Rev. A to Rev. B
Changes to Features Section ............................................................ 1
Changes to Table 1 ............................................................................ 3
Added Endnote 5 to Table 1; Renumbered Sequentially ............ 3
Changes to Table 2 ............................................................................ 5
Added Figure 27, Figure 28, and Figure 29; Renumbered
Sequentially ...................................................................................... 12
Changes to Floating Node Avoidance Section and Figure 36 .... 17
Updated Outline Dimensions ....................................................... 21
2/2017—Rev. 0 to Rev. A
Changes to Features Section ............................................................ 1
Changes to On Resistance Parameter, Table 1 ............................. 3
Change to Table 2 ............................................................................. 5
Changes to Figure 13 and Figure 14 ............................................... 8
Updated Outline Dimensions ....................................................... 20
1/2017—Revision 0: Initial Version
Rev. E | Page 3 of 33
ADGM1004
Data Sheet
FUNCTIONAL BLOCK DIAGRAM
RF1 IN RF2 IN
0.1µF
47pF
10MΩ*
EXTD_EN
VDD
VCP
10MΩ*
RF1
RF2
ADGM1004
OSCILLATOR
CHARGE
PUMP
REFERENCE
AND BIAS
REGULATOR
PIN/SPI
VCP
IN1/SDI
LV
LEVEL
SHIFTER
HV
IN2/CS
LV
LEVEL
SHIFTER
HV
RFC
RFC IN
10MΩ*
IN3/SCLK
LV
LEVEL
SHIFTER
HV
IN4/SDO
LV
LEVEL
SHIFTER
HV
RF4
GND
RF3
10MΩ*
10MΩ*
Figure 1.
Rev. E | Page 4 of 33
15173-001
RF4 IN RF3 IN
*10MΩ RESISTORS ARE REQUIRED TO AVOID ANY FLOATING NODES.
FOR MORE INFORMATION, REFER TO THE CRITICAL OPERATIONAL REQUIREMENTS SECTION
NOTES
1. LV = LOW VOLTAGE.
HV = HIGH VOLTAGE.
Data Sheet
ADGM1004
SPECIFICATIONS
Supply voltage (VDD) = 3.0 V to 3.6 V, GND = 0 V, and all specifications at TA = 25°C, unless otherwise noted. Typical specifications
tested at TA = 25°C with VDD = 3.3 V.
Table 1.
Parameter
ON-RESISTANCE PROPERTIES
Initial On-Resistance
Properties
On Resistance
On-Resistance Match
Between Channels
On-Resistance Drift
Over Time 2, 3
Over Actuations 4
Symbol
Min
Max
Unit
Test Conditions/Comments 1
See Figure 54 to Figure 12 for more details
RON
2.9
Ω
ΔRON CH_CH
1
Ω
Drain source current (IDS) = 50 mA, 0 V input
bias, at 1 ms after first actuation, maximum
specification from 0°C to 85°C
Maximum value tested from 0°C to 85°C
ΔRON TIME
−0.25
Ω
ΔRON
Typ
0.5
Ω
5
RELIABILITY PROPERTIES
Continuously On Lifetime
7.2
Actuation Lifetime
Cold Switched
Hot Switched
109
5.16 ×
109
3.21 ×
106
390 ×
103
10 dBm
15 dBm
20 dBm
DYNAMIC CHARACTERISTICS
Operating Frequency
−3 dB Bandwidth
RF1, RF4
RF2, RF3
Insertion Loss
0/dc
Years
Median time before failure at 50°C 6, see Figure 60
for more details
Actuations
Actuations
Load between toggling is 220 mA, tested at 85°C
RF power = continuous wave (CW), terminated
into 50 Ω, see Figure 13 for details
50% of test population failure point (T50)
Actuations
50% of test population failure point (T50)
Actuations
50% of test population failure point (T50)
13
GHz
0.6
0.95
GHz
GHz
dB
dB
RF1 to RFC and RF4 to RFC channels
RF2 to RFC and RF3 to RFC channels
At 2.5 GHz, RFC to RFx
At 6.0 GHz, RFC to RFx
dB
dB
At 2.5 GHz, RFx to RFC (all channels off)
At 6.0 GHz, RFx to RFC (all channels off)
At 6 GHz, RF2 to RFC is on, RF1 to RFC is off
At 6 GHz, RF1 to RFC is on, RF2 to RFC is off
At 2.5 GHz, RFx to RFx
At 6.0 GHz, RFx to RFx
DC to 6.0 GHz
Input: 900 MHz and 901 MHz, input power =
27 dBm
Input: 900 MHz and 901 MHz, input power =
27 dBm
Input: 5.4 MHz, input power = 0 dBm
Input: 150 MHz and 800 MHz, input power =
27 dBm
BW
9.5
11.5
IL
Isolation
RFx to RFC
22
16
10.8
13
0.45
0.63
24
19
27
26
30
24
17
67
dB
dB
dB
dBm
IP2
95
dBm
HD2
−90
−74
dBc
dBc
RF1 to RFC
RF2 to RFC
Crosstalk
Return Loss
Third-Order Intermodulation
Intercept
Second-Order Intermodulation
Intercept
Second Harmonic Distortion
Ω
RON changed from 1 ms to 100 ms after first
actuation, maximum value tested from 0°C to 85°C
109 actuations, switch is actuated at 25°C and
RON is measured at 25°C
109 actuations, switch is actuated at 85°C and RON is
measured at 25°C, 1 kHz actuating frequency,
220 mA load applied between toggles 5
RL
IP3
27
22
14
Rev. E | Page 5 of 33
ADGM1004
Data Sheet
Parameter
Third Harmonic Distortion
Symbol
HD3
Total Harmonic Distortion
plus Noise
RF Input Power
THD + N
DC Voltage Range
Min
Typ
−80
Max
−102
Unit
dBc
dBc
32
dBm
−6
+6
V
On Switching Time 7
tON
0
75
µs
Off Switching Time7
tOFF
0
75
µs
5
kHz
ms
mV peak
MHz
dBm
Actuation Frequency
Power-Up Time
Video Feedthrough
Internal Oscillator Frequency
Internal Oscillator
Feedthrough 8
CAPACITANCE PROPERTIES
On Switch Channel
Capacitance
Off Switch Channel
Capacitance
LEAKAGE PROPERTIES
On Leakage
Off Leakage
DIGITAL INPUTS
Input High Voltage
Input Low Voltage
Input Current
DIGITAL OUTPUTS
Output Low Voltage
Output High Voltage
POWER REQUIREMENTS
Supply Voltage
Supply Current
Low Power Mode Current 10
External Drive Voltage 11
External Drive Current
8
0.75
16
10
−123
12
−146
dBm/Hz
CRF ON
3
pF
CRF OFF
1.5
pF
Test Conditions/Comments 1
Input: 150 MHz and 800 MHz, input power =
27 dBm
Load resistance (RL) = 300 Ω, f = 1 kHz, RFx =
2.5 V p-p
Switch in the on state and terminated into 50 Ω,
maximum specification tested at 25℃
On switch dc voltage operation range, 0°C to
85°C
50% INx to 90% (0.05 dB of final IL value) RFx,
50 Ω termination, 0°C to 85°C
50% INx to 10% (0.05 dB of final IL value) RFx,
50 Ω termination, 0°C to 85°C
All switches toggled simultaneously, 0°C to 85°C
CCP = 47 pF, 95% VDD to 90% RFx, 0°C to 85°C
1 MΩ termination at RFx pin
0°C to 85°C
Spectrum analyzer resolution bandwidth (RBW) =
200 Hz, one switch in on state, all other switches
off with 50 Ω terminations 9
At 1 MHz, includes LFCSP package capacitance
VINH
VINL
IINL, IINH
VOL
VOH
5
nA
0.5
nA
0.8
1
V
V
µA
2
0.025
0.4
VMAX
VMIN
3.6
2.5
V
mA
50
80.8
20
µA
V
µA
VDD −
0.4
Maximum specification from 0°C to 85°C
RFx (off channels) = −6 V, RFC to RFx (on
channel) = −6 V
RFx = 6 V, RFC = −6 V
Minimum and maximum over 0°C to 85°C
Input voltage (VIN) = VINL or VINH
Minimum and maximum over 0°C to 85°C
Sink current (ISINK) = 1 mA
Source current (ISOURCE) = 1 mA
Minimum and maximum over 0°C to 85°C
VDD
IDD
IDD EXT VCP
VCPEXT
ICP EXT VCP
3.0
79.2
80
Digital inputs = 0 V or VDD, SDO is floating in
SPI mode
This value is IDD in low power mode
RFx is RF1, RF2, RF3, and RF4. INx is IN1, IN2, IN3, and IN4.
Maximum RON over time is RON (max) + ∆RON TIME (max) = 2.65 Ω.
Typically, the on-resistance over time drifts by −0.05 Ω per decade.
4
Maximum RON after 1 billion actuations is RON (max) + ΔRON (max) = 7.9 Ω.
5
Actuating the switch at 85°C and measuring RON at 25°C is the most severe condition for ADGM1004 RON drift over actuations.
6
Failure occurs when 50% of a sample lot fails. For more details, see the Cumulative On Switch Lifetime section.
7
Switch is settled after 75 µs. Do not apply RF power between 0 µs and 75 µs.
8
Disable the internal oscillator to eliminate feedthrough. When the internal oscillator and charge pump circuitry is disabled, the VCP pin (Pin 24) must be driven with
80 V dc (VCPEXT) from an external voltage supply required for MEMS switch actuation, as outlined in Table 3.
9
The spectrum analyzer setup is as follows: RBW = 200 Hz, video bandwidth (VBW) = 2 Hz, span = 100 kHz, input attenuator = 0 dB, the detector type is peak, and the
maximum hold is off. The fundamental feedthrough noise or harmonic (whichever is higher) is tested.
10
For more details, see the Low Power Mode section.
11
For more details, see the Internal Oscillator Feedthrough Mitigation section.
1
2
3
Rev. E | Page 6 of 33
Data Sheet
ADGM1004
TIMING CHARACTERISTICS
VDD = 3.0 V to 3.6 V, GND = 0 V, and all specifications TMIN to TMAX = 0°C to +85°C, unless otherwise noted.
Table 2.
Parameter
t1
t2
t3
t4
t5
t6
t7
t8
t9 1
t10
t11
t12
t13
1
Description
SCLK period
SCLK high pulse width
SCLK low pulse width
CS falling edge to SCLK active edge
Data setup time
Data hold time
SCLK active edge to CS rising edge
CS falling edge to SDO data available
SCLK falling edge to SDO data available
CS rising edge to SDO returns to high impedance
CS high time between SPI commands
SCLK edge rejection to CS falling edge
CS rising edge to SCLK edge rejection
Measured with a 20 pF load, t9 determines the maximum SCLK frequency when the SDO pin is used.
Rev. E | Page 7 of 33
Limit at TMIN
100
45
45
25
20
20
25
Limit at TMAX
20
40
25
100
25
25
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ADGM1004
Data Sheet
Timing Diagrams
t1
SCLK
t2
t3
t4
t7
CS
t5
SDI
t6
A6
R/W
A5
D2
D1
D0
t10
t9
0
0
1
D2
D1
D0
15173-302
SDO
t8
Figure 2. Addressable Mode Timing Diagram
t1
SCLK
t2
t3
t4
t7
CS
SDI
D7
t6
D6
D0
INPUT BYTE FOR DEVICE N
D6
D7
D1
D0
INPUT BYTE FOR DEVICE N + 1
t9
0
t8
0
0
ZERO BYTE
D7
D6
D1
D0
INPUT BYTE FOR DEVICE N
Figure 3. Daisy-Chain Timing Diagram
t11
CS
SCLK
t13
t12
15173-304
SDO
Figure 4. SCLK/CS Timing Relationship
Rev. E | Page 8 of 33
t10
15173-303
t5
Data Sheet
ADGM1004
ABSOLUTE MAXIMUM RATINGS
TA = 25°C, unless otherwise noted.
Table 3.
Parameter
VDD to GND
Digital Inputs1
DC Voltage Rating2
Standoff Voltage3
RFx to AGND
RFC to AGND
RFx to RFC
Current Rating2
RF Power Rating4
Temperature
Operating Range
Storage Range
Reflow Soldering (Pb-Free)
Peak
Time at Peak
Electrostatic Discharge (ESD)
Human Body Model (HBM)
RF1 to RF4 and RFC
All Other Pins
Field Induced Charged Device
Model5
All Pins
Group D
Mechanical Shock (with 0.5 ms
Pulse) 6
Vibration (Acceleration at 50 g)
Constant Acceleration
Rating
−0.3 V to +6 V
−0.3 V to VDD + 0.3 V or
+30 mA (whichever occurs
first)
±7 V
20 V
±10 V
±10 V
20 V
250 mA
33 dBm
0°C to +85°C
−65°C to +150°C
Stresses at or above those listed under Absolute Maximum
Ratings may cause permanent damage to the product. This is a
stress rating only; functional operation of the product at these
or any other conditions above those indicated in the operational
section of this specification is not implied. Operation beyond
the maximum operating conditions for extended periods may
affect product reliability.
Only one absolute maximum rating can be applied at any one time.
THERMAL RESISTANCE
Thermal performance is directly linked to printed circuit board
(PCB) design and operating environment. Careful attention to
PCB thermal design is required.
θJA is the natural convection junction to ambient thermal
resistance measured in a one cubic foot sealed enclosure. θJC is
the junction to case thermal resistance.
Table 4. Thermal Resistance
Package Type
CP-24-41
260 (+0/−5)°C
10 sec to 30 sec
1
5 kV
2.5 kV
1.25 kV
θJA
60
θJC
75
Unit
°C/W
A simulated θJA number is evaluated using the maximum junction
temperature in the package and the total power being dissipated in the
package under operating conditions. For thermal performance calculation
purposes at 25°C, a power dissipation of 113 mW per switch can be used.
This value is calculated from a typical RON of 1.8 Ω and an absolute maximum
current rating of 250 mA.
ESD CAUTION
1500 g
20 Hz to 2000 Hz
30,000 g
Clamp overvoltages at INx by internal diodes. Limit the current to the
maximum ratings given.
2
This rating is with respect to the switch in the on position with no radio
frequency signal applied.
3
This rating is with respect to the switch in the off position.
4
This rating is with respect to the switch in the on position and terminated
into 50 Ω. The rating is 27 dBm when the switch is unterminated.
5
A safe automated handling and assembly process is achieved at this rating
level by implementing industry standard ESD controls.
6
If the device is dropped during handling, do not use the device.
1
Rev. E | Page 9 of 33
ADGM1004
Data Sheet
24
23
22
21
20
19
18
VCP
VDD
GND
GND
RF1
GND
RF2
PIN CONFIGURATION AND FUNCTION DESCRIPTIONS
1
2
3
4
5
ADGM1004
TOP VIEW
(Not to Scale)
EP1
EP2
17
16
15
14
13
GND
GND
RFC
GND
GND
NOTES
1. EXPOSED PAD 1. EP1 IS INTERNALLY CONNECTED TO EP2
AND MUST BE CONNECTED TO GND.
2. EXPOSED PAD 2. EP2 IS INTERNALLY CONNECTED TO EP1
AND MUST BE CONNECTED TO GND.
15173-002
PIN/SPI 6
EXTD_EN 7
GND 8
GND 9
RF4 10
GND 11
RF3 12
IN1/SDI
IN2/CS
IN3/SCLK
IN4/SDO
GND
Figure 5. Pin Configuration
Table 5. Pin Function Descriptions
Pin No.
1
Mnemonic
IN1/SDI
2
IN2/CS
3
IN3/SCLK
4
IN4/SDO
5, 8, 9, 11, 13,
14, 16, 17,
19, 21, 22
6
GND
PIN/SPI
7
EXTD_EN
10
RF4
12
RF3
15
18
RFC
RF2
20
RF1
Description
Parallel Logic Digital Control Input 1. The voltage applied to this pin controls the gate of the RF1 to RFC
MEMS switch. In SPI mode, this pin is the serial data input pin. In parallel mode, if the IN1 pin is low, the
RF1 to RFC switch is open (off). If the IN1 pin is high, the RF1 to RFC switch is closed (on). In SPI mode, this
pin functions as the serial data input (SDI) pin.
Parallel Logic Digital Control Input 2. The voltage applied to this pin controls the gate of the RF2 to RFC
MEMS switch. In parallel mode, if IN2 is low, the RF2 to RFC switch is open (off). If IN2 is high, the RF2 to
RFC switch is closed (on). In SPI mode, this pin is the chip select (CS) pin. CS is an active low signal that
selects the slave device with which the master device intends to communicate. Typically, there is a
dedicated CS signal between the master device and each slave device. The CS pin also functions to
synchronize and frame the communications to and from the slave device.
Parallel Logic Digital Control Input 3. The voltage applied to this pin controls the gate of the RF3 to RFC
MEMS switch. In parallel mode, if IN3 is low, the RF3 to RFC switch is open (off). If IN3 is high, the RF3 to
RFC switch is closed (on). In SPI mode, this pin functions as the serial clock (SCLK) pin that synchronizes the
slave device(s) to the master device. Typically, the SCLK signal is shared for all slave devices on the serial
bus. The SCLK signal is always driven by the master device.
Parallel Logic Digital Control Input 4. The voltage applied to this pin controls the gate of the RF4 to RFC
MEMS switch. In parallel mode, if IN4 is low, the RF4 to RFC switch is open (off). If IN4 is high, the RF4 to
RFC switch is closed (on). In SPI mode, this pin functions as the serial data output (SDO) pin. Typically, the
SDO pin is shared for all slave devices on the serial bus. The SDO pin is driven by only one slave device at a time,
otherwise it is high impedance. The SDO pin is always high impedance when the CS pin is deasserted high.
Ground Connection.
Parallel or Serial Logic Control Enable Pin. The SPI interface is enabled when this pin is high. When this pin
is low the parallel digital interface is enabled.
External Voltage Drive Enable. In normal operation, set EXTD_EN low to enable the built in 10 MHz oscillator,
which enables the internal driver IC voltage boost circuitry. Setting EXTD_EN high disables the internal 10 MHz
oscillator and driver boost circuitry. With the oscillator disabled, the switch can still be controlled via the
logic interface pins (IN1 to IN4) or via SPI interface, but the VCP pin must be driven with 80 V dc from an
external voltage supply. In this mode, the ADGM1004 only consumes 50 µA maximum supply current.
Disabling the internal oscillator eliminates the associated 10 MHz noise feedthrough from the switch.
RF4 Port. This pin can be an input or an output. If unused, connect the pin to GND or terminate the pin
with a 50 Ω resistor to GND.
RF3 Port. This pin can be an input or an output. If unused, connect the pin to GND or terminate the pin
with a 50 Ω resistor to GND.
Common RF Port. This pin can be an input or an output.
RF2 Port. This pin can be an input or an output. If unused, connect the pin to GND or terminate the pin
with a 50 Ω resistor to GND.
RF1 Port. This pin can be an input or an output. If unused, connect the pin to GND or terminate the pin
with a 50 Ω resistor to GND.
Rev. E | Page 10 of 33
Data Sheet
ADGM1004
Pin No.
23
Mnemonic
VDD
24
VCP
EP1
EP2
Description
Positive Power Supply Input. The recommended decoupling capacitor to ground value is 0.1 µF. For the
recommended input voltage for this chip, see the Specifications section.
Charge Pump Capacitor Terminal. The recommended shunt capacitor to ground value is 47 pF (100 V
rated). If the EXTD_EN pin is high, input an 80 V dc drive voltage into VCP to drive the switches.
Exposed Pad 1. EP1 is internally connected to EP2 and must be connected to GND.
Exposed Pad 2. EP2 is internally connected to EP1 and must be connected to GND.
Rev. E | Page 11 of 33
ADGM1004
Data Sheet
TYPICAL PERFORMANCE CHARACTERISTICS
In Figure 13, T50 refers to the number of cycles required for 50% of the population to fail.
3.0
0
SWITCH ACTUATED AT 25°C
RON MEASURED AT 25°C
VDD = 3.3V
VDD = 3.3V
TA = 25°C
–0.05
2.5
RON DRIFT (Ω)
ABSOLUTE RON (Ω)
–0.10
2.0
1.5
–0.15
–0.20
–0.25
1.0
–0.30
1
10
RFC
RFC
RFC
RFC
RF1 TO
RF2 TO
RF3 TO
RF4 TO
–0.35
100
1k
10k
100k
10M
1M
100M
SWITCH ACTUATION NUMBER
–0.40
Figure 6. Absolute RON vs. Switch Actuation Number, Switch Actuated at 25°C
and RON Measured at 25°C
0
RFC
RFC
RFC
RFC
1.0
0.5
1.5
2.0
2.5
3.0
3.5
4.0
4.5
5.0
TIME (Seconds)
15173-510
0
RF1 TO
RF2 TO
RF3 TO
RF4 TO
15173-507
0.5
Figure 9. RON Drift vs. Time (1 ms to 5 sec) on Linear Scale, Normalized at Zero
1.0
0
SWITCH ACTUATED AT 25°C
RON MEASURED AT 25°C
VDD = 3.3V
0.8
VDD = 3.3V
TA = 25°C
–0.05
0.6
–0.10
RON DRIFT (Ω)
RON DRIFT (Ω)
0.4
0.2
0
–0.2
–0.15
–0.20
–0.25
–0.4
–0.30
–0.8
–1.0
1
10
RFC
RFC
RFC
RFC
–0.35
100
1k
10k
1M
100k
10M
100M
SWITCH ACTUATION NUMBER
Figure 7. RON Drift vs. Switch Actuation Number, Normalized at Zero, Switch
Actuated at 25°C and RON Measured at 25°C
RFC
RFC
RFC
RFC
RON DRIFT OVER TIME = –0.05Ω PER DECADE (TYPICALLY).
–0.40
0.001
0.01
0.1
10
1
TIME (Seconds)
Figure 10. RON Drift vs. Time (1 ms to 5 sec) on Log Scale, Normalized at Zero
2.0
2.4
RF1 TO
RF2 TO
RF3 TO
RF4 TO
2.2
VDD = 3.3V
TA = 25°C
RFC
RFC
RFC
RFC
VDD = 3.0V
VDD = 3.3V
VDD = 3.6V
1.8
TA = 25°C
1.6
2.0
1.4
RON (Ω)
1.8
1.6
1.2
1.0
0.8
0.6
1.4
0.4
1.2
1.0
0
0.5
1.0
1.5
2.0
2.5
3.0
3.5
4.0
4.5
5.0
TIME (Seconds)
Figure 8. Absolute RON vs. Time (1 ms to 5 sec) on Linear Scale
0
–6
–4
–2
0
2
SIGNAL BIAS VOLTAGE (V)
4
6
15173-422
0.2
15173-509
ABSOLUTE RON (Ω)
RF1 TO
RF2 TO
RF3 TO
RF4 TO
15173-511
RF1 TO
RF2 TO
RF3 TO
RF4 TO
15173-508
–0.6
Figure 11. RON vs. Signal Bias Voltage over Supply Voltages (Measured 5 sec
Post Switch Turn On Time, RF1 to RFC on)
Rev. E | Page 12 of 33
Data Sheet
2.0
ADGM1004
0
TA = 0°C
TA = 25°C
TA = 85°C
1.8
–0.5
INSERTION LOSS (dB)
1.6
1.4
RON (Ω)
85°C
25°C
0°C
VDD = 3.3V
1.2
1.0
0.8
0.6
0.4
–1.0
–1.5
–2.0
–2.5
6
4
SIGNAL BIAS VOLTAGE (V)
VDD = 3.3V
–3.0
100M
Figure 12. RON vs. Signal Bias Voltage over Temperature (Measured 5 sec Post
Switch Turn On Time, RF1 to RFC on)
0
INSERTION LOSS (dB)
FAILURES (% OF POPULATION)
0
TA = 25°C
VDD = 3.3V
–10
–0.10
82
65
T50
45
25
14
–20
–0.15
–30
–0.20
–0.25
–40
–0.30
–50
–0.35
–60
8
–0.40
4
INSERTION LOSS
OFF ISOLATION
RETURN LOSS
100k
1M
10M
100M
1B
10B
100B
SWITCH ACTUATIONS (Cycles)
15173-521
–0.45
1
10k
Figure 13. Hot Switching Probability Distribution on Log Normal with 95%
Confidence Interval (CI) (RF Power = CW, Terminated into 50 Ω, TA = 25°C,
VDD = 3.3 V)
–0.50
100
50
0
–70
–80
200
150
FREQUENCY (MHz)
Figure 16. Insertion Loss and Off Isolation/Return Loss vs. Frequency
(VDD = 3.3 V, RF1 to RFC)
0
0
–10
–0.5
TA = 25°C
VDD = 3.3V
TA = 25°C
VDD = 3.3V
RF1 TO RFC
RF2 TO RFC
RF2 TO RFC
RF1 TO RFC
OFF ISOLATION (dB)
–20
–1.0
–1.5
–2.0
–30
–40
–50
–60
–2.5
–3.0
0
2
4
6
8
10
12
14
16
FREQUENCY (GHz)
Figure 14. Insertion Loss vs. Frequency, Linear Scale (VDD = 3.3 V)
15173-007
–70
15173-006
INSERTION LOSS (dB)
100G
Figure 15. Insertion Loss vs. Frequency over Temperature (VDD = 3.3 V, RF1 to RFC)
–0.05
10dBm
15dBm
20dBm
10G
FREQUENCY (Hz)
98
94
90
1G
–80
0
1
2
3
4
6
5
FREQUENCY (GHz)
7
8
9
10
Figure 17. Off Isolation vs. Frequency, All Channels Off (VDD = 3.3 V)
Rev. E | Page 13 of 33
OFF ISOLATION/RETURN LOSS (dB)
2
0
–2
15173-005
–4
–6
15173-513
0
15173-004
0.2
ADGM1004
Data Sheet
0
0
TA = 85°C
TA = 25°C
TA = 0°C
–10
–10
–30
–40
–50
–30
–40
–50
–60
–60
–70
–70
–80
0
1
2
3
4
6
5
FREQUENCY (GHz)
7
8
9
15173-009
CROSSTALK (dB)
–20
15173-008
–80
10
0
Figure 18. Off Isolation vs. Frequency over Temperature, All Channels Off
(VDD = 3.3 V, RF1 to RFC)
0
TA = 25°C
VDD = 3.3V
4
6
5
FREQUENCY (GHz)
7
8
9
10
VDD = 3.3V
–20
CROSSTALK (dB)
–30
–40
RF2 TO RFC
RF3 TO RFC
RF4 TO RFC
–50
–30
–40
–50
–60
–60
–70
–70
15173-011
OFF ISOLATION (dB)
3
TA = 85°C
TA = 25°C
TA = 0°C
–10
–20
0
1
2
3
4
5
6
7
8
9
10
FREQUENCY (GHz)
Figure 19. Off Isolation vs. Frequency, RF1 to RFC On (VDD = 3.3 V)
15173-312
–80
–80
0
1
2
4
6
5
FREQUENCY (GHz)
3
7
9
8
10
Figure 22. Crosstalk vs. Frequency over Temperature (VDD = 3.3 V, RF2 to RF1)
0
0
VDD = 3.3V
TA = 25°C
VDD = 3.3V
RF1
RF2
RFC (RF1 ON)
–10
100Hz
1kHz
5kHz
10kHz
15kHz
20kHz
–20
–40
THD + N (dBc)
–20
–30
–60
–40
–80
–50
–100
15173-010
RETURN LOSS (dB)
2
Figure 21. Crosstalk vs. Frequency (VDD = 3.3 V)
0
–10
1
–60
0
1
2
3
4
6
5
FREQUENCY (GHz)
7
8
Figure 20. Return Loss vs. Frequency (VDD = 3.3 V)
9
–120
10
0
2
4
6
8
SIGNAL AMPLITUDE (V p-p)
10
12
15173-322
OFF ISOLATION (dB)
–20
TA = 25°C
VDD = 3.3V
RF1 TO RF2
RF2 TO RF1
VDD = 3.3V
Figure 23. THD + N vs. Signal Amplitude (VDD = 3.3 V, RLOAD = 300 Ω, TA = 25°C,
Signal Source Impedance = 20 Ω)
Rev. E | Page 14 of 33
Data Sheet
ADGM1004
4.0
0
OFF SWITCH CAPACITANCE
ON SWITCH CAPACITANCE
VDD = 3.3V
–10
3.5
SWITCH CAPACITANCE (pF)
–20
–30
THD + N (dBc)
–40
0dBm
5dBm
10dBm
14.5dBm
–50
–60
–70
–80
–90
3.0
2.5
2.0
1.5
1.0
–100
0.5
0
2
4
6
8
10
12
14
16
18
20
FREQUENCY (kHz)
0
15173-323
–120
–6
4
6
TA = 25°C
VDD = 3.3V
28
0.6
24
0.2
0
–0.2
1.0
DIGITAL CONTROL
tON/tOFF TEST SIGNAL
0.5
–0.5
0
10
20
30
TIME (µs)
16
12
–0.4
8
–0.6
0
20
–0.8
4
–1.0
0
40
Figure 25. Digital Control Signal and Test Signal vs. Time (VDD = 3.3 V)
0
4
8
12
16
PIN (dBm)
20
24
28
32
15173-331
1.5
POUT (dBm)
2.0
TEST SIGNAL (V)
0.4
15173-014
DIGITAL CONTROL SIGNAL (V)
2.5
2
32
0.8
TA = 25°C
VDD = 3.3V
0
Figure 26. Switch Capacitance vs. Signal Bias Voltage
1.0
3.0
–2
SIGNAL BIAS VOLTAGE (V)
Figure 24. THD + N vs. Frequency (VDD = 3.3 V, RLOAD = 300 Ω, TA = 25°C, Signal
Source Impedance = 20 Ω
3.5
–4
15173-419
–110
Figure 27. Output Power (POUT) vs. Input Power (PIN) (VDD = 3.3 V, Signal
Frequency = 4 GHz)
Rev. E | Page 15 of 33
ADGM1004
Data Sheet
–120
0
OSCILLATOR FEEDTHROUGH (dB)
–0.5
–1.5
–2.0
–2.5
–3.0
–3.5
–4.0
VDD = 3.3V
TA = 25°C
FREQUENCY = 4GHz
–5.0
0
4
8
12
16
20
24
28
32
INPUT POWER (dBm)
OSCILLATOR FEEDTHROUGH (dB)
–130
–132
0
–124
–126
–128
–130
–132
10.21
10.23
10.25
10.27
15173-334
–134
FREQUENCY (MHz)
20
30
40
50
60
70
80
90
100
Figure 30. Oscillator Feedthrough vs. Frequency, Wide Bandwidth
(VDD = 3.3 V)
TA = 25°C
VDD = 3.3V
–122
10
FREQUENCY (MHz)
–120
10.19
–128
–136
Figure 28. Insertion Loss vs. Input Power
–136
10.17
–126
–134
15173-421
–4.5
–124
Figure 29. Oscillator Feedthrough vs. Frequency, Zoomed in at 10.2 MHz
(VDD = 3.3 V)
Rev. E | Page 16 of 33
15173-335
INSERTION LOSS (dB)
–1.0
NORMAL OPERATING MODE
INTERNAL OSCILLATOR DISABLED
TA = 25°C
VDD = 3.3V
–122
Data Sheet
ADGM1004
TEST CIRCUITS
The test circuits shown in Figure 31 to Figure 42 are applicable to all channels. Additional pins are omitted for clarity and VS is the source
voltage.
VDD
VDD
0.1µF
0.1µF
VOUT
50Ω
RL
50Ω
VDD
RF1
RF1
50Ω
NETWORK
ANALYZER
RFC
RFC
RF2
50Ω
IN2
50Ω
IN2
VS
IN1
VIN2
IN1
VIN1
50Ω
50Ω
RF4
RF4
GND
IN3
GND
GND
VIN3
VIN3
Figure 31. Insertion Loss and Return Loss
Figure 33. Isolation (RF2 to RFC On, RF1 to RFC Off)
VDD
VDD
0.1µF
0.1µF
50Ω
NETWORK
ANALYZER
VS
VDD
VDD
RF1
RF1
VOUT
50Ω
RL
50Ω
RFC
RFC
50Ω
RF2
50Ω
IN2
VIN2
GND
15173-116
VIN4
IN3
15173-015
VIN4
50Ω
IN4
50Ω
IN4
NETWORK
ANALYZER
RF3
RF3
VIN1
VOUT
RL
50Ω
RF2
VIN2
VS
VDD
RF2
NETWORK
ANALYZER
VIN2
IN1
RF3
RF3
VIN1
VOUT
RL
50Ω
IN2
IN1
VS
VIN1
50Ω
50Ω
RF4
50Ω
IN4
VIN4
IN3
IN3
GND
GND
GND
VIN3
15173-016
VIN4
50Ω
IN4
GND
VIN3
Figure 34. Crosstalk
Figure 32. Isolation (All Switches Off)
Rev. E | Page 17 of 33
15173-017
RF4
ADGM1004
Data Sheet
VDD
0.1µF
VDD
RF1
INTERNAL 50Ω
TERMINATION
NC
RFC
OSCILLOSCOPE
RF2
IN2
VIN2
1MΩ
IN1
VDD
0.1µF
RF3
VIN1
NC
VDD
RFC
RF4
IN4
VS
RL
50Ω
INx
IN3
GND
GND
tON
VDD
VDD
0.1µF
VDD
VDD
RF1
RF1
50Ω
RF2 COMBINER
NETWORK
50Ω
RFC
RFC
IN2
RF
AMPLIFIER
50Ω
RF
SOURCE
RF
SOURCE
INPUT
RF2
RF
SOURCE
IN2
VIN2
IN1
IN1
RF3
RF3
VIN1
50Ω
50Ω
RF4
RF4
50Ω
IN4
IN3
VIN4
GND
VIN3
Figure 36. IP2 and IP3
IN3
GND GND
15173-019
GND
50Ω
IN4
VIN3
15173-021
VIN1
VIN4
tOFF
Figure 37. Switch Timing, tON and tOFF (All RFx Terminals Connected to
50 Ω Termination)
0.1µF
VIN2
10%
GND
Figure 35. Video Feedthrough
SPECTRUM
ANALYZER
50%
90%
VOUT
GND
15173-018
VIN3
50%
VINx
15173-020
VIN4
VOUT
RFx
NC
Figure 38. Hot Switching Evaluation Setup, 2 GHz RF Source, 50% Duty Cycle,
5 kHz Switching Actuation Speed
Rev. E | Page 18 of 33
Data Sheet
ADGM1004
VDD
0.1µF
VDD
RF1
50Ω
SPECTRUM
ANALYZER
RFC
RF2
IN2
V
VDD
IN1
VIN2
0.1µF
RF
SOURCE
RF3
VIN1
50Ω
VDD
RFC
RFx
RF4
50Ω
IN4
INx
IN3
GND
VINx
GND
15173-022
VIN4
GND
15173-227
GND
VIN3
Figure 41. Second and Third Harmonics, RF Power
Figure 39. On Resistance
VDD
VDD
0.1µF
0.1µF
VDD
VDD
RF1
RF1
A
–6V
6V
RFC
NC
A
RFC
RF2
RF2
A
–6V
A
VIN2
IN2
6V
IN2
VIN2
IN1
RF3
VIN1
IN1
RF3
VIN1
A
–6V
6V
RF4
RF4
A
VIN4
IN4
6V
IN4
VIN4
IN3
GND
GND
NC = NO CONNECT
IN3
VIN3
15173-328
VIN3
–6V
GND
GND
NC = NO CONNECT
Figure 40. Off Leakage
Figure 42. On Leakage
Rev. E | Page 19 of 33
15173-329
–6V
ADGM1004
Data Sheet
TERMINOLOGY
Insertion Loss
Insertion loss is the amount of signal attenuation between the
input and output ports of the switch when the switch is in the
on state. Expressed in decibels, ensure that insertion loss is as
small as possible for maximum power transfer.
Second-Order Intermodulation Intercept (IP2)
IP2 is the intersection point of the fundamental POUT vs. PIN
extrapolated line and the second-order intermodulation products
extrapolated line of a two-tone test. IP2 is a figure of merit that
characterizes the switch linearity.
An example calculation of insertion loss based on the setup in
Figure 31 is as follows:
Second Distortion Harmonic (HD2)
HD2 is the amplitude of the second distortion harmonic,
where, for a signal whose fundamental frequency is f, the
second distortion harmonic has a frequency of 2 f. This
measurement is a single-tone test expressed with reference to
the carrier signal (dBc).
Insertion Loss (dB) = −20log10|SRF2RFC|
where SRF2RFC is the transmission coefficient measured from RF2
to RFC with RF2 in the on position. All unused switches are in
the off position and terminated in a purely resistive load of 50 Ω.
Isolation
Isolation is the amount of signal attenuation between the input
and output ports of the switch when the switch is in the off
state. Expressed in decibels, ensure that isolation is as large as
possible.
An example calculation of isolation based on the setup in Figure 32
is as follows:
Isolation (dB) = −20log10|SRFCRF1|
where SRFCRF1 is the transmission coefficient measured from RFC
to RF1 with RF1 in the off position. All unused switches are in
the off position and terminated in a purely resistive load of 50 Ω.
Crosstalk
Crosstalk is a measure of unwanted signals coupled through
from one channel to another because of parasitic capacitance.
An example calculation of crosstalk based on the setup in
Figure 34 is as follows:
Crosstalk (dB) = −20log10|SRF1RF2|
where SRF1RF2 is the transmission coefficient measured from RF1
to RF2 with RF1 in the off position and RF2 in the on position.
All unused switches are in the off position and terminated in a
purely resistive load of 50 Ω.
Return Loss
Return Loss is the magnitude of the reflection coefficient
expressed in decibels, and the amount of reflected signal
relative to the incident signal.
Third Distortion Harmonic (HD3)
HD3 is the amplitude of the third distortion harmonic, where, for a
signal whose fundamental frequency is f, the third distortion
harmonic has a frequency of 3 f. This measurement is a single
tone test expressed with reference to the carrier signal (dBc).
On Switching Time (tON)
tON is the time it takes for the switch to turn on. tON is measured
from 50% of the control signal (INx) to 90% of the on level. No
power was applied through the switch during this test (cold
switched). The switch was terminated into a 50 Ω load.
Off Switching Time (tOFF)
tOFF is the time it takes for the switch to turn off. tOFF is
measured from 50% of the control signal (INx) to 10% of the on
level. No power was applied through the switch during this test
(cold switched). The switch was terminated into a 50 Ω load.
Actuation Frequency
The actuation frequency refers to the speed at which the
ADGM1004 can be switched on and off. The actuation
frequency is dependent on both the settling times and the on
and off switching times.
Power-Up Time
The power-up time is a measure of the time required for the
device to power up and start to pass 90% of an RF input signal
after the VDD pin reaches 95%.
Video Feedthrough
Video feedthrough is a measure of the spurious signals present
at the RFx ports of the switch when the control voltage is switched
from high to low or from low to high without an RF signal present.
An example calculation of return loss based on the setup in
Figure 31 is as follows:
Internal Oscillator Frequency
The internal oscillator frequency is the value of the on-board
oscillator that drives the gate control chip of the ADGM1004.
Return Loss (dB) = −20log10|S11|
where S11 is the reflection coefficient of the port under test.
Third-Order Intermodulation Intercept (IP3)
IP3 is the intersection point of the fundamental POUT vs. PIN
extrapolated line and the third-order intermodulation products
extrapolated line of a two-tone test. IP3 is a figure of merit that
characterizes the switch linearity.
Internal Oscillator Feedthrough
The internal oscillator feedthrough is the amount of internal
oscillator signal that feeds through to the RFx and RFC pins of
the switch. This signal appears as a noise spur on the RFx and
RFC pins of the switch at the frequency the oscillator is
operating at and the harmonics thereof.
Rev. E | Page 20 of 33
Data Sheet
ADGM1004
On Resistance (RON)
RON is the resistance of a switch in the closed/on state measured
between the RFx and RFC package pins. Measure resistance in
4-wire mode to null out any cabling or PCB series resistances.
On Resistance Drift
On resistance drift is the change in the RON of the switch over
the specified criteria in Table 1.
Continuously On Lifetime
The continuously on lifetime parameter measures how long the
switch is left in a continuously on state. If the switch is left in
the on position for an extended period, this parameter affects
the turn off mechanism of the device.
Actuation Lifetime
Actuation lifetime is the number of consecutive open, close, and
open cycles that the device can complete without the RON
exceeding a specified limit and no occurrence of failures to
open (FTO) or failures to close (FTC).
Cold Switching
Cold switching operates the switch in a mode so that no voltage
differential exists between the source and the drain when the
switch is closed and/or no current is flowing from the source to
the drain when the switch opens. All switches have longer lives
when cold switched.
Hot Switching
Hot switching is operating the switch in a mode where a voltage
differential exists between the source and the drain when the
switch is closed and/or current is flowing from RFx to RFC
when the switch opens. Hot switching results in a reduced switch
life, depending on the magnitude of the open circuit voltage
between the source and the drain.
Input High Voltage (VINH)
VINH is the minimum input voltage for Logic 1.
Input Low Voltage (VINL)
VINL is the maximum input voltage for Logic 0.
Input Current (IINL, IINH)
IINL and IINH are the low and high input currents of the digital
inputs.
Low Power Mode Current (IDD EXT VCP)
IDD EXT VCP is the amount of supply current used by the gate driver
circuity when the internal oscillator and the charge pump
circuitry are disabled by setting the EXTD_EN pin high.
External Drive Current (ICP EXT VCP)
ICP EXT VCP is the amount of current used by the ADGM1004
from the external 80 V power supply when the internal
oscillator and the charge pump circuitry are turned off by
setting EXTD_EN pin high.
Rev. E | Page 21 of 33
ADGM1004
Data Sheet
THEORY OF OPERATION
The ADGM1004 is a wideband SP4T switch fabricated using
Analog Devices MEMS switch technology. This technology
enables high power, low loss, low distortion GHz switches for
use in demanding RF applications.
The MEMS switch simultaneously brings together high
frequency RF performance and 0 Hz/dc precision performance.
This combination, coupled with superior reliability and a tiny
surface-mountable form factor, makes the MEMS switch an
ideal switching solution for all RF and precision signal
instrumentation needs.
Figure 43 shows a cross section of the switch with dimensions.
The switch is an electrostatically actuated cantilever beam
connected in a 3-terminal configuration. Functionally, the switch
is analogous to a field effect transistor (FET). The terminals can
be used as a source, gate, or drain.
SILICON CAP
CANTILEVER BEAM
SOURCE
DRAIN
METAL
CONTACT GAP
15173-126
GATE
SILICON
Figure 43. Cross Section of the MEMS Switch Design Showing the Cantilever
Switch Beam (Not to Scale)
When a dc actuation voltage is applied between the gate
electrode and the source (the switch beam), an electrostatic
force is generated, resulting in attracting the beam toward the
substrate. A separate on-board driver IC generates the 80 V
bias voltage used for actuation.
When the bias voltage between the gate and the source exceeds
the threshold voltage of the switch (VTH) the contacts on the
beam touch the drain, which completes the circuit between the
source and the drain and turns the switch on. When the bias
voltage is removed, that is, the 0 V on the gate electrode, the
beam acts as a spring generating a sufficient restoring force to
open the connection between the source and the drain, thus
breaking the circuit and turning the switch off.
The silicon cap covering the switch die is shown in Figure 43. This
cap hermetically seals the switch, which improves reliability.
The switch contacts do not suffer from dry switching or low power
switching lifetime degradation.
PARALLEL DIGITAL INTERFACE
The ADGM1004 is controlled via a parallel digital interface.
Standard complimentary metal-oxide semiconductor (CMOS)/
low voltage transistor to transistor logic (LVTTL) signals
applied through this interface control the actuation or release of
all ADGM1004 switch channels. Gate signals applied are
boosted to provide the required voltages required to actuate the
MEMS switch.
Setting the PIN/SPI pin low enables the parallel digital interface
in 4-wire SP4T mode. In parallel mode, Pin 1 to Pin 4 (IN1 to
IN4) control the switching functions of the ADGM1004. When
a Logic 1 is applied to one of these pins, the gate of the
corresponding switch is activated and the switch turns on.
Conversely, when a Logic 0 is applied to one of these pins, the
switch turns off. Note that it is possible to connect more than
one RFx input to RFC at a time. See Table 6 for the ADGM1004
truth table.
Table 6. Truth Table When in Parallel Digital Interface Mode
IN1
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
IN2
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
IN3
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
IN4
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
RF1 to RFC
Off
Off
Off
Off
Off
Off
Off
Off
On
On
On
On
On
On
On
On
RF2 to RFC
Off
Off
Off
Off
On
On
On
On
Off
Off
Off
Off
On
On
On
On
Rev. E | Page 22 of 33
RF3 to RFC
Off
Off
On
On
Off
Off
On
On
Off
Off
On
On
Off
Off
On
On
RF4 to RFC
Off
On
Off
On
Off
On
Off
On
Off
On
Off
On
Off
On
Off
On
Data Sheet
ADGM1004
SPI DIGITAL INTERFACE
Addressable Mode
The ADGM1004 can be controlled via a digital SPI when the
PIN/SPI pin is high. The SPI is compatible with SPI Mode 0
(clock polarity (CPOL) = 0, clock phase (CPHA) = 0) and Mode 3
(CPOL = 1, CPHA = 1) and it operates with SCLK frequencies up
to 10 MHz. When the SPI is active, the default mode is
addressable, in which, the device registers are accessed by a 16-bit
SPI command that is bound by the state of the CS pin. The
ADGM1004 can also operate in daisy-chain mode.
Addressable mode is the default mode for the ADGM1004
upon power-up. A single SPI frame in addressable mode is
bound by a CS falling edge and the succeeding CS rising edge.
The frame is comprised of 16 SCLK cycles. The timing diagram
for addressable mode is shown in Figure 44 for SPI mode 0.
The first SDI signal bit indicates if the SPI command is a read
or write command. The next seven bits determine the target
register address. The remaining eight bits provide the data to
the addressed register. The last eight bits are ignored during a
read command because the SDO pin propagates out the data
contained in the addressed register during these clock cycles.
The SPI interface pins of the ADGM1004 are CS, SCLK, SDI,
and SDO. Hold the CS pin low when using the SPI. The data on
the SDI pin is captured on the rising edge of SCLK, and data is
propagated out on the SDO pin on the falling edge of SCLK. The
SDO pin has a push pull output driver architecture. Therefore,
the ADGM1004 does not require pull-up resistors. The two
modes of SPI operation are: addressable and daisy-chain.
In Mode 0, during any SPI command, SDO sends out eight
alignment bits on the CS falling edge and the first seven SCLK
falling edges (in Mode 3, the first SCLK falling edge is ignored
as shown in Figure 45). The alignment bits observed at SDO are
0x25.
The target register address of an SPI command is determined on
the eighth SCLK rising edge. Data from this register propagates
out on the SDO pin from the 8th to the 15th SCLK falling edge
during SPI reads. A register write occurs on the 16th SCLK rising
edge during SPI writes.
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
R/W
A6
A5
A4
A3
A2
A1
A0
D7
D6
D5
D4
D3
D2
D1
D0
CS
SDI
0
SDO
0
1
0
0
1
0
1
D7
D6
D5
D4
D3
D2
D1
D0
15173-347
SCLK
Figure 44. Addressable Mode Timing Diagram (Mode 0)
CS
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
R/W
A6
A5
A4
A3
A2
A1
A0
D7
D6
D5
D4
D3
D2
D1
D0
SDI
SDO
0
0
1
0
0
1
0
1
D7
D6
D5
D4
Figure 45. Addressable Mode Timing Diagram (Mode 3)
Rev. E | Page 23 of 33
D3
D2
D1
D0
15173-351
SCLK
ADGM1004
Data Sheet
Daisy-Chain Mode
For the timing diagram of a typical daisy-chain SPI frame,
see Figure 48. When the CS pin goes high, Device 1 writes
Command 0, Bits[7:0], to the SWITCH_DATA register, Device 2
writes Command 1, Bits[7:0], to the switches, and so on. The
SPI block uses the last eight bits received through the SDI pin
to update the switches. After entering daisy-chain mode, the
first eight bits sent out by the SDO pin are 0x00. When CS goes
high, the internal shift register value does not reset back to 0.
The connection of several ADGM1004 devices in a daisy-chain
configuration is possible. All devices share the same CS and
SCLK lines while the SDO pin of one device forms a connection
to the SDI pin of the next device, creating a shift register. In
daisy-chain mode, the SDO signal is an 8-cycle delayed version
of the SDI signal (see Figure 47).
The ADGM1004 can only enter daisy-chain mode from
addressable mode by sending the 16-bit SPI command, 0x2500.
See Figure 47 for an example of this command. When the
ADGM1004 receives this command, the SDO pin of the devices
sends out the same command because the alignment bits at the
SDO pin are 0x25. This command allows multiple daisychained devices to enter daisy-chain mode in a single SPI
frame. A hardware reset is required to exit daisy-chain mode.
An SCLK rising edge reads in data on the SDI pin while data is
propagated out of the SDO pin on an SCLK falling edge. The
expected number of SCLK cycles are a multiple of eight before
the CS pin goes high. When this is not the case, the SPI
interface sends the last eight bits received to the
SWITCH_DATA register.
DEVICE 1
DEVICE 2
ADGM1004
ADGM1004
RF2
RF2
RFC
RFC
RF3
RF3
RF4
RF4
SDO
SPI
INTERFACE
SDO
SPI
INTERFACE
15173-449
SDI
CS
SCLK
Figure 46. Two SPI Controlled ADGM1004 Switches Connected in Daisy-Chain Configuration
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
0
0
1
0
0
1
0
1
0
0
0
0
0
0
0
0
CS
SDI
0
SDO
0
1
0
0
1
0
1
0
0
0
0
0
0
0
15173-348
SCLK
0
Figure 47. SPI Command to Enter Daisy-Chain Mode
SDI
COMMAND3[7:0]
COMMAND2[7:0]
COMMAND1[7:0]
COMMAND0[7:0]
DEVICE 1
SDO
8’h00
COMMAND3[7:0]
COMMAND2[7:0]
COMMAND1[7:0]
DEVICE 2
SDO2
8’h00
8’h00
COMMAND3[7:0]
COMMAND2[7:0]
DEVICE 3
SDO3
8’h00
8’h00
8’h00
COMMAND3[7:0]
DEVICE 4
NOTES
1. SDO2 AND SDO3 ARE THE OUTPUT COMMANDS FROM DEVICE 2 AND DEVICE 3, RESPECTIVELY.
Figure 48. Example of SPI Frame with Three ADGM1004 Switches Connected in Daisy-Chain Mode
Rev. E | Page 24 of 33
15173-349
CS
Data Sheet
ADGM1004
Hardware Reset
The digital section of the ADGM1004 goes through an
initialization phase during VDD power-up. To hardware reset the
device, power cycle the VDD input. After power-up or a hardware
reset, ensure that there is a minimum of 10 µs from the time of
power-up or reset before any SPI command is issued. Ensure that
VDD does not drop out during the 10 µs initialization phase because
VDD dropout can result in incorrect operation of the ADGM1004.
Internal Error Status
When an internal error is detected in the device, the internal
error is flagged by the INTERNAL_ERROR bits (Bits[7:6]) of
the SWITCH_DATA register (Register 0x20), as shown in
Table 9. An internal error results from an error in the
configuration of the device at power up.
INTERNAL OSCILLATOR FEEDTHROUGH
The ADGM1004 has an internal oscillator running at a nominal
10 MHz. This oscillator drives the charge pump circuitry that
provides the actuation voltage for each switch gate electrode.
Although this oscillator is low power, the 10 MHz signal is
coupled to the switch and is considered a noise spur on the
switch channels. The magnitude of this feedthrough noise spur
is specified in Table 1 and is typically −123 dBm or
−146 dBm/Hz when one switch is on. When all four switches are
simultaneously on, the feedthrough goes up to −120 dBm. VDD
level and temperature changes affect the frequency of the noise
spur. For the maximum and minimum frequency range over
temperature and voltage supply range, see Table 1.
INTERNAL OSCILLATOR FEEDTHROUGH
MITIGATION
In normal operation, the 80 V actuation voltage is supplied by
the driver IC. Setting the EXTD_EN pin low enables the built in
10 MHz oscillator. This setting enables the charge pump circuitry
to generate the 80 V required for MEMS switch actuation. The
internal oscillator is a source of noise that couples through to
the RF ports. The magnitude of this feedthrough noise spur is
specified in Table 1 and is typically −123 dBm or −146 dBm/Hz
when one switch is on. To eliminate the internal oscillator
feedthrough, set the EXTD_EN pin high to disable the internal
oscillator and charge pump circuitry. When the internal oscillator
and charge pump circuitry is disabled, the VCP pin must be
driven with 80 V dc (VCPEXT) from an external voltage supply
required for MEMS switch actuation, as shown in Table 5. The
switch can still be controlled via the digital logic interface pins.
LOW POWER MODE
Setting the EXTD_EN pin high shuts down the internal
oscillator. The ADGM1004 enters a low power quiescent state,
drawing only 50 µA maximum supply current.
Rev. E | Page 25 of 33
ADGM1004
Data Sheet
TYPICAL OPERATING CIRCUIT
to disable the internal oscillator and eliminate all oscillator
feedthrough. The switches can then be controlled normally via
the logic control interface, IN1 to IN4.
Figure 49 shows the typical operating circuit for the ADGM1004
as used in the EVAL-ADGM1004SDZ evaluation board. A 47 pF
(100 V rated) external capacitor (CCP) is required on the VCP pin.
This capacitor is a holding capacitor for the 80 V dc gate drive
voltage.
To avoid any floating nodes, connect a 10 MΩ shunt resistor to
GND on all RFx pins (RF1 to RF4, and RFC), as shown in
Figure 49. See the Floating Node section for more information.
An example of 10 MΩ resistor that can be used successfully
with the MEMS switch is Multicomp MCRE000262. These
resistors are tested with the switch and have a very small
(negligible) impact on the RF performance of the MEMS
switch.
In the circuit shown in Figure 49, VDD is connected to 3.3 V. EP1
connects to EP2 internally. Typically, one large GND pad on the
PCB is used to short together EP1 and EP2. Figure 49 shows the
ADGM1004 configured to use the internal oscillator as the
reference clock to the driver IC control circuit. Alternatively, set
the EXTD_EN pin high and apply 80 V dc directly to the VCP pin
3.3V
0.1µF
RF2 IN
RF1 IN
10MΩ*
1 IN1
IN2
2 IN2
24
23
22
21
20
19
18
VDD
GND
GND
RF1
GND
RF2
GND 17
GND 16
ADGM1004
RFOUT
RFC 15
IN3
3 IN3
IN4
4 IN4
GND 14
5 GND
GND 13
GND
EXTD_EN
GND
GND
RF4
GND
RF3
TOP VIEW
6
7
8
9
10
11
12
10MΩ*
RF4 IN
10MΩ*
10MΩ*
RF3 IN
*10MΩ RESISTORS ARE REQUIRED TO AVOID ANY FLOATING NODES. FOR MORE INFORMATION,
REFER TO THE FLOATING NODES SECTION.
Figure 49. Typical Operating Circuit
Rev. E | Page 26 of 33
15173-350
IN1
10MΩ*
VCP
47pF
Data Sheet
ADGM1004
APPLICATIONS INFORMATION
POWER SUPPLY RAILS
It is recommended that a 0.1 µF decoupling capacitor is added
to the power supply port of the ADGM1004.
The ADGM1004 can operate with unipolar supplies between
3.0 V and 3.6 V.
The device is fully specified at a 3.3 V analog supply voltage range.
The ADGM1004 MEMS switch with low flat insertion loss, wide
RF bandwidth, and high reliability is suited for use as a switchable
RF attenuator. The ADGM1004, as an SP4T switch, also brings
added flexibility. Figure 51 shows an example attenuation
network configuration using two ADGM1004 switches and
three different attenuators. The fourth channel of the switches
is used as a nonattenuated route in Figure 51.
POWER SUPPLY RECOMMENDATIONS
15dB
Analog Devices has a wide range of power management
products to meet the requirements of most high performance
signal chains.
10dB
An example of a unipolar power solution for the ADGM1004 is
shown in Figure 50. The ADP7142 is a low dropout linear
regulator that operates from 2.7 V to 40 V and is ideal for
regulation of high performance analog and mixed signal
circuits operating from 39 V down to 1.2 V rails. The ADP7142
has 11 µV rms output noise independent of the output voltage.
The ADP7142 can be used to power the supply rail for the
ADGM1004, a microcontroller, and/or other devices in the
signal chain.
3.3V
LDO
ADGM1004
ADGM1004
5dB
Figure 51. Switching RF Attenuators Using Two ADGM1004 MEMS Switches
RECONFIGURABLE RF FILTER
Figure 50. Unipolar Power Solution
If a better noise performance at the power supply is required,
the ADP7142 can be replaced by the LT1962 or the LT3045-1.
Table 7. Recommended Power Management Devices
Product
ADP7142
LT1962
LT3045-1
I/O
ADGM1004
15173-127
ADP7142
15173-050
5V
INPUT
I/O
Description
40 V, 200 mA, low noise, CMOS LDO linear regulator
300 mA, low noise, micropower, LDO regulator
20 V, 500 mA, ultralow noise, ultrahigh PSRR linear
regulator with VIOC control
SWITCHABLE RF ATTENUATOR
RF attenuator networks are commonly used in RF instrumentation
equipment, such as vector network analyzers, spectrum analyzers,
and signal generators. Routing RF signals through an attenuator
can enable the equipment to accept higher power signals and,
therefore, increase the dynamic range of the instrument. In
RF attenuation applications like the vector network analyzers,
spectrum analyzers, and signal generators, maintaining the
bandwidth of the signal after the signal passes through the
network is critical. Any degradation of the signal reduces the
performance of the equipment. Therefore, the RF characteristics
of the switches used for routing are an integral part of the quality
of an attenuator network.
A reconfigurable RF filter is advantageous in many RF frontend applications. A reconfigurable RF filter provides more saved
space. As space becomes more constrained in applications, the
option to have an economical reconfigurable RF filter instead of
individual frequency dependent filters is preferred.
The ADGM1004 low flat insertion loss, wide RF bandwidth,
low parasitic, low capacitance, and high linearity are required
to turn on the lump components (capacitor and inductor),
which make the MEMS switch suited for reconfigurable filter
application.
In applications such as wireless communications or mobile radios,
the number of bands and/or modes constantly increases. A
reconfigurable RF filter allows more bands and/or modes to be
covered using the same components.
Rev. E | Page 27 of 33
ADGM1004
Data Sheet
and center frequency, allowing the filter to dynamically configure
to operate in the UHF bands or very high frequency (VHF)
bands while preserving the 50 Ω match on the input and output
ports. The low RON value and wide bandwidth of the MEMS
switch makes the switch an ideal choice for this application. The
low RON reduces the negative effect a series resistance has on the
quality factor of the shunt inductor. The large bandwidth enables
higher frequency band-pass filters.
The function of the switches includes or omits a shunt inductor
from the circuit. Changing the shunt inductor value affects the
bandwidth and center frequency of the filter. Using inductance
values from 15 nH to 30 nH significantly alters the bandwidth
22nH
INPUT
50Ω
13pF
15nH
18nH
24nH
OUTPUT
50Ω
13pF
30nH
30nH
24nH
18nH
15nH
GND
Figure 52. Reconfigurable Band-Pass Filter Achieved Using Two ADGM1004 MEMS Switches
Rev. E | Page 28 of 33
15173-128
Figure 52 shows an example of a reconfigurable band-pass filter.
The topology shown is of a generalized, two section, inductively
coupled, single-ended band-pass filter, nominally centered on a
400 MHz ultrahigh frequency (UHF) band. The MEMS switches
are positioned in series with each shunt inductor.
Data Sheet
ADGM1004
CRITICAL OPERATIONAL REQUIREMENTS
SYSTEM ERROR CONSIDERATIONS DUE TO ONRESISTANCE DRIFT
ON RESISTANCE SHIFT DUE TO TEMPERATURE
SHOCK POST ACTUATIONS
The RON performance of the ADGM1004 is affected by part to
part variation, channel to channel variation, cycle actuations,
settling time post turn on, bias voltage, and temperature changes
(see Figure 54 to Figure 12).
When the switch is actuated multiples times at one temperature,
and if there is a sudden shift in this temperature, a large shift is
shown in the switch RON. Figure 54 shows the absolute RON
performance of the population of devices over actuation
lifetime. Figure 54 shows how the absolute RON of the device
drifts over actuation lifetime. During this measurement, the
switch is actuated at 85°C and the switch RON is measured at
25°C. Actuating the switch at 85°C and measuring RON at 25°C
is the most severe condition for the ADGM1004 RON drift over
actuations.
In a 50 Ω system, the on-resistance drift over switch actuations
(∆RON) can introduce system inaccuracy. Figure 53 shows the
ADGM1004 connected with the load in a 50 Ω system, where
RS is the source impedance. TO calculate the system error
caused by the ADGM1004 on-resistance drift, use the following
equation:
100
System Error (%) = ΔR/RLOAD
90
where:
ΔR is the ADGM1004 on-resistance drift.
RLOAD is the load impedance.
The ADGM1004 on-resistance drift also affects insertion loss,
which must be considered when using the device. To calculate
the on-resistance impact on insertion loss, use the following
equation:
60
50
40
20
10
ΔR
0
Table 8. System Error and Insertion Loss Error Due to
ADGM1004 RON Drift
System
Error (%)
9.5
10
1
2
3
4
5
6
Figure 54. Population Percentage vs. Absolute RON, Switch Actuated at 85°C
and RON measured at 25°C
Figure 53. 50 Ω System Representation Where the ADGM1004 is Connected
with the Load
On-Resistance Drift
4.75
5
0
ASOLUTE RON (Ω)
15173-426
RLOAD
50Ω
VS
1 ACTUATION
167 MILLION ACTUATIONS
500 MILLION ACTUATIONS
1 BILLION ACTUATIONS
SWITCH ACTUATED AT 85°C
RON MEASURED AT 25°C
VDD = 3.3V
30
Insertion Loss = 10log(1 + (ΔR/RLOAD))
RS
50Ω
70
15173-506
POPULATION (%)
80
Insertion Loss Error (dB)
0.39
0.41
The ADGM1004 has no internal impedance to ground, and
charges can develop on the switch terminals leading to unreliable
switch behavior. To mitigate this behavior, provide a discharge
path to all switch nodes. Figure 55 to Figure 58 show examples
of cases to avoid where floating nodes can occur when using the
switch. Conditions to avoid include the following:
•
•
•
Leaving the RFx pins open circuit (see Figure 55).
Connecting a series capacitor directly to the switch (see
Figure 56).
Connecting the RFx pin of two switches together directly
or connecting the RFC pin to the RFx pin (see Figure 57
and Figure 58).
RFx
RFC
OPEN CIRCUIT
FLOATING
15173-024
The on-resistance drift over time specification is −0.25 Ω
measured after 100 ms, as shown in Figure 8 to Figure 10.
According to the plots, the on-resistance drift over time is
−0.12 Ω after 100 ms. The on-resistance of the ADGM1004
typically drifts by −0.05 Ω per decade. For example, after 100 ms,
the on-resistance drifts −0.12 Ω, after 1 sec it drifts −0.17 Ω, and
after 10 sec it drifts −0.22 Ω. Therefore, after 1,000 sec, the
on-resistance is expected to drift by −0.32 Ω.
FLOATING NODE
Figure 55. RFx Pins Left Open Circuit
Rev. E | Page 29 of 33
ADGM1004
Data Sheet
Avoid connecting shunt capacitors directly to the switch. A
capacitor can store a charge and potentially lead to hot switching
events when the switch opens or closes if there are no alternative
discharge paths. These events affect the cycle lifetime of the switch.
RFC
15173-025
FLOATING
CUMULATIVE ON SWITCH LIFETIME
Figure 56. Series Capacitor Directly Connected to MEMS Switch
RFx
RFC
Leaving the switch in an on state for a long period affects the
lifetime of the switch because of mechanical degradation
effects. These effects can result in the switch failing to turn off.
Figure 62 shows a failure rate at 50°C where the mean time to
failure is 7.2 years (2628 days), resulting in 50% of the sample
lot failing at this point.
15173-026
FLOATING
Figure 57. RFx Pins of Two MEMS Switches Directly Connected
RFx
RFC
RFC
RFx
15173-027
FLOATING
Figure 58. RFC Connected to RFx
Provide a discharge path to the switch nodes to avoid floating
nodes. In a typical application, a 50 Ω termination connected to
the switch provides this path. Driving switch nodes with a
device of adequate impedance (
