FEATURES
FUNCTIONAL BLOCK DIAGRAM
SPI with error detection
Includes CRC, invalid read and write address, and SCLK
count error detection
Supports burst mode and daisy-chain mode
Industry-standard SPI Mode 0 and Mode 3 interface
compatible
Integrated passive components
Route through of digital signals and supplies
Guaranteed break-before-make switching allowing external
wiring of switches to deliver multiplexer configurations
1.5 Ω typical on resistance at 25°C (±15 V dual supply)
0.3 Ω typical on resistance flatness at 25°C (±15 V dual supply)
0.1 Ω typical on resistance match between channels at 25°C
(±15 V dual supply)
VSS to VDD analog signal range
Fully specified at ±15 V, ±5 V, and +12 V
1.8 V logic compatibility with 2.7 V ≤ VL ≤ 3.3 V (excludes SPI
readback to a 1.8 V device)
4 mm × 5 mm, 30-terminal LGA
APPLICATIONS
Automated test equipment
Data acquisition systems
Sample-and-hold systems
Audio and video signal routing
Communications systems
Relay replacement
VDD
ADGS1414D
S1
D1
S2
D2
S3
D3
S4
D4
S5
D5
S6
D6
S7
D7
S8
VL
SPI
INTERFACE
SCLK SDI
CS
RESET/VL
D8
SDO
Figure 1.
The ADGS1414D is suited to high density switching
applications, such as large switching matrices and fanout
applications.
Each switch conducts equally well in both directions when on,
and each switch has an input signal range that extends to the
supplies. In the off condition, signal levels up to the supplies
are blocked.
Multifunction pin names may be referenced by their relevant
function only.
GENERAL DESCRIPTION
The ADGS1414D contains eight independent SPST switches. A
serial peripheral interface (SPI) controls the switches. The SPI
has robust error detection features, such as cyclic redundancy
check (CRC) error detection, invalid read and write address
detection, and SCLK count error detection.
It is possible to daisy-chain multiple ADGS1414D devices
together. Daisy-chain mode enables the configuration of
multiple devices with a minimal amount of digital lines. The
route of digital signals and supplies through the ADGS1414D
allows for a further increase in channel density. Integrated
passive components eliminate the need for external passive
components.
PRODUCT HIGHLIGHTS
1.
2.
3.
4.
5.
6.
7.
Rev. 0
VSS
23895-001
Data Sheet
SPI, 1.5 Ω RON, ±15 V/±5 V/+12 V, High
Density Octal SPST Switch
ADGS1414D
The SPI removes the need for parallel conversion and logic
traces and reduces the general-purpose input and output
(GPIO) channel count.
Daisy-chain mode removes additional logic traces when
multiple devices are used.
Route through of digital signals and supplies eases routing
and allows for an increase in channel density.
Integrated passive components eliminate the need for
external passive components.
CRC error detection, invalid read and write address
detection, and SCLK count error detection ensure a robust
digital interface.
CRC, invalid read and write address, and SCLK error
detection capabilities allow for the use of the ADGS1414D
in safety critical systems.
Minimum distortion.
Document Feedback
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©2020 Analog Devices, Inc. All rights reserved.
Technical Support
www.analog.com
ADGS1414D
Data Sheet
TABLE OF CONTENTS
Features .............................................................................................. 1
Clearing the Error Flags Register ............................................. 21
Applications ...................................................................................... 1
Burst Mode .................................................................................. 21
General Description ......................................................................... 1
Software Reset ............................................................................. 21
Functional Block Diagram .............................................................. 1
Daisy-Chain Mode ..................................................................... 21
Product Highlights ........................................................................... 1
Power-On Reset.......................................................................... 22
Revision History ............................................................................... 2
Applications Information ............................................................. 23
Specifications .................................................................................... 3
System Channel Density ........................................................... 23
±15 V Dual Supply ....................................................................... 3
Break-Before-Make Switching ................................................. 24
±5 V Dual Supply ......................................................................... 5
Digital Input Buffers .................................................................. 24
12 V Single Supply ....................................................................... 7
Power Supply Rails..................................................................... 24
Continuous Current per Channel, Sx or Dx ............................ 9
Power Supply Recommendations ............................................ 24
Timing Characteristics ................................................................ 9
1.8 V Logic Compatibility ......................................................... 24
Absolute Maximum Ratings ......................................................... 11
Register Summary .......................................................................... 25
Thermal Resistance .................................................................... 11
Register Details ............................................................................... 26
Electrostatic Discharge (ESD) Ratings .................................... 11
Switch Data Register .................................................................. 26
ESD Caution................................................................................ 11
Error Configuration Register ................................................... 26
Pin Configuration and Function Descriptions .......................... 12
Error Flags Register.................................................................... 27
Typical Performance Characteristics ........................................... 13
Burst Enable Register ................................................................. 27
Test Circuits .................................................................................... 17
Software Reset Register ............................................................. 27
Terminology .................................................................................... 19
Outline Dimensions ....................................................................... 28
Theory of Operation ...................................................................... 20
Ordering Guide .......................................................................... 28
Address Mode ............................................................................. 20
Error Detection Features ........................................................... 20
REVISION HISTORY
6/2020—Revision 0: Initial Version
Rev. 0 | Page 2 of 28
Data Sheet
ADGS1414D
SPECIFICATIONS
±15 V DUAL SUPPLY
VDD = +15 V ± 10%, VSS = −15 V ± 10%, VL = 2.7 V to 5.5 V, and GND = 0 V, unless otherwise noted.
Table 1.
Parameter
ANALOG SWITCH
Analog Signal Range
On Resistance, RON
On-Resistance Match
Between Channels, ∆RON
On-Resistance Flatness,
RFLAT (ON)
LEAKAGE CURRENTS
Source Off Leakage, IS (Off)
Drain Off Leakage, ID (Off)
Channel On Leakage, ID (On),
IS (On)
+25°C
−40°C to +85°C
VDD to VSS
V
Ω typ
1.8
0.1
2.3
2.6
Ω max
Ω typ
0.18
0.3
0.19
0.21
Ω max
Ω typ
VS = ±10 V, IS = −10 mA
0.36
0.4
0.45
±0.03
±0.55
±0.03
±0.55
±0.15
±2
±2
±4
±2
±12.5
±12.5
nA max
nA typ
nA max
nA typ
VS = ±10 V, VD = 10 V, see Figure 32
VS = VD = ±10 V, see Figure 28
nA max
0.4
0.3
VL − 1.25 V
VL − 0.125 V
V max
V max
V min
V min
pF typ
Sink current, ISINK = 1 mA
ISINK = 100 µA
Source current, ISOURCE = 1 mA
ISOURCE = 100 µA
2
1.35
0.8
0.8
V min
V min
V max
V max
3.3 V < VL ≤ 5.5 V
2.7 V ≤ VL ≤ 3.3 V
3.3 V < VL ≤ 5.5 V
2.7 V ≤ VL ≤ 3.3 V
µA typ
Input voltage, VIN = ground voltage, VGND
or VL
4
0.001
4
µA max
pF typ
400
ns typ
475
160
190
VDD = +16.5 V, VSS = −16.5 V
VS = ±10 V, drain voltage, VD = 10 V, see
Figure 32
±30
±0.1
Off Time, tOFF
Ω max
nA typ
Low, VINL
Digital Input Capacitance,
CIN
DYNAMIC CHARACTERISTICS1
On Time, tON
Test Conditions/Comments
Source voltage, VS = ±10 V, source
current, IS = −10 mA, see Figure 29
VDD = +13.5 V, VSS = −13.5 V
VS = ±10 V, IS = −10 mA
High, VOH
Input Current
Low, IINL or High, IINH
Unit
1.5
DIGITAL OUTPUT
Output Voltage
Low, VOL
Digital Output Capacitance,
COUT
DIGITAL INPUTS
Input Voltage
High, VINH
−40°C to +125°C
480
485
210
225
Rev. 0 | Page 3 of 28
ns max
ns typ
ns max
Load resistance, RL = 300 Ω, load
capacitance, CL = 35 pF
VS = 10 V, see Figure 37
RL = 300 Ω, CL = 35 pF
VS = 10 V, see Figure 37
ADGS1414D
Parameter
Break-Before-Make Time
Delay, tD
Data Sheet
+25°C
215
−40°C to +85°C
−40°C to +125°C
Unit
ns typ
Test Conditions/Comments
RL = 300 Ω, CL = 35 pF
170
ns min
Source 1 voltage, VS1 = Source 2 voltage,
VS2 = 10 V, see Figure 36
VS = 0 V, source resistance, RS = 0 Ω, CL =
1 nF, see Figure 38
RL = 50 Ω, CL = 5 pF, frequency, f = 1 MHz,
see Figure 31
RL = 50 Ω, CL = 5 pF, f = 1 MHz, see
Figure 30
RL = 110 Ω, 15 V p-p, f = 20 Hz to 20 kHz,
see Figure 33
RL = 50 Ω, CL = 5 pF, see Figure 34
RL = 50 Ω, CL = 5 pF, f = 1 MHz, see
Figure 34
VS = 0 V, f = 1 MHz
VS = 0 V, f = 1 MHz
VS = 0 V, f = 1 MHz
VDD = +16.5 V, VSS = −16.5 V
All switches open
Charge Injection, QINJ
−20
pC typ
Off Isolation
−76
dB typ
Channel to Channel
Crosstalk
Total Harmonic Distortion +
Noise, THD + N
−3 dB Bandwidth
Insertion Loss
−75
dB typ
0.014
% typ
170
−0.2
MHz typ
dB typ
20
21
111
pF typ
pF typ
pF typ
Source Capacitance, CS (Off)
Drain Capacitance, CD (Off)
CD (On), CS (On)
POWER REQUIREMENTS
Positive Supply Current, IDD
0.04
4.0
480
800
480
800
Load Current, IL
Inactive
6.3
8.0
Inactive, SCLK = 1 MHz
SCLK = 50 MHz
Inactive, SDI = 1 MHz
SDI = 25 MHz
Active at 50 MHz
14
7
390
210
15
7.5
230
120
1.8
2.1
0.7
1.0
Negative Supply Current, ISS
0.04
VDD/VSS
1
4.0
±4.5/±16.5
Guaranteed by design. Not subject to production test.
Rev. 0 | Page 4 of 28
µA typ
µA max
µA typ
µA max
µA typ
µA max
µA typ
µA max
µA typ
µA typ
µA typ
µA typ
µA typ
µA typ
µA typ
µA typ
mA typ
mA max
mA typ
mA max
µA typ
µA max
V min/V max
All switches closed, VL = 5.5 V
All switches closed, VL = 2.7 V
Digital inputs = 0 V or VL
CS = VL and SDI = 0 V or VL, VL = 5 V
CS = VL and SDI = 0 V or VL, VL = 3 V
CS = VL and SDI = 0 V or VL, VL = 5 V
CS = VL and SDI = 0 V or VL, VL = 3 V
CS and SCLK = 0 V or VL, VL = 5 V
CS and SCLK = 0 V or VL, VL = 3 V
CS and SCLK = 0 V or VL, VL = 5 V
CS and SCLK = 0 V or VL, VL = 3 V
Digital inputs toggle between 0 V and VL,
VL = 5.5 V
Digital inputs toggle between 0 V and VL,
VL = 2.7 V
Digital inputs = 0 V or VL
GND = 0 V
Data Sheet
ADGS1414D
±5 V DUAL SUPPLY
VDD = +5 V ± 10%, VSS = −5 V ± 10%, VL = 2.7 V to 5.5 V, and GND = 0 V, unless otherwise noted.
Table 2.
Parameter
ANALOG SWITCH
Analog Signal Range
On Resistance, RON
On-Resistance Match Between
Channels, ∆RON
On-Resistance Flatness, RFLAT (ON)
+25°C
−40°C to +85°C
−40°C to +125°C
Unit
VDD to VSS
V
Ω typ
3.3
4.9
5.4
Ω max
Ω typ
0.35
0.9
1.1
0.43
0.45
VS = ±4.5 V, IS = −10 mA
1.24
1.31
Ω max
Ω typ
Ω max
nA typ
VDD = +5.5 V, VSS = −5.5 V
VS = ±4.5 V, VD = 4.5 V, see
Figure 32
±0.03
±0.55
±0.03
±2
Drain Off Leakage, ID (Off)
±0.55
±0.05
±1.0
±2
±12.5
±4
±30
DIGITAL OUTPUT
Output Voltage
Low, VOL
High, VOH
Digital Output Capacitance, COUT
DIGITAL INPUTS
Input Voltage
High, VINH
Digital Input Capacitance, CIN
DYNAMIC CHARACTERISTICS1
On Time, tON
±12.5
nA max
nA typ
nA max
nA typ
nA max
VS = VD = ±4.5 V, see Figure 28
V max
V max
V min
V min
pF typ
ISINK = 1 mA
ISINK = 100 µA
ISOURCE = 1 mA
ISOURCE = 100 µA
2
1.35
0.8
0.8
V min
V min
V max
V max
3.3 V < VL ≤ 5.5 V
2.7 V ≤ VL ≤ 3.3 V
3.3 V < VL ≤ 5.5 V
2.7 V ≤ VL ≤ 3.3 V
µA typ
µA max
pF typ
VIN = VGND or VL
±0.1
RL = 300 Ω, CL = 35 pF
VS = 3 V, see Figure 37
RL = 300 Ω, CL = 35 pF
VS = 3 V, see Figure 37
RL = 300 Ω, CL = 35 pF
VS1 = VS2 = 3 V, see Figure 36
VS = 0 V, RS = 0 Ω, CL = 1 nF, see
Figure 38
RL = 50 Ω, CL = 5 pF, f = 1 MHz,
see Figure 31
RL = 50 Ω, CL = 5 pF, f = 1 MHz,
see Figure 30
0.001
4
Break-Before-Make Time Delay, tD
510
645
280
365
245
Charge Injection, QINJ
10
ns typ
ns max
ns typ
ns max
ns typ
ns min
pC typ
Off Isolation
−76
dB typ
Channel to Channel Crosstalk
−75
dB typ
Off Time, tOFF
VS = ±4.5 V, VD = 4.5 V, see
Figure 32
0.4
0.3
VL − 1.25 V
VL − 0.125 V
4
Low, VINL
Input Current
Low, IINL or High, IINH
VS = ±4.5 V, IS = −10 mA, see
Figure 29
VDD = +4.5 V, VSS = −4.5 V
VS = ±4.5 V, IS = −10 mA
4
0.13
LEAKAGE CURRENTS
Source Off Leakage, IS (Off)
Channel On Leakage, ID (On), IS (On)
Test Conditions/Comments
680
710
400
435
200
Rev. 0 | Page 5 of 28
ADGS1414D
Parameter
Total Harmonic Distortion + Noise,
THD + N
−3 dB Bandwidth
Insertion Loss
Source Capacitance, CS (Off)
Drain Capacitance, CD (Off)
CD (On), CS (On)
POWER REQUIREMENTS
Positive Supply Current, IDD
Data Sheet
+25°C
0.03
−40°C to +85°C
−40°C to +125°C
130
MHz typ
−0.3
dB typ
30
31
116
pF typ
pF typ
pF typ
0.04
µA typ
4.0
28
60
Load Current, IL
Inactive
6.3
8.0
Inactive, SCLK = 1 MHz
SCLK = 50 MHz
Inactive, SDI = 1 MHz
SDI = 25 MHz
Active at 50 MHz
14
7
390
210
15
7.5
230
120
1.8
2.1
0.7
1.0
Negative Supply Current, ISS
0.04
VDD/VSS
1
Unit
% typ
4.0
±4.5/±16.5
Guaranteed by design. Not subject to production test.
Rev. 0 | Page 6 of 28
µA max
µA typ
µA max
µA typ
µA max
µA typ
µA typ
µA typ
µA typ
µA typ
µA typ
µA typ
µA typ
mA typ
mA max
mA typ
mA max
µA typ
µA max
V min/V max
Test Conditions/Comments
RL = 110 Ω, 5 V p-p, f = 20 Hz to
20 kHz, see Figure 33
RL = 50 Ω, CL = 5 pF, see
Figure 34
RL = 50 Ω, CL = 5 pF, f = 1 MHz,
see Figure 34
VS = 0 V, f = 1 MHz
VS = 0 V, f = 1 MHz
VS = 0 V, f = 1 MHz
VDD = +5.5 V, VSS = −5.5 V
Digital inputs = 0 V or VL, VL =
5.5 V
All switches closed, VL = 2.7 V
Digital inputs = 0 V or VL
CS = VL and SDI = 0 V or VL, VL = 5 V
CS = VL and SDI = 0 V or VL, VL = 3 V
CS = VL and SDI = 0 V or VL, VL = 5 V
CS = VL and SDI = 0 V or VL, VL = 3 V
CS and SCLK = 0 V or VL, VL = 5 V
CS and SCLK = 0 V or VL, VL = 3 V
CS and SCLK = 0 V or VL, VL = 5 V
CS and SCLK = 0 V or VL, VL = 3 V
Digital inputs toggle between
0 V and VL, VL = 5.5 V
Digital inputs toggle between
0 V and VL, VL = 2.7 V
Digital inputs = 0 V or VL
GND = 0 V
Data Sheet
ADGS1414D
12 V SINGLE SUPPLY
VDD = 12 V ± 10%, VSS = 0 V, VL = 2.7 V to 5.5 V, and GND = 0 V, unless otherwise noted.
Table 3.
Parameter
ANALOG SWITCH
Analog Signal Range
On Resistance, RON
On-Resistance Match
Between Channels, ∆RON
On-Resistance Flatness,
RFLAT (ON)
+25°C
−40°C to +85°C
4.3
4.8
Ω max
Ω typ
0.35
0.6
0.43
0.45
Ω max
Ω typ
VS = 0 V to 10 V, IS = −10 mA
1.1
1.2
±0.55
±0.02
±2
±0.55
±0.15
±2
±1.5
±4
High, VOH
Break-Before-Make Time
Delay, tD
±12.5
±12.5
nA max
nA typ
nA max
nA typ
VDD = 13.2 V, VSS = 0 V
VS = 1 V/10 V, VD = 10 V/1 V, see
Figure 32
VS = 1 V/10 V, VD = 10 V/1 V, see
Figure 32
VS = VD = 1 V/10 V, see Figure 28
nA max
0.4
0.3
VL − 1.25 V
VL − 0.125 V
V max
V max
V min
V min
pF typ
ISINK = 1 mA
ISINK = 100 µA
ISOURCE = 1 mA
ISOURCE = 100 µA
2
1.35
0.8
0.8
V min
V min
V max
V max
3.3 V < VL ≤ 5.5 V
2.7 V ≤ VL ≤ 3.3 V
3.3 V < VL ≤ 5.5 V
2.7 V ≤ VL ≤ 3.3 V
µA typ
µA max
pF typ
VIN = VGND or VL
±0.1
ns typ
ns max
ns typ
ns max
ns typ
RL = 300 Ω, CL = 35 pF
VS = 8 V, see Figure 37
RL = 300 Ω, CL = 35 pF
VS = 8 V, see Figure 37
RL = 300 Ω, CL = 35 pF
VS1 = VS2 = 8 V, see Figure 36
VS = 6 V, RS = 0 Ω, CL = 1 nF, see
Figure 38
RL = 50 Ω, CL = 5 pF, f = 1 MHz, see
Figure 31
0.001
4
470
570
170
215
280
Ω max
±30
4
Low, VINL
Off Time, tOFF
1.3
nA typ
DIGITAL OUTPUT
Output Voltage
Low, VOL
Digital Input Capacitance, CIN
DYNAMIC CHARACTERISTICS1
On Time, tON
V
Ω typ
3.5
0.13
Drain Off Leakage, ID (Off)
Input Current
Low, IINL or High, IINH
0 V to VDD
Test Conditions/Comments
VS = 0 V to 10 V, IS = −10 mA, see
Figure 29
VDD = 10.8 V, VSS = 0 V
VS = 0 V to 10 V, IS = −10 mA
±0.02
Digital Output Capacitance,
COUT
DIGITAL INPUTS
Input Voltage
High, VINH
Unit
2.8
LEAKAGE CURRENTS
Source Off Leakage, IS (Off)
Channel On Leakage, ID (On),
IS (On)
−40°C to +125°C
595
615
240
265
Charge Injection, QINJ
10
225
ns min
pC typ
Off Isolation
−76
dB typ
Rev. 0 | Page 7 of 28
ADGS1414D
Parameter
Channel to Channel Crosstalk
Total Harmonic Distortion +
Noise, THD + N
−3 dB Bandwidth
Insertion Loss
Source Capacitance, CS (Off)
Drain Capacitance, CD (Off)
CD (On), CS (On)
POWER REQUIREMENTS
Positive Supply Current, IDD
Data Sheet
+25°C
−75
−40°C to +85°C
−40°C to +125°C
0.06
% typ
130
−0.3
MHz typ
dB typ
27
28
116
pF typ
pF typ
pF typ
0.04
4.0
420
800
520
850
Load Current, IL
Inactive
6.3
8.0
Inactive, SCLK = 1 MHz
SCLK = 50 MHz
Inactive, SDI = 1 MHz
SDI = 25 MHz
Active at 50 MHz
14
7
390
210
15
7.5
230
120
1.8
2.1
0.7
VDD
1
Unit
dB typ
1.0
5/20
Guaranteed by design. Not subject to production test.
Rev. 0 | Page 8 of 28
µA typ
µA max
µA typ
µA max
µA typ
µA max
µA typ
µA max
µA typ
µA typ
µA typ
µA typ
µA typ
µA typ
µA typ
µA typ
mA typ
mA max
mA typ
mA max
V min/V max
Test Conditions/Comments
RL = 50 Ω, CL = 5 pF, f = 1 MHz, see
Figure 30
RL = 110 Ω, 6 V p-p, f = 20 Hz to 20 kHz,
see Figure 33
RL = 50 Ω, CL = 5 pF, see Figure 34
RL = 50 Ω, CL = 5 pF, f = 1 MHz, see
Figure 34
VS = 6 V, f = 1 MHz
VS = 6 V, f = 1 MHz
VS = 6 V, f = 1 MHz
VDD = 13.2 V
All switches open
All switches closed, VL = 5.5 V
All switches closed, VL = 2.7 V
Digital inputs = 0 V or VL
CS = VL and SDI = 0 V or VL, VL = 5 V
CS = VL and SDI = 0 V or VL, VL = 3 V
CS = VL and SDI = 0 V or VL, VL = 5 V
CS = VL and SDI = 0 V or VL, VL = 3 V
CS and SCLK = 0 V or VL, VL = 5 V
CS and SCLK = 0 V or VL, VL = 3 V
CS and SCLK = 0 V or VL, VL = 5 V
CS and SCLK = 0 V or VL, VL = 3 V
Digital inputs toggle between 0 V and
VL, VL = 5.5 V
Digital inputs toggle between 0 V and
VL, VL = 2.7 V
GND = 0 V, VSS = 0 V
Data Sheet
ADGS1414D
CONTINUOUS CURRENT PER CHANNEL, Sx OR Dx
Table 4. Eight Channels On
Parameter
CONTINUOUS CURRENT, Sx OR Dx1
VDD = +15 V, VSS = −15 V (θJA = 65.5°C/W)
VDD = +12 V, VSS = 0 V (θJA = 65.5°C/W)
VDD = +5 V, VSS = −5 V (θJA = 65.5°C/W)
1
25°C
85°C
125°C
Unit
273
221
206
156
133
126
80
72
70
mA maximum
mA maximum
mA maximum
25°C
85°C
125°C
Unit
490
399
373
225
200
192
87
84
83
mA maximum
mA maximum
mA maximum
Sx refers to the S1 to S8 pins, and Dx refers to the D1 to D8 pins.
Table 5. One Channel On
Parameter
CONTINUOUS CURRENT, Sx OR Dx1
VDD = +15 V, VSS = −15 V (θJA = 65.5°C/W)
VDD = +12 V, VSS = 0 V (θJA = 65.5°C/W)
VDD = +5 V, VSS = −5 V (θJA = 65.5°C/W)
1
Sx refers to the S1 to S8 pins, and Dx refers to the D1 to D8 pins.
TIMING CHARACTERISTICS
VL = 2.7 V to 5.5 V, GND = 0 V, and all specifications minimum temperature (TMIN) to maximum temperature (TMAX), unless otherwise
noted. Guaranteed by design and characterization, not production tested. See Figure 2 to Figure 4 for the timing diagrams.
Table 6.
Parameter
TIMING CHARACTERISTICS
t1
t2
t3
t4
t5
t6
t7
t8
t91
t10
t11
t12
t13
1
Limit
Unit
Test Conditions/Comments
20
8
8
10
6
8
10
20
30
30
20
8
8
ns min
ns min
ns min
ns min
ns min
ns min
ns min
ns max
ns max
ns max
ns min
ns min
ns min
SCLK period
SCLK high pulse width
SCLK low pulse width
CS falling edge to SCLK active edge
Data setup time
Data hold time
SCLK active edge to CS rising edge
CS falling edge to SDO data available
SCLK falling edge to SDO data available
CS rising edge to SDO returns to high
CS high time between SPI commands
CS falling edge to SCLK becomes stable
CS rising edge to SCLK becomes stable
Measured with a 20 pF load. t9 determines the maximum SCLK frequency when SDO is used.
Rev. 0 | Page 9 of 28
ADGS1414D
Data Sheet
Timing Diagrams
t1
SCLK
t4
t2
t3
t7
CS
t5
R/W
SDI
t6
A6
A5
D2
D1
D0
t10
t9
SDO
0
1
D2
D1
D0
23895-002
0
t8
Figure 2. Address Mode Timing Diagram
t1
SCLK
t2
t3
t4
t7
CS
SDI
D7
t6
D6
D0
INPUT BYTE FOR DEVICE N
D7
D6
D1
D0
INPUT BYTE FOR DEVICE N + 1
t9
0
t8
0
0
ZERO BYTE
D7
D6
D1
INPUT BYTE FOR DEVICE N
Figure 3. Daisy-Chain Timing Diagram
t11
CS
SCLK
t13
t12
23895-004
SDO
Figure 4. SCLK and CS Timing Relationship
Rev. 0 | Page 10 of 28
t10
D0
23895-003
t5
Data Sheet
ADGS1414D
ABSOLUTE MAXIMUM RATINGS
TA = 25°C, unless otherwise noted.
Stresses at or above those listed under Absolute Maximum
Ratings may cause permanent damage to the product. This is a
stress rating only; functional operation of the product at these
or any other conditions above those indicated in the
operational section of this specification is not implied.
Operation beyond the maximum operating conditions for
extended periods may affect product reliability.
Table 7.
Parameter
VDD to VSS
VDD to GND
VSS to GND
VL to GND
For VDD ≤ 5.5 V
For VDD > 5.5 V
SDO
Analog Inputs
1
Digital Inputs1
Peak Current, Sx or Dx2
Continuous Current, Sx or Dx2, 3
Temperature
Operating Range
Storage Range
Junction
Reflow Soldering Peak
Temperature, Pb Free
Rating
35 V
−0.3 V to +25 V
+0.3 V to −25 V
−0.3 V to VDD + 0.3 V
−0.3 V to +6 V
−0.3 V to VL + 0.3 V or 6 mA,
whichever occurs first
VSS − 0.3 V to VDD + 0.3 V or
30 mA, whichever occurs first
−0.3 V to +6 V
550 mA (pulsed at 1 ms,
10% duty cycle maximum)
Data + 15%
THERMAL RESISTANCE
Thermal performance is directly linked to printed circuit board
(PCB) design and operating environment. Careful attention to
PCB thermal design is required.
θJA is the natural convection junction to ambient thermal
resistance measured in a one cubic foot sealed enclosure. θJCB is
the junction to the bottom of the case value.
Table 8. Thermal Resistance
−40°C to +125°C
−65°C to +150°C
150°C
260(+0/−5)°C
Package Type
LGA1
1
θJA
65.5
θJCB
48.12
Unit
°C/W
Thermal impedance simulated values are based on a JEDEC 2S2P thermal
test board with four thermal vias. See JEDEC JESD-51.
ELECTROSTATIC DISCHARGE (ESD) RATINGS
Overvoltages at the digital Sx and Dx pins are clamped by internal diodes.
Limit current to the maximum ratings given.
2
Sx refers to the S1 to S8 pins, and Dx refers to the D1 to D8 pins.
3
See Table 4 and Table 5.
1
Only one absolute maximum rating can be applied at any one time.
The following ESD information is provided for handling of
ESD-sensitive devices in an ESD protected area only.
Human body model (HBM) per ANSI/ESDA/JEDEC JS-001.
Field induced charged device model (FICDM) per
ANSI/ESDA/JEDEC JS-002.
ESD Ratings for ADGS1414D
Table 9. ADGS1414D, 30-Terminal LGA
Package Type
HBM
FICDM
ESD CAUTION
Rev. 0 | Page 11 of 28
Withstand Threshold (V)
±2000
±1250
Class
2
C3
ADGS1414D
Data Sheet
PIN CONFIGURATION AND FUNCTION DESCRIPTIONS
VDD
GND
RESET/VL
SDI
SCLK
CS
ADGS1414D
30 29 28 27 26 25
D1
D2
S1
S2
VSS
S3
S4
D3
D4
1
24
23
2
3
4
5
6
22
21
TOP VIEW
(Not to Scale)
20
19
18
7
8
17
9
16
D8
D7
S8
S7
NIC
S6
S5
D6
D5
NOTES
1. NIC = NOT INTERNALLY CONNECTED.
2. EXPOSED PAD. THE EXPOSED PAD IS CONNECTED
INTERNALLY. FOR INCREASED RELIABILITY OF THE
SOLDER JOINTS AND MAXIMUM THERMAL CAPABILITY,
IT IS RECOMMENDED THAT THE EXPOSED PAD IS
CONNECTED TO VSS.
Table 10. Pin Function Descriptions
Pin No.
1
2
3
4
5
6
7
8
9
10, 30
11, 29
12, 28
Mnemonic
D1
D2
S1
S2
VSS
S3
S4
D3
D4
VDD
GND
RESET/VL
13
SDO
14, 26
SCLK
15, 25
CS
16
17
18
19
20
21
22
23
24
27
D5
D6
S5
S6
NIC
S7
S8
D7
D8
SDI
EPAD
23895-005
VDD
GND
RESET/VL
SDO
SCLK
CS
10 11 12 13 14 15
Figure 5. Pin Configuration
Description
Drain Terminal 1. The D1 pin can be an input or an output.
Drain Terminal 2. The D2 pin can be an input or an output.
Source Terminal 1. The S1 pin can be an input or an output.
Source Terminal 2. The S2 pin can be an input or an output.
Most Negative Power Supply Potential. In single-supply applications, tie the VSS pin to ground.
Source Terminal 3. The S3 pin can be an input or an output.
Source Terminal 4. The S4 pin can be an input or an output.
Drain Terminal 3. The D3 pin can be an input or an output.
Drain Terminal 4. The D4 pin can be an input or an output.
Most Positive Power Supply Potential. Both VDD pins are connected internally.
Ground (0 V) Reference. Both GND pins are connected internally.
RESET/Logic Power Supply Input (VL). Under normal operation, drive RESET/VL with a 2.7 V to 5.5 V supply. Pull
RESET/VL low to complete a hardware reset. After a reset, all switches open, and the appropriate registers are
set to their default. Both RESET and VL are connected internally.
Serial Data Output. Use the SDO pin for daisy-chaining a number of these devices together or for reading
back the data stored in a register for diagnostic purposes. The serial data is propagated on the falling edge of
SCLK.
Serial Clock Input. Data is captured on the positive edge of SCLK. Data can be transferred at rates up to
50 MHz. Both SCLK pins are connected internally.
Active Low Control Input. CS is the frame synchronization signal for the input data. Both CS pins are
connected internally.
Drain Terminal 5. The D5 pin can be an input or an output.
Drain Terminal 6. The D6 pin can be an input or an output.
Source Terminal 5. The S5 pin can be an input or an output.
Source Terminal 6. The S6 pin can be an input or an output.
Not Internally Connected.
Source Terminal 7. The S7 pin can be an input or an output.
Source Terminal 8. The S8 pin can be an input or an output.
Drain Terminal 7. The D7 pin can be an input or an output.
Drain Terminal 8. The D8 pin can be an input or an output.
Serial Data Input. Data is captured on the positive edge of SCLK.
Exposed Pad. The exposed pad is connected internally. For increased reliability of the solder joints and
maximum thermal capability, it is recommended that the exposed pad is connected to VSS.
Rev. 0 | Page 12 of 28
Data Sheet
ADGS1414D
TYPICAL PERFORMANCE CHARACTERISTICS
3.0
2.5
VDD = +10V,
VSS = –10V
2.5
VDD = +12V,
VSS = –12V
1.5
VDD = +13.5V,
VSS = –13.5V
1.0
VDD = +16.5V,
VSS = –16.5V
VDD = +15V,
VSS = –15V
0.5
TA = +125°C
2.0
TA = +85°C
1.5
TA = +25°C
TA = –40°C
1.0
0.5
VDD = +15V
VSS = –15V
IS = –10mA
TA = 25°C
IS = –10mA
–12.5
–8.5
–4.5
–0.5
11.5
7.5
3.5
15.5
VS OR VD (V)
0
–15
23895-006
0
–16.5
15
4.0
ON RESISTANCE (Ω)
ON RESISTANCE (Ω)
10
4.5
2.5
2.0
VDD = +7V,
VSS = –7V
VDD = +5.5V,
VSS = –5.5V
1.5
5
5.0
VDD = +5V,
VSS = –5V
3.0
0
Figure 9. On Resistance vs. VS or VD for Various Temperatures,
±15 V Dual Supply
VDD = +4.5V,
VSS = –4.5V
3.5
–5
VS OR VD (V)
Figure 6. On Resistance vs. VS or VD for Various Dual Supplies, ±10 V to
±16.5 V
4.0
–10
23895-009
ON RESISTANCE (Ω)
ON RESISTANCE (Ω)
2.0
3.5
TA = +85°C
3.0
TA = +25°C
2.5
2.0
TA = –40°C
1.5
1.0
1.0
0.5
TA = 25°C
IS = –10mA
–6
–5
–4
–3
–2
–1
0
1
2
3
5
4
6
7
VS OR VD (V)
0
–5
23895-007
0
–7
VDD = +5V
VSS = –5V
IS = –10mA
–3
–4
–2
–1
0
1
2
3
4
5
VS OR VD (V)
Figure 7. On Resistance vs. VS or VD for Various Dual Supplies, ±4.5 V to
±7 V
23895-010
0.5
Figure 10. On Resistance vs. VS or VD for Various Temperatures,
±5 V Dual Supply
7
4.5
VDD = 5V,
VSS = 0V
6
4.0
VDD = 12V,
VSS = 0V
3
2
VDD = 13.2V,
VSS = 0V
1
TA = 25°C
IS = –10mA
0
2
4
6
8
10
12
14
VS OR VD (V)
TA = +85°C
2.5
TA = +25°C
2.0
TA = –40°C
1.5
1.0
VDD = 15V,
VSS = 0V
0
3.0
VDD = 12V
VSS = 0V
IS = –10mA
0.5
0
0
2
4
6
8
10
12
VS OR VD (V)
Figure 8. On Resistance vs. VS or VD for Various Single Supplies
Figure 11. On Resistance vs. VS or VD for Various Temperatures,
12 V Single Supply
Rev. 0 | Page 13 of 28
23895-011
4
ON RESISTANCE (Ω)
VDD = 10.8V,
VSS = 0V
VDD = 8V,
VSS = 0V
23895-008
ON RESISTANCE (Ω)
3.5
5
ADGS1414D
Data Sheet
5.0
9
4.5
8
TA = 125°C
IS = 100mA
3.5
3.0
2.5
TA = 25°C
IS = 190mA
2.0
1.5
6
5
4
3
2
1
1.0
0
VDD = +5V
VSS = –5V
–4
–3
–2
–1
0
1
2
3
4
5
VS OR VD (V)
–1
0
40
60
80
100
120
TEMPERATURE (°C)
Figure 12. On Resistance vs. VS or VD for Various Current Levels and
Temperatures, ±5 V Dual Supply
Figure 15. Leakage Current vs. Temperature, 12 V Single Supply
400
1.5
TA = 25°C
ID, IS (ON) + +
1.0
ID (OFF) – +
0.5
VDD = +15V, VSS = –15V
300
IS (OFF) + –
200
CHARGE INJECTION (pC)
0
–0.5
–1.0
ID, IS (ON) – –
–1.5
ID (OFF) + –
–2.0
100
VDD = +5V, VSS = –5V
0
–100
VDD = +12V, VSS = 0V
–200
–300
–2.5
IS (OFF) – +
80
100
120
TEMPERATURE (°C)
–500
–15
–5
–10
0
10
5
23895-016
60
–400
23895-013
VDD = +15V
–3.0 VSS = –15V
VBIAS = +10V/–10V
–3.5
20
40
0
15
VS (V)
Figure 16. Charge Injection vs. VS
Figure 13. Leakage Current vs. Temperature, ±15 V Dual Supply
(VBIAS = Bias Voltage)
700
1.5
VDD = +5V
VSS = –5V
VBIAS = +4.5V/–4.5V
1.0
600
15V DUAL SUPPLY, tON
15V DUAL SUPPLY, tOFF
5V DUAL SUPPLY, tON
5V DUAL SUPPLY, tOFF
12V SINGLE SUPPLY, tON
12V SINGLE SUPPLY, tOFF
tON AND tOFF (ns)
500
0.5
400
0
300
–0.5
IS (OFF) + –
ID (OFF) + –
IS (OFF) – +
ID (OFF) – +
ID, IS (ON) ++
ID, IS (ON) – –
–1.5
0
20
40
100
60
80
100
120
TEMPERATURE (°C)
Figure 14. Leakage Current vs. Temperature, ±5 V Dual Supply
0
–40
23895-014
–1.0
200
–20
0
20
40
60
TEMPERATURE (°C)
80
100
120
23895-017
LEAKAGE CURRENT (nA)
20
23895-015
0
–5
23895-012
0.5
LEAKAGE CURRENT (nA)
IS (OFF) + –
ID (OFF) + –
IS (OFF) – +
ID (OFF) – +
ID, IS (ON) ++
ID, IS (ON) – –
7
LEAKAGE CURRENT (nA)
ON RESISTANCE (Ω)
4.0
VDD = 12V
VSS = 0V
VBIAS = 1V/10V
Figure 17. tON and tOFF vs. Temperature for Single Supply and Dual Supply
Rev. 0 | Page 14 of 28
Data Sheet
ADGS1414D
0
VDD = +15V
VSS = –15V
TA = 25°C
–20
–40
–40
AC PSRR (dB)
–60
–80
NO EXTERNAL
DECOUPLING
–60
–80
–100
10µF DECOUPLING
CAPACITOR
–100
–120
1k
10k
100k
1M
10M
100M
1G
FREQUENCY (Hz)
–120
100
23895-018
–140
100
Figure 18. Off Isolation vs. Frequency, ±15 V Dual Supply
1k
10k
100k
1M
10M
VDD = +15V
VSS = –15V
TA = 25°C
0.025
VDD = +15V
VSS = –15V
TA = 25°C
RL = 110Ω, VS = 20V p-p
0.020
THD + N (%)
–40
CROSSTALK (dB)
1G
Figure 21. AC Power Supply Rejection Ratio (AC PSRR) vs. Frequency,
±15 V Dual Supply
0
–20
100M
FREQUENCY (Hz)
23895-021
OFF ISOLATION (dB)
–20
0
VDD = +15V
VSS = –15V
TA = 25°C
–60
–80
0.015
RL = 110Ω, VS = 15V p-p
0.010
RL = 110Ω, VS = 10V p-p
RL = 1kΩ, VS = 20V p-p
–100
0.005
100k
1M
10M
100M
1G
FREQUENCY (Hz)
0
20
23895-019
–140
10k
2k
20k
Figure 22. THD + N vs. Frequency, ±15 V Dual Supply
0
0.20
VDD = +15V
VSS = –15V
TA = 25°C
RL = 110Ω, VS = 10V p-p
VDD = +5V
VSS = –5V
TA = 25°C
0.15
THD + N (%)
–2
–3
0.10
–4
0.05
RL = 110Ω, VS = 5V p-p
RL = 1kΩ, VS = 10V p-p
RL = 110Ω, VS = 2.5V p-p
RL = 1kΩ, VS = 5V p-p
RL = 1kΩ, VS = 2.5V p-p
–6
10k
100k
1M
10M
100M
FREQUENCY (Hz)
1G
0
20
200
2k
FREQUENCY (Hz)
Figure 23. THD + N vs. Frequency, ±5 V Dual Supply
Figure 20. Insertion Loss vs. Frequency, ±15 V Dual Supply
Rev. 0 | Page 15 of 28
20k
23895-023
–5
23895-020
INSERTION LOSS (dB)
200
FREQUENCY (Hz)
Figure 19. Crosstalk vs. Frequency, ±15 V Dual Supply
–1
RL = 1kΩ, VS = 10V p-p
23895-022
RL = 1kΩ, VS = 15V p-p
–120
ADGS1414D
Data Sheet
0.14
80
VDD = 12V
VSS = 0V
0.12 TA = 25°C
70
RL = 110Ω, VS = 9V p-p
VDD = +15V
VSS = –15V
60
0.10
50
IDD (µA)
0.08
RL = 110Ω, VS = 6V p-p
0.06
RL = 110Ω, VS = 3V p-p
RL = 1kΩ, VS = 9V p-p
0.02
RL = 1kΩ, VS = 6V p-p
30
20
10
RL = 1kΩ, VS = 3V p-p
0
20
200
VDD = +12V
VSS = 0V
40
2k
20k
FREQUENCY (Hz)
VDD = +5V
VSS = –5V
0
2.7
4.0
3.5
3.0
4.5
5.0
5.5
VL (V)
23895-126
0.04
23895-124
THD + N (%)
TA = 25°C
IDD PER CLOSED SWITCH
Figure 26. IDD vs. VL
Figure 24. THD + N vs. Frequency, 12 V Single Supply
2.0
450
VDD = +15V
VSS = –15V
1.5 T = 25°C
A
SCLK = 2.5MHz
SCLK IDLE
TA = 25°C
400
350
1.0
300
IL (uA)
0
250
200
–0.5
150
–1.0
100
50
–2.0
0
0
2
4
6
8
TIME (µs)
VL = 5V
VL = 3V
1
10
20
30
40
SCLK FREQUENCY (MHz)
Figure 27. IL vs. SCLK Frequency When CS Is High
Figure 25. Digital Feedthrough (VOUT = Output Voltage)
Rev. 0 | Page 16 of 28
50
23895-226
–1.5
23895-125
VOUT (mV)
0.5
Data Sheet
ADGS1414D
TEST CIRCUITS
IS (OFF)
A
A
VS
VD
ID (OFF)
Sx
Dx
A
VS
VD
Figure 32. Off Leakage
Figure 28. On Leakage
IDS
VDD
VSS
VDD
VSS
V
AUDIO PRECISION
RS
Dx
Sx
23895-025
Sx
23895-028
ID (ON)
Dx
23895-024
Sx
VS
RON = V/IDS
VS
V p-p
Dx
Figure 29. On Resistance
(IDS = Drain and Source Current)
VDD
VSS
VDD
VSS
S1
RL
50Ω
D1
VDD
VSS
VDD
VSS
23895-029
NETWORK
ANALYZER
NC
50Ω
Sx
S2
D2
VS
RL
50Ω
Dx
V
RL OUT
50Ω
VS
GND
VOUT
VS
23895-026
CHANNEL TO CHANNEL CROSSTALK = 20 log
GND
INSERTION LOSS = 20 log
Figure 34. −3 dB Bandwidth
Figure 30. Channel to Channel Crosstalk
VDD
VOUT WITH SWITCH
VS WITHOUT SWITCH
VSS
VSS
NETWORK
ANALYZER
VDD
NETWORK
ANALYZER
VSS
Sx
50Ω
RL
50Ω
50Ω
INTERNAL
BIAS
VDD
VSS
VS
VS
Dx
S1
RL
50Ω
AC PSRR = 20 log
OFF ISOLATION = 20 log
VOUT
VS
23895-027
GND
VOUT
V
RL OUT
50Ω
GND
D1
VOUT
VS
NOTES
1. BOARD AND COMPONENT EFFECTS ARE NOT DE-EMBEDDED
FROM THE AC PSRR MEASUREMENT.
Figure 35. AC PSRR
Figure 31. Off Isolation
Rev. 0 | Page 17 of 28
NC
23895-235
VOUT
Figure 33. THD + N
23895-030
NETWORK
ANALYZER
VOUT
RL
110Ω
GND
ADGS1414D
Data Sheet
V DD
V SS
SCLK
50%
50%
0V
V SS
VS1
S1
D1
VS2
S2
D2
INPUT LOGIC
80%
VOUT1
C L2
35pF
R L2
300Ω
VOUT2
C L1
35pF
R L1
300Ω
VOUT1
80%
0V
80%
80%
VOUT2
0V
GND
tD
23895-236
V DD
tD
Figure 36. Break-Before-Make Time Delay, tD
VSS
VDD
VSS
Sx
VOUT
Dx
RL
300Ω
VS
INPUT LOGIC
CL
35pF
SCLK
50%
50%
90%
VOUT
GND
10%
tON
tOFF
23895-031
VDD
Figure 37. Switching Times, tON and tOFF
3V
SCLK
RS
VDD
VSS
VDD
VSS
Sx
Dx
QINJ = CL × ΔVOUT
INPUT LOGIC
ΔVOUT
SWITCH OFF
GND
SWITCH ON
Figure 38. Charge Injection, QINJ (ΔVOUT = Change in Output Voltage)
Rev. 0 | Page 18 of 28
23895-032
VOUT
VOUT
CL
1nF
VS
Data Sheet
ADGS1414D
TERMINOLOGY
IDD
IDD represents the positive supply current.
CIN
CIN is the digital input capacitance.
ISS
ISS represents the negative supply current.
COUT
COUT is the digital output capacitance.
VD, VS
VD and VS represent the analog voltage on Terminal Dx and
Terminal Sx, respectively.
tON
tON represents the delay between applying the digital control
input and the output switching on.
RON
RON represents the ohmic resistance between Terminal Dx and
Terminal Sx.
tOFF
tOFF represents the delay between applying the digital control
input and the output switching off.
∆RON
∆RON represents the difference between the RON of any two
channels.
Off Isolation
Off isolation is a measure of unwanted signal coupling through
an off switch.
RFLAT (ON)
RFLAT (ON) is flatness that is defined as the difference between the
maximum and minimum value of on resistance measured over
the specified analog signal range.
Charge Injection
Charge injection is a measure of the glitch impulse transferred
from the digital input to the analog output during switching.
IS (Off)
IS (Off) is the source leakage current with the switch off.
ID (Off)
ID (Off) is the drain leakage current with the switch off.
ID (On), IS (On)
ID (On) and IS (On) represent the channel leakage currents with
the switch on.
VINL
VINL is the maximum input voltage for Logic 0.
Crosstalk
Crosstalk is a measure of unwanted signal that is coupled
through from one channel to another as a result of parasitic
capacitance.
−3 dB Bandwidth
Bandwidth is the frequency at which the output is attenuated
by 3 dB.
On Response
On response is the frequency response of the on switch.
Insertion Loss
Insertion loss is the loss due to the on resistance of the switch.
VINH
VINH is the minimum input voltage for Logic 1.
IINL, IINH
IINL and IINH represent the low and high input currents of the
digital inputs.
CD (Off)
CD (Off) represents the off switch drain capacitance, which is
measured with reference to ground.
CS (Off)
CS (Off) represents the off switch source capacitance, which is
measured with reference to ground.
Total Harmonic Distortion + Noise (THD + N)
THD + N is the ratio of the harmonic amplitude plus noise of
the signal to the fundamental.
AC Power Supply Rejection Ratio (AC PSRR)
AC PSRR is the ratio of the amplitude of the signal on the
output to the amplitude of the modulation. AC PSRR is a
measure of the ability of the device to avoid coupling noise and
spurious signals that appear on the supply voltage pin to the
output of the switch. The dc voltage on the device is modulated
by a sine wave of 0.62 V p-p.
CD (On), CS (On)
CD (On) and CS (On) represent on switch capacitances, which
are measured with reference to ground.
Rev. 0 | Page 19 of 28
ADGS1414D
Data Sheet
THEORY OF OPERATION
During any SPI command, SDO sends out eight alignment bits
as the first eight bits. The alignment bits observed at SDO are 0x25.
The ADGS1414D is a set of serially controlled, octal SPST switches
with error detection features. SPI Mode 0 and Mode 3 can be
used with the ADGS1414D, and the device operates with SCLK
frequencies up to 50 MHz. The default mode for the ADGS1414D
is address mode in which the registers of the device are accessed
by a 16-bit SPI command that is bounded by CS. The SPI
command is a 24-bit command if the user enables CRC error
detection. Other error detection features include SCLK count
error and invalid read and write error. Read the error flags register
to detect if any of these SPI errors occur. The ADGS1414D can
also operate in two other modes: burst mode and daisy-chain
mode.
ERROR DETECTION FEATURES
Protocol and communication errors on the SPI are detectable.
There are three error detection features: incorrect SCLK count
error detection, invalid read and write address error detection,
and CRC error detection. Each of these error detection features
has a corresponding enable bit in the error configuration
register. In addition, there is an error flag bit for each of these
error detection features in the error flags register.
Cyclic Redundancy Check (CRC) Error Detection
The CRC error detection feature extends a valid SPI frame by
8 SCLK cycles. These eight extra cycles are needed to send the
CRC byte for that SPI frame. The CRC byte is calculated by the
SPI block using the 16-bit payload: the R/W bit, the register
address, Bits[6:0], and the register data, Bits[7:0]. The CRC
polynomial used in the SPI block is x8 + x2 + x1 + 1 with a seed
value of 0. For a timing diagram with CRC enabled, see Figure 40.
Register writes occur at the 24th SCLK rising edge with CRC
error checking enabled.
The interface pins of the ADGS1414D are CS, SCLK, SDI, and
SDO. Hold CS low when using the SPI. Data is captured on the
SDI on the rising edge of SCLK, and data is propagated out on the
SDO on the falling edge of SCLK.
ADDRESS MODE
Address mode is the default mode for the ADGS1414D upon
power up. A single SPI frame in address mode is bounded by
a CS falling edge and the succeeding CS rising edge. The SPI frame
is comprised of 16 SCLK cycles. The timing diagram for address
mode is shown in Figure 39. The first SDI bit indicates if the
SPI command is a read or write command. When the first bit is
set to 0, a write command is issued, and if the first bit is set to 1, a
read command is issued. The next seven bits determine the target
register address. The remaining eight bits provide the data to the
addressed register. The last eight bits are ignored during a read
command, because during these clock cycles, SDO propagates out
the data contained in the addressed register.
During an SPI write, the microcontroller or central processing
unit (CPU) provides the CRC byte through SDI. The SPI block
checks the CRC byte just before the 24th SCLK rising edge. On
this same edge, the register write is prevented if an incorrect
CRC byte is received by the SPI. The CRC error flag asserts in
the error flags register in the case of the incorrect CRC byte
being detected.
During an SPI read, the CRC byte is provided to the
microcontroller through SDO.
The target register address of an SPI command is determined
on the eighth SCLK rising edge. Data from this register propagates
out on SDO from the 8th to the 15th SCLK falling edge during
SPI reads. A register write occurs on the 16th SCLK rising edge
during SPI writes.
The CRC error detection feature is disabled by default and can
be configured by the user through the error configuration register.
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
R/W
A6
A5
A4
A3
A2
A1
A0
D7
D6
D5
D4
D3
D2
D1
D0
CS
SDI
SDO
0
0
1
0
0
1
0
1
D7
D6
D5
D4
D3
D2
D1
D0
23895-033
SCLK
Figure 39. Address Mode Timing Diagram
1
2
8
9
10
16
17
18
19
20
21
22
23
24
R/W
A6
A0
D7
D6
D0
C7
C6
C5
C4
C3
C2
C1
C0
CS
SDI
SDO
0
0
1
D7
D6
D0
C7
C6
C5
Figure 40. Timing Diagram with CRC Enabled
Rev. 0 | Page 20 of 28
C4
C3
C2
C1
C0
23895-034
SCLK
Data Sheet
ADGS1414D
SCLK Count Error Detection
BURST MODE
SCLK count error detection allows the user to detect if an incorrect
number of SCLK cycles are sent by the microcontroller or CPU.
When in address mode, with CRC disabled, 16 SCLK cycles are
expected. If 16 SCLK cycles are not detected, the SCLK count
error flag asserts in the error flags register. When less than
16 SCLK cycles are received by the device, a write to the register
map does not occur. When the ADGS1414D receives more
than 16 SCLK cycles, a write to the memory map still occurs at
the 16th SCLK rising edge, and the flag asserts in the error flags
register. With CRC enabled, the expected number of SCLK
cycles is 24. SCLK count error detection is enabled by default
and can be configured by the user through the error
configuration register.
The SPI can accept consecutive SPI commands without the need
to deassert the CS line, which is called burst mode. Burst mode
is enabled through the burst enable register. This mode uses the
same 16-bit command to communicate with the device. In
addition, the response of the device at SDO is still aligned with
the corresponding SPI command. Figure 41 shows an example
of SDI and SDO during burst mode.
An invalid read and write address error detects when a nonexistent
register address is a target for a read or write. In addition, this
error asserts when a write to a read only register is attempted.
The invalid read and write address error flag asserts in the error
flags register when an invalid read and write address error occurs.
The invalid read and write address error is detected on the ninth
SCLK rising edge, which means a write to the register does not
occur when an invalid address is targeted. Invalid read and
write address error detection is enabled by default and can be
disabled by the user through the error configuration register.
CLEARING THE ERROR FLAGS REGISTER
CS
SDI
COMMAND0[15:0]
SDO
RESPONSE0[15:0]
COMMAND1[15:0]
COMMAND2[15:0]
COMMAND3[15:0]
RESPONSE1[15:0]
RESPONSE2[15:0]
RESPONSE3[15:0]
Figure 41. Burst Mode Frame
SOFTWARE RESET
When in address mode, the user can initiate a software reset by
writing two consecutive SPI commands, 0xA3 followed by
0x05, targeting Register 0x0B. After a software reset, all register
values are set to default.
DAISY-CHAIN MODE
To clear the error flags register, write the special 16-bit SPI
frame, 0x6CA9, to the device. This SPI command does not
trigger the invalid R/W address error. When CRC is enabled,
the user must also send the correct CRC byte for a successful
error clear command. At the 16th or 24th SCLK rising edge, the
error flags register resets to zero.
The connection of several ADGS1414D devices in a daisy-chain
configuration is possible, and Figure 42 illustrates this setup. All
devices share the same CS, SCLK, and VL line, whereas the SDO of
a device forms a connection to the SDI of the next device, creating
a shift register. In daisy-chain mode, SDO is an eight cycle delayed
version of SDI. When in daisy-chain mode, all commands target
the switch data register. Therefore, it is not possible to make
configuration changes while in daisy-chain mode.
ADGS1414D
ADGS1414D
DEVICE 2
DEVICE 1
S1
D1
S1
D1
S2
D2
S2
D2
S3
D3
S3
D3
S4
D4
S4
D4
S5
D5
S5
D5
S6
D6
S6
D6
S7
D7
S7
D7
S8
D8
S8
D8
SPI
INTERFACE
23895-035
Invalid Read and Write Address Error
The invalid read and write address and CRC error checking
functions operate similarly during burst mode as these error
checking functions do during address mode. However, SCLK
count error detection operates in a slightly different manner.
The total number of SCLK cycles within a given CS frame are
counted, and if the total is not a multiple of 16, or a multiple of
24 when CRC is enabled, the SCLK count error flag asserts.
SDO
SPI
INTERFACE
SDO
23895-036
SDI
SCLK
CS
VL
Figure 42. Two ADGS1414D Devices Connected in a Daisy-Chain Configuration
Rev. 0 | Page 21 of 28
ADGS1414D
Data Sheet
When in address mode, the ADGS1414D can only enter daisychain mode by sending the 16-bit SPI command, 0x2500
(see Figure 43). When the ADGS1414D receives this command,
the SDO of the device sends out the same command because
the alignment bits at SDO are 0x25, which allows multiple daisy
connected devices to enter daisy-chain mode in a single SPI
frame. A hardware reset is required to exit daisy-chain mode.
on each device in the chain are 0x00. When CS goes high, the
internal shift register value does not reset back to zero.
An SCLK rising edge reads data on SDI while data is
propagated out SDO on an SCLK falling edge.
POWER-ON RESET
The digital section of the ADGS1414D goes through an
initialization phase during VL power up. This initialization also
occurs after a hardware or software reset. After VL power-up or
a reset, ensure that a minimum of 120 µs passes from the time
of power-up or reset before any SPI command is issued. Ensure
that VL does not drop out during the 120 µs initialization phase
because it may result in the incorrect operation of the
ADGS1414D.
For the timing diagram of a typical daisy-chain SPI frame, see
Figure 44. When CS goes high, Device 1 writes Command 0,
Bits[7:0] to its switch data register, Device 2 writes Command 1,
Bits[7:0] to its switches, and so on. The SPI block uses the last
eight bits it received through SDI to update the switches. After
entering daisy-chain mode, the first eight bits sent out by SDO
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
0
0
1
0
0
1
0
1
0
0
0
0
0
0
0
0
CS
SDI
0
SDO
0
1
0
0
1
0
1
0
0
0
0
0
0
0
23895-037
SCLK
0
Figure 43. SPI Command to Enter Daisy-Chain Mode
SDI
COMMAND3[7:0]
COMMAND2[7:0]
COMMAND1[7:0]
COMMAND0[7:0]
DEVICE 1
SDO
0x00
COMMAND3[7:0]
COMMAND2[7:0]
COMMAND1[7:0]
DEVICE 2
SDO2
0x00
0x00
COMMAND3[7:0]
COMMAND2[7:0]
DEVICE 3
0x00
0x00
0x00
COMMAND3[7:0]
DEVICE 4
SDO3
NOTES
1. SDO2 AND SDO3 ARE THE OUTPUT COMMANDS FROM DEVICE 2 AND DEVICE 3, RESPECTIVELY.
Figure 44. Example of an SPI Frame Where Four ADGS1414D Devices Connect in Daisy-Chain Mode
Rev. 0 | Page 22 of 28
23895-038
CS
Data Sheet
ADGS1414D
APPLICATIONS INFORMATION
SYSTEM CHANNEL DENSITY
The ADGS1414D feature set allows for large system channel
density. These features include route through pins for the
digital signals and power supplies, as well as integrated passive
components.
Route Through Pins
When multiple ADGS1414D devices are used in a system, the
route through pins allow for a greater channel density layout.
The route through pins enable the passing of power supplies
and digital lines between devices with ease. The VDD, RESET/VL,
and GND power lines, as well as the SCLK, CS, SDI, and SDO
digital lines, are available on both the top and bottom pins of
the package. These route through pins simplify PCB routing
and reduce the need for vias when connecting many
ADGS1414D devices together. Figure 45 shows an example
layout where the route through pins on four ADGS1414D
devices configured in daisy-chain mode are used to reduce the
overall size of the layout.
Integrated Passive Components
Note the lack of external passive components in the layout in
Figure 45. The ADGS1414D has integrated decoupling
capacitors for the VDD, VSS, and RESET/VL power supplies.
Therefore, the need for external decoupling capacitors is
eliminated, reducing the total system footprint of the
ADGS1414D. If additional decoupling is required for extremely
noise sensitive applications, add an external decoupling
capacitor. Figure 21 shows the AC PSRR performance with and
without external decoupling capacitors.
CS
SCLK
SDO
RESET/VL
GND
VDD
23895-245
CS
SCLK
SDO
RESET/VL
GND
VDD
Figure 45. Layout Example Showing the Use of the Route Pins and the Elimination of External Passive Components
Rev. 0 | Page 23 of 28
ADGS1414D
Data Sheet
The ADGS1414D exhibits break-before-make switching action.
This feature allows for the use of the device in multiplexer
applications. To use the device as a multiplexer, externally
hardwire a device into the desired mux configuration, as shown
in Figure 46.
The ADP7142 can generate the VL voltage that is required to
power digital circuitry within the ADGS1414D.
ADP7142
LDO
+15.5V
+5V
INPUT
ADP7142
LDO
LT3463
–15.5V
4:1 MUX
ADP7182
LDO
+3.3V
+15V
–15V
23895-247
BREAK-BEFORE-MAKE SWITCHING
Figure 47. Bipolar Power Solution
Table 11. Recommended Power Management Devices
4 × SPST
Product
LT3463
S1
Description
Dual micropower, dc to dc converter with Schottky
diodes
40 V, 200 mA, low noise, CMOS, LDO linear regulator
−28 V, −200 mA, low noise, LDO linear regulator
S2
ADP7142
ADP7182
Dx
S3
1.8 V LOGIC COMPATIBILITY
S4
SPI
INTERFACE
Figure 46. An SPI Controlled Switch Configured into a 4:1 Mux
DIGITAL INPUT BUFFERS
There are input buffers present on the digital input pins (CS,
SCLK, and SDI). These buffers are active at all times. Therefore,
there is current draw from the VL supply if SCLK or SDI is
toggled, regardless of whether CS is active. For typical values of
this current draw, refer to the Specifications section and
Figure 27.
POWER SUPPLY RAILS
The ADGS1414D can operate with bipolar supplies between
±4.5 V and ±16.5 V. The supplies on VDD and VSS do not have
to be symmetrical. However, the VDD to VSS range must not
exceed 33 V. The ADGS1414D can also operate with single
supplies between 5 V and 20 V with VSS connected to GND.
The voltage range that can be supplied to VL is from 2.7 V to 5.5 V.
The device is fully specified at ±15 V, ±5 V, and +12 V analog
supply voltage ranges.
The SDO digital output levels are proportional to the VL voltage.
For example, if VL = 3 V, a logic high on the SDO is approximately
3 V. When performing an SPI readback from the ADGS1414D
with a controller device using 1.8 V logic, there may be an issue
if the digital pins on the controller cannot tolerate digital input
signals that exceed 1.8 V.
Figure 48 describes how to use the ADG3231 level translator to
perform a 1.8 V SPI readback with a device that has 1.8 V logic
ports, such as a microcontroller or field programmable gate array
(FPGA). Place the ADG3231 between the SDO of the ADGS1414D
and the microcontroller or FPGA. Supply VCC1 of the ADG3231
with the VL voltage of the ADGS1414D and connect VCC2 to the
1.8 V supply from the microcontroller or FPGA. The ADG3231
then translates the logic level of the SDO from VL to 1.8 V.
This solution is only required if the 1.8 V microcontroller or
FPGA cannot tolerate digital input signals that exceed 1.8 V.
ADGS1414D
POWER SUPPLY RECOMMENDATIONS
S1
S2
D2
Analog Devices, Inc., has a wide range of power management
products to meet the requirements of high performance signal
chains.
S3
D3
S4
D4
S5
D5
S6
D6
An example of a bipolar power solution is shown in Figure 47.
The LT3463 (a dual switching regulator) generates a positive and
negative supply rail for the ADGS1414D, an amplifier, and/or a
precision converter in a typical signal chain. Also shown in
Figure 47 are two optional low dropout regulators (LDOs),
the ADP7142 and ADP7182 (positive and negative LDOs,
respectively), which can reduce the output ripple of the LT3463
in ultralow noise sensitive applications.
S7
D7
S8
D8
D1
VL
VCC1
VCC2
SDO A
SPI
INTERFACE
ADG3231
CS
1.8V
VL
Y
GND
MICROCONTROLLER
OR
FPGA
SDI
SCLK
Figure 48. Using the ADG3231 to Perform a 1.8 V SPI Readback
Rev. 0 | Page 24 of 28
23895-248
23895-045
SCLK SDI CS RESET/VL
The SDI, CS, and SCLK digital inputs of the ADGS1414D are
compatible with 1.8 V logic when VL is between or equal to
2.7 V and 3.3 V.
Data Sheet
ADGS1414D
REGISTER SUMMARY
Table 12. Register Summary
Reg. Name
Bit 7
0x01 SW_DATA
SW8_EN SW7_EN SW6_EN SW5_EN SW4_EN SW3_EN
0x02 ERR_CONFIG
0x03 ERR_FLAGS
0x05 BURST_EN
0x0B SOFT_RESETB
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Reserved
Reserved
Bit 1
Bit 0
Default R/W
SW2_EN
SW1_EN
0x00
R/W
0x06
R/W
0x00
BURST_MODE_EN 0x00
0x00
R
R/W
RW_ERR_EN
SCLK_ERR_EN
CRC_ERR_EN
RW_ERR_FLAG SCLK_ERR_FLAG CRC_ERR_FLAG
Reserved
SOFT_RESETB
Rev. 0 | Page 25 of 28
W
ADGS1414D
Data Sheet
REGISTER DETAILS
SWITCH DATA REGISTER
Address: 0x01, Reset: 0x00, Name: SW_DATA
Use the switch data register to control the status of the eight switches of the ADGS1414D.
Table 13. Bit Descriptions for SW_DATA
Bit
7
Bit Name
SW8_EN
Setting
0
1
6
SW7_EN
0
1
5
SW6_EN
0
1
4
SW5_EN
0
1
3
SW4_EN
0
1
2
SW3_EN
0
1
1
SW2_EN
0
1
0
SW1_EN
0
1
Description
Enable the SW8_EN bit for Switch 8.
Switch 8 open.
Switch 8 closed.
Enable the SW7_EN bit for Switch 7.
Switch 7 open.
Switch 7 closed.
Enable the SW6_EN bit for Switch 6.
Switch 6 open.
Switch 6 closed.
Enable the SW5_EN bit for Switch 5.
Switch 5 open.
Switch 5 closed.
Enable the SW4_EN bit for Switch 4.
Switch 4 open.
Switch 4 closed.
Enable the SW3_EN bit for Switch 3.
Switch 3 open.
Switch 3 closed.
Enable the SW2_EN bit for Switch 2.
Switch 2 open.
Switch 2 closed.
Enable the SW1_EN bit for Switch 1.
Switch 1 open.
Switch 1 closed.
Default
0x0
Access
R/W
0x0
R/W
0x0
R/W
0x0
R/W
0x0
R/W
0x0
R/W
0x0
R/W
0x0
R/W
Default
0x0
0x1
Access
R
R/W
0x1
R/W
ERROR CONFIGURATION REGISTER
Address: 0x02, Reset: 0x06, Name: ERR_CONFIG
Use the error configuration register to enable and disable the relevant error features as required.
Table 14. Bit Descriptions for ERR_CONFIG
Bits
[7:3]
2
Bit Name
Reserved
RW_ERR_EN
Settings
0
1
1
SCLK_ERR_EN
0
1
Description
Bits[7:3] are reserved. Set Bits[7:3] to 0.
Enable the RW_ERR_EN bit to detect an invalid read and write address.
Disabled.
Enabled.
Enable the SCLK_ERR_EN bit to detect the correct number of SCLK cycles
in an SPI frame. 16 SCLK cycles are expected when CRC is disabled and
burst mode is disabled. 24 SCLK cycles are expected when CRC is enabled
and burst mode is disabled. A multiple of 16 SCLK cycles are expected
when CRC is disabled and burst mode is enabled. A multiple of 24 SCLK
cycles are expected when CRC is enabled and burst mode is enabled.
Disabled.
Enabled.
Rev. 0 | Page 26 of 28
Data Sheet
Bits
0
Bit Name
CRC_ERR_EN
ADGS1414D
Settings
0
1
Description
Enable the CRC_ERR_EN bit for CRC error detection. SPI frames are 24 bits
wide when enabled.
Disabled.
Enabled.
Default
0x0
Access
R/W
ERROR FLAGS REGISTER
Address: 0x03, Reset: 0x00, Name: ERR_FLAGS
Use the error flags register to determine if an error has occurred. To clear the error flags register, write the special 16-bit SPI command,
0x6CA9, to the device. This SPI command does not trigger the invalid R/W address error. When CRC is enabled, include the correct
CRC byte during the SPI write for the clear error flags register command to succeed.
Table 15. Bit Descriptions for ERR_FLAGS
Bits
[7:3]
2
Bit Name
Reserved
RW_ERR_FLAG
Settings
0
1
1
SCLK_ERR_FLAG
0
1
0
CRC_ERR_FLAG
0
1
Description
Bits[7:3] are reserved and are set to 0.
Error flag for invalid read and write address. The error flag asserts during
an SPI read if the target address does not exist. The error flag also asserts
when the target address of an SPI write does not exist or is read only.
No error.
Error.
Error flag for the detection of the correct number of SCLK cycles in an SPI
frame.
No error.
Error.
Error flag that determines if a CRC error has occurred during a register
write.
No error.
Error.
Default
0x0
0x0
Access
R
R
0x0
R
0x0
R
BURST ENABLE REGISTER
Address: 0x05, Reset: 0x00, Name: BURST_EN
Use the burst enable register to enable or disable burst mode. When burst mode is enabled, the user can send multiple consecutive SPI
commands without deasserting CS.
Table 16. Bit Descriptions for BURST_EN
Bits
[7:1]
0
Bit Name
Reserved
BURST_MODE_EN
Settings
0
1
Description
Bits[7:1] are reserved. Set Bits[7:1] to 0.
Burst mode enable bit.
Disabled.
Enabled.
Default
0x0
0x0
Access
R
R/W
SOFTWARE RESET REGISTER
Address: 0x0B, Reset: 0x00, Name: SOFT_RESETB
Use the software reset register to perform a software reset. Consecutively write 0xA3 followed by 0x05 to this register, and the registers of
the device reset to their default state.
Table 17. Bit Descriptions for SOFT_RESETB
Bits
[7:0]
Bit Name
SOFT_RESETB
Settings
Description
To perform a software reset, consecutively write 0xA3 followed by 0x05
to the SOFT_RESETB register.
Rev. 0 | Page 27 of 28
Default
0x0
Access
W
ADGS1414D
Data Sheet
OUTLINE DIMENSIONS
4.10
4.00
3.90
2.50
REF
0.075
REF
25
30
1
24
5.10
5.00
4.90
0.50
BSC
TOP VIEW
PKG-006441
1.73
1.63
1.53
2.60
BSC
EXPOSED
PAD
4.00
REF
0.40
0.35
0.30 0.32
0.27
0.22
16
9
10
15
BOTTOM VIEW
2.40
BSC
SIDE VIEW
1.30
REF
0.372
0.332
0.292
SEATING
PLANE
FOR PROPER CONNECTION OF
THE EXPOSED PAD, REFER TO
THE PIN CONFIGURATION AND
FUNCTION DESCRIPTIONS
SECTION OF THIS DATA SHEET.
04-27-2020-A
PIN 1
INDICATOR
AREA
Figure 49. 30-Terminal Land Grid Array [LGA]
(CC-30-3)
4 mm × 5 mm Body and 1.63 mm Package Height
Dimensions shown in millimeters
ORDERING GUIDE
Model1
ADGS1414DBCCZ
ADGS1414DBCCZ-RL7
EV-ADGS1414DSDZ
1
Temperature Range
−40°C to +125°C
−40°C to +125°C
Package Description
30-Terminal Land Grid Array [LGA]
30-Terminal Land Grid Array [LGA]
Evaluation Board
Z = RoHS Compliant Part.
©2020 Analog Devices, Inc. All rights reserved. Trademarks and
registered trademarks are the property of their respective owners.
D23895-6/20(0)
Rev. 0 | Page 28 of 28
Package Option
CC-30-3
CC-30-3
工商网监
湘ICP备2023018690号
