24 V to 220 V Precision
Operational Amplifier
ADHV4702-1
Data Sheet
FEATURES
TYPICAL APPLICATION CIRCUIT
APPLICATIONS
High-side current sensing
Automated test equipment
High voltage drivers
Piezotransducers
Digital-to-analog converter (DAC) output buffers
Light detecting and ranging (LiDAR), avalanche photodiode
(APD), single photon avalanche diode (SPAD) biasing
5kΩ
+105V
ADHV4702-1
VOUT
–105V
–5V
Figure 1.
The ADHV4702-1 also has a 2 μV/°C maximum input offset
voltage (VOS) drift and an 8 nV/√Hz input voltage noise.
The exceptional dc precision of the ADHV4702-1 is
complemented by excellent dynamic performance with a small
signal bandwidth of 10 MHz and a slew rate of 74 V/μs. The
ADHV4702-1 has an output current of 20 mA typical.
The ADHV4702-1 offers high voltage input common-mode
swing as well as high voltage output swing, enabling precision
high voltage use cases such as high-side current sensing. The
ADHV4702-1 is also ideally suited for forcing a voltage in
precision bias and control applications.
The ADHV4702-1 is available in a 12-lead, 7 mm × 7 mm lead
frame chip scale package (LFCSP) with an exposed pad (EPAD)
compliant to international electrotechnical commission
(IEC) 61010-1 creepage and clearance standards. The copper
EPAD provides a low thermal resistance path to improve heat
dissipation and features high voltage isolation, allowing it to be
safely connected to a 0 V ground plane regardless of VCC or
VEE voltages. The ADHV4702-1 operates over the −40°C to
+85°C industrial temperature range.
180
For precision performance, the ADHV4702-1 has a 170 dB
typical open-loop gain (AOL) and a 160 dB typical commonmode rejection ratio (CMRR), as shown in Figure 2.
AOL
CMRR
160
140
AOL AND CMRR (dB)
The ADHV4702-1 is a high voltage (220 V), unity-gain stable
precision operational amplifier. The ADHV4702-1 offers high
input impedance with low input bias current, low input offset
voltage, low drift, and low noise for precision demanding
applications. The next generation of proprietary semiconductor
processes and innovative architecture from Analog Devices, Inc.,
enable this precision operational amplifier to operate from
symmetrical dual supplies of ±110 V, asymmetrical dual
supplies, or a single supply of 220 V. The ADHV4702-1
requires a minimum supply voltage of ±12 V from the
reference voltage for normal operation.
16047-101
10kΩ
+5V
GENERAL DESCRIPTION
Rev. B
100kΩ
120
100
80
60
40
20
0
–20
0.001 0.01
0.1
1
10
100
1k
10k
100k
FREQUENCY (Hz)
1M
10M
16047-102
Wide range of operating voltages
Dual-supply: ±12 V to ±110 V
Asymmetrical supply operation: 24 V to 220 V
Wide input common-mode voltage range: 3 V from rails
High common-mode rejection ratio: 160 dB typical
High AOL: 170 dB typical
High slew rate
74 V/μs typical
24 V/μs typical with external input clamping diodes
Low input bias current: 2 pA maximum
Low input offset voltage: 1 mV maximum
Low input offset voltage drift: 2 μV/°C maximum
Low input voltage noise: 8 nV/√Hz typical at 10 kHz
Wide small signal bandwidth: 10 MHz typical
Resistor adjustable quiescent current: 0.6 mA to 3 mA (VS =
±110 V)
Unity-gain stable
Thermal monitoring
Small footprint: 12-lead, 7 mm × 7 mm LFCSP compliant with
IEC 61010-1 spacing
Shutdown mode
Figure 2. ADHV4702-1 Precision Performance
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ADHV4702-1
Data Sheet
TABLE OF CONTENTS
Features .............................................................................................. 1
Shutdown Pin (SD) .................................................................... 17
Applications ....................................................................................... 1
Temperature Monitor (TMP) ................................................... 17
General Description ......................................................................... 1
Overtemperature Protection ..................................................... 17
Typical Application Circuit ............................................................. 1
Output Current Drive and Short-Circuit Protection ............ 18
Revision History ............................................................................... 2
Functional Block Diagram .............................................................. 3
External Compensation and Capacitive Load (CLOAD) Driving
....................................................................................................... 18
Specifications..................................................................................... 4
Safe Operating Area ................................................................... 19
±12 V to ±110 V Supply .............................................................. 4
LFCSP Package and High Voltage Pin Spacing ...................... 19
Absolute Maximum Ratings............................................................ 6
Exposed Pad (EPAD) ................................................................. 19
Maximum Power Dissipation ..................................................... 6
Applications Information .............................................................. 20
Thermal Resistance ...................................................................... 6
Power Supply and Decoupling.................................................. 20
ESD Caution .................................................................................. 6
High Voltage Guard Ring .......................................................... 20
Pin Configuration and Function Descriptions ............................. 7
High Voltage DAC Voltage Subtractor .................................... 20
Typical Performance Characteristics ............................................. 8
High Current Output Driver .................................................... 20
Theory of Operation ...................................................................... 15
Signal Range Extender ............................................................... 20
Internal Electrostatic Discharge (ESD) Protection ................ 15
Outline Dimensions ....................................................................... 21
Slew Boost Circuit and Protection ........................................... 15
Ordering Guide .......................................................................... 21
Digital Ground (DGND) ........................................................... 16
Resistor Adjustable Quiescent Current (RADJ) ..................... 16
REVISION HISTORY
1/2020—Rev. A to Rev. B
Changes to General Description Section ...................................... 1
Change to CMRR Parameter in Table 1 ........................................ 4
Added Figure 33 and Figure 34; Renumbered
Sequentially ..................................................................................... 12
Change to External Compensation and Capacitive Load (CLOAD)
Driving Section ............................................................................... 18
Changes to Power Supply and Decoupling Section ................... 20
3/2019—Rev. 0 to Rev. A
Changes to Figure 59 ...................................................................... 19
Changes to Ordering Guide .......................................................... 21
11/2018—Revision 0: Initial Version
Rev. B | Page 2 of 21
Data Sheet
ADHV4702-1
FUNCTIONAL BLOCK DIAGRAM
IN–
COMP
DGND
12
11
10
BIAS
CELL
BIAS
CURRENT
9 RADJ
RESERVED 1
SLEW BOOST CIRCUIT
SLEW BOOST
CURRENT
HIGH-SIDE
GAIN STAGE
+
–
–
INPUT
STAGE
8 SD
TEMPERATURE
SENSOR
+
5V
+
–
LOW-SIDE
GAIN STAGE
RESERVED 3
AMPLIFIER
SIGNAL
PATH
7 VCC
4
5
6
VEE
TMP
OUT
Figure 3.
Rev. B | Page 3 of 21
16047-001
IN+ 2
ADHV4702-1
Data Sheet
SPECIFICATIONS
±12 V TO ±110 V SUPPLY
Supply voltage (VS) = ±12 V to ±110 V, TA = 25°C with an EPAD connected to a 0 V analog ground (AGND), DGND pin tied to 0 V
AGND, RADJ1 = 0 Ω, gain (AV) = 1, feedback resistor (RF) = 100 kΩ, and load resistance (RLOAD) = 10 kΩ, unless otherwise noted.
Table 1.
Parameter
DYNAMIC PERFORMANCE
−3 dB Bandwidth
Slew Rate
Settling Time to 0.1%
NOISE PERFORMANCE
Input Voltage Noise
Input Voltage Noise 1/f Corner
Input Current Noise
DC PERFORMANCE
Input Offset Voltage
Drift
Input Bias Current
Drift
Input Offset Current
Drift
Open-Loop Gain
INPUT CHARACTERISTICS
Input Resistance
Common-Mode
Differential
Input Capacitance
Common-Mode
Differential
Input Common-Mode Voltage Range
CMRR
SHUTDOWN PIN (SD)
SD Input Voltage
Low
High
SD Input Current
Low
High
Test Conditions/Comments
Min
AV = 1, output voltage (VOUT) = 200 mV p-p, RF = 0 Ω
AV = 20, VOUT = 200 V p-p, 20% to 80%
AV = 20, VOUT = 200 V p-p, 20% to 80%, with external
input clamping diodes2
AV = 1, VOUT = 40 V p-p, RF = 0 Ω
AV = 20, VOUT = 40 V p-p
AV = 40, VOUT = 40 V p-p
Frequency = 10 kHz
Frequency = 40 Hz
VS = ±110 V, TA = 25°C to 85°C
VS = ±12 V, TA = 25°C to 85°C
TA = 25°C
TA = 85°C
TA = 25°C to 85°C
TA = 25°C
TA = 85°C
TA = 25°C to 85°C
VS = ±110 V
VS = ±12 V
−1
−2
−3
−2
−100
−2
−50
146
130
Common-mode voltage (VCM) = −60 V to +60 V
VCM = −90 V to +90 V
VCM = −70 V to +70 V
140
Disabled
Enabled
1.6
Typ
Max
10
74
24
MHz
V/μs
V/μs
8.4
6.2
13
μs
μs
μs
8
10
1
nV/√Hz
Hz
fA/√Hz
±0.15
±0.25
±0.25
±0.3
±19
±0.3
±0.15
±8
±0.13
170
150
+1
+2
+3
+2
+100
+2
+50
TΩ
TΩ
TΩ
7.9
17.9
±107
160
pF
pF
V
dB
−11
−1
Rev. B | Page 4 of 21
mV
μV/°C
μV/°C
pA
pA
pA/°C
pA
pA
pA/°C
dB
dB
45
30
4.2
0.8
SD = 0 V
SD = 5 V
Unit
V
V
μA
μA
Data Sheet
Parameter
OUTPUT CHARACTERISTICS
Output Voltage Range
High
Low
Output Current
THERMAL MONITOR
TMP Pin Voltage3
TMP Pin Voltage Drift
POWER SUPPLY
Operating Range
Quiescent Current
SD = 5 V (Enabled)4
SD = 0 V (Disabled)
Positive Power Supply Rejection Ratio
(PSRR)
Negative Power Supply Rejection Ratio
ADHV4702-1
Test Conditions/Comments
Min
Typ
Max
Unit
108
108.5
−108.5
20
−108
V
V
mA
RLOAD = 5 kΩ, TA = −40°C to +85°C
TA = 25°C
TA = −40°C to +85°C
Symmetrical and asymmetrical supplies
1.9
−4.5
24
RADJ1 = 0 Ω, TA = 25°C, VS = ±110 V
RADJ1 = 0 Ω, TA = 25°C, VS = ±12 V
RADJ1 = 0 Ω, TA = −40°C to +85°C
RADJ1 = 50 kΩ, TA = 25°C, VS = ±110 V
RADJ1 = 50 kΩ, TA = 25°C, VS = ±12 V
RADJ1 = 50 kΩ, TA = −40°C to +85°C
RADJ1 = 100 kΩ, TA = 25°C, VS = ±110 V
Positive supply voltage (+VS) = 107 V to 112.5 V,
negative supply voltage (−VS) = 110 V
+VS = 10 V to 14 V, −VS = −12 V
+VS = 110 V, −VS = −107 V to −112.5 V
+VS = 12 V, −VS = −10 V to −14 V
1
3
2.7
0.9
0.8
130
0.6
0.18
155
110
130
110
130
155
130
V
mV/°C
220
V
3.3
3.3
3.3
1
1
1
mA
mA
mA
mA
mA
mA
mA
mA
dB
0.2
dB
dB
dB
RADJ is a resistor that connects the RADJ pin to DGND.
This slew rate result is tested while the ADHV4702-1 inputs are clamped at the forward-biased voltage of two diodes using ON Semiconductor® SBAV199LT1G. For
more information, see the Slew Boost Circuit and Protection section.
3
The TMP pin voltage may have device to device variation. For more information, see the Temperature Monitor (TMP) section.
4
This specification is for quiescent current only. For supply current or dynamic supply current information, see the Theory of Operation section.
2
Rev. B | Page 5 of 21
ADHV4702-1
Data Sheet
ABSOLUTE MAXIMUM RATINGS
MAXIMUM POWER DISSIPATION
Table 2.
Parameter
Supply Voltage (VCC to VEE)
Output Voltage
Common-Mode Input Voltage
Differential Input Voltage
Input Current
DGND Voltage
Voltage
RESERVED, SD, and TMP Pins
COMP Pin
RADJ Pin
Storage Temperature Range
Operating Temperature Range
Lead Temperature (Soldering 10 sec)1
Junction Temperature (TJ)
1
Rating
225 V
VCC to VEE
VCC to VEE
±2.0 V
±5 mA
VCC − 12 V to VEE
The maximum safe power dissipation in the package is limited
by the associated rise in TJ on the die. At approximately 150°C,
which is the glass transition temperature, the plastic begins to
change its properties. Exceeding a TJ of 150°C can result in changes
in the silicon devices, potentially causing failure. Table 3 shows the
junction-to-case thermal resistance (θJC) for the LFCSP. For
more detailed information on power dissipation and thermal
management, see the Applications Information section.
DGND to DGND + 6 V
VCC − 5 V to VCC
DGND to DGND + 0.6 V
−65°C to +150°C
−40°C to +85°C
260°C
150°C
THERMAL RESISTANCE
Thermal performance is directly linked to printed circuit board
(PCB) design and operating environment. Careful attention to
PCB thermal design is required.
θJA is the natural convection, junction to ambient thermal resistance
measured in a one cubic foot sealed enclosure. θJC is the junction
to case thermal resistance.
See IPC/JEDEC J-STD-020 for more information.
Stresses at or above those listed under Absolute Maximum
Ratings may cause permanent damage to the product. This is a
stress rating only; functional operation of the product at these
or any other conditions above those indicated in the operational
section of this specification is not implied. Operation beyond
the maximum operating conditions for extended periods may
affect product reliability.
Table 3. Thermal Resistance
Package Type
CP-12-81
1
θJA
37
θJC
1
Unit
°C/W
The data is collected from a 2S2P board. A cold plate is attached to the
bottom side of the PCB using 100 μm thermal interface material (TIM) for θJC
simulation. See JEDEC standard for additional information.
ESD CAUTION
Rev. B | Page 6 of 21
Data Sheet
ADHV4702-1
PIN CONFIGURATION AND FUNCTION DESCRIPTIONS
11 COMP
10 DGND
12 IN–
ADHV4702-1
9 RADJ
RESERVED 1
TOP VIEW
(Not to Scale)
TMP 5
OUT 6
7 VCC
VEE 4
RESERVED 3
8 SD
NOTES
1. RESERVED. THESE PINS ARE INTERNALLY CONNECTED.
FLOAT OR TIE THESE PINS TO THE DIGITAL GROUND.
2. EXPOSED THERMAL PAD. NO INTERNAL ELECTRICAL
CONNECTION. TIE EPAD TO EXTERNAL GROUND PLANE
AND/OR HEAT SINK FOR THERMAL MANAGEMENT.
16047-103
IN+ 2
Figure 4. Pin Configuration
Table 4. Pin Function Descriptions
Pin No.
1, 3
2
4
5
6
7
8
9
10
11
12
Mnemonic
RESERVED
IN+
VEE
TMP
OUT
VCC
SD
RADJ
DGND
COMP
IN−
EPAD
Description
Reserved. These pins are internally connected. Float or connect these pins to the digital ground.
Noninverting Input.
Negative Power Supply Input.
Temperature Monitor Output.
Output.
Positive Power Supply Input.
Shutdown (Active Low). SD is referenced to DGND.
Resistor Adjustable Quiescent Current. Connect RADJ to DGND to fully bias the amplifier.
Logic Reference for RADJ and SD. Connect DGND to 0 V analog ground.
External Compensation.
Inverting Input.
Exposed Thermal Pad. No internal electrical connection. Tie EPAD to external ground plane and/or heat sink for
thermal management.
Rev. B | Page 7 of 21
ADHV4702-1
Data Sheet
TYPICAL PERFORMANCE CHARACTERISTICS
50
NUMBER OF UNITS
40
35
POSITIVE IB
TEMPERATURE COEFFICIENT
MEAN: –0.37pA/°C
NEGATIVE I B
TEMPERATURE COEFFICIENT
MEAN: –0.30pA/°C
VCC PSRR
MEAN: 161dB
VEE PSRR
MEAN: 163dB
50
40
NUMBER OF HITS
45
30
25
20
15
10
30
20
10
–1.2
–0.9
–0.6
–0.3
0
0.3
0.6
0.9
IB TEMPERATURE COEFFICIENT (pA/°C)
0
120
140
160
180
200
PSRR (dB)
Figure 8. PSRR Distribution, TA = 25°C, VS = ±110 V, RADJ = 0 Ω
Figure 5. Positive and Negative Input Bias (IB) Current Drift Distribution,
TA = 25°C, VS = ±110 V, VCM = 0 V, ∆TA = 60°C, RADJ = 0 Ω
MEAN: 2.77mA
POSITIVE CMRR
MEAN: 161dB
NEGATIVE CMRR
MEAN: 163dB
70
25
60
20
NUMBER OF UNITS
NUMBER OF UNITS
16047-006
0
–1.5
16047-004
5
15
10
50
40
30
20
5
2.6
2.7
2.8
2.9
3.0
3.1
SUPPLY CURRENT (mA)
0
AVERAGE INPUT OFFSET VOLTAGE
FOR 50 DEVICES (µV)
NUMBER OF UNITS
25
20
15
10
–1.0
–0.5
0
0.5
1.0
1.5
16047-115
5
VOS TEMPERATURE COEFFICIENT (µV/°C)
170
180
190
200
210
220
30
30
–1.5
160
Figure 9. CMRR Distribution, TA = 25°C, VS = ±110 V, RADJ = 0 Ω
MEAN: –0.49µV/°C
35
0
–2.0
150
CMRR (dB)
Figure 6. Supply Current Distribution, TA = 25°C, VS = ±110 V, RADJ = 0 Ω
40
140
16047-007
2.5
20
10
0
–10
–20
–30
–40 –30 –20 –10
0
10
20
30
40
TEMPERATURE (°C)
Figure 7. Input Offset Voltage Drift Distribution, TA = 25°C, VS = ±110 V,
VCM = 0 V, ∆TJ = 60°C, RADJ = 0 Ω
50
60
70
80
16047-310
0
16047-114
10
Figure 10. Average Input Offset Voltage for 50 Devices vs. Temperature,
VS = ±110 V
Rev. B | Page 8 of 21
Data Sheet
ADHV4702-1
135
60
MEAN: ±0.15mV
300
50
30
150
45
20
10
AOL
100
0
0
50
–0.2
0
VOS (mV)
0.2
0.4
0.6
–20
10k
180
160
160
140
140
AOL (dB)
AOL
PHASE
180
135
80
90
100
80
45
60
60
40
40
0
20
20
1
10
100
1k
10k
FREQUENCY (Hz)
100k
1M
10M
16047-008
0.1
10
100
1k
10k 100k 1M
–45
10M 100M
FREQUENCY (Hz)
150
150
100
100
TA = –40°C
TA = 0°C
TA = +25°C
TA = +85°C
VOUT (V)
50
0
–50
–100
–100
16047-010
–50
TIME (1µs/DIV)
1
Figure 15. AOL and Phase Margin vs. Frequency, TA = 25°C, VS = ±110 V,
RADJ = 0 Ω
Figure 12. CMRR vs. Frequency, TA = 25°C, VS = ±110 V, RLOAD = 10 kΩ,
RADJ = 0 Ω
–150
0.1
16047-009
0
–20
0.001 0.01
TA = –40°C
TA = 0°C
TA = +25°C
TA = +85°C
–150
TIME (1µs/DIV)
Figure 13. Large Signal Pulse Response at Various TA, Rising Edge, AV = 20,
VS = ±110 V, VOUT = 200 V p-p, RF = 100 kΩ, RLOAD = 10 kΩ, RADJ = 0 Ω
16047-011
CMRR (dB)
100
VOUT (V)
–45
100M
120
120
0
10M
Figure 14. AOL and Phase Margin vs. Frequency at Various TA, VS = ±110 V,
RADJ = 0 Ω
180
50
1M
FREQUENCY (Hz)
Figure 11. Input Offset Voltage Distribution, TA = 25°C, VS = ±110 V,
VCM = 0 V, RADJ = 0 Ω
0
0.01
100k
PHASE MARGIN (Degrees)
–0.4
16047-311
0
–0.6
–10
TA = –40°C
TA = 0°C
TA = +25°C
TA = +85°C
16047-321
200
AOL (dB)
NUMBER OF UNITS
90
40
PHASE MARGIN (Degrees)
PHASE MARGIN
250
Figure 16. Large Signal Pulse Response at Various TA, Falling Edge, AV = 20,
VS = ±110 V, VOUT = 200 V p-p, RF = 100 kΩ, RLOAD = 10 kΩ, RADJ = 0 Ω
Rev. B | Page 9 of 21
ADHV4702-1
150
150
100
100
50
–40°C
0
VOUT (V)
50
VOUT (V)
Data Sheet
TA = 0°C
TA = +25°C
TA = +85°C
TA = 0°C
TA = +25°C
TA = +85°C
0
–50
–50
–100
–100
–150
TIME (2µs/DIV)
Figure 17. Large Signal Pulse Response at Various TA, Rising Edge, AV = 40,
VS = ±110 V, VOUT = 200 V p-p, RF = 100 kΩ, RLOAD = 10 kΩ, RADJ = 0 Ω
–150
TIME (2µs/DIV)
Figure 20. Large Signal Pulse Response at Various TA, Falling Edge, AV = 40,
VS = ±110 V, VOUT = 200 V p-p, RF = 100 kΩ, RLOAD = 10 kΩ, RADJ = 0 Ω
150
AV = 20
AV = 40
AV = 20
AV = 40
100
100
50
50
VOUT (V)
0
–50
–100
–100
16047-016
–50
–150
TIME (1µs/DIV)
Figure 18. Large Signal Pulse Response at Various Gains, Rising Edge,
TA = 25°C, VS = ±110 V, VOUT = 200 V p-p, RF = 100 kΩ, RLOAD = 10 kΩ,
RADJ = 0 Ω
–150
TIME (1µs/DIV)
Figure 21. Large Signal Pulse Response at Various Gains, Falling Edge,
TA = 25°C, VS = ±110 V, VOUT = 200 V p-p, RF = 100 kΩ, RLOAD = 10 kΩ,
RADJ = 0 Ω
1
150
AV = 20
AV = 40
0
100
–1
–2
GAIN (dB)
50
VOUT (V)
16047-017
0
0
–50
–3
–4
–5
–6
–7
–100
–150
TIME (100µs/DIV)
16047-015
–8
Figure 19. Large Signal Pulse Response at Various Gains, TA = 25°C,
VS = ±110 V, VOUT = 200 V p-p, RF = 100 kΩ, RLOAD = 10 kΩ, RADJ = 0 Ω
–9
100
VOUT = 50V p-p
VOUT = 100V p-p
VOUT = 150V p-p
VOUT = 200V p-p
1k
10k
FREQUENCY (Hz)
100k
1M
16047-202
VOUT (V)
150
16047-013
16047-012
TA = –40°C
Figure 22. Large Signal Frequency Response at Various Output Swings with
Input Clamping Diodes (See the Slew Boost Circuit and Protection Section),
TA = 25°C, AV = 40, VS = ±110 V, RF = 100 kΩ, RLOAD = 10 kΩ, RADJ = 0 Ω
Rev. B | Page 10 of 21
Data Sheet
ADHV4702-1
1
70
0
50
–1
VOUT (mV)
–4
–5
–6
–9
100
–10
–30
VOUT = 50V p-p
VOUT = 100V p-p
VOUT = 150V p-p
VOUT = 200V p-p
1k
–50
10k
100k
1M
FREQUENCY (Hz)
–70
16047-201
–8
10
16047-018
GAIN (dB)
–3
–7
AV = 1, RF = 0Ω
AV = 20, RF = 100kΩ
AV = 40, RF = 100kΩ
30
–2
TIME (100µs/DIV)
Figure 23. Large Signal Frequency Response at Various Output Swings with
Input Clamping Diodes (See the Slew Boost Circuit and Protection Section),
TA = 25°C, AV = 20, VS = ±110 V, RF = 100 kΩ, RLOAD = 10 kΩ, RADJ = 0 Ω
Figure 26. Small Signal Pulse Response at Various Gains, TA = 25°C,
VS = 110 V, VOUT = 100 mV p-p, RLOAD = 10 kΩ, RADJ = 0 Ω
70
70
AV = 1, RF = 0Ω
AV = 20, RF = 100kΩ
AV = 40, RF = 100kΩ
50
50
30
VOUT (mV)
10
–10
0
–10
–30
–30
–70
TIME (500ns/DIV)
–50
16047-019
AV = 1, RF = 0Ω
AV = 20, RF = 100kΩ
AV = 40, RF = 100kΩ
–50
–70
TIME (500ns/DIV)
Figure 24. Small Signal Pulse Response at Various Gains, Rising Edge,
TA = 25°C, VS = ±110 V, VOUT = 100 mV p-p, RLOAD = 10 kΩ, RADJ = 0 Ω
Figure 27. Small Signal Pulse Response at Various Gains, Falling Edge,
TA = 25°C, VS = ±110 V, VOUT = 100 mV p-p, RLOAD = 10 kΩ, RADJ = 0 Ω
35
3
TA = –40°C
RF = 0Ω, AV = 1
RF = 100kΩ, AV = 20
RF = 100kΩ, AV = 40
30
25
0
TA = 0°C
TA = +25°C
TA = +85°C
GAIN (dB)
20
–3
15
10
5
–6
–5
–9
0.1
1
10
100
FREQUENCY (MHz)
Figure 25. Small Signal Frequency Response at Various TA, AV = 1,
VS = ±110 V, VOUT = 100 mV p-p, RL = 10 kΩ, RADJ = 0 Ω
VS = ±110V
VOUT = 100mV p-p
RL = 10kΩ
–10
10k
100k
1M
FREQUENCY (Hz)
10M
100M
16047-014
0
16047-312
GAIN (dB)
10
16047-020
VOUT (mV)
30
Figure 28. Small Signal Frequency Response at Various Gains, TA = 25°C,
VS = ±110 V, VOUT = 100 mV p-p, RL = 10 kΩ, RADJ = 0 Ω
Rev. B | Page 11 of 21
ADHV4702-1
Data Sheet
150
INTEGRATED NOISE (µV rms)
OUTPUT IMPEDANCE (Ω)
100
10
1
0.01
1k
10k
100k
1M
10M
100M
FREQUENCY (Hz)
10k
100k
1M
FREQUENCY (Hz)
10M
100M
Figure 32. Integrated Noise vs. Frequency, TA = 25°C, VS = ±110 V,
RADJ = 0 Ω
VS = ±110V
INVERTING IB
NONINVERTING IB
3
2
OUTPUT NOISE (100nV/DIV)
INPUT BIAS CURRENT (pA)
50
0
1k
Figure 29. Output Impedance vs. Frequency, TA = 25°C, AV = 1,
VS = ±110 V, VOUT = 100 mV p-p, RF = 0 Ω, RADJ = 0 Ω
4
100
16047-203
0.1
VS = ±110V
16047-104
1000
1
0
–1
–2
–3
0
50
100
COMMON-MODE VOLTAGE (V)
TIME (1s/DIV)
Figure 33. 0.1 Hz to 10 Hz Noise
Figure 30. Input Bias Current vs. Common-Mode Voltage, TA = 25°C,
VS = ±110 V, RADJ = 0 Ω
100k
INPUT CURRENT NOISE (fA/√Hz)
VS = ±110V
100
10
1
1
10
100
1k
FREQUENCY (Hz)
10k
100k
10k
1k
100
10
1
0.1
16047-106
INPUT VOLTAGE NOISE (nV/√Hz)
1000
16047-233
–50
1
10
100
1k
10k
100k
1M
10M
FREQUENCY (Hz)
Figure 34. Input Current Noise vs. Frequency
Figure 31. Input Voltage Noise vs. Frequency, TA = 25°C, VS = ±110,
RADJ = 0 Ω
Rev. B | Page 12 of 21
100M
16047-234
–5
–100
16047-204
–4
ADHV4702-1
0
–15
10
–20
0
0
100
200
300
400
500
600
700
–25
900
800
TIME (Seconds)
1.8
1.6
OUTPUT HEADROOM (V)
RLOAD = 5kΩ, POSITIVE VOUT
1.2
1.0
RLOAD = 5kΩ, NEGATIVE VOUT
0.8
0.6
RLOAD = 10kΩ, POSITIVE VOUT
0.4
RLOAD = 10kΩ, NEGATIVE VOUT
0
–40 –30 –20 –10
0
10
20
30
40
50
60
70
80
90
AMBIENT TEMPERATURE (°C)
16047-303
0.2
Figure 36. Output Headroom vs. Ambient Temperature at Various RLOAD,
VS = ±110 V, RADJ = 0 Ω
TA = +85°C
TA = +50°C
TA = +25°C
TA = –40°C
2.8
2.7
2.6
12
22
32
42
52
62
+VS (V)
72
82
92
102
112
16047-305
QUIESCENT CURRENT (mA)
3.0
2.9
–50
VOUT = 200 V p-p
VOUT = 150 V p-p
VOUT = 100 V p-p
VOUT = 50 V p-p
–60
–70
–80
–90
10
100
1k
10k
FREQUENCY (Hz)
Figure 38. Total Harmonic Distortion and Noise vs. Frequency at Various
Large Output Swings, TA = 25°C, AV = 20, VS = ±110 V, RF = 100 kΩ,
RLOAD = 10 kΩ, RADJ = 0 Ω
Figure 35. Offset Voltage Warmup Drift and TJ, VS = ±110, RADJ = 0 Ω
1.4
–40
Figure 37. Quiescent Current vs. Positive Supply Voltage at Various TA,
RADJ = 0 Ω
–20
WITH INPUT CLAMPING DIODES
WITHOUT INPUT CLAMPING DIODES
–30
–40
–50
VOUT = 200 V p-p
VOUT = 150 V p-p
VOUT = 100 V p-p
VOUT = 50 V p-p
–60
–70
–80
–90
10
100
1k
10k
FREQUENCY (Hz)
16047-307
20
WITH INPUT CLAMPING DIODES
WITHOUT INPUT CLAMPING DIODES
–30
Figure 39. Total Harmonic Distortion and Noise vs. Frequency at Various
Large Output Swings, TA = 25°C, AV = 40, VS = ±110 V, RF = 100 kΩ,
RLOAD = 10 kΩ, RADJ = 0 Ω
–30
–40
–50
VOUT = 200 Vp-p
VOUT = 150 Vp-p
VOUT = 100 Vp-p
VOUT = 50 Vp-p
–60
HD3
–70
–80
VOUT = 200 Vp-p
VOUT = 150 Vp-p
VOUT = 100 Vp-p
VOUT = 50 Vp-p
–90
–100
HD2
–110
–120
–130
10
100
1k
FREQUENCY (Hz)
10k
16047-308
–10
TOTAL HARMONIC DISTORTION AND NOISE (dBc)
VOS (µV)
30
VOS (µV)
–5
40
SECOND AND THIRD HARMONIC DISTORTION (dBc)
50
16047-302
JUNCTION TEMPERATURE (°C)
TJ (°C)
–20
16047-306
5
60
TOTAL HARMONIC DISTORTION AND NOISE (dBc)
Data Sheet
Figure 40. Second Harmonic Distortion (HD2) and Third Harmonic Distortion
(HD3) vs. Frequency at Various Output Swings, TA = 25°C, AV = 20, VS = ±110 V,
RF = 100 kΩ, RLOAD = 10 kΩ, RADJ = 0 Ω
Rev. B | Page 13 of 21
Data Sheet
–30
100
–40
90
80
VOUT = 200 Vp-p
VOUT = 150 Vp-p
VOUT = 100 Vp-p
VOUT = 50 Vp-p
HD3
70
PSRR (dB)
–70
–80
–90
VOUT = 200 Vp-p
VOUT = 150 Vp-p
VOUT = 100 Vp-p
VOUT = 50 Vp-p
–100
–110
40
20
10
10
100
1k
10k
Figure 41. Second Harmonic Distortion (HD2) and Third Harmonic Distortion
(HD3) vs. Frequency at Various Output Swings, TA = 25°C, AV = 40, VS = ±110 V,
RF = 100 kΩ, RLOAD = 10 kΩ, RADJ = 0 Ω
0
100
160
114
100k
1M
112
AMPLITUDE (V)
+PSRR
80
60
110
108
VOUT
106
104
40
102
20
1
10
100
1k
FREQUENCY (Hz)
10k
100k
1M
100
16047-322
0.1
10k
VIN
–PSRR
100
0
1k
Figure 43. PSRR vs. Frequency at Various TA, VS = ±110 V, RLOAD = 10 kΩ,
RADJ = 0 Ω
116
120
TA = –40°C
TA = 0°C
TA = +25°C
TA = +85°C
FREQUENCY (Hz)
180
140
+PSRR
30
FREQUENCY (Hz)
PSRR (dB)
50
HD2
–120
–130
60
16047-323
–60
–PSRR
Figure 42. PSRR vs. Frequency, TA = 25°C, VS = ±110 V, RLOAD = 10 kΩ,
RADJ = 0 Ω
TIME (5µs/DIV)
16047-325
–50
16047-309
SECOND AND THIRD HARMONIC DISTORTION (dBc)
ADHV4702-1
Figure 44. Output Overdrive Recovery, VS = ±110 V, AV = 40, RLOAD = 10 kΩ,
RADJ = 0 Ω
Rev. B | Page 14 of 21
Data Sheet
ADHV4702-1
THEORY OF OPERATION
The ADHV4702-1 is a high voltage (220 V) precision amplifier
designed using the next generation of proprietary bipolar/
complementary metal-oxide semiconductor (CMOS)/laterally
diffused metal-oxide semiconductor (BCDMOS) process from
Analog Devices. Figure 3 shows the functional block diagram.
The input stage architecture offers the advantages of high input
impedance with low input bias current, low input offset voltage,
low drift, and low noise for precision demanding applications,
such as automated test equipment (ATE).
INTERNAL ELECTROSTATIC DISCHARGE (ESD)
PROTECTION
As shown in Figure 45, the ADHV4702-1 has an internal ESD
configuration to prevent damage due to overvoltage. The ESD
protection circuitry involves current steering diodes connected
from the input and output pins to the power supply rails. The
ADHV4702-1 also includes internal input clamping diodes across
the inverting and noninverting inputs to prevent large differential
input voltages from damaging the input stage transistors. This
input clamping circuit greatly reduces the input impedance for
differential input voltages greater than the forward-biased
voltage (VF) of four diodes.
The ESD protection circuitry remains inactive under normal
operation. To avoid forward biasing the ESD diodes, do not
overdrive the pin voltages above the absolute maximum ratings,
and ensure that the input differential voltage does not exceed
4 VF. Additional external input clamping diodes may be
required to protect the slew boost circuit. See the Slew Boost
Circuit and Protection section.
IN–
COMP
DGND
12
11
10
125Ω
~5V
RESERVED 1
9
RADJ
8
SD
7
VCC
VEE VCC
~5V
DGND
DGND
125Ω
IN+ 2
~5V
DGND
RESERVED 3
~5V
DGND
225V ESD
SLEW BOOST CIRCUIT AND PROTECTION
The ADHV4702-1 uses a supplementary slew boosting circuit
to achieve its typical slew rate of 74 V/μs across a 200 V p-p
output range at unity gain. This slew boosting circuit works by
sensing the differential input voltage of the amplifier and
converting this voltage into a dynamic current to help drive
capacitances within the signal path of the amplifier. With
greater input voltage across the inputs, more dynamic current is
produced, which enables the amplifier to slew faster. The
current produced by the slew boosting circuit transmits to all
stages of the amplifier during slewing.
Internally, the ADHV4702-1 contains differential input voltage
clamps that limit transient differential signals to 4 VF, placing an
upper limit on the slew boost. Large differential input voltages
(which can be occur with signal frequencies approaching the
full power bandwidth) trigger the slew boosting circuit,
resulting in an increased dynamic supply current. The
relationship between slew rate and full power bandwidth (fM) is
given in the following equation:
SR = VO × 2πfM
where VO is the peak output voltage.
When operating continuously at or near full power bandwidth,
the increased supply current may cause an increase in TJ
beyond the safe operating temperature, resulting in device
damage. The dynamic safe operating area (SOA) for the EVALADHV4702-1CPZ evaluation board is shown in Figure 61 in
the Safe Operating Area section. The dynamic SOA shows the
connection between the output swing and the maximum
input/output frequency for pulse response. To expand the SOA
curve, use additional thermal management or limit the
differential voltage across the inputs to 2 VF with external
diodes, which limits the current produced by the slew boosting
circuit and reduces the internal power dissipation. Clamping
the differential input voltage of the ADHV4702-1 in this way
protects the amplifier in dynamic operation but limits slew rate
and large signal bandwidth. Figure 46 shows a simplified
schematic with external input clamping diodes, and Figure 47 to
Figure 50 show the large signal pulse response at various
temperatures and gains while the ADHV4702-1 inputs are
clamped by two ON Semiconductor SBAV199LT1G diode pairs
at 2 VF.
5kΩ
100kΩ
5
6
VEE
TMP
OUT
Figure 45. Simplified ESD Configuration
ADHV4702-1
EXTERNAL
INPUT
CLAMPING
DIODES
VOUT
10kΩ
VIN
16047-133
4
16047-032
~5V
DGND
Figure 46. External Input Clamping Diodes Schematic
Rev. B | Page 15 of 21
ADHV4702-1
Data Sheet
150
100
100
0
50
TA = –40°C
TA = 0°C
TA = +25°C
TA = +85°C
VOUT (V)
VOUT (V)
50
0
–50
–100
–100
TIME (2µs/DIV)
16047-141
–50
–150
Figure 47. Large Signal Pulse Response at Various TA with Two-Diode
Forward Voltages, Rising Edge, AV = 20, VS = ±110 V, VOUT = 200 V p-p,
RF = 100 kΩ, RLOAD = 10 kΩ, RADJ = 0 Ω
150
AMPLITUDE (V)
TA = –40°C
TA = 0°C
TA = +25°C
TA = +85°C
RESISTOR ADJUSTABLE QUIESCENT CURRENT
(RADJ)
–50
–150
TIME (2µs/DIV)
16047-142
–100
Figure 48. Large Signal Pulse Response at Various TA with Two-Diode
Forward Voltages, Falling Edge, AV = 20, VS = ±110 V, VOUT = 200 V p-p,
RF = 100 kΩ, RLOAD = 10 kΩ, RADJ = 0 Ω
150
100
50
VOUT (V)
TIME (2µs/DIV)
Figure 50. Large Signal Pulse Response at Various TA with Two-Diode
Forward Voltages, Falling Edge, AV = 40, VS = ±110 V, VOUT = 200 V p-p,
RF = 100 kΩ, RLOAD = 10 kΩ, RADJ = 0 Ω
DGND is the reference for all low voltage pins of the amplifier
(RADJ, TMP, and SD) and serves as a signal ground for
communication to a microprocessor or other low voltage logic
circuit. Connect DGND to a 0 V digital ground or analog
ground. Do not float DGND.
0
0
–150
DIGITAL GROUND (DGND)
100
50
TA = –40°C
TA = 0°C
TA = +25°C
TA = +85°C
16047-144
150
TA = –40°C
TA = 0°C
TA = +25°C
TA = +85°C
To reduce further power consumption, the quiescent current of
the ADHV4702-1 can be adjusted by placing a resistor (RADJ)
between the RADJ pin and DGND.
To fully bias the amplifier, short the RADJ pin directly to
DGND to allow maximum dynamic performance. To bias the
amplifier with minimum quiescent power consumption, place a
100 kΩ resistor from RADJ to DGND. This resistor reduces
quiescent supply current to approximately 0.6 mA. Operating
the amplifier at a lower quiescent current has minimal effect on
dc performance but can result in an associated reduction in
dynamic performance, such as bandwidth and noise. Figure 51
and Figure 52 show the small signal frequency response and
noise performance at various RADJ values.
2
–50
1
0
–100
Figure 49. Large Signal Pulse Response at Various TA with Two-Diode
Forward Voltages, Rising Edge, AV = 40, VS = ±110 V, VOUT = 200 V p-p,
RF = 100 kΩ, RLOAD = 10 kΩ, RADJ = 0 Ω
GAIN (dB)
–2
–3
–4
–5
–6
–7
–8
1k
10k
100k
1M
FREQUENCY (Hz)
10M
100M
16047-205
TIME (2µs/DIV)
16047-143
–150
RADJ = 0Ω
RADJ = 50kΩ
RADJ = 100kΩ
–1
Figure 51. Small Signal Frequency Response at Various RADJ, TA = 25°C, AV = 1,
VS = ±110 V, VOUT = 100 mV p-p, RF = 0 Ω, RLOAD = 10 kΩ
Rev. B | Page 16 of 21
ADHV4702-1
100
RADJ = 100kΩ
RADJ = 50kΩ
RADJ = 0Ω
10
3.5
7
3.0
6
2.5
5
2.0
4
3
1.5
SUPPLY CURRENT
1.0
2
0.5
1
0
0
1
10
100
1k
10k
100k
FREQUENCY (Hz)
–0.5
16047-317
1
SD VOLTAGE
–1
TIME (50µs/DIV)
16047-314
SUPPLY CURRENT (mA)
INPUT VOLTAGE NOISE (nV√Hz)
1000
SD VOLTAGE (V)
Data Sheet
Figure 54. SD Pin Response Time, Turning Off
Figure 52. Input Voltage Noise at Various RADJ, TA = 25°C, VS = ±110
SHUTDOWN PIN (SD)
TEMPERATURE MONITOR (TMP)
The ADHV4702-1 is equipped with a power saving shutdown
feature. When the SD pin voltage is brought low to within 0.8 V
of DGND, the amplifier is disabled and put in a low power state,
reducing its quiescent current to approximately 0.18 mA. The
SD pin has an internal approximately 400 kΩ pull-up resistor
that enables the amplifier if SD is left floating. When turning
the amplifier on from the shutdown state, pull the SD pin high to
at least 1.6 V above the DGND pin. The SD pin response time
for starting up and coming out of shutdown is shown in
Figure 53 and Figure 54. The SD pin can support digital logic
levels down to 2.5 V. The SD pin can be used to implement
thermal shutdown and short-circuit protection when used in
conjunction with the temperature monitor feature of the
ADHV4702-1.
The ADHV4702-1 features an on-chip temperature sensor in
close proximity to the output stage, where die temperature is the
highest. The output voltage of the temperature sensor appears at
the TMP pin. As an approximate indicator of die temperature,
TMP voltage can be used to monitor power dissipation and
implement thermal shutdown. The TMP voltage at room
temperature is nominally 1.9 V, changing at approximately
−4.5 mV/°C, as shown in Figure 55. More precise temperature
readings can be achieved through a one-time room temperature
calibration of the TMP pin.
5
2.0
SD VOLTAGE
4
1.5
3
1.0
2
0.5
1
0
0
2.0
1.8
1.6
1.4
1.2
–60
–40
–20
0
20
40
60
80
100
120
JUNCTION TEMPERATURE (°C)
140
16047-319
2.5
SD VOLTAGE (V)
6
Figure 55. TMP Pin Voltage vs. Junction Temperature
–0.5
TIME (50µs/DIV)
Figure 53. SD Pin Response Time, Turning On
–1
16047-313
SUPPLY CURRET (mA)
SUPPLY CURRENT
3.0
2.2
TMP PIN VOLTAGE (V)
7
3.5
2.4
OVERTEMPERATURE PROTECTION
Operation at or beyond the operating temperature specified
in the Absolute Maximum Ratings section can affect product
reliability. To minimize this risk, the ADHV4702-1 features an
optional, resistor programmable thermal shutdown where the
TMP pin voltage asserts the SD pin. In addition to proper heat
sinking, thermal shutdown is recommended to protect the
amplifier from an overtemperature condition. To implement the
thermal shutdown function, tie TMP to SD, as shown in Figure 56,
and connect a 200 kΩ resistor (RTMP) from TMP and SD to
DGND in close proximity to the ADHV4702-1.
Rev. B | Page 17 of 21
ADHV4702-1
Data Sheet
Device to device variation in the TMP pin voltage may result in
different shutdown threshold temperatures or shutdown
response times among various devices while implementing the
200 kΩ RTMP. The shutdown threshold can be adjusted with a
smaller RTMP resistance, yielding a lower threshold temperature.
The RTMP together with the internal resistors of TMP form a
voltage divider that influences the TMP pin reading and TMP
voltage drift. The TMP data in Table 1 and the Temperature
Monitor (TMP) section is only valid when RTMP is uninstalled.
~5.3V
400kΩ
SD
8
120kΩ
HIGH IMPEDANCE
NODE
In addition to the series resistor, the ADHV4702-1 includes an
optional external compensation feature for driving capacitive
loads. A capacitor (CCOMP) can be installed between COMP and
OUT to reduce output stage peaking associated with capacitive
loads. CCOMP must be rated for the full supply differential.
Figure 60 shows the effect of CCOMP on various capacitive loads.
The values shown in Figure 58, Figure 59, and Figure 60 are for
unity gain configuration with a purely CLOAD. This is a worst
case scenario because the amplifier is more stable at higher
gains and with some resistive load in parallel with the load
capacitance. Although the RS or CCOMP significantly increases
the stability while driving CLOAD, they also reduce the headroom
and bandwidth while driving a resistive load. For resistive loads,
leave the COMP pin floating.
VIN
RS
~5.3V
100kΩ
5kΩ
5
140kΩ
Figure 57. Circuit for CLOAD Drive
160
Figure 56. TMP and SD Pin Configuration for Short-Circuit Protection and
Thermal Shutdown
140
120
OUTPUT CURRENT DRIVE AND SHORT-CIRCUIT
PROTECTION
EXTERNAL COMPENSATION AND CAPACITIVE
LOAD (CLOAD) DRIVING
80
60
40
20
0
10p
100p
1n
10n
1µ
Figure 58. RS vs. CLOAD for Maximum 2 dB Peaking for Circuit from Figure 57,
TA = 25°C, AV = 1, VS = ±110 V, VOUT = 100 mV p-p, RF = 0 Ω, RADJ = 0 Ω
3
RS = 50Ω
0
–3
GAIN (dB)
When driving a CLOAD, the amplifier output resistance and the
load capacitance form a pole in the transfer function of the
amplifier. This additional pole reduces phase margin at higher
frequencies and, if left uncompensated, can result in excessive
peaking and instability. Placing a series resistor (RS) between the
amplifier output and CLOAD (as shown in Figure 57) allows the
ADHV4702-1 to drive capacitive loads beyond 1 μF. Figure 58
shows the series resistor value vs. load capacitance for a
maximum of 2 dB peaking in the circuit of Figure 57.
100n
CLOAD (F)
16047-202
The ADHV4702-1 uses an output stage constructed with
cascaded, double diffused, metal-oxide-semiconductor
(DMOS) high voltage transistors that provide wide output
swing. The ADHV4702-1 can typically drive a 20 mA load
current continuously. Though with proper thermal management,
the ADHV4702-1 can deliver up to 50 mA. Short-circuit
protection is provided by means of the thermal shutdown
feature. To enable short-circuit protection, connect the SD and
TMP pins, and tie both to DGND with a 200 kΩ RTMP.
RS (Ω)
100
RS = 57.6Ω,
CLOAD = 1nF
–6
–9
RS = 130Ω,
CLOAD = 200pF
–12
–15
–18
10k
RS = 2.21Ω,
CLOAD = 1µF
100k
1M
FREQUENCY (Hz)
10M
100M
16047-326
DGND
16047-035
DGND
CLOAD
ITMP
TMP
16047-320
RTMP
Figure 59. Small Signal Response for Various CLOAD and RS Values, TA = 25°C,
AV = 1, VS = ±110 V, VOUT = 100 mV p-p, RF = 0 Ω, RADJ = 0 Ω
Rev. B | Page 18 of 21
ADHV4702-1
230
2
210
0
–1
–2
–3
–4
–5
–6
–7
–8
–9
100k
CLOAD
CLOAD
CLOAD
CLOAD
= 200pF
= 200pF, CCOMP = 5.6pF
= 1nF
= 1nF, CCOMP = 6.8pF
1M
190
170
150
130
110
TA = 25°C
90
70
50
30
10M
EXTERNAL COMPENSATION (Hz)
100M
Figure 60. Small Signal Frequency Response vs. External Compensation,
TA = 25°C, AV = 1, VS = ±110 V, VOUT = 100 mV p-p, RF = 0 Ω, RADJ = 0 Ω
10
TA = 85°C
0
The dc SOA is a curve of output current vs. the voltage across
the output stage, which is the voltage difference between supply
and output (VS − VOUT) under which the amplifier can operate
at a safe TJ. The areas under the curves of Figure 62 show the
operational boundaries of the ADHV4702-1 that maintain a TJ
≤ 150°C.
The SOA curves are unique to the conditions under which they
were developed, such as PCB, heat sink, and TA. All testing was
performed in a still air environment. Forced air convection in
any of the test cases effectively lowers θJA and expands the SOA.
40k
60k
80k
100k
120k
140k
160k
Figure 61. Dynamic SOA at TA = 25°C and TA = 85°C With and Without Input
Clamping Diodes, AV = 20, VS = ±110 V, RF = 100 kΩ, RLOAD = 10 kΩ, RADJ = 0 Ω
55
MAXIMUM TJ = 150°C
50
45
OUTPUT CURRENT (mA)
The power dissipation of the ADHV4702-1 occurs primarily
from the slew boosting circuit and output stage. The slew
boosting circuit requires additional supply current. Operating
the amplifier at its maximum slew rate at larger swing or at a
high frequency increases the current consumption of the slew
boosting circuit, increasing the TJ. Figure 61 shows the dynamic
SOA that maintains a TJ less than 150°C. The curve shows the
maximum safe square wave frequency for a given amplitude.
Operating the ADHV4702-1 outside of the boundaries can
cause permanent damage. Using additional thermal
management or input clamping diodes expands the dynamic
SOA significantly. However, using input clamping diodes can
compromise the slew rate and the large signal bandwidth.
20k
INPUT/OUTPUT FREQUENCY (Hz)
SAFE OPERATING AREA
The SOA represents the power handling capability of the device
under various conditions.
WITH DIODES
WITHOUT DIODES
40
35
TA = 25°C
30
25
20
15
TA = 85°C
10
5
5
15
25
35
45
55
65
75
85
95
105
SUPPLY TO VOUT DIFFERENTIAL (V)
115
16047-318
1
MAXIMUM TJ = 150°C
16047-315
PEAK-TO-PEAK OUTPUT SWING (V)
3
16047-304
SMALL SIGNAL FREQUENCY RESPONSE (dB)
Data Sheet
Figure 62. DC SOA at TA = 25°C and TA = 85°C, AV = 20, VS = ±110 V, RF =
100 kΩ, RADJ = 0 Ω
LFCSP PACKAGE AND HIGH VOLTAGE PIN
SPACING
A 7 mm × 7 mm, 12-lead LFCSP with EPAD was selected for the
ADHV4702-1 to provide high reliability and compliance to
regional and global high voltage standards regarding dielectric
withstanding (clearance) and carbonization of package surface
(creepage). The package dimensions are shown in Figure 66.
The ADHV4702-1 meets the minimum 1.25 mm spacing
requirement of IEC Standard 61010-1 for creepage distance
to preclude failure due to carbon tracking at 250 V rms. To
maintain these protections, it is essential to remove all flux and
soldering residue around the package pins and exposed pad. Refer
to the IEC 61010-1 standard for additional information.
EXPOSED PAD (EPAD)
The copper EPAD of the LFCSP provides a thermally conductive
path to the PCB, which can be attached to a heat sink to improve
heat dissipation. There is no internal electrical connection to
the EPAD. High voltage isolation allows the EPAD to be safely
biased to a 0 V ground plane, regardless of VCC or VEE voltages.
Rev. B | Page 19 of 21
ADHV4702-1
Data Sheet
APPLICATIONS INFORMATION
POWER SUPPLY AND DECOUPLING
HIGH CURRENT OUTPUT DRIVER
The ADHV4702-1 can operate from a single supply or dual
supply. The total supply voltage (VCC − VEE) must be between
24 V and 220 V. The ADHV4702-1 requires a minimum supply
voltage of ±12 V from the reference voltage for normal
operation. Decouple each supply pin to ground using high
quality, low effective series resistance (ESR), 0.1 μF capacitors.
Place decoupling capacitors as close to the supply pins as possible.
Additionally, place 1.2 μF tantalum capacitors from each supply
to ground to provide sufficient low frequency decoupling and
supply the needed current to support large, fast slewing signals
at the ADHV4702-1 output. To ensure reliable operation under
high voltages, the voltage ratings for the bypass capacitors must
be higher than the supply voltages of the ADHV4702-1.
Figure 64 shows a system level application of the ADHV4702-1
that boosts the output current drive of the amplifier. By introducing
a discrete unity-gain output stage, the ADHV4702-1 can be
used as a high power output driver retaining the precision
performance capabilities of the standalone amplifier, such as
offset, drift, open-loop gain, and CMRR, while increasing the
output current drive up to the current handling capabilities of
the discrete devices.
N CHANNEL
ADHV4702-1
+VS
+
Figure 64. High Current Output Driver Schematic
SIGNAL RANGE EXTENDER
Figure 65 shows an example of a signal range extender
configuration. By introducing two additional high power, discrete,
metal-oxide semiconductor field effect transistors (MOSFETs), the
range extender can deliver at least twice the signal range
(depending on the MOSFET selection), while retaining the original
performance characteristics of the amplifier.
The ADHV4702-1 can be combined with a dual, 16-bit
voltage output, DAC, such as the AD5752R, to produce a
versatile high voltage DAC solution. For this configuration,
set up the ADHV4702-1 as a voltage subtractor with a gain
of 20, which is ideally suited for chemical analysis (mass
spectrometry), piezodrive, scanning electron microscope
(SEM), LiDAR APD/SPAD, and silicon photomultiplier bias
control applications.
+VS
RTOP
ADHV4702-1
VIN
ADHV4702-1
RS
RBOT
HVOUT_SENSE
Figure 63. ADHV4702-1 Configured as a Voltage Subtractor Using DACs
Rev. B | Page 20 of 21
–VS
RFB
Figure 65. Voltage Extender Schematic
16047-130
–VS
–VS
40kΩ
RLOAD
RTOP
HVOUT_FORCE
2.5kΩ
VOUT
P CHANNEL
2kΩ
VOUTB
RBOT
+
RG
+VS
16047-002
DIN2 n
+VS
N CHANNEL
2kΩ
VOUTA
16047-129
P CHANNEL
RFB
HIGH VOLTAGE DAC VOLTAGE SUBTRACTOR
DIN1
RLOAD
RG
The ADHV4702-1 features a pin placement that facilitates the
use of a guard ring around the noninverting input of the
amplifier. Guarding minimizes leakage from nearby pins and
helps to achieve the benefit of low input bias current. The guard
must be free of solder mask so that it remains exposed on the
surface of the PCB. Drive the guard ring to a potential that
tracks the input of the amplifier.
40kΩ
VOUT
R5
–VS
HIGH VOLTAGE GUARD RING
n
R3
VIN
Data Sheet
ADHV4702-1
OUTLINE DIMENSIONS
DETAIL A
(JEDEC 95)
7.10
7.00 SQ
6.90
10
1.70
BSC
PIN 1
IN D IC ATO R AR E A OP T IO N S
(SEE DETAIL A)
12
1
9
2.90
2.80 SQ
2.70
EXPOSED
PAD
7
0.55
0.50
0.45
0.80
0.75
0.70
SIDE VIEW
0.05 MAX
0.02 NOM
COPLANARITY
0.08
0.203 REF
BOTTOM VIEW
FOR PROPER CONNECTION OF
THE EXPOSED PAD, REFER TO
THE PIN CONFIGURATION AND
FUNCTION DESCRIPTIONS
SECTION OF THIS DATA SHEET.
PKG-005281
SEATING
PLANE
3
4
6
08-23-2018-A
PIN 1
INDICATOR
AREA
0.35
0.30
0.25
Figure 66. 12-Lead Lead Frame Chip Scale Package [LFCSP]
7 mm × 7 mm Body and 0.75 mm Package Height
(CP-12-8)
Dimensions shown in millimeters
ORDERING GUIDE
Model1
ADHV4702-1BCPZ
ADHV4702-1BCPZ-R7
EVAL-ADHV4702-1CPZ
1
Temperature Range
−40°C to +85°C
−40°C to +85°C
Package Description
12-Lead Lead Frame Chip Scale Package [LFCSP]
12-Lead Lead Frame Chip Scale Package [LFCSP]
Evaluation Board
Z = RoHS Compliant Part.
©2018–2020 Analog Devices, Inc. All rights reserved. Trademarks and
registered trademarks are the property of their respective owners.
D16047-0-1/20(B)
Rev. B | Page 21 of 21
Package Option
CP-12-8
CP-12-8
