Data Sheet
ADIN1110
Robust, Industrial, Low Power 10BASE-T1L Ethernet MAC-PHY
FEATURES
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APPLICATIONS
10BASE-T1L IEEE Standard 802.3cg-2019 compliant
Integrated MAC with SPI
► SPI supporting 10 Mbps full duplex
► Supports OPEN Alliance 10BASE-T1x MAC-PHY serial
interface
Low power consumption: dual supply 42 mW typical
Supports 1.0 V p-p and 2.4 V p-p transmit levels
Autonegotiation capability
Supports intrinsic safety applications
External termination resistors
Separate receive and transmit pins
MDIO memory map accessible via SPI
On-chip FIFOs: 20 kB receive, 8 kB transmit (configurable)
► Cut through or store and forward operation
► Receive high and low priority queues
► IEEE 1588 timestamp support
► Statistics counters
► 16 MAC addresses supported for frame filtering
Unmanaged configuration using pin strapping including
► Master/slave selection
► Transmit amplitude
25 MHz crystal oscillator/25 MHz external clock input
Single supply 1.8 V/3.3 V operation (mode dependent)
Cable reach
► Up to 1700 meters with 1.0 V p-p
► Up to 1700 meters with 2.4 V p-p
EMC test standards
► IEC 61000-4-4 electrical fast transient (±4 kV)
► IEC 61000-4-2 ESD (±4 kV contact discharge)
► IEC 61000-4-2 ESD (±8 kV air discharge)
► IEC 61000-4-6 conducted immunity (10 V/m)
► IEC 61000-4-5 surge (±4 kV)
► IEC 61000-4-3 radiated immunity (Class A)
► EN55032 radiated emissions (Class B)
Link LED
Small package: 40-lead (6 mm × 6 mm) LFCSP
Wide temperature range: −40°C to +105°C
Field instruments
► Flow meters
► Pressure and temperature transducers
► Building automation
► Actuators
► Fire panels
► Elevators
► Edge node sensors
► Factory automation
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GENERAL DESCRIPTION
The ADIN1110 is an ultra low power, single port, 10BASE-T1L
transceiver design for industrial Ethernet applications and is compliant with the IEEE® 802.3cg-2019™ Ethernet standard for long
reach, 10 Mbps single pair Ethernet (SPE). Featuring an integrated
media access control (MAC) interface, the ADIN1110 enables direct
connectivity with a variety of host controllers via a serial peripheral
interface (SPI). This SPI enables the use of lower power processors
without an integrated MAC, which provides for the lowest overall
system level power consumption. The ADIN1110 is designed for
edge node sensors and field instruments deployed in building,
factor, and process automation.
The device operates from a single power supply rail of 1.8 V or
3.3 V. Supporting both 1.0 V and 2.4 V amplitude modes of operations and external termination resistors, the ADIN1110 supports use
within intrinsically safe environments. The programmable transmit
levels, external termination resistors, and independent receive and
transmit pins make the ADIN1110 suited to intrinsic safety applications.
The ADIN1110 has an integrated voltage supply monitoring and
power-on reset (POR) circuitry to improve system level robustness,
and has a 4-wire SPI for communication between the MAC interface and host processor.
The ADIN1110 is available in a 40-lead, 6 mm × 6 mm lead frame
chip scale package (LFCSP).
Table 1. Related Products
Product
Description
ADIN1100
Robust, industrial, low power 10BASE-T1L Ethernet PHY in
40-lead (6 mm × 6 mm) LFCSP
Rev. 0
DOCUMENT FEEDBACK
TECHNICAL SUPPORT
Information furnished by Analog Devices is believed to be accurate and reliable "as is". However, no responsibility is assumed by Analog
Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications subject to
change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and
registered trademarks are the property of their respective owners.
Data Sheet
ADIN1110
TABLE OF CONTENTS
Features................................................................ 1
Applications........................................................... 1
General Description...............................................1
Functional Block Diagram......................................3
Specifications........................................................ 4
Timing Characteristics........................................... 6
Power-Up Timing................................................6
SPI......................................................................6
Absolute Maximum Ratings...................................8
Thermal Resistance........................................... 8
Electrostatic Discharge (ESD) Ratings...............8
ESD Caution.......................................................8
Pin Configuration and Function Descriptions........ 9
Typical Performance Characteristics................... 11
Theory of Operation.............................................12
Power Supply Domains.................................... 12
MAC ................................................................ 12
Autonegotiation................................................ 12
MDI Interface....................................................13
Reset Operation............................................... 13
LED Functions..................................................14
Link Status Pin................................................. 15
Power-Down Modes......................................... 15
Hardware Configuration Pins...............................16
Hardware Configuration Pin Functions.............16
Bringing Up 10BASE-T1L Links.......................... 18
Unmanaged PHY Operation.............................18
Managed PHY Operation................................. 18
On-Chip Diagnostics............................................21
Loopback Modes.............................................. 21
Frame Generator and Checker........................ 22
Test Modes....................................................... 23
Applications Information...................................... 24
System Level Power Management...................24
LED Circuit Examples...................................... 24
Component Recommendations........................25
802.1AS Support.............................................. 26
Electromagnetic Compatibility (EMC) and
Electromagnetic Immunity (EMI).................... 27
MAC SPI..............................................................28
Generic SPI Protocol........................................28
OPEN Alliance SPI Protocol.............................31
Frame Filtering on Receive.............................. 38
SPI Access to the PHY Registers.................... 39
Registers............................................................. 42
SPI Register Map............................................. 42
PHY Clause 22 Register Details...................... 65
PHY Clause 45 Register Map.......................... 68
PCB Layout Recommendations........................ 103
Package Layout..............................................103
Component Placement and Routing.............. 103
Crystal Placement and Routing......................103
PCB Stack...................................................... 103
Outline Dimensions........................................... 104
Ordering Guide...............................................104
REVISION HISTORY
10/2021—Revision 0: Initial Version
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Rev. 0 | 2 of 104
Data Sheet
ADIN1110
FUNCTIONAL BLOCK DIAGRAM
Figure 1.
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Data Sheet
ADIN1110
SPECIFICATIONS
AVDD_H = AVDD_L = VDDIO = 3.3 V, DVDD_1P1 supplied from internal low dropout (LDO) regulator (DVDD_1P1 = DLDO_1P1), and all
specifications are at −40°C to +105°C, unless otherwise noted.
Table 2.
Parameter
Min
Typ
Max
Unit
Test Conditions/Comments
POWER REQUIREMENTS
Supply Voltage Range
AVDD_H
AVDD_L
AVDD_H, AVDD_L
DVDD_1P1
VDDIO
3.13
1.71
1.71
1.0
1.71
3.3
1.8 or 3.3
1.8
1.1
1.8, 2.5, or
3.3
3.46
3.46
3.46
1.2
3.46
V
V
V
V
V
2.4 V p-p or 1.0 V p-p transmit Level
1.0 V p-p Transmit Level (Single Supply)
AVDD_H = AVDD_L = VDDIO = 1.8 V, DVDD_1P1 =
DLDO_1P1
AVDD_x Supply Current, IAVDD
Power Consumption
1.0 V p-p Transmit Level (Dual Supply)
28
50
mA
mW
AVDD_x Supply Current, IAVDD
DVDD_1P1 Supply Current, IDVDD
Power Consumption
2.4 V p-p Transmit Level (Single Supply)
16
12
42
mA
mA
mW
AVDD_x Supply Current, IAVDD
Power Consumption
2.4 V p-p Transmit Level (Dual Supply)
36
119
mA
mW
AVDD_x Supply Current, IAVDD
VDDIO Supply Current, IVDDIO
Power Consumption
2.4 V p-p Transmit Level (Triple Supply)
16.5
18
87
mA
mA
mW
16.5
6
12
78
mA
mA
mA
mW
AVDD_x Supply Current, IAVDD
VDDIO Supply Current, IVDDIO
DVDD_1P1 Supply Current, IDVDD
Power Consumption
DIGITAL INPUTS/OUTPUTS
VDDIO = 3.3 V
Input Low Voltage (VIL)
Input High Voltage (VIH)
Output Low Voltage (VOL)
Output High Voltage (VOH)
VDDIO = 2.5 V
VIL
VIH
VOL
VOH
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1.0 V p-p transmit level
0.8
2.0
0.4
2.4
0.7
1.7
0.4
2.0
100% data throughput, full activity
AVDD_H = AVDD_L = VDDIO = 1.8 V, DVDD_1P1 =
external 1.1 V
100% data throughput, full activity
AVDD_H = AVDD_L = VDDIO = 3.3 V, DVDD_1P1 =
DLDO_1P1
100% data throughput, full activity
AVDD_H = 3.3 V, AVDD_L = VDDIO = 1.8 V, DVDD_1P1
= DLDO_1P1
100% data throughput, full activity
AVDD_H = 3.3 V, AVDD_L = VDDIO = 1.8 V, DVDD_1P1
= external 1.1 V
100% data throughput, full activity
Applies to SPI pins, SWPD_EN, TX2P4_EN, TS_TIMER/
MS_SEL, TS_CAPT, INT, LINK_ST, RESET, and LED_x
V
V
V
V
Output low current (IOL) (minimum) = 2 mA
Output high current (IOH) (minimum) = 2 mA
V
V
V
V
IOL (minimum) = 2 mA
IOH (minimum) = 2 mA
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Data Sheet
ADIN1110
SPECIFICATIONS
Table 2.
Parameter
VDDIO = 1.8 V
VIL
VIH
VOL
VOH
RESET Deglitch Time
LED OUTPUT
Output Drive Current
Min
Typ
Max
Unit
0.3 × VDDIO
V
V
0.2 × VDDIO
V
V
1
µs
0.7 ×
VDDIO
0.8 ×
VDDIO
0.3
0.5
8
6
4
mA
mA
mA
CLOCKS
External Crystal (XTAL)
1.5
Crystal Load Capacitance (CL)1
10
Start-up Time
Clock Input (CLK_IN)
Clock Input Frequency
25
+30
10 μs. RESET does not require a pull-up resistor because an internal
pull-up resistor is present.
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Data Sheet
ADIN1110
PIN CONFIGURATION AND FUNCTION DESCRIPTIONS
Table 8. Pin Function Descriptions (Hardware Pin Configuration Groupings Are Subject to Change)
Pin No.
Media Dependent Interface (MDI)
12
13
14
15
Configuration/Status
3
Mnemonic1
Description
TXN
RXN
RXP
TXP
Transmit Negative Pin.
Receive Negative Pin.
Receive Positive Pin.
Transmit Positive Pin.
LED_0
Programmable LED Indicator for General-Purpose LED. The LED is active low. The LED can be active
high or active low. By default, LED_0 is configured to turn on when a link is established and blink when
there is activity. See the LED Functions section.
Link Status Output. LINK_ST indicates whether a valid link is established. LINK_ST is active high.
Programmable LED Indicator for General-Purpose LED. The LED can be active high or active low. By
default, LED_1 is disabled. See the LED Functions section.
Transmit Level Amplitude Hardware Configuration Pin. Set high for 1.0 V p-p transmit amplitude only.
Set low to support both 1.0 V p-p and 2.4 V p-p transmit amplitude. See Table 13.
Software Power-Down Configuration. Set low to configure PHY to enter software power-down mode
after power-up/reset. See Table 11.
4
6
LINK_ST
LED_1
31
TX2P4_EN2
33
SWPD_EN2
LDOs and REFERENCE
19
20
Power and Ground Pins
16, 17
CEXT_2
CEXT_3
AVDD_H
22
AVDD_L
23
DLDO_1P1
24
DVDD_1P1
35
VDDIO
EP
Other Pins
10, 11, 18, 21, 28, 32, 34, 36,
39
26
27
External Decoupling for LDO Circuit. Connect a 0.1 μF capacitor to ground as close as possible to this
pin. Do not use this pin as a voltage source for an external circuit.
External Decoupling for LDO Circuit. Connect a 1 μF capacitor to ground as close as possible to this
pin. Do not use this pin as a voltage source for an external circuit.
Analog Supply Voltage for the Various Analog Circuits in the Device. This supply rail can be supplied by
1.8 V to 3.3 V depending on the transmit level configuration. If AVDD_H is 3.3 V, both 1.0 V p-p and
2.4 V p-p transmit operating modes are supported. If AVDD_H is 1.8 V only, only 1.0 V p-p transmit
operating mode is supported. Connect 0.1 μF and 0.01 μF capacitors to GND as close as possible to
this pin.
Analog Supply Voltage for the Internal LDO Circuits. This supply rail can be supplied by 1.8 V to 3.3
V. AVDD_L can be connected direct to the AVDD_H rail in long reach applications or to an alternative
lower voltage rail when the device is configured with dual supplies for lower power consumption.
Connect 0.1 μF and 0.01 μF capacitors to GND as close as possible to this pin.
Digital Core 1.1 V Power Supply Output Pin. Connect a 0.68 μF capacitor to GND as close as possible
to the pin. When using the internal LDO regulator, connect this pin directly to the DVDD_1P1 pin.
Input Pin for 1.1 V DVDD_1P1 Supply Rail. When using the internal LDO regulator, connect this pin
directly to the DLDO_1P1 pin. Alternatively, an external 1.1 V rail can be provided to the pin for greater
power efficiency. Connect a 0.1 μF capacitor to GND as close as possible to the pin.
3.3 V, 2.5 V, or 1.8 V Digital Power for SPI. Connect 0.1 μF and 0.01μF capacitors to GND as close as
possible to the pin.
Exposed Pad. This GND paddle must be connected to ground. The LFCSP package has an exposed
pad that needs to be connected to GND for electrical reasons and must be soldered to a metal plate on
the PCB for mechanical reasons. A 4 × 4 array of thermal vias beneath the exposed GND pad is also
recommended.
DNC
Do Not Connect. These pins must be left open circuit.
TEST1
TEST2
This pin requires a 1.5 kΩ pull-up resistor to VDDIO.
This pin must be left open circuit.
1
Where a pin is shared between a functional signal and a hardware pin configuration, the hardware pin configuration signal is listed last and the pin is referred to using the
functional signals name throughout the data sheet.
2
All of the hardware configuration pins have internal pull-down resistors. The default mode of operation without any external resistors connected to these pins is shown in
Table 10. If an alternative mode of operation is required, use 4.7 kΩ pull-up resistors.
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Data Sheet
ADIN1110
TYPICAL PERFORMANCE CHARACTERISTICS
Figure 5. Power vs. Temperature, 1.8 V Single Supply, Internal LDO Circuit
Figure 6. Power vs. Temperature, AVDD_H = 3.3 V, VDDIO = 3.3 V, AVDD_L =
1.8V, Internal LDO Circuit
Figure 8. Power vs. Temperature, AVDD_H = 3.3 V, AVDD_L = VDDIO = 1.8 V,
Internal LDO Circuit
Figure 9. Power vs. Temperature, AVDD_H = AVDD_L = 3.3 V, VDDIO = 1.8 V,
Internal LDO Circuit
Figure 7. Power vs. Temperature, 3.3 V Single Supply, Internal LDO Circuit
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Data Sheet
ADIN1110
THEORY OF OPERATION
The ADIN1110 is a low power, single port 10 Mb/s Ethernet MACPHY device, compliant with the IEEE 802.3cg Ethernet standard for
long reach, 10 Mbps single pair Ethernet.
The ADIN1110 integrates the following features:
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10BASE-T1L Ethernet PHY core and MAC with all the associated common analog circuitry
Input and output clock buffering
SPI and subsystem registers
Control logic to manage the reset and clock
Hardware configuration pins
Two configurable LED pins
POWER SUPPLY DOMAINS
The ADIN1110 has four power supply domains and requires a
minimum of one supply rail, as follows:
AVDD_H is the analog power supply input for the analog front
end (AFE) circuitry in the ADIN1110.
► AVDD_L is the analog supply voltage for the internal LDO
circuits. AVDD_L can be connected to the AVDD_H rail when
in single supply mode, or to an alternative lower voltage rail
when the device is configured with dual supplies for lower power
consumption.
► DVDD_1P1 is the 1.1 V digital core power supply input.
DVDD_1P1 can operate from an internal 1.1 V LDO output coming from the DLDO_1P1 pin to the DVDD_1P1 pin. Alternatively,
DVDD_1P1 can be driven from an external 1.1 V supply for
greater power efficiency.
► VDDIO enables the SPI voltage supply to be configured independently of the other circuitry on the ADIN1110. VDDIO can be
connected directly to the AVDD_L rail.
►
In a single supply application, connect AVDD_H = AVDD_L =
VDDIO and use the internal 1.1 V LDO circuit for DVDD_1P1. The
appropriate supply voltage used depends on the end application
and cable length. For long reach/trunk applications, the higher
transmit amplitude of 2.4 V p-p requires AVDD_H = 3.3 V, whereas
spur applications can use a lower transmit amplitude of 1.0 V p-p
with an AVDD_H = 1.8 V.
MAC
The MAC included in the ADIN1110 supports 16 different MAC
addresses. The MAC also has one low priority receive first in, first
out (FIFO), one high priority receive FIFO and one transmit FIFO.
These FIFOs can ship data in store and forward mode when using
the generic SPI protocol, and in either store and forward or cut
through mode when using the OPEN Alliance protocol.
A generic version and OPEN Alliance version of the SPI protocol
are available. The data is transferred over the SPI half duplex using
the generic SPI protocol and full duplex using the OPEN Alliance
SPI protocol. See the MAC SPI section.
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Interrupt (INT)
The ADIN1110 is capable of generating an interrupt to a host processor using the INT pin in response to a variety of user selectable
conditions. The following conditions can be selected to generate an
interrupt:
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►
Link status change
Port 1 receive FIFO receive data available
Frame transmit complete or transmit space available
Time stamp captured
Operation error detected
PHY related interrupts
When an interrupt occurs, the system can poll the MAC status
registers (STATUS0 and STATUS1) to determine the origin of the
interrupt.
AUTONEGOTIATION
The ADIN1110 uses the autonegotiation capability in accordance
with IEEE 802.3 Clause 98, providing a mechanism for exchanging
information between PHYs to allow link partners to agree to a
common mode of operation. During the autonegotiation process,
the PHY advertises its own capabilities and compares to those
received from the link partner. The concluded operating mode is
the transmit amplitude mode and master/slave preference common
across the two devices.
If a link is dropped, the autonegotiation process restarts automatically. An autonegotiation restart can also be requested by writing
to the autonegotiation restart bit (AN_RESTART) in the autonegotiation control register.
The autonegotiation process takes some time to complete, depending on the number of pages exchanged, but is always the fastest
way to bring up a link. Clause 98 of the IEEE 802.3 standard details
the timers related to autonegotiation.
Note that autonegotiation is enabled by default for the ADIN1110,
and it is strongly recommended that autonegotiation is always
enabled.
Transmit Amplitude Resolution
Autonegotiation is used to resolve the transmit amplitude resolution.
The PHY can be configured to support both 1.0 V p-p and 2.4 V
p-p transmit levels or to operate with 1.0 V p-p transmit level only
through the hardware configuration (see Table 13). This configuration can also be done in software using the 10BASE-T1L high level
transmit operating mode ability (AN_ADV_B10L_TX_LVL_HI_ABL)
and 10BASE-T1L high level transmit operating mode request
(AN_ADV_B10L_TX_LVL_HI_REQ) register bits.
To operate at 2.4 V p-p transmit level, both the local and remote
PHYs must advertise that they are capable of operating at 2.4
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Data Sheet
ADIN1110
THEORY OF OPERATION
V, and at least one PHY must request 2.4 V p-p transmit level
operation.
If it is required to only operate the PHY at 1.0 V p-p transmit
level operation, AN_ADV_B10L_TX_LVL_HI_ABL must be 0 so
that 2.4 V p-p transmit level operation is not advertised. In this
case, autonegotiation can only resolve to 1.0 V p-p transmit level
operation, irrespective of what setting the remote PHY advertises.
Master/Slave Resolution
Autonegotiation is also used to resolve master or slave status. The
PHY can be configured to prefer slave or prefer master through
the hardware configuration (see Table 12). If autonegotiation is
disabled, the MS_SEL hardware configuration pin sets the default
master/slave selection. Note that the recommended use of the
ADIN1110 is with autonegotiation enabled.
During autonegotiation, when prefer slave is selected, and the
remote end is prefer or forced master, the local PHY is set to slave
(and remote to master). When the remote end is prefer or forced
slave, the local PHY is set to master (and remote to slave).
MDI INTERFACE
The media dependent interface (MDI) connects the ADIN1110 to
the Ethernet network via a twisted wire pair.
The ADIN1110 requires an external hybrid between the TXN/TXP
and RXN/RXP pins and the twisted wire pair. This external hybrid
allows the system to have full duplex communication by removing
the local transmit signal from the combined signal on the cable,
leaving the desired receive signal.
The ADIN1110 hybrid requires a specific topology and values for
proper operation. Figure 10 shows the topology and values for
the components. Consider the size, power, and voltage rating of
these components in the context of other system requirements, for
example, requirements of intrinsic safety.
RESET OPERATION
The ADIN1110 supports the following chip resets:
►
►
►
►
►
Power-on reset
Hardware reset
Software reset
MAC subsystem reset
PHY subsystem reset
All of these resets put the ADIN1110, including the PHY core and
MAC, into a known state. Whenever the MAC is reset, the SDO pin
is pulled down and the TS_TIMER pin is driven to a low state.
Power-On Reset
The ADIN1110 includes power monitoring circuitry to monitor all of
the supplies. During power-up, the ADIN1110 is held in hardware
reset until each of the supplies has crossed its minimum rising
threshold value and the power is considered good.
The POR module includes brownout protection by monitoring the
supplies to detect if one or more of the supplies falls below a
minimum falling threshold value. If brownout detection occurs, the
device is held in hardware reset until the power is good.
Hardware Reset
A hardware reset is initiated by the power-on reset circuitry or
by asserting the RESET pin low. Bring the RESET pin low for a
minimum of 10 µs. Deglitch circuitry is included on this pin to reject
pulses shorter than 0.3 μs.
When the RESET pin is deasserted, all the input/output (I/O) pins
are held in tristate mode, the hardware configuration pins are latched, and the I/O pins are configured for their functional mode. When
all the external and internal supplies are valid and stable, the crystal
oscillator circuit is enabled. After the crystal starts up and stabilizes,
the phase-locked loop PLL is enabled. After approximately 50 ms
(maximum) from the deassertion of the RESET pin, all the internal
clocks are valid, internal logic is released from reset, and all the
management interface registers are accessible so that the device
can be programmed.
Software Reset
A full chip software reset can be initiated by writing 1 to the
SWRESET field of the RESET register.
If a transmission is taking place when the SPI software reset is initiated, the frame transmission stops abruptly and a runt or a frame
with a bad cyclic redundancy check (CRC) may be transmitted.
Once the MAC-PHY is reset, the ADIN1110 is ready to bring up
links.
Figure 10. Recommended Hybrid for the ADIN1110
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When this software reset is initiated, a full initialization of the chip,
almost equivalent to a hardware reset, is done. The I/O pins are
Rev. 0 | 13 of 104
Data Sheet
ADIN1110
THEORY OF OPERATION
held in tristate mode, the hardware configuration pins are latched,
and the I/O pins are configured for their functional mode. The crystal oscillator circuit is enabled, and after the crystal starts up and
stabilizes, the PLL is enabled. Approximately 10 ms (maximum)
after writing the SOFT_RST keys, the internal logic is released from
reset and all the management interface registers are accessible.
MAC Subsystem Reset
A MAC only software reset is initiated by writing the required pair of
keys to the SOFT_RST register.
The reset is applied for about 1.2 µs. The MAC subsystem reset
interrupts any transmit/receive packet exchange between the MAC
and the PHY, but does not drop any existing link nor prevents
a link from establishing. The PHY management registers are not
initialized.
The PHY needs to be out of software power-down to trigger a MAC
only software reset.
PHY subsystem reset is initiated by setting the PHY subsystem
reset register bit (CRSM_PHY_SUBSYS_RST). When this bit is
set, the PHY subsystem is reset. The reset is applied for about
1.2 µs and then this bit self clears. All of the PHY digital circuitry
is reset and any existing link drops. The management registers
are not initialized by this reset, and access to all the management
registers is available during the PHY subsystem reset. This is a
short reset and can be used to put the device into a known state
while retaining any software initialization of the device.
LED FUNCTIONS
LED_0 and LED_1 can be configured to display various activities
of the ADIN1110 using the LED function feature. The LED function
is configurable using the LED0_FUNCTION and LED1_FUNCTION
bits (see the LED Control Register section).
The 7, 8, 9, and 10 (decimal) bit settings for LEDx_FUNCTION are
not available in LED Mode 2.
PHY Subsystem Reset
The PHY subsystem is the part of the ADIN1110 that incorporates
the 10BASE-T1L PHY transceiver analog and digital circuits. A
Table 9. LED_x Pins Configuration Summary
Parameter
LED_0
LED_1
Pin Number
Internal Pull-Up or PullDown Resistor
Status at Power-Up or
Reset
LED Pin Mux
3
Pull-up
6
Pull-down
Enabled
Disabled
Enable LED
LED Polarity
LED Mode
LED Function1
LED Blink Rate
Maximum Current2
Not applicable
DIGIO_LED1_PINMUX bits (see the Pin Mux Configuration 1 Register
section)
LED0_EN bit (see the LED Control Register section)
LED1_EN bit (see the LED Control Register section)
LED0_POLARITY bits (see the LED Polarity Register section)
LED1_POLARITY bits (see the LED Polarity Register section)
LED0_MODE bit (see the LED Control Register section), default: LED
LED1_MODE bit (see the LED Control Register section), default: LED
Mode 1
Mode 1
LED0_FUNCTION bits (see the LED Control Register section), default: LED1_FUNCTION bits (see the LED Control Register section), default:
LINKUP_TXRX_ACTIVITY
TXRX_ACTIVITY
LED0_BLINK_TIME_CNTRL (see the LED_0 On/Off Blink Time Register LED1_BLINK_TIME_CNTRL (see the LED 1 On/Off Blink Time Register
section)
section
8 mA at 3.3 V
8 mA at 3.3 V
1
The 7, 8, 9, and 10 (decimal) settings in the LEDx_FUNCTION bits are not available in LED Mode 2.
2
See Table 2.
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Data Sheet
ADIN1110
THEORY OF OPERATION
Typical Use
The LED_0 and LED_1 pins can be used to connect external
LEDs to indicate the ADIN1110 link status and transmit or receive
activity. The activity assigned to each LED is configurable through
LED_CNTRL (see the LED Control Register section).
The LED pins are suitable for ultra low power LEDs. The maximum
output current for the LED_0 and LED_1 pins is 8 mA with a VDDIO
= 3.3 V. For higher LED power requirements, the use of an external
transistor is recommended.
The LED_x pins can also be connected to a host microcontroller
general-purpose input/output (GPIO) (configured as a pulse-width
modulated input or hardware interrupt). This configuration can be
useful in applications where the user interface needs to be fully
handled by an external host controller (for example, an external
LED module or display). Note that in this context, it is recommended to place a low value resistance in series between the ADIN1110
LED_x pins and the controller to avoid any potential transient surge
current.
Blink Time Register section) and LED1_BLINK_TIME_CNTRL
register (see the LED 1 On/Off Blink Time Register section),
respectively
► LED Mode 2: blink duty cycle automatically defined by the
ADIN1110 based on activity level (%)
LINK STATUS PIN
The LINK_ST pin is asserted high when the link status bit
(AN_LINK_STATUS) is asserted and indicates that the link between
the ADIN1110 and its link partner is active.
By default, the LINK_ST signal is active high and can be configured to be either active high or active low using the DIGIO_LINK_ST_POLARITY bit (see the Pin Mux Configuration 1
Register section).
POWER-DOWN MODES
The ADIN1110 supports two power-down modes, as follows:
►
►
LED Pin Multiplexing
An internal multiplexer needs to be configured to enable the LED_1
signal on the LED_1 pin. LED_1 is disabled by default and can
be enabled using the DIGIO_LED1_PINMUX bits (see the Pin Mux
Configuration 1 Register section).
The LED_0 pin does not need multiplexing.
LED Polarity
The LED_0 and LED_1 pins can be configured to support various
LED circuit polarities through the LED polarity mode feature (see
the LED Polarity Register section). Three polarity modes are available for each LED, as follows:
Autosense (default)
► Active high
► Active low
►
In autosense mode, the ADIN1110 automatically senses the pin at
power-up or reset to select the appropriate polarity configuration. In
active high mode, the ADIN1110 is configured to drive the LED from
the anode side. In active low mode, the ADIN1110 is configured to
drive the LED from the cathode side.
Example circuits are described in the LED Circuit Examples section.
LED Mode
LED_0 and LED_1 activity behavior can be configured using the
two LED modes, as follows:
►
LED Mode 1: blink duty cycle defined using the
LED0_BLINK_TIME_CNTRL register (see the LED_0 On/Off
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Hardware power-down
Software power-down
The lowest power mode is hardware power-down mode in which
the device is turned off and the registers are not accessible.
Hardware Power-Down Mode
Hardware power-down mode can be used when no operation is
required on the ADIN1110 and the power consumption needs to
be minimized. The ADIN1110 enters hardware power-down mode
when the RESET pin is asserted and held low. In this mode, all
analog and digital circuits are disabled, the clocks are gated off, all
the I/O pins are held in tristate mode, and the only power is the
leakage power of the circuits. The management registers are not
accessible in this mode.
Software Power-Down Mode
Software power-down mode can be used to configure the
ADIN1110 registers before bringing a link up. The ADIN1110 can
be configured to enter software power-down mode after reset using
the SWPD_EN pin. The ADIN1110 can also be instructed to enter
software power-down mode by setting the software power-down bit
(CRSM_SFT_PD).
The software power-down status bit (CRSM_SFT_PD_RDY) indicates that the device is in the software power-down state. In
software powerdown mode, the analog and digital circuits are in
a low power state, and the PLL is active and can provide output
clocks if configured to do so. Any signal or energy on the MDI pins
is ignored and no link is brought up. The management interface
registers are accessible, and the device can be configured using
software. The ADIN1110 exits software power-down mode when the
CRSM_SFT_PD bit is cleared. At this point, the MAC-PHY starts
autonegotiation and attempts to bring up a link after autonegotiation
completes.
Rev. 0 | 15 of 104
Data Sheet
ADIN1110
HARDWARE CONFIGURATION PINS
The ADIN1110 can operate in unmanaged or managed applications. In unmanaged applications, it is possible to configure the
desired link configuration of the MAC-PHY from hardware configuration pins without any software intervention. After coming out of
reset, the MAC-PHY attempts to bring up a link. Note that for
an unmanaged application, the MAC-PHY must not be hardware
configured to enter software power-down mode.
In managed applications, software is available to configure the
MAC-PHY via the management interface. In this case, the user can
configure the MAC-PHY to enter software power-down after reset.
Software can then intervene to configure the device as required
and bring the device out of software power-down to allow linking to
establish.
Hardware configuration pins are often shared with functional pins,
and the voltage level on the pin is sensed and latched upon exiting
from a reset. All hardware configuration pins are 2-level sense
using a pull-down or pull-up resistor.
HARDWARE CONFIGURATION PIN
FUNCTIONS
The following functions are configurable from the ADIN1110 hardware configuration pins:
Software power-down mode after reset
► Transmit amplitude configuration
► Master/slave selection
► SPI protocol configuration
►
All of the hardware configuration pins have internal pull-down resistors. The default mode of operation without any external resistors
connected to these pins is shown in Table 10. If an alternative mode
of operation is required, use 4.7 kΩ pull-up resistors.
Table 10. Default Hardware Configuration Modes
Hardware Configuration Pin Function Default Mode
Software Power-Down Mode after
Reset
Master/Slave Selection
Transmit Amplitude
SPI Protocol Configuration
PHY in software power-down mode
after reset
Prefer slave
1.0 V p-p and 2.4 V p-p
OPEN Alliance protocol with protection
Software Power-Down After Reset
If the ADIN1110 is configured so that it does not enter software
power-down mode after reset, the ADIN1110 starts autonegotiation
when it exits reset and attempts to bring up a link after autonegotiation completes. If the ADIN1110 is configured so that it enters
software power-down mode after reset, the ADIN1110 waits in
software power-down mode until it is configured over the SPI.
At this point, the PHY configuration can be set to exit software
power-down by software.
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Table 11. Software Power-Down (Hardware Configuration)
Software Power-Down Configuration
SWPD_EN
PHY in software power-down after reset
PHY not in software power-down
0
1
Master/Slave Preference
The MS_SEL hardware configuration pin is shared with the
TS_TIMER pin and configures the default master/slave selection.
If MS_SEL is pulled low during power-up or reset, the device
is configured by default to prefer slave (this is the case if no
external pull-up resistor is connected to the MS_SEL pin due to the
presence of the internal pull-down resistor). If MS_SEL is pulled
high during power-up or reset, the device is configured by default to
prefer master.
If autonegotiation is disabled, MS_SEL sets the default master/slave selection. Autonegotiation is enabled by default for the
ADIN1110 and it is strongly recommended that autonegotiation is
always enabled.
During autonegotiation, when prefer slave is selected and the
remote end is prefer or forced master, the local PHY is set to slave
(and remote to master). When the remote end is prefer or forced
slave, the local PHY is set to master (and remote to slave).
Table 12. Master/Slave Selection (Hardware Configuration)
Master/Slave Selection
MS_SEL
Prefer Slave Selection
Prefer Master Selection
0
1
Transmit Amplitude
The TX2P4_EN hardware configuration pin allows the user to
configure the required transmit amplitude mode for the intended application (see Table 13). If TX2P4_EN is pulled low, the ADIN1110
is configured by default to support both 1.0 V p-p and 2.4 V p-p
transmit levels, decided by autonegotiation. If TX2P4_EN is pulled
high, the ADIN1110 is configured to disable 2.4 V p-p transmit
operating mode by default and operate with 1.0 V p-p transmit
level only. If the TX2P4_EN pin is strapped high (1.0 V p-p only),
the associated register cannot be changed through the SPI. For
example, 2.4 V p-p operation is not possible if the ADIN1110 is
hardware pin configured for 1.0 V p-p only.
The 1.0 V p-p transmit operating mode supports the spur use case
and can operate at a lower AVDD_H supply voltage of 1.8 V. This
supports intrinsic safe applications.
The higher transmit operating mode of 2.4 V p-p supports trunk
applications and requires a higher AVDD_H supply voltage of 3.3
V. This mode can be used for longer cable lengths in industrial
Ethernet environments with high noise levels.
Rev. 0 | 16 of 104
Data Sheet
ADIN1110
HARDWARE CONFIGURATION PINS
Table 13. Transmit Amplitude Configuration (Hardware Configuration)
Table 14. SPI Protocol (Hardware Configuration)
Transmit Amplitude Selection
TX2P4_EN
SPI Protocol
SPI_CFG1
SPI_CFG0
1.0 V p-p or 2.4 V p-p
1.0 V p-p
0
1
OPEN Alliance with Protection
OPEN Alliance Without Protection
Generic SPI with 8-bit CRC
Generic SPI Without 8-bit CRC
0
0
1
1
0
1
0
1
SPI Protocol Configuration
The ADIN1110 allows the use of a generic SPI protocol with or
without the use of CRC, or the OPEN Alliance SPI protocol with or
without protection.
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Rev. 0 | 17 of 104
Data Sheet
ADIN1110
BRINGING UP 10BASE-T1L LINKS
UNMANAGED PHY OPERATION
For an unmanaged PHY application or lightly managed PHY application where there is no software management of the PHY, the
hardware configuration pins determine the operating mode. The
TX2P4_EN pin configures the PHY to advertise the support of both
1.0 V p-p and 2.4 V p-p transmit level operation or to only advertise
support of 1.0 V p-p transmit level operation. The MS_SEL pin
is used to configure the PHY to advertise prefer slave or prefer
master. The SWPD_EN pin must be pulled up at power-up and
reset so that the PHY does not enter software power-down mode
when it exits reset. Once the PHY exits reset, the ADIN1110 starts
autonegotiation and attempts to bring up a link after autonegotiation
completes.
A lightly managed PHY can use the hardware configuration pins to
determine the operation of the PHY and to bring up a 10BASE-T1L
link. Afterwards, software can monitor the operation of the PHY.
MANAGED PHY OPERATION
In a managed PHY application, software is used to configure the
PHY operation using the management interface. The hardware
configuration pins can be used to set the default values of the
registers used to control the transmit amplitude and master/slave
setting. The SWPD_EN pin must be pulled low at power-up and
reset so that the PHY enters software power-down mode when
it exits reset. The PHY remains in software power-down mode
until the software configures the PHY and takes it out of software
power-down mode to start autonegotiation and attempt to bring up
a link.
Power-Up and Reset Complete
To confirm that the MAC has exited reset, read the PHY identification register (PHYID). If the reset value of the register (0x283BC91)
can be read, the device has exited reset and is ready for configuration.
Next, the host must read the STATUS0 register and confirm that
the RESETC field is 1. Note that if the RESETC field is 0, and the
SYNC field of the CONFIG0 register is 1, the MAC-PHY is already
configured by the host and, therefore, has not been reset. This
can indicate that the host is reset, but the MAC-PHY has not been
reset.
Write 1 to the RESETC field in the STATUS0 register to clear this
field, and the interrupt pin asserts high.
The PHYINT field of the STATUS0 register also asserts. To
clear this field, the corresponding status registers, PHY_SUBSYS_IRQ_STATUS and CRSM_IRQ_STATUS, must be cleared or
masked.
The system ready bit (CRSM_SYS_RDY) can also be read to verify
that the start-up sequence is complete and the system is ready for
normal operation.
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The software power-down status bit (CRSM_SFT_PD_RDY) can be
read to check if the device is in the software power-down state. This
bit is configured by the SWPD_EN hardware configuration pin.
MAC Initialization
After power-up or reset, configure the ADIN1110 MAC. Write the
IMASK0 and IMASK1 registers to enable interrupts as required.
Write CONFIG0 and CONFIG2 to set up the required functionality
of the MAC. For example, set the OPEN Alliance chunk size or
enable cut through, if required.
When the MAC is configured, write 1 to the SYNC field in the CONFIG0 register to indicate that the MAC configuration is complete.
Configuring the Device for Linking
After power-up or reset, configure the ADIN1110 PHY for the
desired operation for linking. The ADIN1110 may already be configured as required for linking by the hardware configuration pins, but
greater control is available using the management registers.
The autonegotiation process is used to match the operating mode
between a local and remote PHY. For example, autonegotiation is
used to ensure that the modes agree between the two devices on
which PHY operates as master and which as slave. Autonegotiation
is also used to match the transmit level between the two PHYs.
Autonegotiation is enabled by default for the ADIN1110, and it is
strongly recommended to always keep autonegotiation enabled.
Autonegotiation is defined by the IEEE standard and includes a
number of mechanisms to ensure robust linking operation between
PHYs and is the fastest way to bring up a link.
Advertisement of Transmit Level Operating
Mode
The ADIN1110 can support transmit level operation at either 1.0 V
p-p or 2.4 V p-p if the 10BASE-T1L high voltage transmit ability
read only register bit (B10L_TX_LVL_HI_ABLE) is 1 and there is
a 3.3 V supply provided on the AVDD_H pins. The higher transmit
level can support longer reach but also has higher power consumption. The ADIN1110 can support 1.0 V p-p transmit level operation
with a 1.8 V supply on the AVDD_H pins at very low power
consumption. The 1.0 V p-p transmit level operation is required for
intrinsically safe operation.
The ADIN1110 can either be configured to advertise support
of both 1.0 V p-p and 2.4 V p-p transmit level operation
(if B10L_TX_LVL_HI_ABLE = 1) or to advertise support of
only 1.0 V p-p transmit level operation. This is set using
the 10BASE-T1L high level transmit operating mode ability
bit within the BASE-T1 autonegotiation advertisement register
(AN_ADV_B10L_TX_LVL_HI_ABL). 0 = support 1.0 V p-p transmit
level only, and 1 = support both 1.0 V p-p and 2.4 V p-p transmit
level.
Rev. 0 | 18 of 104
Data Sheet
ADIN1110
BRINGING UP 10BASE-T1L LINKS
The ADIN1110 can also be configured to advertise a request for 2.4
V p-p transmit level operation (if B10L_TX_LVL_HI_ABLE = 1). This
is set using the 10BASE-T1L high level transmit operating mode
request bit (AN_ADV_B10L_TX_LVL_HI_REQ). 0 = request 1.0 V
p-p transmit level, and 1 = request 2.4 V p-p transmit level.
The ADIN1110 has an internal pull-down resistor on the MS_SEL
pin, which results in a default setting of configuring the PHY to
advertise prefer slave. It is recommended to either use the default
setting of advertise prefer slave or to use a setting of advertise
prefer master.
The link partner advertised transmit level ability can be read in
the link partner 10BASE-T1L high level transmit operating mode
ability register bit (AN_LP_ADV_B10L_TX_LVL_HI_ABL). The link
partner advertised transmit level request can be read in the link
partner 10BASE-T1L high level transmit operating mode request
register bit (AN_LP_ADV_B10L_TX_LVL_HI_REQ). These bits are
updated during the autonegotiation process and are valid when the
autonegotiation complete register bit (AN_COMPLETE) is set.
If it is mandatory for the PHY to operate as master, use an
advertise forced master configuration. However, this configuration
must be used with caution because if remote end is also forced
master, there is a configuration fault, autonegotiation fails, and the
link is not brought up.
Operation at the 1.0 V p-p transmit level operation occurs if either
the local or remote PHY advertises that it is not capable of transmitting in the high level (2.4 V p-p) transmit operating mode, or if
neither the local nor remote PHY advertises a request for high level
(2.4 V p-p) transmit operating mode.
Operation at the 2.4 V p-p transmit level occurs if both the local
and remote PHY advertises that they are capable of transmitting in
the high level (2.4 V p-p) transmit operating mode, and if either the
local or remote PHY advertises a request for high level (2.4 V p-p)
transmit operating mode.
Therefore, a PHY can ensure it must operate at 1.0 V p-p transmit
level, but it can only request operation at the 2.4 V p-p transmit
level.
Table 15. Determination of Transmit Level by Autonegotiation1
HI_ABL2
HI_REQ
LP_HI_ABL
LP_HI_REQ
Transmit Level
0
1
0
1
1
1
1
X
X
X
0
0
1
1
0
0
1
1
1
1
1
X
X
X
0
1
0
1
1.0 V p-p
1.0 V p-p
1.0 V p-p
1.0 V p-p
2.4 V p-p
2.4 V p-p
2.4 V p-p
1
X means don't care.
2
HI_ABL, HI_REQ, LP_HI_ABL, and LP_HI_REQ refer to the advertisement bits
AN_LP_ADV_B10L_TX_LVL_HI_ABL, AN_LP_ADV_B10L_TX_LVL_HI_REQ,
AN_ADV_B10L_TX_LVL_HI_ABL, and AN_ADV_B10L_TX_LVL_HI_REQ, respectively.
The force master/slave configuration register bit
(AN_ADV_FORCE_MS) is used to configure the PHY to advertise
its master/slave configuration as a preference or as a forced value,
as follows: 0 = master/slave configuration is a preferred mode, and
1 = master/slave configuration is a forced mode.
The master/slave configuration register bit (AN_ADV_MST) is used
to configure the PHY to advertise its master/slave configuration, as
follows: 0 = slave and 1 = master.
The link partner advertised master/slave setting can be read
in the link partner force master/slave configuration register bit
(AN_LP_ADV_FORCE_MS) and the link partner master/slave configuration register bit (AN_LP_ADV_MST). These bits are updated
during the autonegotiation process and are valid when the autonegotiation complete register bit (AN_COMPLETE) is set.
When the local and remote PHY have the same preferred configuration (for example, both slave or both master), a random
process is used to determine which is the master and which is the
slave. When one PHY has a forced configuration, its master/slave
configuration is given priority over a PHY with a preferred setting
where both PHYs have the same master/slave configuration. If
both PHYs have a forced configuration and the same master/slave
configuration, configuration fault occurs and autonegotiation fails.
The resolution of master/slave can be read using the master/slave
resolution result register bits (AN_MS_CONFIG_RSLTN). This result indicates if the PHY is configured as a slave or a master or
if there was a configuration fault. These bits are updated during
the autonegotiation process and are valid when the autonegotiation
complete register bit (AN_COMPLETE) is set.
Advertisement of Master/Slave
The 10BASE-T1L standard uses what is known as a master/slave
clock scheme. This scheme is commonly used in full duplex transceiver standards using echo cancellation. One PHY is designated
as the master and the other PHY as the slave. Autonegotiation is
used to agree which PHY is the master and which is the slave, and
it generally doesn’t matter which PHY is which.
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Rev. 0 | 19 of 104
Data Sheet
ADIN1110
BRINGING UP 10BASE-T1L LINKS
Table 16. Determination of Master/Slave by Autonegotiation1
Local
Remote
AN_ADV_FORCE_MS
AN_ADV_MST
AN_LP_ADV_FORCE_MS AN_LP_ADV_MST
0
0
0
0
0
0
1
1
1
1
1
1
0
0
1
1
X
X
0
1
0
0
1
1
0
0
0
0
1
1
0
0
1
1
1
1
1
0
1
0
1
0
1
X
X
0
1
0
1
Local
Remote
Master/Slave Resolution
Master/Slave
Slave
Master
Master/Slave
Master
Slave
Slave
Master
Configuration Fault
Slave
Master
Configuration Fault
Slave/Master
Master
Slave
Slave/Master
Slave
Master
Master
Slave
Configuration Fault
Master
Slave
Configuration Fault
X means don't care.
Completion of Autonegotiation
When read as 1, this bit indicates that a valid link is established.
When autonegotiation completes, the autonegotiation complete indication register bit (AN_LINK_GOOD) is set. This bit indicates
completion of the autonegotiation transmission, and that the enabled PHY technology is either bringing up its link or that it has
brought up its link.
If this bit reads 0, the link has failed since the last time it was read.
If the value of this bit is read as 0, this bit must be read a second
time to determine the link status (see Latch Low Registers section).
When autonegotiation has completed and the link is up, the autonegotiation complete register bit (AN_COMPLETE) is set. When
this bit is read as 1, the autonegotiation process is complete, the
PHY link is up, and the contents of the AN_ADV_ABILITY and
AN_LP_ADV_ABILITY register bits are valid.
If the link is dropped, the autonegotiation process restarts automatically. Autonegotiation can be restarted by request through a write
to the autonegotiation restart bit (AN_RESTART) in the autonegotiation control register (AN_CONTROL).
Link Status
The status of the link can be determined by reading the link status
register bit (AN_LINK_STATUS). This bit latches low.
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Rev. 0 | 20 of 104
Data Sheet
ADIN1110
ON-CHIP DIAGNOSTICS
LOOPBACK MODES
The PHY core within the MAC-PHY provides the following loopback
modes:
Physical medium attachment (PMA) loopback
► Physical coding sublayer (PCS) loopback
► MAC interface loopback
► MAC interface remote loopback
►
These loopback modes test and verify various functional blocks
within the PHY. The use of the built-in frame checker and frame
generator allows completely self contained in-circuit testing of the
digital and analog data paths within the PHY core. A loopback can
also be established that includes the MAC portion of the ADIN1110
(not limited to just the PHY core) by implementing the necessary
software within the host processor.
PMA Loopback
For PMA loopback, leave the MDI pins open circuit, thereby transmitting into an unterminated connector or cable. For the most
accurate results, leave the cable disconnected. The PHY can
then operate by receiving the reflection from its own transmission.
This loopback is intended as an implementation of IEEE Standard
802.3cg Subclause 146.5.6 PMA local loopback.
Note that for 10BASE-T1L PMA local loopback, the device
must be configured in the forced link configuration mode (autonegotiation disabled). Setting the B10L_LB_PMA_LOC_EN bit
(B10L_PMA_CNTRL register) enables PMA loopback.
PCS Loopback
PCS loopback mode loops the transmit data back to the receiver
within the PCS block at the input stage of the PHY digital block.
Setting the B10L_LB_PCS_EN bit (B10L_PCS_CNTRL register)
enables PCS loopback.
When the PCS loopback mode is enabled, no signal is transmitted
to the MDI pins.
MAC Interface Loopback
MAC interface loopback mode loops the data received on the MAC
interface back to the SPI host. Setting the MAC_IF_LB_EN bit
(MAC_IF_LOOPBACK register) enables MAC interface loopback.
If the MAC_IF_LB_TX_SUP_EN bit within the same register is set
(set by default), the transmission of the signal is suppressed to the
MDI pins.
MAC Interface Remote Loopback
MAC interface remote loopback requires a link up with a remote
PHY and enables looping of the data received from the remote
PHY back to the remote PHY. This linking allows a remote PHY to
verify a complete link by ensuring that the PHY receives the proper data. Setting the MAC_IF_REM_LB_EN bit (MAC_IF_LOOPBACK register) enables MAC interface remote loopback. If the
MAC_IF_REM_LB_RX_SUP_EN bit within the same register is set
(set by default), the data received by the PHY is suppressed and
not sent to the MAC.
MAC Loopback
The MAC loopback loops the data received on the MAC transmit
channel back to the SPI host. The MAC loopback is enabled with
the P1_LOOP register.
Host Processor Loopback
Outside of the loopback modes associated with the PHY core within
the ADIN1110, the host processor can be used to create a full MAC
loopback. In a full MAC loopback, whatever frame is received from
the MAC is transmitted back to the MAC, as shown in Figure 11.
Figure 11. ADIN1110 Loopback Modes
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Rev. 0 | 21 of 104
Data Sheet
ADIN1110
ON-CHIP DIAGNOSTICS
FRAME GENERATOR AND CHECKER
The ADIN1110 can be configured to generate frames and to check
received frames (see Figure 12). The frame generator and checker
can be used independently to generate frames or check frames,
or the frame generator and checker can be used together to
simultaneously generate frames and check frames. If frames are
looped back at the remote end, the frame checker can be used to
check frames generated by the ADIN1110.
then read all other frame counters and error counters. A latched
copy of the receive frame counter register is available in the
FC_FRM_CNT_H register and FC_FRM_CNT_L register.
When the frame generator is enabled, the source of the data for the
PHY comes from the frame generator and not the MAC.
In addition to CRC errors, the frame checker counts frame length
errors, frame alignment errors, symbol errors, oversized frames
errors, and undersized frame errors. In addition to the received
frames, the frame checker counts frames with an odd number of
nibbles in the frame, and counts packets with an odd number of
nibbles in the preamble. The frame checker also counts the number
of false carrier events, which is a count of the number of times the
bad start of the stream delimiter (bad SSD) state is entered.
The frame generator control registers configure the type of frames
to be sent (for example, random data, all 1s), the frame length, and
the number of frames to be generated.
Frame Generator and Checker Used with
Remote Loopback with Two MAC-PHYs
The generation of the requested frames starts by enabling the
frame generator (FG_EN). When the generation of the frames
completes, the frame generator done bit is set (FG_DONE).
The frame checker is enabled using the frame checker enable
bit (FC_EN). The frame checker can be configured to check and
analyze received frames from either the MAC interface or the PHY,
which is configured using the frame checker transmit select bit
(FC_TX_SEL). The frame checker reports the number of frames
received, CRC errors, and various other frame errors. The frame
checker frame counter register and frame checker error counter
register count these events.
The frame checker counts the number of CRC errors and these are
reported in the receive error counter register (RX_ERR_CNT). To
ensure synchronization between the frame checker error counter
and frame checker frame counters, all of the counters are latched
when the receive error counter register is read. Therefore, when
using the frame checker, read the receive error counter first, and
Using two MAC-PHY devices, the user can configure a convenient
self contained validation of the PHY core to PHY core connection,
or can exercise the full signal chain by using the host processor
to perform the loopback at the remote end. Figure 12 shows an
overview of how each MAC-PHY is configured. An external cable
is connected between both devices, and MAC-PHY 1 is generating
frames using the frame generator.
When limiting the test to just the PHY core portions of the
ADIN1110, MAC-PHY 2 has MAC interface remote loopback enabled (MAC_IF_REM_LB_EN). The frames issued by MAC-PHY
1 are sent through the cable, through the PHY 2 signal chain
returned by the PHY 2 MAC interface remote loopback, back again
through the cable, and checked by the MAC-PHY 1 frame checker.
Alternatively, the frames from MAC-PHY 1 can be sent all the way
to the host processor of the remote device and looped back from
there, through the MAC and PHY blocks within MAC-PHY 2, and
back to MAC-PHY 1.
Figure 12. Remote Loopback Used Across Two PHYs for Self Check Purposes
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Rev. 0 | 22 of 104
Data Sheet
ADIN1110
ON-CHIP DIAGNOSTICS
TEST MODES
The ADIN1110 provides several test modes that allow testing of
the transmitter waveform, distortion, jitter, and droop. These test
modes change only the data symbols provided to the transmitter
circuitry and do not alter the electrical and jitter characteristics of
the transmitter and receiver from the normal operation.
The following test modes included in theADIN1110 are defined in
Subclause 146.5.2 from the IEEE 802.3cg:
Test Mode 1. This is a transmitter output voltage and timing jitter
test mode. When this mode is selected, the ADIN1110 repeatedly
transmits the data symbol sequence (+1, –1).
► Test Mode 2. This is a transmitter output droop test mode. In this
mode, the ADIN1110 transmits ten +1 symbols followed by ten
−1 symbols. This sequence repeats indefinitely.
► Test Mode 3. Normal operation in idle mode test mode. When
this test mode is selected, the ADIN1110 transmits as in non test
operation and in the master data mode with data set to normal
interframe idle signals.
►
In addition to these test modes, the ADIN1110 provides the transmit disable mode defined in Subclause 45.2.1.186a.2. This mode
maintains both the receive and transmit path active as in normal
operation, but only transmits 0 symbols. This mode can be used to
measure the MDI return loss specified in Subclause 146.8.3.
Accessing Test Mode 1 to Test Mode 3
To set the ADIN1110 into Test Mode 1, Test Mode 2, or Test
Mode 3, the device must be in software power-down mode
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(CRSM_SFT_PD). The power-down status of the ADIN1110
can be checked reading the software power-down status bit
(CRSM_SFT_PD_RDY).
When the ADIN1110 is in software power-down mode, disable
autonegotiation by clearing the autonegotiation enable bit (AN_EN).
With autonegotiation disabled, force the autonegotiation configuration by writing to the autonegotiation forced mode bit
(AN_FRC_MODE_EN).
The desired test mode can now be selected by writing the appropriate value to the 10BASE-T1L test mode control register
(B10L_TEST_MODE_CNTRL) and exiting the device from powerdown by clearing the software power-down bit (CRSM_SFT_PD).
Accessing Transmit Disable Test Mode
To configure the ADIN1110 in the transmit disable test mode, the
device must be in software power-down mode (CRSM_SFT_PD).
The power-down status of the ADIN1110 can be checked reading
the software power-down status bit (CRSM_SFT_PD_RDY).
When the ADIN1110 is in software power-down mode, disable
autonegotiation by clearing the autonegotiation enable bit (AN_EN).
With autonegotiation disabled, force the autonegotiation configuration by writing to the autonegotiation forced mode bit
(AN_FRC_MODE_EN).
The transmit disable test mode can now be enabled by setting the
B10L_TX_DIS_MODE_EN bits to 1. To exit from the test mode,
write 0 to CRSM_SFT_PD.
Rev. 0 | 23 of 104
Data Sheet
ADIN1110
APPLICATIONS INFORMATION
SYSTEM LEVEL POWER MANAGEMENT
mode of operation still allows the 1.0 V p-p operating mode to be
selected via MDIO or via autonegotiation.
Transmit Level = 1.0 V p-p
Figure 14 shows an overview of the proposed power configuration.
For single supply operation, the same rail can be used to supply the
AVDD_H, AVDD_L, and VDDIO supply rails. The DVDD_1P1 1.1 V
rail can be derived internally or alternatively provided by an external
1.1 V rail. Note that this configuration requires that AVDD_H is 3.3
V even if the link is established at 1.0 V p-p transmit operating
mode via MDIO or autonegotiation.
The transmit mode of 1.0 V p-p can be used for shorter reach
applications supporting cable lengths up to 400 m where signal
amplitude requirements tend to be lower.
For applications where the ADIN1110 must operate in a 1.0 V p-p
transmit operating mode, the TX2P4_EN pin must be tied high via
a 4.7 kΩ resistor (see Figure 13). This configuration forces the
ADIN1110 to only operate at 1.0 V p-p transmit operating mode
and enables the operation of the ADIN1110 from a signal supply
voltage, operating at a lower voltage rail (for example, 1.8 V),
allowing the user to minimize power dissipation in the system.
Figure 14. Supplies and Capacitors for 2.4 V p-p and 1.0 V p-p Transmit Mode
LED CIRCUIT EXAMPLES
Figure 13. Supplies and Capacitors for 1.0 V p-p Transmit Mode
Transmit Level = 2.4 V p-p
For longer reach applications, a higher signal amplitude of 2.4 V p-p
is required. The ADIN1110 is designed to operate with long reach
cables up to 1000 m in this mode, requiring a higher AVDD_H
supply voltage of 3.3 V.
For the ADIN1110 to be able to operate in 2.4 V p-p, the TX2P4_EN
pin must be tied low (no external connection required to achieve
this due to the presence of an internal pull-down resistor). This
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The LED_0 and LED_1 pins can be used in various circuit configurations depending on the LED polarity mode selected (see LED
Polarity Register). The example circuits described in this section
provide examples for the three polarity modes available for each
LED, as follows:
Autosense (default)
Active low
► Active high
►
►
As described in the LED Functions section, the maximum output
current for both LED_0 and LED_1 is 8 mA with a VDDIO =
Rev. 0 | 24 of 104
Data Sheet
ADIN1110
APPLICATIONS INFORMATION
3.3 V. For higher current requirements, consider using the circuit
described in Transistor Controlled LED.
Active High LED Polarity
In the active high configuration, the LED_x pin can drive an external
LED from the anode side. Select the R0 and R1 resistors to control
the LED current (refer to the selected LED specifications in Table
2 for information). External pull-down resistors (RPD0, RPD1) with a
value of 4.7 kΩ are recommended.
the maximum rating of the LED during the actuation (refer to the
transistor technical specifications for information). If required, the
inrush current can be reduced by placing a resistance between
the transistor gate and the ADIN1110 pin, and/or adding a parallel
capacitor between the GND and the LED_x pin. The additional resistor and capacitor values must be defined based on the transistor
selection.
Select the R0 and R1 resistors to control the LED current. External
pull-down resistors (RPD0, RPD1) with a value of 4.7 kΩ are recommended.
VCC can be set to match the LED power requirements.
Figure 15. Recommended Active High LED Circuit
Active Low LED Polarity
In active low configuration, the LED_x pin can drive an external
LED from the cathode side. Select the R0 and R1 resistors to
control the LED current (refer to the selected LED specifications in
Table 2 for information). External pull-up resistors (RPU0, RPU1) with
a value of 4.7 kΩ are recommended.
Figure 17. Recommended Transistor Controlled LED Circuit
Autosense Polarity
In autosense mode, the polarity of the LED is automatically detected during power-up, hardware reset, or software reset.
LED_0 (internal pull-up) and LED_1 (internal pull-down) have different autosense behaviors due to their internal pull-up and pull-down
configurations. Use one of the configurations described in the
Active High LED Polarity, Active Low LED Polarity, and Transistor
Controlled LED sections so that the two LED_x pins can be controlled the same way.
COMPONENT RECOMMENDATIONS
Crystal
Figure 16. Recommended Active Low LED Circuit
Transistor Controlled LED
Figure 17 displays a typical configuration where the LED current
required is higher than what the LED_0 and LED_1 pins can supply.
The circuit operates using the active high LED mode. An external
transistor such as an N-channel metal-oxide semiconductor field
effect transistor (MOSFET) can be used. The transistor must be
selected so the gate input capacitance is not sinking current above
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The typical connection for an external crystal (XTAL) is shown in
Figure 18. To ensure minimum current consumption and minimize
stray capacitances, make connections between the crystal, capacitors, and ground as close to the ADIN1110 as possible. Consult
individual crystal vendors for recommended load information and
crystal performance specifications.
The crystal specification defines CL. CPCB1 and CPCB2 are the
parasitic impedances of the PCB between XTAL_I/CLK_IN and
ground, and between XTAL_O and ground, respectively. CX1 is the
capacitor connected to XTAL_I/CLK_IN, and CX2 is the capacitor
connected to XTAL_O.
Rev. 0 | 25 of 104
Data Sheet
ADIN1110
APPLICATIONS INFORMATION
Assuming the following:
CPCB1 ≈ CPCB2 ≈ CPCB
► CX1 ≈ CX2 ≈ CXx
►
Then, CXx = 2 × CL – CPCB – 3 pF
Choose precision capacitors for CXx with low appreciable temperature coefficient to minimize frequency errors. Ensure good ground
connections on CX1, CX2, the package ground of the quartz resonator, and the ground paddle of the ADIN1110 package.
Figure 19. External Clock Connection
802.1AS SUPPORT
Typically, any device operating in an 802.1AS network executes the
following operations periodically:
Generate peer delay request and handle response
► Receive peer delay request and generate response
► Receive synchronization frame (slave clock)
► Transmit synchronization frame (master clock)
►
These features require that the MAC is capable of time stamping
specific incoming and outgoing frames.
Figure 18. Crystal Oscillator Connection
To assist with these features, the ADIN1110 MAC provides the
following hardware:
External Clock Input
►
If using a single-ended reference clock on XTAL_I/CLK_IN, leave
XTAL_O open-circuit. This clock must be an ac-coupled 0.8 V
p-p to 2.5 V p-p sine or (filtered) square wave signal. This signal
also applies when connecting the CLK25_REF output clock from
one 10BASE-T1L device to the XTAL_I/CLK_IN input of another
10BASE-T1L device.
►
If VS p-p < 2.5 V p-p,
►
►
C2 is not required
C1 = 1 nF
If VS p-p ≥ 2.5 V p-p
►
►
C2 = 10 pF
C1 = 2.5 (13 pF + CPCBx) / (VS p-p – 2.5)
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Internal free-running counter
Syntonized counter
► Waveform generation on TS_TIMER output
Internal Free Running Counter
The ADIN1110 has an internal free running counter running at 120
MHz. This counter provides an accuracy of 8.333 ns. When using
this counter, there is a period of approximately 35 s. This period
ensures that the clock does not wrap during any of the necessary
operations, for example, between receipt of peer delay request and
transmission of the response.
To enable the free running counter, the TS_EN bits must be set to
1.
When the free running counter is enabled, the ADIN1110 captures
the time stamp for all received frames, and it is appended before
each data frame received. The time stamps of transmitted frames
are captured when requested. See Time Stamp Capture for more
details.
Rev. 0 | 26 of 104
Data Sheet
ADIN1110
APPLICATIONS INFORMATION
The value of the free running counter can be captured using the
input capture signal (TS_CAPT), capturing the value of the counter
in the TS_FREECNT_CAPT register.
Syntonized Counter
The syntonized counter is a 64-bit counter in which the lower 32
bits represent nanoseconds with 1 LSB = 1 ns. When the lower 32
bits reach the value stored in TS_1SEC_CMP, these bits clear and
the upper 32 bits increment representing seconds.
To enable the syntonized counter, the TS_EN bits must be set to 1.
Three modes are supported for capturing time stamps for transmitted and received frames, as follows:
1. Capture a 2-bit sec and a 30-bit ns time stamp as defined in the
OPEN Alliance Specification Section 7.8. See the Configuration
Register 0 section.
2. Capture a 32-bit sec and a 30-bit ns time stamp as defined in
the OPEN Alliance Specification Section 7.8. See the Configuration Register 0 section.
3. Capture the 32-bit free running counter. See the Timer Configuration Register section.
To enable capturing of time stamps for transmitted and received
frames, set FTSE (CONFIG0 register) to 1.
Waveform Generation on TS_TIMER Output
The ADIN1110 can generate an output signal (TS_TIMER) that
uses two counters to generate repeating waveforms driven by the
syntonized time. These two counters, TS_TIMER_HI and TS_TIMER_LO, specify the high and low period of the TS_TIMER signal
and need to be programmed with multiples of 16 because they are
driven by the syntonized time.
Because it is frequent that the required period of TS_TIMER cannot
be programmed as a multiple of 16, the quantization error correction register can be programmed with a value between 0 and 15 to
compensate for the TS_TIMER quantization error.
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It is possible to specify a time with respect to the 64-bit syntonized timer to start the generation of the TS_TIMER output. The
TS_TIMER_START register can be programmed with a value that is
compared with the nanoseconds portion of the syntonized counter
to generate a one-shot start.
The sequence to enable the TS_TIMER output is as follows:
1. If required, change the default value of the TS_TIMER output
from 0 to 1 by writing to the TS_TIMER_DEF bits.
2. Write the values required for the high and low times for the
TS_TIMER output to the TS_TIMER_HI and TS_TIMER_LO
registers.
3. Write the value required for the quantization error correction to
the TS_TIMER_QE_CORR register.
4. Write a start time to the TS_TIMER_START registers. When the
nanoseconds part of the syntonized counter matches this value,
TS_TIMER starts toggling.
The TS_TIMER output can be stopped by writing 1 to the TS_TIMER_STOP bits. When the TS_TIMER output is stopped, the output
goes back to the default value specified in TS_TIMER_DEF.
ELECTROMAGNETIC COMPATIBILITY (EMC)
AND ELECTROMAGNETIC IMMUNITY (EMI)
The ADIN1110 was tested at the system level for EMC and EMI.
Table 17 summarizes the results.
Table 17. EMC/EMI Tests Conducted on ADIN1110 at System Level
EMC/EMI Test
Withstand Threshold
IEC 61000-4-4 Electrical Fast Transient (EFT)
±4 kV
IEC 61000-4-2 ESD (Contact Discharge)
±4 kV
IEC 61000-4-2 ESD (Air Discharge)
±8 kV
IEC 61000-4-5 Surge
±4 kV
IEC 61000-4-6 Conducted Immunity
10 V/m
IEC 61000-4-3 Radiated Immunity
Class A
EN 55032 Radiated Emissions
Class B
Rev. 0 | 27 of 104
Data Sheet
ADIN1110
MAC SPI
The ADIN1110 register interface is via a 4-wire SPI consisting of the
following pins: SCLK, CS, SDI, and SDO/SPI_CFG0.
The R/W and TA fields are defined as follows:
R/W: read/write
► 0: read
► 1: write
► TA: turn around
►
The possible access permissions of the registers are as follows:
R/W: read/write
R: read only
► W: write only
► R/W1C: read/write 1 to clear
►
►
Burst writes and reads must be in multiples of 4 bytes. The last
word (4 bytes) written can contain between 1 byte and 4 bytes of
valid data. However, TX_FSIZE is still written with the original frame
size + 2 bytes for the frame header (see Figure 20). For example,
to transmit a 65-byte frame that is prepended with a 2-byte header,
67 is written to TX_FSIZE, but 68 bytes are transferred over SDI.
The last byte is not used.
The ADIN1110 also allows access to the PHY registers via an SPI
to MDIO master bridge. See the SPI Access to the PHY Registers
section.
The following registers have additional access permissions:
It is possible to enable a CRC on the SPI protocol via a hardware
configuration pin on power-up. This 8-bit CRC uses the polynomial
x8 + x2 + x + 1 seeded with 0x0, and provides up to 3-bit error
detection. The 8-bit CRC is included for every control and data
transaction after the ADDR bits, and then after every 32-bit data
word for every control transaction. There is no 8-bit CRC after
each 32-bit data word in data transactions because Ethernet frames
include their own 32-bit CRC.
R LL: read only, latch low
► R LH: read only, latch high
► R/W SC: read/write, self clear
►
GENERIC SPI PROTOCOL
The generic SPI protocol is detailed in Table 18 to Table 25. The
protocol is determined by the hardware configuration pins. The
register map is organized as a 32-bit map, and all accesses are in
multiples of 32-bit words. Both single and burst access in multiples
of 32-bit words are supported. The MSB of the data is transmitted
first.
Table 18. Control Write Transaction
MSB
SDI
LSB
D47
D46
D45
D44 to D32
D31 to D24
D23 to D16
D15 to D8
D7 to D0
1
0
R/W
ADDR[12:0]
DATA[31:24]
DATA[23:16]
DATA[15:8]
DATA[7:0]
Table 19. Control Read Transaction
MSB
SDI
SDO
LSB
D55
D54
D53
D52 to D40
D39 to D32
D31 to D24
D23 to D16
D15 to D8
D7 to D0
1
0
R/W
ADDR[12:0]
TA[7:0]
0
DATA[31:24]
0
DATA[23:16]
0
DATA[15:8]
0
DATA[7:0]
Table 20. Burst Write Transaction (Control or Data)
MSB
SDI
LSB
D79
D78
D77
D76 to D64
D63 to D56
D55 to D48
D47 to D40
D39 to D32
1
0
R/W
ADDR[12:0]
DATA0[31:24] DATA0[23:16] DATA0[15:8] DATA0[7:0]
D31 to D24
D23 to D16
D15 to D8
DATA1[31:24] DATA1[23:16] DATA1[15:8]
D7 to D0
DATA1[7:0]
Table 21. Burst Read Transaction (Control or Data)
MSB
SDI
SDO
LSB
D87
D86
D85 D84 to D72 D71 to D64 D63 to D56 D55 to D48 D47 to D40 D39 to D32 D31 to D24 D23 to D16 D15 to D8
D7 to D0
1
0
R/W ADDR[12:0] TA[7:0]
0
DATA1
[7:0]
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0
DATA0
[31:24]
0
DATA0
[23:16]
0
DATA 0
[15:8]
0
DATA0
[7:0]
0
DATA1
[31:24]
0
DATA1
[23:16]
0
DATA1
[15:8]
Rev. 0 | 28 of 104
Data Sheet
ADIN1110
MAC SPI
Table 22. Control Write Transaction with CRC
MSB
SDI
LSB
D102
D101
D101
D100 to D89
D88 to D80
D79 to D48
D47 to D40
D39 to D8
D7 to D0
1
0
R/W
ADDR[12:0]
CRC[7:0]
DATA0[31:0]
CRC[7:0]
DATA1[31:0]
CRC[7:0]
Table 23. Control Read Transaction with CRC
MSB
SDI
LSB
D110
D109
D108
D107 to D96
D95 to D88
D87 to D80
D79 to D48
D47 to D40
D39 to D8
D7 to D0
1
0
R/W
ADDR[12:0]
CRC[7:0]
TA[7:0]
0
0
0
0
DATA0[31:0]
CRC[7:0]
DATA1[31:0]
CRC[7:0]
SDO
Table 24. Data Write Transaction with CRC
MSB
SDI
LSB
D86
D85
D84
D83 to D71
D71 to D64
D63 to D32
D31 to D0
1
0
R/W
ADDR[12:0]
CRC[7:0]
DATA0[31:0]
DATA1[31:0]
Table 25. Data Read Transaction with CRC
MSB
SDI
LSB
D94
D93
D92
D91 to D80
D79 to D72
D71 to D64
D63 to D32
D31 to 0
1
0
R/W
ADDR[12:0]
CRC[7:0]
TA[7:0]
0
0
DATA0[31:0]
DATA1[31:0]
SDO
The generic SPI protocol is half duplex. Therefore, it is not possible
to write frame data into the MAC_TX register and read from the
MAC_RX register at the same time. Because of this, the SPI SCLK
frequency must be 25 MHz to achieve full duplex transmissions on
Ethernet at 10 Mbps.
MAC Frame: Transmit and Receive
The 2-byte frame header shown in Table 26 is appended to all
transmitted and received frames. This always precedes the frame
data (see Figure 20).
Time Stamp Capture
On receive, if TIME_STAMP_PRESET is asserted, an additional
4-byte or 8-byte time stamp is provided after the 2-byte header in
Table 26 and before the data frame. This time stamp can then be
stored or discarded by software when reading the receive FIFO.
On transmit, if EGRESS_CAPTURE is set other than 00, the
ADIN1110 captures the time stamp of the transmitted frame into the
respective TTSCxH and TTSCxL registers.
To capture time stamps, enable the counter by setting TS_EN
(TS_CFG register) to 1 and setting FTSE (CONFIG0 register) to 1.
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Transmit Frame over SPI
The following sequence must be followed when using the generic
SPI protocol in store and forward mode:
1. The device defaults to operating in store and forward mode.
2. Verify that there is space for the frame by reading the transmit
FIFO space register. The MAC internally appends a 2-byte size
field to the frame in the FIFO, so ensure that there is sufficient
space for the Ethernet frame plus 2-byte header plus 2-byte
size field.
3. Write the size of the frame in bytes including the 2-byte header
to the MAC transmit frame size register. If the host has appended a frame check sequence (FCS) to the frame, this is also
included in the size.
4. Write the frame data including the 2-byte frame header to the
transmit FIFO using MAC transmit register. The first byte for
transmission is written to TXD, Bits[31:24]. The full frame can
be written in a single burst or split up into multiple smaller burst
writes. The burst write data must always be in multiples of 4
bytes, that is, the last word (4 bytes) can contain between 1
byte and 4 bytes of valid data.
5. When the end of frame (EOF) byte of a frame is read from the
transmit FIFO, the bit transmit ready asserts, and an interrupt
triggers if the TX_RDY_MASK is set.
Rev. 0 | 29 of 104
Data Sheet
ADIN1110
MAC SPI
Figure 20. MAC Frame: Transmit
Figure 21. MAC Frame: Receive
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Rev. 0 | 30 of 104
Data Sheet
ADIN1110
MAC SPI
Table 26. Frame Header
D15 to D11
D10
D9 to D8
D7 to D6
D5 to D4
D3
D2
D1 to D0
Reserved
Priority
Reserved
EGRESS_CAPTURE
Reserved
TIME_STAMP_PARITY
TIME_STAMP_PRESENT
Reserved
See the following definitions:
Priority: indicates which priority queue the frame was received
from. Not used on transmit. Set 0 in transmitted frames.
► EGRESS_CAPTURE: capture an egress time stamp into the
host readable egress time registers, as follows:
►
00: no action.
► 01: capture in the pair of TTSCAL and TTSCAH registers. The
TTSCAA bits in the STATUS0 register assert when captured.
► 10: capture in the pair of TTSCBL and TTSCBH registers. The
TTSCAB bits in the STATUS0 register assert when captured.
► 11: capture in the pair of TTSCCL and TTSCCH registers. The
TTSCAC bits in the STATUS0 register assert when captured.
► TIME_STAMP_PARITY: odd parity for the appended time stamp.
Not used on transmit. Set to 0 in transmitted frames.
► TIME_STAMP_PRESENT: on receive, the first 4 bytes or 8 bytes
of data contain the time stamp for the frame. Not used on
transmit. Set to 0 in transmitted frames.
► Reserved: always set to 0.
►
Receive Frame over SPI
The following procedure must be followed to receive an Ethernet
frame when using the generic SPI protocol in store and forward
mode:
1. The device defaults to operating in store and forward mode.
2. Set the P1_RX_RDY_MASK bit to 0 to enable an interrupt
when a full frame is received.
3. If the P1_RX_RDY bit is asserted, read the MAC receive frame
size register to determine the size of the received frame.
4. Read the frame via the MAC receive register. It is possible to
burst read the entire frame or split it up into multiple smaller
burst reads. The first byte of the received frame is returned
in P1_RX, Bits[31:24]. The burst read transaction must be a
multiple of 4 bytes. Some of the last 4 bytes are padded with 0s
if the frame is not a multiple of 4 bytes in size.
5. Read P1_RX_RDY again. If the value of the bit is 1, another
frame is available to read. Repeat from Step 3.
Cut Through
The generic SPI protocol supports cut through mode for transmit
operations.
Before transmitting any frames, write 1 to the transmit cut through
enable bits.
The threshold at which the frame transmit starts can be modified via
the host transmit start threshold (see the Transmit Threshold Regisanalog.com
ter section). This register has a default value of 1. Therefore, by
default, transmit starts immediately on writing to the host transmit
FIFO.
To ensure that the frame transmission does not under run, the host
transmit FIFO has to be written at a rate greater than 10 Mbps. If
the frame under runs, the host transmit under run error bit asserts.
Generic SPI Errors
Generic SPI CRC Error
If an SPI CRC error occurs on a write to a register, the register is
not written.
If the write is to the transmit register, the transmit FIFO is missing
data and must be cleared by the host. Similarly, a read of the
receive register has missing data in the receive frame, and the
FIFO must be cleared.
If the errored transaction was a write to a configuration register,
the SPI host must issue the write again. If the software does not
know which configuration, the MAC must be reset by writing the
RST_MAC_ONLY keys to the SOFT_RST register.
Generic SPI Transmit Protocol Error (TXPE)
TXPE asserts when the TX_FSIZE register is written, but the MAC
still expects further writes to the transmit register related to the
previous frame size written to the TX_FSIZE register. This error
does not occur in normal operation and indicates an issue with
the software driver, for example, two consecutive writes to the
TX_FSIZE register without any writes to the transmit register.
In response to the assertion of TXPE, the host must clear the
transmit FIFO.
OPEN ALLIANCE SPI PROTOCOL
The OPEN Alliance SPI protocol Version 1.0 can transfer data over
the SPI using full duplex operation, achieving 10 Mbps bidirectional
frame transfer with an SPI clock frequency in the region of 12 MHz
to 16 MHz or greater.
The ADIN1110 supports the following OPEN Alliance SPI capabilities (see the Supported Capabilities Register section for more
details):
Transmit FCS validation
► Cut through
► IEEE 1588 time stamp capture on transmit and receive
► Minimum supported chunk size is 8 bytes
►
Rev. 0 | 31 of 104
Data Sheet
ADIN1110
MAC SPI
The OPEN Alliance SPI protocol defines two types of transactions:
data transactions for Ethernet frame transfers and control transactions for register read/write operations.
A chunk is the basic element of data transactions, and they are
composed of 4 bytes of overhead plus the configured payload size.
Data transactions consist of an equal number of transmit and
receive chunks. Chunks in both transmit and receive directions
may or may not contain valid frame data independent from each
other, allowing for the simultaneous transmission and reception of
different length frames. The data header of the chunk in transmit
frames, and the data footer in receive frames, indicate which bytes
of the payload contain valid frame data. For full information on the
OPEN Alliance SPI protocol used by the ADIN1110, refer to OPEN
Alliance 10BASE-T1x MAC-PHY Serial Interface v1.0.
Note that CS has to be deasserted between data transactions and
control transactions, as shown in Figure 22.
Figure 22. Ethernet Data Frame Transfer Followed by Control Transfer
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Rev. 0 | 32 of 104
Data Sheet
ADIN1110
MAC SPI
Data Chunks
Transmit data chunks consist of a 4-byte header followed by the
transmit data chunk payload, as shown in Figure 23.
The default size of the data chunk payload is 64 bytes. This size
can be configured to 8 bytes, 16 bytes, 32 bytes, or 64 bytes via
the chunk payload selector bits. The data chunk size must be configured before enabling data transmission or reception. Therefore,
when the data chunk size is configured, it must not be changed
without resetting the MAC-PHY.
Data Chunk Transactions
Figure 23. Transmit Data Chunk
Receive data chunks consist of the receive data chunk payload
followed by a 4-byte footer, as shown in Figure 24
Figure 24. Receive Data Chunk
Data transactions consist of 1 to N chunks on SDO and SDI. The
4-byte data header occurs at the beginning of each transmit data
chunk on SDO, and the 4-byte data footer occurs at the end of
each data chunk on SDI. These headers and footers contain the
information needed to determine the validity and location of the
transmitted and received frames within the data chunk payload.
The Ethernet frames start at any 32-bit aligned word within the
payloads, as shown in Figure 25 and Figure 26.
Figure 25. Transmit Data Chunk Cases
Figure 26. Receive Data Chunk Cases
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Rev. 0 | 33 of 104
Data Sheet
ADIN1110
MAC SPI
Transmit Data Header
Table 27. Transmit Data Header
D31
D30
D29
D28 to D24
D23 to D22
D21
D20
D19 to D16
D15
D14
D13 to D8
D7 to D6
D5 to D1
D0
1
SEQ
NORX
RSVD
00
DV
SV
SWO
RSVD
EV
EBO
TSC
RSVD
P
See the following definitions:
►
►
►
►
►
►
SEQ: data chunk sequence. The sequence functionality is not
supported by the ADIN1110. This bit must be set to 0.
NORX: no receive flag. The SPI host can set this bit to indicate
to the MAC-PHY that it does not process receive frame data that
is in the current receive data chunk. For normal operation, set
NORX to 0 to indicate that it accepts and process any receive
frame data within the current chunk.
DV: data valid flag. The SPI host uses this bit to indicate if the
current chunk contains valid transmit data (DV = 1) or not. When
this bit is 0, the MAC-PHY ignores the chunk payload.
SV: start valid flag. When this bit is 1, the beginning of an
Ethernet frame is present in the current transmit data chunk
payload. The SV bit is not to be confused with the start of frame
delimiter (SFD) byte described in IEEE Standard 802.3.
SWO: start word offset. When SV is 1, this field contains the
32-bit word offset into the transmit data chunk payload that
points to the start of the new Ethernet frame. If SV is 0, the host
must write this field as 0.
EV: end valid flag. When this bit is 1, the end of an Ethernet
frame is present in the current transmit data chunk payload.
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EBO: end byte offset. When EV is 1, this field contains the byte
offset into the transmit data chunk payload that points to the last
byte of the Ethernet frame to transmit. If EV is 0, the host must
write this field as 0.
► TSC: time stamp capture. Request a time stamp capture when
the frame is transmitted onto the network. See the following:
► 00: no action.
► 01: capture in the pair of TTSCAL and TTSCAH registers. The
TTSCAA bits in the STATUS0 register assert when captured.
► 10: capture in the pair of TTSCBL and TTSCBH registers. The
TTSCAB bits in the STATUS0 register assert when captured.
► 11: capture in the pair of TTSCCL and TTSCCH registers. The
TTSCAC bits in the STATUS0 register assert when captured.
► P: parity. Parity bit calculated over the transmit data header.
Method is odd parity.
► RSVD: reserved. Always set to 0.
►
Rev. 0 | 34 of 104
Data Sheet
ADIN1110
MAC SPI
Receive Data Footer
Table 28. Receive Data Footer
D31
D30
D29
D28 to D24
D23 to D22
D21
D20
D19 to D16
D15
D14
D13 to D8
D7
D6
D5 to D1
D0
EXST
HDRB
SYNC
RCA
VS
DV
SV
SWO
FD
EV
EBO
RTSA
RTSP
TXC
P
See the following definitions:
►
►
►
►
►
►
►
►
►
►
►
►
►
►
EXST: extended status. This bit is set when any bit in the
STATUS0 or STATUS1 registers are set and not masked.
HDRB: received header bad. When this bit is set, the MAC-PHY
has received a control or data header with a parity error.
SYNC: configuration synchronized flag. This field reflects the
state of the SYNC bit in the CONFIG0 register. When 0, this
bit indicates that the MAC-PHY configuration may not be as
expected by the SPI host. Following configuration, the SPI host
sets the corresponding bit in the configuration register, which is
reflected in this field.
RCA: receive chunks available. The RCA field indicates the
minimum number of additional receive data chunks of frame data
that are available for reading beyond the current one. This field is
0 when there is no more receive frame data pending in the buffer
of the MAC-PHY to be read.
VS: when this bit is 1, it indicates the priority of a received frame.
DV: data valid flag. The SPI host uses this bit to indicate if the
current chunk contains valid transmit data (DV = 1) or not. When
this bit is 0, the SPI host ignores the chunk payload.
SV: start valid flag. When this bit is 1, the beginning of an
Ethernet frame is present in the current transmit data chunk
payload. The SV bit is not to be confused with the SFD byte
described in IEEE Standard 802.3.
SWO: start word offset. When SV is 1, this field contains the
32-bit word offset into the receive data chunk payload that points
to the start of the new Ethernet frame. When a receive time
stamp is added to the beginning of the received frame (RTSA =
1), SWO points to the most significant byte of the time stamp. If
SV is 0, the host must write this field as 0.
FD: frame drop. When set, this bit indicates that the MAC has
detected a condition for which the SPI host must drop the
received Ethernet frame. This bit is only valid at the end of a
received frame (EV = 1), and must be 0 at all other times.
EV: end valid flag. When this bit is 1, the end of an Ethernet
frame is present in the current receive data chunk payload.
EBO: end byte offset. When EV is 1, this field contains the byte
offset into the receive data chunk payload that points to the last
byte of the received Ethernet frame. This field is 0 when EV = 0.
RTSA: receive time stamp added. This bit is set when a 32-bit
or 64-bit time stamp is added to the beginning of the SPI frame.
This bit must be 0 when SV = 0.
TXC: transmit credits. This field contains the minimum number of
transmit data chunks of frame data that the SPI host can write in
a single transaction without incurring a transmit buffer overflow.
P: parity. Parity bit calculated over the receive data header.
Method is odd parity.
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OPEN Alliance SPI Cut Through Mode
If cut through from or to the host is enabled, the method to transfer
frames remains the same as when using store and forward mode.
However, the frame receive starts when sufficient frame data to fill a
chunk is received, and the frame transmit starts when a configured
transmit threshold is reached (see the Transmit Threshold Register
section).
The cut thorough mode can be enabled via the receive cut through
enable bits and transmit cut through enable bits (see the Configuration Register 0 section).
On receive, the MAC returns data as it becomes available. Unlike
in store and forward mode, there may be empty chunks (DV = 0)
between a start of frame (SOF) chunk and an end of frame (EOF)
chunk.
If the host does not read frames fast enough to keep the receive
FIFO empty, the frames are then buffered in the receive FIFO as if
it is operating in store and forward mode. When all the frames are
read, the FIFO returns to operating in cut through mode.
On transmit, the host must provide frame data at a rate fast
enough (>10 Mbps) to ensure that the frame does not under run on
transmit. If the MAC under runs, TXBUE in the STATUS0 register
asserts and the MAC stops transmitting the frame in progress and
appends a bad CRC to the frame.
Cut Through Transmit Latency
The time interval between the time the start of an SPI data transaction with a transmit header SWO of 0 (frame starts immediately
in the chunk), and the time TX_EN rises on the MII with an SPI
frequency of 16 MHz and TX_THRESH = 1 is 4 μs. The PHY
transmit latency is 3.2 μs. This makes a total transmit latency of 7.2
μs.
Cut Through Receive Latency
The receive latency varies based on the chunk size and the SPI
frequency. Table 29 indicates the latency for an SPI frequency of 16
MHz and all supported chunk sizes.
Rev. 0 | 35 of 104
Data Sheet
ADIN1110
MAC SPI
Table 29. Receive Latency for 16 MHz for All Supported Chunk Sizes
PHY Rx Latency (μs)
Time to Receive a Chunk
of Data on the Ethernet
Wire (μs) 1
Time to Start of Frame
Transfer over SPI (μs) 2
Total Rx Latency onto Wire Total Rx Latency to End of
(μs)
First Chunk Transfer (μs) 3
64
6.4
57.6
17
81
98
32
6.4
32
9
47.4
56.4
16
6.4
19.2
5
30.6
35.6
8
6.4
12.8
3
22.2
25.2
Chunk Size
(Bytes)
1
Enough frame data to fill a chunk must be received before a transfer starts on the SPI. The time to receive the frame preamble is also included in this.
2
Assuming that the μC is not waiting for an interrupt and that it is providing back-to-back OPEN Alliance data transactions on the SPI. The frame transfers start in the middle
of the chunk on average.
3
Realistically, the μC cannot use the data until it receives the receive header at the end of the chunk.
Control Transactions
Table 30. Control Command Header
D31
D30
D29
D28
D27 to D24
D23 to D8
LEN7 to LEN1
P
0
HDRB
WNR
AID
MMS
ADDR [15:0]
LEN
P
Control transactions consist of one or more control commands.
These commands are used by the SPI host to read and write
registers within the MAC-PHY, and each one is composed of a
32-bit control command header followed by register data. See Table
30.
Table 31. Register Memory Maps (MMS)
See the following definitions:
Control Write
►
►
►
►
►
►
HDRB: received header bad. When set by the MAC-PHY, HDRB
indicates that a header was received with a parity error. The SPI
host must always clear this bit. The MAC-PHY ignores this value.
WNR: write not read. If 1, data is to be written to registers.
Otherwise, data is to be read.
AID: address increment disable. When clear, the address is
automatically post-incremented by one following each register
read or write.
MMS: memory map selector. This field selects the specific register memory map to access. See Table 31.
ADDR: address of the first register within the selected memory
map to access.
LEN: length. Specifies the number of registers to read/write. This
field is interpreted as the number of registers − 1. Therefore, a
length of 0 reads or writes a single register.
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MMS
Memory Map Description
0
1
Standard control and status (SPI Address 0x00 to Address 0x20)
MAC (from SPI Address 0x30)
The MAC-PHY ignores the final 32 bits of data from the SPI host at
the end of the control write command. The write command and data
is also echoed from the MAC-PHY back to the SPI so it can identify
which register write failed in the case of any bus errors.
Control write commands can write either a single or multiple registers. When multiple registers are written, the address is automatically post incremented.
When a control write command is followed by another control
command, the new control header must immediately follow the last
word of the echoed register write data. The SPI host must deassert
CS following the last word of the echoed register write data when
the write command is the last command of the transaction.
Rev. 0 | 36 of 104
Data Sheet
ADIN1110
MAC SPI
Figure 27. OPEN Alliance Control Transaction
Control Read
The MAC-PHY ignores all data from the SPI host following the control header for the rest of the control read command. Control read commands
can read either a single or multiple registers. When multiple registers are read, the address is automatically post-incremented according to the
address increment disable bit in the control header.
Figure 28. Control Read Transaction
OPEN Alliance SPI Errors
See the following OPEN Alliance SPI errors:
►
SPI Header Parity Error. If a parity error is detected on a transmit
header and there is a transmit frame in the process of being
transferred over SPI, this frame is dropped. If the MAC is operating in cut through mode, the frame transmit stops and a bad
CRC is appended to the frame.
The MAC-PHY returns a fixed value of 0x4000_0000 in every
word until CS goes high. The MAC-PHY responds with DV = 1,
EV = 1, EBO = 0, and FD = 1 in the first data footer following a
new assertion of CS.
If there is a parity error on a control transaction, the operation
does not complete. Software can determine which transaction
caused the error as the MAC-PHY returns a fixed 0x4000_0000
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on SDO for the duration of the SPI transaction. Software can
then resend the corrupted control transaction after clearing the
header error bit.
► Transmit Protocol Error. Occurs when the MAC-PHY detects
protocol errors in the transfer of transmit data chunks. These
errors are usually due to SPI host firmware issues and do not
occur in normal operation. The transmit protocol error bit is set
when a data header received by the MAC-PHY indicates data
valid (DV = 1) without a prior start of frame indication (SV = 1),
in which case the data chunk is ignored. Or, when the MAC-PHY
receives two data headers indicating a start of frame (SV =
1) without and end of frame (EV = 1), the MAC-PHY drops
the frame data from the previous start of frame indicator and
begins accepting the frame data from the second start of frame
indicator.
Rev. 0 | 37 of 104
Data Sheet
ADIN1110
MAC SPI
►
►
►
►
►
Transmit Buffer Overflow. Occurs when attempting to write transmit frame data to the MAC-PHY when there is no transmit buffer
space available as indicated by the transmit credit field (TXC) of
the previous data footer. In this condition, the MAC-PHY ignores
the transmit data chunk and sets the host transmit FIFO overflow
bit, and the frame data already in the buffer is dropped.
Transmit Buffer Under Run. This error can only occur in cut
through mode. The SPI host must always send frame data to
the MAC-PHY faster than the network to avoid this error. When
this error occurs, the host transmit FIFO under run error bit is
set, and the MAC-PHY terminates the frame being transmitted
in a way that invalidates the frame. Additionally, the MAC-PHY
ignores any additional frame data received from the SPI host
until it receives an end of frame indication (EV = 1).
Loss of Framing Error. This error occurs when the CS signal is
deasserted before the expected end of the data chunk or control
command. The MAC-PHY and the loss of frame error is set, any
transmit frame in progress is dropped, and any receive frame in
progress of being sent to the SPI host is terminated.
Receive Buffer Overflow. This error occurs when the SPI host
does not read frame data from the MAC-PHY fast enough. This
error can occur both in store and forward and cut through modes.
When this error occurs, the MAC-PHY terminates the frame
being received from the PHY. In store and forward mode, no
portion of the frame is transferred to the SPI host. In cut through
mode, the MAC-PHY terminates the frame (EV = 1) with frame
drop set (FD = 1).
Control Data Protection Error. The control data protection error
(CDPE) and the loss of frame error (LOFE) bits assert when
protection is enabled on the OPEN Alliance SPI and there is an
error on write data received from the host. The write does not
complete in this case.
If possible, the software executes the write again. If software
does not know which configuration register was written, the device might not be configured properly. In this case, the MAC must
be reset by writing the RST_MAC_ONLY keys to the software
reset register.
FRAME FILTERING ON RECEIVE
By default, the device filters all frames received. To receive frames,
set up the address filtering table, or the default operation for all
received frames can be changed.
The device can be configured to filter up to 16 different MAC
addresses based on the destination MAC address (DA).
To receive frames with a particular DA, that DA has to be programmed to one of the 16 ADDR_FILT_x registers. Each register is 32
bits wide. Therefore, for example, to program a DA of 0800 005A
646B to ADDR_FILT[0], write the following:
To forward frames with this DA to the host, set the TO_HOST
bit within the ADDR_FILT_UPRn to 1. To apply this rule, set the
APPLY2PORT1 bit to 1.
MAC addresses can be masked using the ADDR_MSK_x registers.
For example, to receive all the MAC addresses in the range 0x8000
005A 64xx, write:
1. 0xFFFF to ADDR_MSK_UPR0.
2. 0XFFFFFF00 to ADDR_MSK_LWR0.
Frames that do not match any of the 16 ADDR_FILT_x registers
are dropped by default. If the P1_FWD_UNK2HOST bits within the
HOST_CFG register are set to 1, all frames that do not match a DA
are forwarded to the host. Figure 29 shows the filtering algorithm.
Figure 29. Filtering Algorithm
Frames received with a bad CRC or with RX_ER asserted from the
PHY, as well as runt and jabber frames, are dropped and counted.
Receive Priority Queues
There are two different FIFOs on receive: a high priority FIFO and a
low priority FIFO.
By default, the low priority FIFO is configured to 12 kB, and the
high priority FIFO is configured to 8 kB. The sizes of these FIFOs
can be changed before receiving or transmitting any frames via
the P1_RX_LO_SIZE and P1_RX_HI_SIZE fields in the FIFO_SIZE
register.
Frames are always returned from the high priority FIFO first.
1. 0x0800 to ADDR_FILT_UPR0.
2. 0x005A6468 to ADDR_FILT_LWR0.
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Rev. 0 | 38 of 104
Data Sheet
ADIN1110
MAC SPI
Statistics Counters
There are 15 32-bit counters on the receive port that increment on
each frame transmit and receive.
Table 32. Statistics Counters
Name
Description
P1_RX_FRM_CNT
P1_RX_UCAST_CNT
P1_RX_MCAST_CNT
P1_RX_BCAST_CNT
P1_RX_CRC_ERR_CNT
P1_RX_ALGN_ERR_CNT
P1_RX_PHY_ERR_CNT
P1_RX_LS_ERR_CNT
P1_TX_FRM_CNT
P1_TX_UCAST_CNT
P1_TX_MCAST_CNT
P1_TX_BCAST_CNT
P1_RX_DROP_FULL_CNT
P1_RX_DROP_FILT_CNT
P1_RX_IFG_ERR_CNT
Rx frame count
Rx unicast frame count
Rx multicast frame count
Rx broadcast frame count
Rx CRC errored frame count
Rx alignment error count
Rx PHY error count
Rx long and short frame error count
Tx frame count
Tx unicast frame count
Tx multicast frame count
Tx broadcast frame count
Rx frames dropped due to FIFO full
Rx frames dropped due to filtering
Rx frames received with interframe gap (IFG)
errors
Receive Drop FIFO Full Counter
Before the first byte of a received frame is written into the appropriate receive FIFO, the space in the FIFO is checked. If there is
no space for at least 256 bytes, the frame is dropped and the
P1_RX_DROP_FULL_CNT counter increments. If there is space
for at least 256 bytes in the FIFO, the logic commences writing
the frame to the receive FIFO. If the received frame exceeds 256
bytes and the receive FIFO fills, the frame is dropped and the
P1_RX_DROP_FULL_CNT counter increments.
Frame Receive and Transmit Errors
By default, all received errored frames are dropped and counted.
Received errored frames do not generate interrupts. Instead, they
are dropped and counted, and the software must monitor the
statistics counters.
SRAM ECC Error
When writing a frame to the FIFO, the size of the frame is inserted
in a 16-bit word at the front of the frame and written to the FIFO. A
5-bit error correction code (ECC) is placed alongside the size field.
When this location is read from static random-access memory
(SRAM), the ECC is checked. If a double bit error is detected,
the RX_ECC_ERR or TX_ECC_ERR bits of the STATUS1 register
assert. If a double bit error is detected on reading a frame header
from the receive FIFO, the frame is not transmitted.
In response to an ECC error, a FIFO automatically clears. All
frames in the FIFO are lost, transmission stops, and a bad CRC
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is appended to the frame that was transmitted. The next frame
received is written to a FIFO.
SPI ACCESS TO THE PHY REGISTERS
The ADIN1110 provides indirect access using the SPI to access the
PHY management registers. The 8 registers MDIOACCn in the SPI
register map are used to access the PHY management registers.
Each MDIOACCn register corresponds to an MDIO transaction.
The MDC default speed is 2.5 MHz. Either 2.5 MHz or 4.166
MHz MDC frequency can be selected via the MSPEED bits in the
CONFIG2 register.
The MDIO master polls in round robin mode the TRDONE bits of
the eight MDIOACCn registers. When the MDIO master detects that
one of the TRDONE fields is 0, an MDIO transaction is started
by the MDIO master. When the MDIO transaction completes, the
TRDONE bits are set to 1, and the master proceeds to check the
TRDONE bits of the next MDIOACCn register.
Note that MDIO_DEVAD is always written with the device ID of the
register being accessed, MDIO_PRTAD is always written to 0x1,
and MDIO_ST is written to 0x0 for Clause 45 access (this applies to
all of the following examples).
Example write to PHY Register XYZ:
1. Write MDIOACC0 with MDIO_DATA = the address of Register XYZ, MDIO_DEVAD = the device ID of Register XYZ,
MDIO_PRTAD = 0x1, MDIO_OP = 0x0(ADDR), MDIO_ST =
0x0, and TRDONE = 0x0.
2. Write MDIOACC1 with MDIO_DATA = the value to be written to
Register XYZ, MDIO_OP = 0x1(WR) and TRDONE = 0x0.
3. Optionally, poll MDIOACC0.TRDONE = 0x1 to determine that
the write address operation has completed.
4. Poll MDIOACC1.TRDONE = 0x1 to determine that the write
data operation has completed.
Example read of PHY Register XYZ:
1. Write MDIOACC0 with MDIO_DATA = the address of Register
XYZ, MDIO_OP = 0x0(ADDR), and TRDONE = 0x0.
2. Write MDIOACC1 with MDIO_OP = 0x3(RD) and TRDONE =
0x0.
3. Poll MDIOACC1. TRDONE= 0x1 to determine that the write data operation has completed. MDIOACC1. MDIO_DATA reflects
the content of MDIO Register XYZ.
Example write operation followed by a read to verify the write
operation:
1. Write MDIOACC0 with MDIO_DATA = the address of register
ABC and TRDONE = 0x0.
2. Write MDIOACC1 with MDIO_DATA = the value to be written to
register ABC, MDIO_OP = 0x1(WR), and TRDONE = 0x0.
3. Write MDIOACC2 MDIO_OP = 0x3(RD) and TRDONE = 0x0.
Rev. 0 | 39 of 104
Data Sheet
ADIN1110
MAC SPI
4. Poll MDIOACC2.TRDONE = 0x1 to verify that all operations are
completed. MDIO_DATA reflects the content of register ABC.
Example of four consecutive writes. It is possible to write a command to all 8 register before checking any.
1. Write MDIOACC0 with MDIO_DATA = the address of register
ABC and TRDONE = 0x0.
2. Write MDIOACC1 with the write data for register ABC,
MDIO_OP = 0x1, and TRDONE = 0x0.
3. Write MDIOACC2 with MDIO_DATA = the address of register
DEF and TRDONE = 0x0.
4. Write MDIOACC3 with the write data for register DEF,
MDIO_OP = 0x1, and TRDONE = 0x0.
5. Write MDIOACC4 with MDIO_DATA = the address of register
GHJ and TRDONE = 0x0.
6. Write MDIOACC5 with the write data for register GHJ,
MDIO_OP = 0x1, and TRDONE = 0x0.
7. Write MDIOACC6 with MDIO_DATA = the address of Register
XYZ and TRDONE = 0x0.
8. Write MDIOACC7 with the write data for Register XYZ,
MDIO_OP = 0x1, and TRDONE = 0x0.
9. Host polls MDIOACC7. TRDONE = 0x1 to verify that all write
data operations are complete.
Example burst read starting from Register XYZ:
1. Write MDIOACC0 with MDIO_DATA = the address of the Register XYZ, MDIO_OP = 0x0(ADDR), and TRDONE = 0x0
2. Write MDIOACC1 with MDIO_OP = 0x2(INC_RD) and
TRDONE = 0x0.
3. Write MDIOACC2 with MDIO_OP = 0x2(INC_RD) and
TRDONE = 0x0.
4. Write MDIOACC3 with MDIO_OP = 0x2(INC_RD) and
TRDONE = 0x0.
5. Write MDIOACC4 with MDIO_OP = 0x2(INC_RD) and
TRDONE = 0x0.
6. Write MDIOACC5 with MDIO_OP = 0x2(INC_RD) and
TRDONE = 0x0.
7. Write MDIOACC6 with MDIO_OP = 0x2(INC_RD) and
TRDONE = 0x0.
8. Write MDIOACC7 with MDIO_OP = 0x2(INC_RD) and
TRDONE = 0x0.
9. Poll MDIOACC7. TRDONE = 1 to verify that all read data
operations are complete.
10. Read MDIOACC1. MDIO_DATA, reflects the content of Register
XYZ.
11. Read MDIOACC2. MDIO_DATA, reflects the content of register
at address XYZ. ADDR + 1.
12. Read MDIOACC3. MDIO_DATA, reflects the content of register
at address XYZ. ADDR + 2.
13. Read MDIOACC4. MDIO_DATA, reflects the content of register
at address XYZ. ADDR + 3.
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14. Read MDIOACC5. MDIO_DATA, reflects the content of register
at address XYZ. ADDR + 4.
15. Read MDIOACC6. MDIO_DATA, reflects the content of register
at address XYZ. ADDR + 5.
16. Read MDIOACC7. MDIO_DATA, reflects the content of register
at address XYZ. ADDR + 6.
Example of Clause 22 write of Register XYZ:
1. Write MDIOACC0 with MDIO_DATA = write data,
MDIO_DEV_AD = the address of the Register XYZ,
MDIO_PRTAD = 0x1, MDIO_OP = 0x1(WR), MDIO_ST =
0x1(Clause 22), and TRDONE = 0x0.
2. Poll MDIOACC0. TRDONE= 0x1 to determine that the write
data operation is complete.
Example of Clause 22 read of Register XYZ:
1. Write MDIOACC0 with MDIO_DEV_AD = the address of the
Register XYZ, MDIO_PRTAD = 0x1, MDIO_OP = 0x3(RD),
MDIO_ST = 0x1(Clause 22), and TRDONE = 0x0.
2. Poll MDIOACC0. TRDONE = 0x1 to determine that the read
operation is complete. MDIO_DATA reflects the contents of
MDIO Register XYZ.
Example of Clause 22 write and read back of Register XYZ:
1. Write MDIOACC0 with MDIO_DATA = write data,
MDIO_DEV_AD = the address of the Register XYZ,
MDIO_PRTAD = 0x1, MDIO_OP = 0x1(WR), MDIO_ST =
0x1(Clause 22), and TRDONE = 0x0.
2. Write MDIOACC1 with MDIO_DEV_AD = the address of the
Register XYZ, MDIO_PRTAD = 0x1, MDIO_OP = 0x3(RD),
MDIO_ST = 0x1(Clause 22), and TRDONE = 0x0.
3. Poll MDIOACC1. TRDONE = 0x1 to determine that the read
operation is complete. MDIO_DATA reflects the contents of
MDIO Register XYZ.
MDIO PHY Address Determination
The MDIO PHY address for the ADIN1110 PHY is 0x1.
PHY Registers Contents
The PHY registers provide access to control and status information
in the management registers.
The registers of the PHY Clause 45 register map are made up of
four device address groupings (see Table 33) based on the MDIO
manageable device (MMD). Within each device address space,
IEEE standard registers are located in register addresses between
0x0000 and 0x7FFF, and vendor specific registers are located in
register addresses from 0x8000 to 0xFFFF.
Rev. 0 | 40 of 104
Data Sheet
ADIN1110
MAC SPI
Table 33. Clause 45 Register Groupings
Device Address
MMD Name
0x01
Physical medium attachment (PMA)/physical medium
dependent (PMD)
Physical coding sublayer (PCS)
Autonegotiation
Vendor Specific 1
0x03
0x07
0x1E
Clause 45 can access to up to 32 PHYs consisting of up to 32
MMDs through a single MDIO interface.
The default value of some of the registers are determined by the
value of the hardware configuration pins, which are read just after
the RESET pin is deasserted. In these cases, the reset value
in the register table is listed as pin dependent, which allows the
default operation of the ADIN1110 to be configured without having
to write to it over the SPI. This method is useful in unmanaged
applications where the desired operation of the PHY is configured
from the hardware configuration pins without any software intervention. For unmanaged applications, do not configure the PHY to
enter software power-down mode after reset to ensure that the PHY
immediately attempts to bring up links as configured by the other
hardware configuration pins. In managed applications, software is
available to configure the PHY via the management interface. In
this case, it is possible to use the hardware configuration pins to
configure the PHY to enter software power-down mode after reset,
such that the PHY can be configured before linking is attempted.
Recommended Register Operation
Many of the PHY registers in the ADIN1110 are defined in the IEEE
Standard 802.3, and the exact behavior of these registers follows
the standard. This behavior may not always be obvious and is
described in this section, including the recommended operation and
use of the registers.
Latch Low Registers
Another implication is that it is important that software take account of the interaction between MDIO accessible bits that share
a register address. For example, the AN_PAGE_RX bits and
AN_LINK_STATUS bits reside at the same register address. As
a result, reading the AN_PAGE_RX bits clears any active latching
condition associated with the AN_LINK_STATUS bits.
IEEE Duplicated Registers
The IEEE Standard 802.3-2018 covers a very wide range of
standards and speeds, from 10 Mbps to 40 Gbps and higher,
and includes a very large number of clauses. There are registers
associated with many clauses, and different PHYs can include
different clauses and combinations of clauses. Therefore, registers
for common functions like software reset, software power-down,
loopback, and so on, tend to be implemented in multiple clauses.
In the ADIN1110, the physical implementation of these registers is
in a single location, but they can be accessed at multiple addresses. For example, the software reset bit, can be read or written in
all the following IEEE MMD locations and vendor specific register
locations:
PMA_SFT_RST
B10L_PMA_SFT_RST
► PCS_SFT_RST
► B10L_PCS_SFT_RST
► CRSM_SFT_RST
►
►
In this example, these are the PMA/PMD, PCS, autonegotiation,
and Vendor Specific MMD 1 device address locations (per Table
33).
Having multiple address locations for the same register makes
the use of the device more complex than necessary, particularly
in relation to registers that have latch low or self clear access
permissions. This is an unavoidable consequence of the IEEE
standard.
The IEEE Standard 802.3-2018 requires certain MDIO accessible registers to exhibit latch low behavior. The idea is to allow
software that only intermittently reads these registers to detect
conditions that can be transitory or short lived. For example, the
AN_LINK_STATUS bit is required to latch low. When the device
exits from a reset or power-down state, the latching condition is
not active and the value of the AN_LINK_STATUS bit reflects the
current status of the link. However, if the link comes up and drops,
the latching condition is active. In this case, the AN_LINK_STATUS
bit reads as 0 even if the link has come back up again in the interim. The latching condition is only cleared when the AN_LINK_STATUS bit is read, ensuring the software has had the opportunity to
observe that the link dropped.
The ADIN1110 data sheet only calls out a single recommended
address location for each of these IEEE registers to simplify the
operation and use of the device. In general, the registers introduced in the 802.3cg (10BASE-T1L) section of the standard are
recommended over older (equivalent) registers. Often, registers in
a vendor specific address are recommended, particularly where a
register brings a number of useful IEEE register bits into a single
register address. The ADIN1110 responds to register accesses to
all the IEEE register address locations covered by the 10BASE-T1L
standard when the start-up is complete after a power-on reset,
hardware reset, or software reset.
One implication of this latch low behavior is that, if software wishes
to determine the current status of the link, it must perform two reads
of the AN_LINK_STATUS bit back to back. The first read is needed
to clear any active latching condition.
All register write operations must be performed as read modify write
operations. If this process is not followed, the value of the register
bits can inadvertently change.
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Rev. 0 | 41 of 104
Data Sheet
ADIN1110
REGISTERS
SPI REGISTER MAP
Table 34. SPI Register Map
Address
Name
Description
Reset
Access
0x00
0x01
0x02
0x03
0x04
0x06
0x08
0x09
0x0B
0x0C
0x0D
0x10
0x11
0x12
0x13
0x14
0x15
0x20 to 0x27 by 1
0x30
0x31
0x32
0x34
0x36
0x37 to 0x3A by 1
0x3B
0x3C
0x3D
0x3E
0x3F
0x40
0x41
0x42
0x43 to 0x49 by 1
0x50 to 0x6E by 2
0x51 to 0x6F by 2
0x70 to 0x72 by 2
0x71 to 0x73 by 2
0x80
0x81
0x82
0x83
0x84
0x85
0x86
0x87
IDVER
PHYID
CAPABILITY
RESET
CONFIG0
CONFIG2
STATUS0
STATUS1
BUFSTS
IMASK0
IMASK1
TTSCAH
TTSCAL
TTSCBH
TTSCBL
TTSCCH
TTSCCL
MDIOACCn
TX_FSIZE
TX
TX_SPACE
TX_THRESH
FIFO_CLR
SCRATCHn
MAC_RST_STATUS
SOFT_RST
SPI_INJ_ERR
FIFO_SIZE
TFC
TXSIZE
HTX_OVF_FRM_CNT
MECC_ERR_ADDR
CECC_ERRn
ADDR_FILT_UPRn
ADDR_FILT_LWRn
ADDR_MSK_UPRn
ADDR_MSK_LWRn
TS_ADDEND
TS_1SEC_CMP
TS_SEC_CNT
TS_NS_CNT
TS_CFG
TS_TIMER_HI
TS_TIMER_LO
TS_TIMER_QE_CORR
Identification Version Register.
PHY Identification Register.
Supported Capabilities Register.
Reset Control and Status Register.
Configuration Register 0.
Configuration Register 2.
Status Register 0.
Status Register 1.
Buffer Status Register.
Interrupt Mask Register 0.
Mask Bits for Driving the Interrupt Pin Register.
Transmit Time Stamp Capture Register A (High).
Transmit Time Stamp Capture Register A (Low).
Transmit Time Stamp Capture Register B (High).
Transmit Time Stamp Capture Register B (Low).
Transmit Time Stamp Capture Register C (High).
Transmit Time Stamp Capture Register C (Low).
MDIO Access Registers.
MAC Tx Frame Size Register.
MAC Transmit Register.
Tx FIFO Space Register.
Transmit Threshold Register.
MAC FIFO Clear Register.
Scratch Registers.
MAC Reset Status.
Software Reset Register.
Inject an Error on MISO from the DUT.
FIFO Sizes Register.
Tx FIFO Frame Count Register.
Tx FIFO Valid Half Words Register.
Host Tx Frames Dropped Due to FIFO Overflow.
Address of a Detected ECC Error in Memory.
Corrected ECC Error Counters.
MAC Address Rule and DA Filter Upper 16 Bits Registers.
MAC Address DA Filter Lower 32 Bits Registers.
Upper 16 Bits of the MAC Address Mask.
Lower 32 Bits of the MAC Address Mask.
Time Stamp Accumulator Addend Register.
Timer Update Compare Register.
Seconds Counter Register.
Nanoseconds Counter Register.
Timer Configuration Register.
High Period for TS_TIMER Register.
Low Period for TS_TIMER Register.
Quantization Error Correction Register.
0x00000010
0x0283BC91
0x000006C3
0x00000000
0x00000006
0x00000800
0x00000040
0x00000000
0x00007700
0x00001FBF
0x43FA1F1A
0x00000000
0x00000000
0x00000000
0x00000000
0x00000000
0x00000000
0x8C000000
0x00000000
0x00000000
0x00000FFF
0x00000041
0x00000000
0x00000000
0x00000003
0x00000000
0x00000000
0x00000464
0x00000000
0x00000000
0x00000000
0x00000000
0x00000000
0x00000000
0x00000000
0x0000FFFF
0xFFFFFFFF
0x85555555
0x3B9ACA00
0x00000000
0x00000000
0x00000000
0x00000000
0x00000000
0x00000000
R
R
R
W
R/W
R/W
R/W
R/W
R
R/W
R/W
R
R
R
R
R
R
R/W
R/W
W
R
R/W
W
R/W
R
W
R/W
R/W
R
R
R
R
R
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
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Rev. 0 | 42 of 104
Data Sheet
ADIN1110
REGISTERS
Table 34. SPI Register Map
Address
Name
Description
Reset
Access
0x88
0x89
0x8A
0x8B
0x90
0x91
0xA0
0xA1
0xA2
0xA3
0xA4
0xA5
0xA6
0xA7
0xA8
0xA9
0xAA
0xAB
0xAC
0xAD
0xAE
0xB0
0xB3
0xB4
0xB5
0xB6
0xB7
0xB8
0xB9
0xBA
0xBB
TS_TIMER_START
TS_EXT_CAPT0
TS_EXT_CAPT1
TS_FREECNT_CAPT
P1_RX_FSIZE
P1_RX
P1_RX_FRM_CNT
P1_RX_BCAST_CNT
P1_RX_MCAST_CNT
P1_RX_UCAST_CNT
P1_RX_CRC_ERR_CNT
P1_RX_ALGN_ERR_CNT
P1_RX_LS_ERR_CNT
P1_RX_PHY_ERR_CNT
P1_TX_FRM_CNT
P1_TX_BCAST_CNT
P1_TX_MCAST_CNT
P1_TX_UCAST_CNT
P1_RX_DROP_FULL_CNT
P1_RX_DROP_FILT_CNT
P1_RX_IFG_ERR_CNT
P1_TX_IFG
P1_LOOP
P1_RX_CRC_EN
P1_RX_IFG
P1_RX_MAX_LEN
P1_RX_MIN_LEN
P1_LO_RFC
P1_HI_RFC
P1_LO_RXSIZE
P1_HI_RXSIZE
TS_TIMER Counter Start Time Register.
TS_CAPT Pin 0 Time Stamp Register.
TS_CAPT Pin 1 Time Stamp Register.
TS_CAPT Free Running Counter Register.
P1 MAC Rx Frame Size Register.
P1 MAC Receive Register.
P1 Rx Frame Count Register.
P1 Rx Broadcast Frame Count Register.
P1 Rx Multicast Frame Count Register.
P1 Rx Unicast Frame Count Register.
P1 Rx CRC Errored Frame Count Register.
P1 Rx Align Error Count Register.
P1 Rx Long/Short Frame Error Count Register.
P1 Rx PHY Error Count Register.
P1 Tx Frame Count Register.
P1 Tx Broadcast Frame Count Register.
P1 Tx Multicast Frame Count Register.
P1 Tx Unicast Frame Count Register.
P1 Rx Frames Dropped Due to FIFO Full Register.
P1 Rx Frames Dropped Due to Filtering Register.
Frame Received on Port 1 with IFG Errors.
P1 Transmit Inter Frame Gap Register.
P1 MAC Loopback Enable Register.
P1 CRC Check Enable on Receive Register.
P1 Receive Inter Frame Gap Register.
P1 Max Receive Frame Length Register.
P1 Min Receive Frame Length Register.
P1 Rx Low Priority FIFO Frame Count Register.
P1 Rx High Priority FIFO Frame Count Register.
P1 Low Priority Rx FIFO Valid Half Words Register.
P1 High Priority Rx FIFO Valid Half Words Register.
0x00000000
0x00000000
0x00000000
0x00000000
0x00000000
0x00000000
0x00000000
0x00000000
0x00000000
0x00000000
0x00000000
0x00000000
0x00000000
0x00000000
0x00000000
0x00000000
0x00000000
0x00000000
0x00000000
0x00000000
0x00000000
0x0000000B
0x00000000
0x00000001
0x0000000A
0x00000618
0x00000040
0x00000000
0x00000000
0x00000000
0x00000000
R/W
R
R
R
R
R
R
R
R
R
R
R
R
R
R
R
R
R
R
R
R
R/W
R/W
R/W
R/W
R/W
R/W
R
R
R
R
Identification Version Register
Address: 0x00, Reset: 0x00000010, Name: IDVER
Table 35. Bit Descriptions for IDVER
Bits
Bit Name
Description
Reset
Access
[31:8]
[7:4]
RESERVED
MAJVER
0x0
0x1
R
R
[3:0]
MINVER
Reserved.
OPEN Alliance Major Version. Major version identifier of the OPEN Alliance serial 10BASE-T1x MAC-PHY
interface specification supported by this device.
OPEN Alliance Minor Version. Minor version identifier of the OPEN Alliance serial 10BASE-T1x MAC-PHY
interface specification supported by this device.
0x0
R
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Rev. 0 | 43 of 104
Data Sheet
ADIN1110
REGISTERS
PHY Identification Register
Address: 0x01, Reset: 0x0283BC91, Name: PHYID
Table 36. Bit Descriptions for PHYID
Bits
Bit Name
Description
[31:10]
OUI
[9:4]
[3:0]
MODEL
REVISION
Organizationally Unique Identifier (Bits[23:2]). The 22 bits in the OUI field correspond to the 22 most
0xA0EF
significant bits of the manufacturer’s assigned 24-bit organizationally unique identifier (OUI). The OUI is
arranged into the PHYID register such that OUI Bit 2 is located at PHYID Bit 31, and OUI Bit 23 is located at
PHYID Bit 10.
Manufacturer’s Model Number. The manufacturer’s model number is used to identify the device.
0x9
Manufacturer’s Revision Number. The manufacturer’s product revision number is used to indicate a revision 0x1
level of the device.
Reset
Access
R
R
R
Supported Capabilities Register
Address: 0x02, Reset: 0x000006C3, Name: CAPABILITY
Table 37. Bit Descriptions for CAPABILITY
Bits
Bit Name
Description
Reset
Access
[31:11]
10
RESERVED
TXFCSVC
0x0
0x1
R
R
9
IPRAC
0x1
R
8
DPRAC
0x0
R
7
CTC
0x1
R
6
FTSC
0x1
R
5
AIDC
0x0
R
4
SEQC
Reserved.
Transmit Frame Check Sequence Validation Capability. Indicates the ability to validate the FCS appended by
and received from the SPI host. When this bit is set it also indicates the ability of the MAC to be configured to
accept egress frames with padding and FCS appended by the SPI host, and send ingress frames to the SPI
host with the received FCS.
0: transmit FCS validation is not supported.
1: transmit FCS validation is supported.
Indirect PHY Register Access Capability. Indicates if PHY registers are directly accessible within the SPI
register memory space.
0: PHY registers are not indirectly accessible.
1: PHY registers are indirectly accessible.
Direct PHY Register Access Capability. Indicates if PHY registers are directly accessible within the SPI
register memory space.
0: PHY registers are not directly accessible.
1: PHY registers are directly accessible.
Cut Through Capability. Indicates if the MAC-PHY device supports cut through transfer of frames through the
MAC-PHY to and from the network.
0: cut through not supported.
1: cut through supported.
Frame Time Stamp Capability. Frame Time Stamp Capability. Indicates if the MAC-PHY device supports the
capturing of IEEE 1588 time stamps on frame receive from or transmit to the network.
1: IEEE 1588 time stamp capture on frame Tx/Rx is supported.
0: IEEE 1588 time stamp capture on frame Tx/Rx is not supported.
Address Increment Disable Capability. Indicates if the MAC-PHY device supports the disabling of the
automatic post-incrementing of the register address in control command reads and writes through the AID bit
in the control command header. Address increment disable is not supported. This field is only used with the
OPEN Alliance SPI protocol.
Tx Data Chunk Sequence and Retry Capability. Indicates if the MAC-PHY supports monitoring the SEQ bit
sent by the SPI host in the Tx data chunk header and the retry of Tx data chunks. This field is only used with
the OPEN Alliance SPI protocol.
1: Tx data chunk sequence and retry is supported.
0: Tx data chunk sequence and retry is not supported.
0x0
R
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Rev. 0 | 44 of 104
Data Sheet
ADIN1110
REGISTERS
Table 37. Bit Descriptions for CAPABILITY
Bits
Bit Name
Description
Reset
Access
3
[2:0]
RESERVED
MINCPS
Reserved.
Minimum Supported Chunk Payload Size (CPS). Indicates the minimum size chunk payload that can be
configured into the CPS field of the CONFIG0 register. The minimum supported chunk payload size is 2^N,
where N is the value of these bits. This field is only used with the OPEN Alliance SPI protocol.
110: minimum supported chunk payload size is 64 bytes.
101: minimum supported chunk payload size is 32 bytes.
100: minimum supported chunk payload size is 16 bytes.
011: minimum supported chunk payload size is 8 bytes.
0x0
0x3
R
R
Reset
Access
Reset Control and Status Register
Address: 0x03, Reset: 0x00000000, Name: RESET
Table 38. Bit Descriptions for RESET
Bits
Bit Name
Description
[31:1]
0
RESERVED
SWRESET
Reserved.
0x0
Software Reset. MAC-PHY Software Reset. The action of writing a 1 to this bit fully resets the MAC-PHY,
0x0
including the integrated PHY, to an initial state including, but not limited to, resetting all state machines and
registers to their default value. When this bit is set, the reset does not occur until CS is deasserted to allow for
the control command write to complete. CS must be held asserted for at least 100 ns for the reset to take effect.
This bit is self clearing.
R
W
Configuration Register 0
Address: 0x04, Reset: 0x00000006, Name: CONFIG0
Table 39. Bit Descriptions for CONFIG0
Bits
Bit Name
Description
Reset
Access
[31:16]
15
RESERVED
SYNC
0x0
0x0
R
R/W1S
14
TXFCSVE
0x0
R/W
13
CSARFE
0x0
R/W
12
ZARFE
0x0
R/W
[11:10]
TXCTHRESH
Reserved.
Configuration Synchronization. The state of this bit is reflected in the Rx footer SYNC bit. This bit defaults
to 0 upon reset. When written to a 1 by the SPI host, writing 0 does not clear this bit. Immediately after any
reset, the SYNC bit clears to 0 and RESETC bit is set to 1, and the interrupt pin asserts.
0: the MAC-PHY has reset and is not configured.
1: the MAC-PHY is configured.
Transmit Frame Check Sequence Validation Enable. When set, the final 4 octets of all Ethernet frames
received are validated. CRC_APPEND must be 0 if this bit is set. That is, the MAC must not be configured
to append a CRC to each transmitted frame.
CS Align Receive Frame Enable. When set, all receive Ethernet frames data only start at the beginning of
the first receive chunk payload following CS assertion. The start word offset (SWO) is always 0. Receive
frames can begin within any receive chunk when this bit is clear. Only applies to the OPEN Alliance SPI
Protocol.
Zero Align Receive Frame Enable. When set, all receive Ethernet frames data are aligned to start at the
beginning of the receive chunk payload with a SWO of 0. Receive frames can begin anywhere within the
receive chunk payload when this bit is clear. Only applies to the OPEN Alliance SPI protocol.
Transmit Credit Threshold. This field configures the number of transmit credits (TXC) of free buffer that
must be available for writing before IRQn is asserted. 00 ≥ 1 credit (default), 01 ≥ 4 credits, 10 ≥ 8 credits,
and 11 ≥ 16 credits. Only applies to the OPEN Alliance SPI Protocol.
00: ≥1 credit.
01: ≥4 credit.
10: ≥8 credit.
11: ≥16 credit.
0x0
R/W
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Data Sheet
ADIN1110
REGISTERS
Table 39. Bit Descriptions for CONFIG0
Bits
Bit Name
Description
Reset
Access
9
TXCTE
0x0
R/W
8
RXCTE
0x0
R/W
7
FTSE
0x0
R/W
6
FTSS
0x0
R/W
5
PROTE
0x0
R
4
SEQE
0x0
R/W
3
[2:0]
RESERVED
CPS
Transmit Cut Through Enable. This bit enables the cut through mode of frame transfer through the
MAC-PHY device from the SPI host to the network. When cut through on Tx is enabled, the host must
ensure that data is provided to the device at a rate of >10 Mbps to ensure frame transmission does not
under run.
Receive Cut Through Enable. This bit enables the cut through mode of frame transfer through the
MAC-PHY device from the network to the SPI host. Cut through must be enabled on device configuration
before receiving frames is enabled. That is, enable cut through before setting P1_FWD_UNK2HOST or
writing to the ADDR_FILT_x registers. RXCTE must be 0 when using the generic SPI protocol.
Frame Time Stamp Enable. This bit enables IEEE 1588 receive and transmit frame time stamps.
0: frame receive/transmit time stamps are disabled.
1: frame receive/transmit time stamps are enabled.
Receive Frame Time Stamp Select. When supported by this MAC-PHY device and enabled by FTSE = 1,
this bit configures the size and format of the time stamps appended to received frames and capture on
request of transmit frames.
0: 32-bit time stamps.
1: 64-bit time stamps.
Enable Control Data Read Write Protection. When set and using the OPEN Alliance SPI protocol, all
control data written to and read from the MAC-PHY is transferred with its complement for detection of bit
errors. When set and using the generic SPI protocol, a CRC8 must be provided on SDI, and read data on
SDO provides a CRC8. Note this bit cannot be written. Its value is set via sensing a pin on power-up.
Enable TX Data Chunk Sequence and Retry. When supported by this MAC-PHY device, this bit enables
MAC-PHY monitoring of the SEQ bit transmitted in the Tx data chunk header by the SPI host and Tx data
chunk retries. 0: support for Tx data chunk sequence and retry is disabled. The MAC-PHY ignores the Tx
header SEQ bit. 1: support for Tx data chunk sequence and retry is enabled. The MAC-PHY monitors the
SEQ bit in the Tx header and allows rewriting of the Tx data chunks when the SEQ bit does not change.
Not supported. Only applies to the OPEN Alliance SPI protocol.
Reserved.
Chunk Payload Selector (N). Chunk Payload Size is 2^N. N = 3 minimum and 6 maximum. Default is 64
bytes. This field must be set on device configuration before frame transmission from the host starts and
before enabling receiving frames into the Rx FIFOs. This field cannot be modified while transmitting a
frame from the host or while sending a received frame to the host. Once the configuration synchronization
(SYNC) bit is set, the chunk payload size does not change without a reset of the MAC-PHY. The minimum
supported chunk payload size for this MAC-PHY device is indicated in the CPSMIN field of the capability
register. Only applies to the OPEN Alliance SPI protocol.
011: chunk size is 8 bytes.
100: chunk size is 16 bytes.
101: chunk size is 32 bytes.
110: chunk size is 64 bytes.
0x0
0x6
R
R/W
Configuration Register 2
Address: 0x06, Reset: 0x00000800, Name: CONFIG2
Vendor specific.
Table 40. Bit Descriptions for CONFIG2
Bits
Bit Name
Description
Reset
Access
[31:9]
8
RESERVED
TX_RDY_ON_EMPTY
0x4
0x0
R
R/W
7
SFD_DETECT_SRC
Reserved.
Assert TX_RDY When the Tx FIFO is Empty. By default, TX_RDY asserts when a frame
transmits. If this bit is set, TX_RDY asserts when the Tx FIFO is empty. This field is only used
with the generic SPI protocol.
Determines If the SFD is Detected in the PHY or MAC.
0x0
R/W
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Data Sheet
ADIN1110
REGISTERS
Table 40. Bit Descriptions for CONFIG2
Bits
Bit Name
Description
6
STATS_CLR_ON_RD
5
CRC_APPEND
4
P1_RCV_IFG_ERR_FRM
3
2
RESERVED
P1_FWD_UNK2HOST
[1:0]
MSPEED
0: select the SFD from the PHY. This option provides the least jitter as the SFD is detected in
the same 120 MHz clock domain as is used in 1588 timer logic.
1: select the SFD from the MAC. The SFD from the MAC is from the 25 MHz clock domain
and results in additional jitter on the SFD detection.
Statistics Clear on Reading. This field determines if
the following registers/counters are cleared on reading:
P1_RX_FRM_CNT, P1_RX_BCAST_CNT, P1_RX_MCAST_CNT, P1_RX_UCAST_CNT,
P1_RX_CRC_ERR_CNT,P1_RX_ALGN_ERR_CNT, P1_RX_LS_ERR_CNT,
P1_RX_PHY_ERR_CNT, P1_TX_FRM_CNT, P1_TX_BCAST_CNT, P1_TX_MCAST_CNT,
P1_TX_UCAST_CNT, P1_RX_DROP_FULL_CNT, P1_RX_DROP_FILT_CNT,
P1_RX_IFG_ERR_CNT, and CECC_ERRn
0: statistic counter is not cleared on reading. When the maximum value is reached, the
counters roll over to 0x0.
1: clear statistics counters on reading. If a counter reaches its maximum value, the counter
holds at its maximum until read. When using the generic SPI protocol, the status counters
must be burst read in one SPI transaction to ensure all counters are cleared properly in
sequence. If a single SPI register/counter is read, it clears and the next counter (address
location) also clears when using the generic SPI protocol.
Enable CRC Append. Enable CRC append in the MAC Tx path. Enables (1) or disables
(0) CRC appendage by the MAC. If this field is set to 0, the MAC assumes that the host
is providing a frame with a valid CRC header at the end. It is recommended that the host
always appends a CRC32 with the frame as this provides errors detection over the SPI for
transmitted frames. The CRC32 is checked as the frame is transmitted. If an error is detected,
TXFCSE asserts. Similarly, on receive, the CRC32 is forwarded with the frame to the host
where the host must verify it is correct.
Admit Frames with IFG Errors on Port 1 (P1). If enabled, the MAC admits frames with IFG
errors on Port 1. Enables reception of frames that violate the minimum IFG requirement on
Port 1.
Reserved.
Forward Frames Not Matching Any MAC Address to the Host. Determines the default rule for
forwarding unknown frames. Frames with an unknown destination address are placed in the
low priority FIFO.
SPI to MDIO Bridge MDC Clock Speed.
00: 2.5 MHz.
01: 4.166 MHz.
Reset
Access
0x0
R/W
0x0
R/W
0x0
R/W
0x0
0x0
R/W
R/W
0x0
R/W
Status Register 0
Address: 0x08, Reset: 0x00000040, Name: STATUS0
Table 41. Bit Descriptions for STATUS0
Bits
Bit Name
Description
Reset
Access
[31:13]
12
RESERVED
CDPE
0x0
0x0
R
R/W1C
11
TXFCSE
0x0
R/W1C
10
9
8
TTSCAC
TTSCAB
TTSCAA
Reserved.
Control Data Protection Error. When control data read/write protection is enabled, this bit indicates that the
MAC-PHY detected an error in protected control write data received from the host. When not implemented,
this bit must be reserved with a read-only value of 0. This field is only used with the OPEN Alliance SPI
protocol.
Transmit Frame Check Sequence Error. This bit indicates that a frame was received over SPI from the host
with an invalid FCS appended. The frame is still forwarded from the device because the FCS is checked as
the frame is being transmitted.
Transmit Time Stamp Capture Available C.
Transmit Time Stamp Capture Available B.
Transmit Time Stamp Capture Available A.
0x0
0x0
0x0
R/W1C
R/W1C
R/W1C
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Table 41. Bit Descriptions for STATUS0
Bits
Bit Name
Description
Reset
Access
7
PHYINT
0x0
R
6
RESETC
0x1
R/W1C
5
HDRE
0x0
R/W1C
4
LOFE
0x0
R/W1C
3
RXBOE
0x0
R/W1C
2
TXBUE
0x0
R/W1C
1
TXBOE
0x0
R/W1C
0
TXPE
PHY Interrupt for Port 1. Host software must read the MDIO Interrupt Status registers (PhySubsysIrqStatus
or CrsmIrqStatus) to determine the source of the interrupt. On exiting power-on reset or pin reset, this bit
asserts, but this field is masked from asserting an interrupt by default.
Reset Complete. This bit is set when the MAC-PHY reset is complete and ready for configuration. When set, it
generates a non-maskable interrupt assertion on IRQn to alert the SPI host. Additionally, setting the RESETC
bit also sets EXST = 1 in the first Rx footer, or until this bit is cleared by action of the SPI host writing a 1.
Header Error. When set, this bit indicates that the MAC-PHY has detected an invalid header received from the
SPI host. The invalid header is due to a parity check error. This field is only used with the OPEN Alliance SPI
protocol.
Loss of Frame Error. When set, this bit indicates that the MAC-PHY has detected an early deassertion of CS
before the expected end of a data chunk or command control transaction. Note that this bit also asserts if
CDPE asserts.
Receive Buffer Overflow Error. When set, this bit indicates that the receive buffer (from the network) has
overflowed and receive frame data was lost.
Host Tx FIFO Under Run Error. This error can only assert when cut through from the host is enabled. The
host software must ensure this bit never asserts by writing frame data to the MAC at a rate greater than 10
Mbps.If an under run error occurs, transmit of the current packet stops.
Host Tx FIFO Overflow. The host software must ensure this bit never asserts by checking the space available
in the Tx FIFO before writing to the Tx FIFO. If using the OPEN Alliance SPI Data protocol, the space in
the Tx FIFO is indicated in the TXC field of the Rx footer. If using the Generic SPI protocol, the TX_SPACE
register indicates the remaining space in the Tx FIFO. If the host Tx FIFO overflows, the frame being written is
dumped and software may chose to resend the entire frame. Writes to the FIFO commence at the next SOF.
There is always room for more than one frame in the Host Tx FIFO as it is 4 kB (or greater) in size. Therefore,
a frame currently transmitting is interrupted by an overflow on the write side of the FIFO.
Transmit Protocol Error. When set, this bit indicates that a Tx data chunk protocol error occurred. Data chunk
received with DV = 1 but without a prior SV = 1. Data chunk received with SV = 1 but with no EV = 1
(repeated SV = 1 received). When using the generic SPI protocol, this bit indicates that the previous frame
was not fully written. A write of the TX_FSIZE register was detected, but the MAC still expects further writes to
the Tx register related to the previous frame size written to the TX_FSIZE register.
0x0
R/W1C
Status Register 1
Address: 0x09, Reset: 0x00000000, Name: STATUS1
Table 42. Bit Descriptions for STATUS1
Bits
Bit Name
Description
Reset
Access
[31:13]
12
RESERVED
TX_ECC_ERR
0x0
0x0
R/W1C
R/W1C
11
RX_ECC_ERR
0x0
R/W1C
10
SPI_ERR
0x0
R/W1C
9
8
RESERVED
P1_RX_IFG_ERR
0x0
0x0
R/W1C
R/W1C
[7:6]
5
RESERVED
P1_RX_RDY_HI
0x0
0x0
R
R
4
P1_RX_RDY
Reserved.
ECC Error on Reading the Frame Size from a Tx FIFO. An uncorrectable ECC error was detected
on a read of the size field from the Tx FIFO. The FIFO is automatically cleared and the frame
associated with the ECC error and any other frames in the Tx FIFO are lost or dropped.
ECC Error on Reading the Frame Size from an Rx FIFO. An uncorrectable ECC error was detected
on a reading the frame size field from an Rx FIFO. The FIFO is automatically cleared and the frame
associated with the ECC error and other frames in the Rx FIFO are not lost or dropped.
Detected an Error on an SPI Transaction. When using the generic SPI protocol, this field indicates
that a CRC error was detected. This field is not used with the OPEN Alliance Protocol. See HDRE
and CDPE in the Status Register 0 section for OPEN Alliance SPI errors.
Reserved.
Rx MAC Interframe Gap Error. If the IFG is too short, the frame is dropped on receive. The threshold
used for measuring the IFG on receive can be set in the P1_RX_IFG register.
Reserved.
Port1 Rx Ready High Priority. Indicates that there is a high priority frame available. This field does
not drive the interrupt pin. This field is only used with the generic SPI protocol on LES.
Port 1 Rx FIFO Contains Data. In store and forward mode, this field indicates that there are 1 or
more frames in Port 1 Rx FIFO. In cut through mode, this field indicates that the receive threshold
0x0
R
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Data Sheet
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REGISTERS
Table 42. Bit Descriptions for STATUS1
Bits
Bit Name
3
TX_RDY
2
1
0
RESERVED
LINK_CHANGE
P1_LINK_STATUS
Description
(RX_THRESH) is reached or the EOF byte of a frame is received. If there are frames in both the Rx
high and low priority FIFOs, the frame from the high priority FIFO is read first by default. This field is
only used with the generic SPI protocol.
Tx Ready. If TX_RDY_ON_EMPTY is 0, TX_RDY asserts when frame transmission completes. If
TX_RDY_ON_EMPTY is 1, TX_RDY asserts when the Tx FIFO is empty and frame transmission
completes. This bit is cleared by writing 1 to this field. This field is only used with the generic SPI
protocol.
Reserved.
Link Status Changed. Indicates that the link status has changed on Port 1.
Port 1 Link Status. This bit does not generate an interrupt event.
0: link down.
1: link pp.
Reset
Access
0x0
R/W1C
0x0
0x0
0x0
R
R/W1C
R
Reset
Access
Buffer Status Register
Address: 0x0B, Reset: 0x00007700, Name: BUFSTS
Table 43. Bit Descriptions for BUFSTS
Bits
Bit Name
Description
[31:16]
[15:8]
RESERVED
TXC
[7:0]
RCA
Reserved.
0x0
Transmit Credits Available. Number of chunk buffers of transmit data currently available for the SPI host to
0x77
write. Reading this field allows the SPI host to queue up the number of transmit chunks available into a single
DMA, if desired. The value in this field is saturated to 31 and sent in the 5-bit TXC field of every RX data
footer. The default (maximum) number of transmit buffer credits available is implementation specific. This field
is only used with the OPEN Alliance SPI protocol
Receive Chunks Available. Number of chunks of receive data currently available for the SPI host to read.
0x0
Reading this field allows the SPI host to queue up the number of receive chunks available into a single DMA,
if desired. This field is only used with the OPEN Alliance SPI protocol.
R
R
R
Interrupt Mask Register 0
Address: 0x0C, Reset: 0x00001FBF, Name: IMASK0
Table 44. Bit Descriptions for IMASK0
Bits
Bit Name
Description
Reset
Access
[31:13]
12
RESERVED
CDPEM
0x0
0x1
R
R/W
11
TXFCSEM
0x1
R/W
10
TTSCACM
0x1
R/W
9
TTSCABM
0x1
R/W
8
TTSCAAM
0x1
R/W
7
PHYINTM
0x1
R/W
6
RESETCM
0x0
R
5
HDREM
Reserved.
Control Data Protection Error Mask. Setting this bit to 1 prevents the control data protection error status bit in
STATUS0 from asserting the footer EXST bit. This field is only used with the OPEN Alliance SPI protocol.
Transmit Frame Check Sequence Error Mask. Setting this bit to 1 prevents the transmit frame check
sequence error status bit in STATUS0 from asserting the interrupt pin.
Transmit Time Stamp Capture Available C Mask. Setting this bit to 1 prevents the Transmit Time Stamp
Capture Available C status bit in STATUS0 from asserting the footer EXST bit.
Transmit Time Stamp Capture Available B Mask. Setting this bit to 1 prevents the Transmit Time Stamp
Capture Available B status bit in STATUS0 from asserting the footer EXST bit.
Transmit Time Stamp Capture Available A Mask. Setting this bit to 1 prevents the Transmit Time Stamp
Capture Available A status bit in STATUS0 from asserting the footer EXST bit.
Physical Layer Interrupt Mask. Setting this bit to 1 prevents the physical layer interrupt (PHYINT) status bit in
STATUS0 from asserting the footer EXST bit.
RESET Complete Mask. This bit is reserved as a mask for the reset complete (RESETC) status bit. This bit
is read only and always 0 because the RESETC status bit is a non maskable interrupt that causes IRQn to
always assert when RESETC is set.
Header Error Mask. Setting this bit to 1 prevents the header error (HDRE) status bit in STATUS0 from
asserting the footer EXST bit. This field is only used with the OPEN Alliance SPI protocol.
0x1
R/W
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Table 44. Bit Descriptions for IMASK0
Bits
Bit Name
Description
Reset
Access
4
LOFEM
0x1
R/W
3
RXBOEM
0x1
R/W
2
TXBUEM
0x1
R/W
1
TXBOEM
0x1
R/W
0
TXPEM
Loss of Frame Error Mask. Setting this bit to 1 prevents the loss of the frame error (LOFE) status bit in
STATUS0 from asserting the footer EXST bit.
Receive Buffer Overflow Error Mask. Setting this bit to 1 prevents the receive buffer overflow error (RXBOE)
status bit in STATUS0 from asserting the footer EXST bit.
Transmit Buffer Underflow Error Mask. Setting this bit to 1 prevents the transmit buffer underflow error
(TXBUE) status bit in STATUS0 from asserting the footer EXST bit.
Transmit Buffer Overflow Error Mask. Setting this bit to 1 prevents the transmit buffer overflow error (TXBOE)
status bit in STATUS0 from asserting the footer EXST bit.
Transmit Protocol Error Mask. Setting this bit to 1 prevents the transmit protocol error (TXPE) status bit in
STATUS0 from asserting IRQn.
0x1
R/W
Mask Bits for Driving the Interrupt Pin Register
Address: 0x0D, Reset: 0x43FA1F1A, Name: IMASK1
Table 45. Bit Descriptions for IMASK1
Bits
Bit Name
Description
Reset
Access
[31:13]
12
11
10
9
8
[7:5]
4
3
2
1
0
RESERVED
TX_ECC_ERR_MASK
RX_ECC_ERR_MASK
SPI_ERR_MASK
RESERVED
P1_RX_IFG_ERR_MASK
RESERVED
P1_RX_RDY_MASK
TX_RDY_MASK
RESERVED
LINK_CHANGE_MASK
RESERVED
Reserved.
Mask Bit for TXF_ECC_ERR.
Mask Bit for RXF_ECC_ERR.
Mask Bit for SPI_ERR. This field is only used with the generic SPI protocol.
Reserved.
Mask Bit for RX_IFG_ERR.
Reserved.
Mask Bit for P1_RX_RDY. This field is only used with the generic SPI protocol.
Mask Bit for TX_FRM_DONE. This field is only used with the generic SPI protocol.
Reserved.
Mask Bit for LINK_CHANGE.
Reserved.
0x21FD0
0x1
0x1
0x1
0x1
0x1
0x0
0x1
0x1
0x0
0x1
0x0
R
R/W
R/W
R/W
R/W
R/W
R
R/W
R/W
R
R/W
R
Transmit Time Stamp Capture Register A (High)
Address: 0x10, Reset: 0x00000000, Name: TTSCAH
This field contains the upper 32 bits of the captured time stamp for when the requested frame was transmitted.
Table 46. Bit Descriptions for TTSCAH
Bits
Bit Name
Description
Reset
Access
[31:0]
TTSCH_A
Transmit Time Stamp A. Bits[63:32].
0x0
R
Transmit Time Stamp Capture Register A (Low)
Address: 0x11, Reset: 0x00000000, Name: TTSCAL
This field contains the lower 32 bits of the captured time stamp for when the requested frame was transmitted.
Table 47. Bit Descriptions for TTSCAL
Bits
Bit Name
Description
Reset
Access
[31:0]
TTSCL_A
Transmit Time Stamp A. Bits[31:0].
0x0
R
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Transmit Time Stamp Capture Register B (High)
Address: 0x12, Reset: 0x00000000, Name: TTSCBH
This field contains the upper 32 bits of the captured time stamp for when the requested frame was transmitted.
Table 48. Bit Descriptions for TTSCBH
Bits
Bit Name
Description
Reset
Access
[31:0]
TTSCH_B
Transmit Time Stamp B. Bits[63:32].
0x0
R
Transmit Time Stamp Capture Register B (Low)
Address: 0x13, Reset: 0x00000000, Name: TTSCBL
This field contains the lower 32 bits of the captured time stamp for when the requested frame was transmitted.
Table 49. Bit Descriptions for TTSCBL
Bits
Bit Name
Description
Reset
Access
[31:0]
TTSCL_B
Transmit Time Stamp B. Bits[31:0].
0x0
R
Transmit Time Stamp Capture Register C (High)
Address: 0x14, Reset: 0x00000000, Name: TTSCCH
This field contains the upper 32 bits of the captured time stamp for when the requested frame was transmitted.
Table 50. Bit Descriptions for TTSCCH
Bits
Bit Name
Description
Reset
Access
[31:0]
TTSCH_C
Transmit Time Stamp C. Bits[63:32].
0x0
R
Transmit Time Stamp Capture Register C (Low)
Address: 0x15, Reset: 0x00000000, Name: TTSCCL
This field contains the lower 32 bits of the captured time stamp for when the requested frame was transmitted.
Table 51. Bit Descriptions for TTSCCL
Bits
Bit Name
Description
Reset
Access
[31:0]
TTSCL_C
Transmit Time Stamp C. Bits[31:0].
0x0
R
MDIO Access Registers
Address: 0x20 to 0x27 (Increments of 1), Reset: 0x8C000000, Name: MDIOACCn
Use this register to access the PHY registers via the SPI to MDIO bridge.
Table 52. Bit Descriptions for MDIOACCn
Bits
Bit Name
Description
Reset
Access
31
MDIO_TRDONE
Transaction Done. This bit must be written to 0 by the SPI host to initiate an MDIO transaction. The
MAC-PHY sets this bit to 1 when the MDIO transaction has completed.
0x1
R/W
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Table 52. Bit Descriptions for MDIOACCn
Bits
Bit Name
Description
Reset
Access
30
MDIO_TAERR
0x0
R
[29:28]
MDIO_ST
0x0
R/W
[27:26]
MDIO_OP
0x3
R/W
[25:21]
MDIO_PRTAD
0x0
R/W
[20:16]
MDIO_DEVAD
0x0
R/W
[15:0]
MDIO_DATA
Turnaround Error. The MAC-PHY sets this bit to 1 when a turnaround error occurs during the MDIO
transaction. If this occurs, the contents of the data field for read and read-post-increment-address
operations is ignored.
Start of Frame. This field selects between Clause 45 and Clause 22 MDIO access.
01: Clause 22
00: Clause 45
Operation Code.
00: MD address command.
01: write command.
11: read command.
10: incremental read command.
MDIO Port Address. This is the address of target port (PHY). This is called port address (PRTAD) for
Clause 45, and called PHY address (PHYAD) for Clause 22.
MDIO Device Address. When using Clause 45, this is the device address. When using Clause 22, this
is the register address.
Data/Address Value. For a write operation (Clause 45 or Clause 22) the SPI host must set this
to the 16-bit value to be written. For an address operation (Clause 45), the SPI host must set
this to the 16-bit register address value. For a read operation (Clause 45 or Clause 22), or for
a read-post-increment-address operation (Clause 45), the SPI host must set this value to 0. On
completion of the MDIO transaction (as indicated by TRDONE), the MAC-PHY sets this to the 16-bit
value read.
0x0
R/W
MAC Tx Frame Size Register
Address: 0x30, Reset: 0x00000000, Name: TX_FSIZE
Table 53. Bit Descriptions for TX_FSIZE
Bits
Bit Name
Description
Reset
Access
[31:11]
[10:0]
RESERVED
TX_FRM_SIZE
Reserved.
Transmit Frame Size. This field indicates the size of the frame that is written to the transmit FIFO in
bytes when using the generic SPI protocol. The size must include the 2-byte frame header. This is used
on the SPI side of the Tx FIFO to determine when the full frame written. When the full frame byte
count is reached, subsequent writes to MAC_TX register are ignored until the MAC_TXF_SIZE is written
again.This field is only used with the generic SPI protocol.
0x0
0x0
R
R/W
MAC Transmit Register
Address: 0x31, Reset: 0x00000000, Name: TX
The transmit FIFO is written via this register.
Table 54. Bit Descriptions for TX
Bits
Bit Name
Description
Reset
Access
[31:0]
TDR
Transmit Data Register. Writing to this register adds 4 bytes to the host Tx FIFO. Note that the last word of a
frame can only contain less than 4 bytes of data. The hardware uses MAC_TXF_SIZE to determine if there is 1
byte, 2 bytes, 3 bytes, or 4 bytes valid in the last SPI write of a frame. Only used with the generic SPI protocol.
0x0
W
Tx FIFO Space Register
Address: 0x32, Reset: 0x00000FFF, Name: TX_SPACE
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Table 55. Bit Descriptions for TX_SPACE
Bits
Bit Name
Description
Reset
[31:14]
[13:0]
RESERVED
TX_SPACE
Reserved.
0x0
Transmit FIFO Space Available in Half Words (16 Bits). This is used by the host software to determine if there 0xFFF
is space in the Tx FIFO for a frame. Note that the software can queue 2 frames for transmission and wait for
a TX_RDY interrupt, or it can fill the Tx FIFO with multiple frames and use TX_SPACE to determine if there is
space for the next frame. Note that an extra 2 words of space are needed per frame in the host TX FIFO to
store the frame size and header. For example, if the TX_SPACE is 64, the maximum size frame that can be
written is (64 -2) × 2 bytes = 124 bytes. Only used with the generic SPI protocol.
Access
R
R
Transmit Threshold Register
Address: 0x34, Reset: 0x00000041, Name: TX_THRESH
Table 56. Bit Descriptions for TX_THRESH
Bits
Bit Name
Description
Reset
Access
[31:6]
[5:0]
RESERVED
HOST_TX_THRESH
Reserved.
Host Transmit Start Threshold in Cut Through. When cut through on Tx is enabled
(TX_CUT_THRU_EN = 1), this field is used to set the threshold in half words (16 bits) at which
frame transmission starts for frames coming from the host. The range of valid values for this field is
1 to 26 half words.
0x1
0x1
R
R/W
MAC FIFO Clear Register
Address: 0x36, Reset: 0x00000000, Name: FIFO_CLR
Table 57. Bit Descriptions for FIFO_CLR
Bits
Bit Name
Description
Reset
Access
[31:2]
1
RESERVED
MAC_TXF_CLR
0x0
0x0
R
W
0
MAC_RXF_CLR
Reserved.
Clear the Host Transmit FIFO. If a frame is currently being transmitted, the transmission stops and a bad
CRC is appended to the frame.
Clear the Receive FIFOs. Writes to the Rx FIFO resume at the start of the next frame.
0x0
W
Scratch Registers
Address: 0x37 to 0x3A (Increments of 1), Reset: 0x00000000, Name: SCRATCHn
Table 58. Bit Descriptions for SCRATCHn
Bits
Bit Name
Description
Reset
Access
[31:0]
SCRATCH_DATA
Scratch Data.
0x0
R/W
MAC Reset Status Register
Address: 0x3B, Reset: 0x00000003, Name: MAC_RST_STATUS
If this register returns 0x00000000_00000001 when read, the oscillator clock is active, but the 25 MHz crystal clock is not active.
If this register returns 0x00000000_00000003 when read, both the oscillator clock and the 25 MHz crystal clock are active.
If this register returns 0x00000000_00000000 (SDO output pad is enabled while CS is low), the SPI slave and MAC core are both still in reset.
Only single SPI reads of this register are supported. An SPI burst read must not increment into this register.
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Table 59. Bit Descriptions for MAC_RST_STATUS
Bits
Bit Name
Description
Reset
[31:2]
1
RESERVED
MAC_CRYSL_CLK_RDY
0
MAC_OSC_CLK_RDY
Reserved.
0x0
MAC Crystal Clock Ready. If 0, this field indicates that the MAC core has not been released
0x1
from reset. If 1, this field indicates that the MAC core is released from reset. The MAC core is
released from reset when the crystal clock (25 MHz) is ready.
MAC Oscillator Clock Ready.
0x1
Access
R
R
R
Software Reset Register
Address: 0x3C, Reset: 0x00000000, Name: SOFT_RST
Table 60. Bit Descriptions for SOFT_RST
Bits
Bit Name
Description
Reset
[31:16]
[15:0]
RESERVED
RST_KEY
Reserved.
0x0
Software Reset. Write a pair of keys in order and back to back on the SPI to trigger a reset.
0x0
0x4F1C: Key 1 to reset the MAC logic only.
0xC1F4: Key 2 to reset the MAC logic only. Reset does not take effect until CS is brought high, and CS must
be held asserted for at least 100 ns for the reset to take effect. If the MAC-PHY is in software power-down
mode, the MAC_ONLY reset has no effect. That is, CRSM_SFT_P_CNTRL.CRSM_SFT_PD must be 0.
0x6F1A: Key 1 to request release of reset to the MAC core logic. Use MAC_RST_EXIT_REQ_KEYx to
request a release of reset to the MAC core logic when the 25 MHz crystal clock is not available. This brings
the MAC out of reset using the oscillator clock (12.5 MHz to 25.7 MHz). SPI accesses can then proceed at 15
MHz to allow debug access to MAC and PHY registers.
0xA1F6: Key 2 to request release of reset to the MAC core logic.
Access
R
W
Inject an Error on MISO from the DUT Register
Address: 0x3D, Reset: 0x00000000, Name: SPI_INJ_ERR
Table 61. Bit Descriptions for SPI_INJ_ERR
Bits
Bit Name
Description
Reset
[31:1]
0
RESERVED
TEST_SPI_INJ_ERR
Reserved.
0x0
Inject an Error on the SPI MISO Path. This function allows software to test that errors received on
0x0
MISO are properly detected in software. If set and using the OPEN Alliance SPI protocol for data
transaction, the parity bit in the Rx footer is inverted. Also, the time stamp parity bit in the in Rx
footer is inverted. If set and using the OPEN Alliance SPI protocol for protected control burst write
transactions, starting from the second word in a burst, the MS bit of each echoed 32-bit word is
inverted. If set and using the OPEN Alliance SPI protocol for protected control read transactions, the
MS bit of each 32-bit complement word is inverted. If set and using the generic SPI protocol with
protection enabled, the CRC8 returned on a register read is inverted.
Access
R
R/W
FIFO Sizes Register
Address: 0x3E, Reset: 0x00000464, Name: FIFO_SIZE
Before modifying the FIFO sizes, frame reception and transmission must be stopped and the FIFOs must be empty.
Configure the forwarding rules to drop all frames and set P1_UNK2HOST to 0 to ensure all received frames are dropped.
Use RXF_CLR & TXF_CLR to reset the FIFOs. Then, the FIFO sizes can be modified.
The total FIFO size must be less than or equal to 28 kB.
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Table 62. Bit Descriptions for FIFO_SIZE
Bits
Bit Name
Description
Reset
Access
[31:12]
[11:8]
RESERVED
P1_RX_HI_SIZE
0x0
0x4
R
R/W
[7:4]
P1_RX_LO_SIZE
0x6
R/W
[3:0]
HTX_SIZE
Reserved.
Port 1 Rx High Priority FIFO Size.
0000: 0 kB.
0001: 2 kB.
0010: 4 kB.
0011: 6 kB.
0100: 8 kB.
0101: 10 kB.
0110: 12 kB.
0111: 14 kB.
1000: 16 kB.
Port 1 Rx Low Priority FIFO Size.
0000: 0 kB.
0001: 2 kB.
0010: 4 kB.
0011: 6 kB.
0100: 8 kB.
0101: 10 kB.
0110: 12 kB.
0111: 14 kB.
1000: 16 kB.
Host Transmit FIFO Size.
0000: 0 kB.
0001: 2 kB.
0010: 4 kB.
0011: 6 kB.
0100: 8 kB.
0101: 10 kB.
0110: 12 kB.
0111: 14 kB.
1000: 16 kB.
0x4
R/W
Tx FIFO Frame Count Register
Address: 0x3F, Reset: 0x00000000, Name: TFC
For debug only. Number of frames in the transmit FIFO.
Table 63. Bit Descriptions for TFC
Bits
Bit Name
Description
Reset
Access
[31:9]
[8:0]
RESERVED
TFC
Reserved.
Number of Frames in the Tx FIFO.
0x0
0x0
R
R
Tx FIFO Valid Half Words Register
Address: 0x40, Reset: 0x00000000, Name: TXSIZE
Number of Valid Half Words (16 Bit) in the Host Tx FIFO.
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Table 64. Bit Descriptions for TXSIZE
Bits
Bit Name
Description
Reset
Access
[31:14]
[13:0]
RESERVED
TX_SIZE
Reserved.
Data in the Tx FIFO. Number of Half Words(16 Bit).
0x0
0x0
R
R
Host Tx Frames Dropped Due to FIFO Overflow Register
Address: 0x41, Reset: 0x00000000, Name: HTX_OVF_FRM_CNT
Table 65. Bit Descriptions for HTX_OVF_FRM_CNT
Bits
Bit Name
Description
Reset
Access
[31:0]
HTX_OVF_FRM_CNT
Counts Host Tx Frames Dropped Due to FIFO Overflow.
0x0
R
Address of a Detected ECC Error in Memory Register
Address: 0x42, Reset: 0x00000000, Name: MECC_ERR_ADDR
Table 66. Bit Descriptions for MECC_ERR_ADDR
Bits
Bit Name
Description
Reset
Access
[31:14]
[13:0]
RESERVED
MECC_ERR_ADDR
Reserved.
Address of an Uncorrectable ECC Error in Memory. This is the address of the first uncorrectable
ECC error detected. That is when either RX_ECC_ERR or TX_ECC_ERR assert. When
RX_ECC_ERR and TX_ECC_ERR are cleared, the register is opened to catch the address
of the next ECC error. SRAM is 16 bits wide and this address points to a location in SRAM.
0x0
0x0
R
R
Corrected ECC Error Counters Register
Address: 0x43 to 0x49 (Increments of 1), Reset: 0x00000000, Name: CECC_ERRn
Table 67. Bit Descriptions for CECC_ERRn
Bits
Bit Name
Description
Reset
Access
[31:10]
[9:0]
RESERVED
CECC_ERR_CNT
Reserved.
Corrected ECC Error Count. The counters map to FIFOs as follows: CECC_ERR[0] low priority Rx
FIFO for P1CECC_ERR[1], high priority Rx FIFO for P1CECC_ERR[4] - Tx FIFO from the host.
0x0
0x0
R
R
MAC Address Rule and DA Filter Upper 16 Bits Registers
Address: 0x50 to 0x6E (Increments of 2), Reset: 0x00000000, Name: ADDR_FILT_UPRn
Contains the upper 16 bits of a MAC address and the filtering rule associated with the MAC address.
When writing the ADDR_FILT_x registers, two register locations must be written in order for a given table entry.
For example, to write table entry 0, the registers must be written in the following order:
1. ADDR_FILT_UPR0.
2. ADDR_FILT_LWR0.
Table 68. Bit Descriptions for ADDR_FILT_UPRn
Bits
Bit Name
Description
Reset
Access
31
30
RESERVED
APPLY2PORT1
Reserved.
Apply to Port 1.
0: do not apply to Port 1. Do not apply this table entry/rule to frames received on Port 1.
0x0
0x0
R/W
R/W
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Table 68. Bit Descriptions for ADDR_FILT_UPRn
Bits
Bit Name
[29:20]
19
RESERVED
HOST_PRI
[18:17]
16
RESERVED
TO_HOST
[15:0]
MAC_ADDR, Bits[47:32]
Description
1: apply to Port 1. Apply this table entry/rule to frames received on Port 1.
Reserved.
Host Rx Port Priority. On the receive port to the host, there are two FIFOs: low and high priority.
This field determines which FIFO the frame is placed in. 0 = low priority, and 1 = high priority.
By default, memory resources are provided for a high priority FIFO. However, if the memory
assigned to the high priority FIFO is moved to another FIFO by writing to the FIFO_SIZE register,
this field must not be set to 1.
Reserved.
Forward Frames Matching This MAC Address to the Host. If APPLY2PORT1 is set to 1 and
TO_HOST is 1, frames matching this DA are forwarded to the host. If TO_HOST is 0, frames
matching the DA for this entry are dropped.
MAC Address.
Reset
Access
0x0
0x0
R
R/W
0x0
0x0
R
R/W
0x0
R/W
MAC Address DA Filter Lower 32 Bits Registers
Address: 0x51 to 0x6F (Increments of 2), Reset: 0x00000000, Name: ADDR_FILT_LWRn
Contains the lower 32 bits of a MAC address in the DA filter table.
A write to one of these registers must be preceded by a write to the corresponding ADDR_FILT_UPRn register.
Table 69. Bit Descriptions for ADDR_FILT_LWRn
Bits
Bit Name
Description
Reset
Access
[31:0]
MAC_ADDR, Bits[31:0]
MAC Address.
0x0
R/W
Upper 16 Bits of the MAC Address Mask Register
Address: 0x70 to 0x72 (Increments of 2), Reset: 0x0000FFFF, Name: ADDR_MSK_UPRn
The upper 16 bits of a MAC address mask in the DA mask table.
When writing the ADDR_MSK_x registers, all two register locations must be written in order for a given table entry. They must be written in
order with the UPR register written first and the LWR register written last.
Table 70. Bit Descriptions for ADDR_MSK_UPRn
Bits
Bit Name
Description
Reset
Access
[31:16]
[15:0]
RESERVED
MAC_ADDR_MASK, Bits[47:32]
Reserved.
MAC Address Bit Mask for the Address Table.
0x0
0xFFFF
R
R/W
Lower 32 Bits of the MAC Address Mask Register
Address: 0x71 to 0x73 (Increments of 2), Reset: 0xFFFFFFFF, Name: ADDR_MSK_LWRn
The lower 32 bits of a MAC address mask in the DA mask table.
When writing the ADDR_MSK_x registers, all two register locations must be written in order for a given table entry. The register locations must
be written in order with the UPR register written first and the LWR register written last.
Table 71. Bit Descriptions for ADDR_MSK_LWRn
Bits
Bit Name
Description
Reset
Access
[31:0]
MAC_ADDR_MASK, Bits[31:0]
MAC Address Bit Mask for the Address Table.
0xFFFFFFFF
R/W
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Time Stamp Accumulator Addend Register
Address: 0x80, Reset: 0x85555555, Name: TS_ADDEND
Table 72. Bit Descriptions for TS_ADDEND
Bits
Bit Name
Description
Reset
Access
[31:0]
TS_ADDEND
Time Stamp Accumulator Addend.
0x85555555
R/W
Timer Update Compare Register
Address: 0x81, Reset: 0x3B9ACA00, Name: TS_1SEC_CMP
Table 73. Bit Descriptions for TS_1SEC_CMP
Bits
Bit Name
Description
Reset
Access
[31:0]
TS_1SEC_CMP
Time Stamp 1 Second Compare Value.
0x3B9ACA00
R/W
Seconds Counter Register
Address: 0x82, Reset: 0x00000000, Name: TS_SEC_CNT
Use this register to write to the seconds counter.
Table 74. Bit Descriptions for TS_SEC_CNT
Bits
Bit Name
Description
Reset
Access
[31:0]
TS_SEC_CNT
Write to the Seconds Counter.
0x0
R/W
Nanoseconds Counter Register
Address: 0x83, Reset: 0x00000000, Name: TS_NS_CNT
Use this register to write to the nanoseconds counter.
Table 75. Bit Descriptions for TS_NS_CNT
Bits
Bit Name
Description
Reset
Access
[31:0]
TS_NS_CNT
Write to the Nanoseconds Counter. This register must be programmed with a value that is divisible by 16
decimal because the counters are driven by a 120 MHz clock and increment in steps of 16.
0x0
R/W
Timer Configuration Register
Address: 0x84, Reset: 0x00000000, Name: TS_CFG
Table 76. Bit Descriptions for TS_CFG
Bits
Bit Name
Description
Reset
Access
[31:5]
4
RESERVED
TS_CAPT_FREE_CNT
0x0
0x0
R
R/W
3
TS_TIMER_STOP
0x0
W
2
TS_TIMER_DEF
Reserved.
Capture the Free Running Counter. When this bit is 1 and FTSS is 0, the time stamps are
captured from the 32-bit free running counter. If this bit is 0 and FTSS is 0, the 32-bit time stamps
as defined in the OPEN Alliance MAC-PHY specification are captured. If FTSS is 1, the 64 bit
time stamps as defined in the OPEN Alliance MAC-PHY specification are captured.
Stop Toggling the TS_TIMER Output. Write 1 to this field to stop the TS_TIMER output toggling
and return it to its default value. Write to the TS_TIMER_START registers to start the TS_TIMER
output signal again. This bit automatically clears to 0.
The Default Value for the TS_TIMER Output. To change the default value of the TS_TIMER
from 0, write 1 to this field before enabling the TS_TIMER (it is enabled when TS_TSTART is
0x0
R/W
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Table 76. Bit Descriptions for TS_CFG
Bits
Bit Name
1
TS_CLR
0
TS_EN
Description
Reset
written). Note that on writing 1 to this register, the TS_TIMER output immediately toggles from 0
to 1.Writing to this field has no effect if the TS_TIMER has already been enabled.
Clear the 1588 Time Stamp Counters. Write a 1 to reset the time stamp counters to 0. This field
0x0
automatically clears to 0 after it is written to 1. Four counters are cleared, the accumulator, the
nanoseconds counter, the seconds counter, and the free running counter.
Enable the 1588 Time Stamp Counter. When set to 1, the time stamp counter is enabled and time 0x0
stamps are captured for all received frames. The counters are not cleared when TS_EN is 0, they
simply freeze. Therefore, it is recommended to write to use TS_CLR after disabling the counters
to get them to a known state before starting again.
Access
W
R/W
High Period for TS_TIMER Register
Address: 0x85, Reset: 0x00000000, Name: TS_TIMER_HI
Table 77. Bit Descriptions for TS_TIMER_HI
Bits
Bit Name
Description
Reset
[31:0]
TS_TIMER_HI
TS_TIMER High Period. This register must be programmed with a value that is divisible by 16 decimal
0x0
because the counters are driven by a 120 MHz clock and increment in steps of 16. The minimum value that
can be written to this field is 16 decimal.
Access
R/W
Low Period for TS_TIMER Register
Address: 0x86, Reset: 0x00000000, Name: TS_TIMER_LO
Table 78. Bit Descriptions for TS_TIMER_LO
Bits
Bit Name
Description
[31:0]
TS_TIMER_LO
TS_TIMER Low Period. This register must be programmed with a value that is divisible by 16 decimal
0x0
because the counters are driven by a 120 MHz clock and increment in steps of 16.The minimum value that
can be written to this field is 16 decimal.
Reset
Access
R/W
Quantization Error Correction Register
Address: 0x87, Reset: 0x00000000, Name: TS_TIMER_QE_CORR
Table 79. Bit Descriptions for TS_TIMER_QE_CORR
Bits
Bit Name
Description
Reset
Access
[31:8]
[7:0]
RESERVED
TS_TIMER_QE_CORR
Reserved.
TS_TIMER Quantization Error Correction Value. If the required TS_TIMER low and high periods
are not directly divisible by 16, program this field with a value between 0 and 15 to compensate
for the TS_TIMER quantization error.
0x0
0x0
R
R/W
TS_TIMER Counter Start Time Register
Address: 0x88, Reset: 0x00000000, Name: TS_TIMER_START
Point in Time at Which to Start the TS_TIMER Counter.
Table 80. Bit Descriptions for TS_TIMER_START
Bits
Bit Name
Description
Reset
Access
[31:0]
TS_TSTART
Point in Time at Which to Start the TS_TIMER Counter. Writing to this register starts the TS_TIMER output.
To start the TS_TIMER output, this field must be written to a value greater than or equal to 16. After the
0x0
R/W
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Table 80. Bit Descriptions for TS_TIMER_START
Bits
Bit Name
Description
Reset
Access
TS_TIMER starts, writing to TS_TIMER_STOP stops the timer and returns the TS_TIMER output to its default
value.
TS_CAPT Pin 0 Time Stamp Register
Address: 0x89, Reset: 0x00000000, Name: TS_EXT_CAPT0
Time stamp captured on the assertion of the TS_CAPT pin.
Table 81. Bit Descriptions for TS_EXT_CAPT0
Bits
Bit Name
Description
Reset
Access
[31:0]
TS_EXT_CAPTD, Bits[31:0]
Time Stamp Captured on the Assertion of the TS_CAPT Pin.
0x0
R
TS_CAPT Pin 1 Time Stamp Register
Address: 0x8A, Reset: 0x00000000, Name: TS_EXT_CAPT1
Time stamp captured on the assertion of the TS_CAPT pin.
Table 82. Bit Descriptions for TS_EXT_CAPT1
Bits
Bit Name
Description
Reset
Access
[31:0]
TS_EXT_CAPTD, Bits[63:32]
Time stamp captured on the assertion of the TS_CAPT pin.
0x0
R
Reset
Access
TS_CAPT Free Running Counter Register
Address: 0x8B, Reset: 0x00000000, Name: TS_FREECNT_CAPT
Capture of the free running counter when TS_CAPT asserts.
Table 83. Bit Descriptions for TS_FREECNT_CAPT
Bits
Bit Name
Description
[31:0]
TS_CNT_CAPTD
Captured Free Running Counter. This 32-bit counter is captured on the assertion of TS_CAPT pin, as is 0x0
TS_EXT_CAPT.
R
P1 MAC Rx Frame Size Register
Address: 0x90, Reset: 0x00000000, Name: P1_RX_FSIZE
Table 84. Bit Descriptions for P1_RX_FSIZE
Bits
Bit Name
Description
Reset
Access
[31:11]
[10:0]
RESERVED
P1_RX_FRM_SIZE
Reserved.
Receive Frame Size. The size of the frame at the head of the Rx FIFO in bytes. The size includes
the appended header. When using the generic SPI protocol, this register must be read before
reading a frame from a receive FIFO via P1_RX.
0x0
0x0
R
R
P1 MAC Receive Register
Address: 0x91, Reset: 0x00000000, Name: P1_RX
The receive FIFO is read via this register.
It is possible to burst read data from the Rx FIFO over SPI.
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Table 85. Bit Descriptions for P1_RX
Bits
Bit Name
Description
Reset
[31:0]
P1_RDR
Receive Data Register. This field is only used with the generic SPI protocol. Reading this register returns the
0x0
four bytes at the top of the receive FIFO and pops these four bytes from the FIFO. The upper 8 bits contain the
first byte, the next 8 bits contain the second byte, and so on. When a complete frame is read out, no further data
is returned from the P1 Rx FIFOs until the P1_RX_FRM_SIZE register is read first. Only used with the generic
SPI protocol.
Access
R
P1 Rx Frame Count Register
Address: 0xA0, Reset: 0x00000000, Name: P1_RX_FRM_CNT
Table 86. Bit Descriptions for P1_RX_FRM_CNT
Bits
Bit Name
Description
Reset
Access
[31:0]
P1_RX_FRM_CNT
Rx Frame Count. This counter increments for received good and bad frames.
0x0
R
P1 Rx Broadcast Frame Count Register
Address: 0xA1, Reset: 0x00000000, Name: P1_RX_BCAST_CNT
Table 87. Bit Descriptions for P1_RX_BCAST_CNT
Bits
Bit Name
Description
Reset
Access
[31:0]
P1_RX_BCAST_CNT
Rx Broadcast Frame Count. This counter increments for received good and bad frames.
0x0
R
P1 Rx Multicast Frame Count Register
Address: 0xA2, Reset: 0x00000000, Name: P1_RX_MCAST_CNT
Table 88. Bit Descriptions for P1_RX_MCAST_CNT
Bits
Bit Name
Description
Reset
Access
[31:0]
P1_RX_MCAST_CNT
Rx Multicast Frame Count. This counter increments for received good and bad frames.
0x0
R
P1 Rx Unicast Frame Count Register
Address: 0xA3, Reset: 0x00000000, Name: P1_RX_UCAST_CNT
Table 89. Bit Descriptions for P1_RX_UCAST_CNT
Bits
Bit Name
Description
Reset
Access
[31:0]
P1_RX_UCAST_CNT
Rx Unicast Frame Count.
0x0
R
P1 Rx CRC Errored Frame Count Register
Address: 0xA4, Reset: 0x00000000, Name: P1_RX_CRC_ERR_CNT
Table 90. Bit Descriptions for P1_RX_CRC_ERR_CNT
Bits
Bit Name
Description
Reset
Access
[31:0]
P1_RX_CRC_ERR_CNT
Rx CRC Errored Frame Count.
0x0
R
P1 Rx Align Error Count Register
Address: 0xA5, Reset: 0x00000000, Name: P1_RX_ALGN_ERR_CNT
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Table 91. Bit Descriptions for P1_RX_ALGN_ERR_CNT
Bits
Bit Name
Description
Reset
Access
[31:0]
P1_RX_ALGN_ERR_CNT
Rx Align Error Count.
0x0
R
P1 Rx Long/Short Frame Error Count Register
Address: 0xA6, Reset: 0x00000000, Name: P1_RX_LS_ERR_CNT
Table 92. Bit Descriptions for P1_RX_LS_ERR_CNT
Bits
Bit Name
Description
Reset
Access
[31:0]
P1_RX_LS_ERR_CNT
Rx Long/Short Frame Error Count.
0x0
R
P1 Rx PHY Error Count Register
Address: 0xA7, Reset: 0x00000000, Name: P1_RX_PHY_ERR_CNT
Table 93. Bit Descriptions for P1_RX_PHY_ERR_CNT
Bits
Bit Name
Description
Reset
Access
[31:0]
P1_RX_PHY_ERR_CNT
Rx PHY Error Count.
0x0
R
P1 Tx Frame Count Register
Address: 0xA8, Reset: 0x00000000, Name: P1_TX_FRM_CNT
Table 94. Bit Descriptions for P1_TX_FRM_CNT
Bits
Bit Name
Description
Reset
Access
[31:0]
P1_TX_FRM_CNT
Tx Frame Count.
0x0
R
P1 Tx Broadcast Frame Count Register
Address: 0xA9, Reset: 0x00000000, Name: P1_TX_BCAST_CNT
Table 95. Bit Descriptions for P1_TX_BCAST_CNT
Bits
Bit Name
Description
Reset
Access
[31:0]
P1_TX_BCAST_CNT
Tx Broadcast Frame Count.
0x0
R
P1 Tx Multicast Frame Count Register
Address: 0xAA, Reset: 0x00000000, Name: P1_TX_MCAST_CNT
Table 96. Bit Descriptions for P1_TX_MCAST_CNT
Bits
Bit Name
Description
Reset
Access
[31:0]
P1_TX_MCAST_CNT
Tx Multicast Frame Count.
0x0
R
P1 Tx Unicast Frame Count Register
Address: 0xAB, Reset: 0x00000000, Name: P1_TX_UCAST_CNT
Table 97. Bit Descriptions for P1_TX_UCAST_CNT
Bits
Bit Name
Description
Reset
Access
[31:0]
P1_TX_UCAST_CNT
Tx Unicast Frame Count.
0x0
R
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P1 Rx Frames Dropped Due to FIFO Full Register
Address: 0xAC, Reset: 0x00000000, Name: P1_RX_DROP_FULL_CNT
Table 98. Bit Descriptions for P1_RX_DROP_FULL_CNT
Bits
Bit Name
Description
Reset
Access
[31:0]
P1_RX_DROP_FULL_CNT
Rx Frames Dropped Due to FIFO Full. Counts frames dropped due to a full receive FIFO.
0x0
R
P1 Rx Frames Dropped Due to Filtering Register
Address: 0xAD, Reset: 0x00000000, Name: P1_RX_DROP_FILT_CNT
Table 99. Bit Descriptions for P1_RX_DROP_FILT_CNT
Bits
Bit Name
Description
Reset
Access
[31:0]
P1_RX_DROP_FILT_CNT
Rx Frames Dropped Due to Filtering.
0x0
R
Frame Received on Port 1 with IFG Errors Register
Address: 0xAE, Reset: 0x00000000, Name: P1_RX_IFG_ERR_CNT
Table 100. Bit Descriptions for P1_RX_IFG_ERR_CNT
Bits
Bit Name
Description
Reset
Access
[31:0]
P1_RX_IFG_ERR_CNT
IFG Error Counter for Port 1 Received Frames.
0x0
R
P1 Transmit Interframe Gap Register
Address: 0xB0, Reset: 0x0000000B, Name: P1_TX_IFG
Table 101. Bit Descriptions for P1_TX_IFG
Bits
Bit Name
Description
Reset
Access
[31:8]
[7:0]
RESERVED
P1_TX_IFG
Reserved.
Interframe Gap. Generates an IFG of (P1_TX_IFG + 1) × 8 bit times between frames on Tx.
0x0
0xB
R
R/W
P1 MAC Loopback Enable Register
Address: 0xB3, Reset: 0x00000000, Name: P1_LOOP
Table 102. Bit Descriptions for P1_LOOP
Bits
Bit Name
Description
Reset
Access
[31:1]
0
RESERVED
P1_LOOPBACK_EN
Reserved.
MAC Loopback. Enable loopback on the MII interface to the PHY.
0: normal operation, loopback disabled.
1: loopback enabled.
0x0
0x0
R
R/W
P1 CRC Check Enable on Receive Register
Address: 0xB4, Reset: 0x00000001, Name: P1_RX_CRC_EN
Table 103. Bit Descriptions for P1_RX_CRC_EN
Bits
Bit Name
Description
Reset
Access
[31:1]
RESERVED
Reserved.
0x0
R
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Table 103. Bit Descriptions for P1_RX_CRC_EN
Bits
Bit Name
Description
Reset
Access
0
P1_CRC_CHK_EN
CRC Check Enable on Receive.
0x1
R/W
P1 Receive Interframe Gap Register
Address: 0xB5, Reset: 0x0000000A, Name: P1_RX_IFG
Table 104. Bit Descriptions for P1_RX_IFG
Bits
Bit Name
Description
Reset
Access
[31:6]
[5:0]
RESERVED
P1_RX_IFG
Reserved.
Interframe Gap. The receive MAC checks that the IFG is greater than P1_RX_IFG × 8 bit times. If the received
IFG is too small, the MAC drops the received frame and asserts P1_RX_IFG_ERR. The maximum value
supported in this field is 63 decimal.
0x0
0xA
R
R/W
P1 Max Receive Frame Length Register
Address: 0xB6, Reset: 0x00000618, Name: P1_RX_MAX_LEN
Maximum receive frame length in bytes.
Table 105. Bit Descriptions for P1_RX_MAX_LEN
Bits
Bit Name
Description
Reset
Access
[31:16]
[15:0]
RESERVED
P1_MAX_FRM_LEN
Reserved.
Maximum Frame Length on Receive.
0x0
0x618
R
R/W
P1 Min Receive Frame Length Register
Address: 0xB7, Reset: 0x00000040, Name: P1_RX_MIN_LEN
Minimum receive frame length in bytes.
Table 106. Bit Descriptions for P1_RX_MIN_LEN
Bits
Bit Name
Description
Reset
Access
[31:16]
[15:0]
RESERVED
P1_MIN_FRM_LEN
Reserved.
Minimum frame length on receive.
0x0
0x40
R
R/W
P1 Rx Low Priority FIFO Frame Count Register
Address: 0xB8, Reset: 0x00000000, Name: P1_LO_RFC
The number of frames in the receive FIFO.
Table 107. Bit Descriptions for P1_LO_RFC
Bits
Bit Name
Description
Reset
Access
[31:9]
[8:0]
RESERVED
P1_LO_RFC
Reserved.
Receive Frame Count for the Low Priority FIFO. The number of frames in the Rx FIFO. Provided for debug
purposes. In store and forward mode, the host software only needs to know that there is at least one frame
available. See P1_RX_RDY in the Status Register 1 section.
0x0
0x0
R
R
P1 Rx High Priority FIFO Frame Count Register
Address: 0xB9, Reset: 0x00000000, Name: P1_HI_RFC
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The number of frames in the receive FIFO.
Table 108. Bit Descriptions for P1_HI_RFC
Bits
Bit Name
Description
Reset
Access
[31:9]
[8:0]
RESERVED
P1_HI_RFC
Reserved.
Receive Frame Count for the High Priority FIFO. The number of frames in the Rx FIFO. Provided for debug
purposes. In store and forward mode, the host software only needs to know that there is at least one frame
available. See P1_RX_RDY in the Status Register 1 section.
0x0
0x0
R
R
P1 Low Priority Rx FIFO Valid Half Words Register
Address: 0xBA, Reset: 0x00000000, Name: P1_LO_RXSIZE
Number of valid half words (16 bits) in the low priority Rx FIFO.
Table 109. Bit Descriptions for P1_LO_RXSIZE
Bits
Bit Name
Description
Reset
Access
[31:14]
[13:0]
RESERVED
P1_LO_RXSIZE
Reserved.
Data in the Rx FIFO. Number of half words (16 Bits).
0x0
0x0
R
R
P1 High Priority Rx FIFO Valid Half Words Register
Address: 0xBB, Reset: 0x00000000, Name: P1_HI_RXSIZE
Number of valid half words (16 bits) in the high priority Rx FIFO.
Table 110. Bit Descriptions for P1_HI_RXSIZE
Bits
Bit Name
Description
Reset
Access
[31:14]
[13:0]
RESERVED
P1_HI_RXSIZE
Reserved.
Data in the Rx FIFO. Number of half words (16 bits).
0x0
0x0
R
R
PHY CLAUSE 22 REGISTER DETAILS
Table 111. PHY Clause 22 Register Summary
Address
Name
Description
Reset
Access
0x0
0x1
0x2
0x3
0xD
0xE
MI_CONTROL
MI_STATUS
MI_PHY_ID1
MI_PHY_ID2
MMD_ACCESS_CNTRL
MMD_ACCESS
MII Control Register.
MII Status Register.
PHY Identifier 1 Register.
PHY Identifier 2 Register.
MMD Access Control.
MMD Access.
0x1100
0x1009
0x0283
0xBC91
0x0000
0x0000
R/W
R
R
R
R/W
R/W
MII Control Register
Address: 0x0, Reset: 0x1100, Name: MI_CONTROL
This address corresponds to the MII control register specified in Clause 22.2.4.1 of Standard 802.3.
Table 112. Bit Descriptions for MI_CONTROL
Bits
Bit Name
Description
Reset
Access
15
MI_SFT_RST
0x0
R/W SC
14
MI_LOOPBACK
Software Reset. The software reset register allows a software reset cycle to be initiated. Mirrors
CRSM_SFT_RST.
Local Loopback (PCS). The loopback register allows the PHY loopback mode to be engaged.
Mirrors LB_PCS_EN.
0x0
R/W
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REGISTERS
Table 112. Bit Descriptions for MI_CONTROL
Bits
Bit Name
Description
Reset
Access
13
12
MI_SPEED_SEL_LSB
MI_AN_EN
0x0
0x1
R
R
11
MI_SFT_PD
Pin Dependent
R/W
10
9
8
MI_ISOLATE
RESERVED
MI_FULL_DUPLEX
0x0
0x0
0x1
R/W
R/W SC
R
7
MI_COLTEST
0x0
R
6
MI_SPEED_SEL_MSB
0x0
R
5
MI_UNIDIR_EN
0x0
R
[4:0]
RESERVED
MII Speed Selection LSB. See MI_SPEED_SEL_MSB.
Autonegotiation Enable. Use the AN_FRC_MODE_EN register to enable forced link configuration
mode. Mirrors AN_EN.
1 = enable autonegotiation.
0 = disable autonegotiation.
Software Power-Down. The software power-down register allows the PHY to be placed in software
power-down mode. In this mode, most of the PHY circuitry is switched off. However, MDIO access
to all registers is still possible. The default value for this register is configurable via a pin. This
allows the PHY to be held in reset until an appropriate software initialization is performed. Mirrors
CRSM_SFT_PD.
MII Isolate. The isolate bit allows the PHY to be isolated from the MII.
Reserved.
MII Full Duplex. The duplex mode register cannot be written and always reads as 1 because the
PHY is only able to operate in full duplex mode.
MII Collision Test. The collision test register cannot be written and always reads as 0 because the
PHY is only able to operate in full duplex mode and does not have a COL pin.
MII Speed Selection MSB. The speed selection MSB/LSB registers cannot be written and always
read as 00 because the PHY is only able to operate in 10 Mbps.
MII Unidirectional Enable. The unidirectional enable register cannot be written and always reads as
0 because the PHY does not have the ability to transmit data from the MII, regardless of whether or
not it has determined that a valid link is established.
Reserved.
0x0
R
MII Status Register
Address: 0x1, Reset: 0x1009, Name: MI_STATUS
This address corresponds to the MII status register specified in Clause 22.2.4.2 of Standard 802.3.
Table 113. Bit Descriptions for MI_STATUS
Bits
Bit Name
Description
Reset
Access
15
MI_T4_SPRT
0x0
R
14
MI_FD100_SPRT
0x0
R
13
MI_HD100_SPRT
0x0
R
12
MI_FD10_SPRT
0x1
R
11
MI_HD10_SPRT
0x0
R
10
MI_FD_T2_SPRT
0x0
R
9
MI_HD_T2_SPRT
0x0
R
8
MI_EXT_STAT_SPRT
0x0
R
7
MI_UNIDIR_ABLE
0x0
R
6
MI_MF_PREAM_SUP_ABLE
100BASE-T4 Ability. The 100BASE-T4 ability bit always reads as 0 to indicate that the PHY does
not support this technology.
Full Duplex 100BASE-X Ability. The 100BASE-X full duplex ability bit always reads as 0 to indicate
that the PHY does not support this technology.
Half-Duplex 100BASE-X Ability. The 100BASE-X half-duplex ability bit always reads as 0 to indicate
that the PHY does not support this technology.
Full Duplex 10 Mbps Ability. The 10 Mbps full duplex ability bit indicates that the PHY supports this
technology.
Half-Duplex 10 Mbps Ability. The 10 Mbps half-duplex ability bit always reads as 0 to indicate that
the PHY does not support this technology.
Full Duplex 100BASE-T2 Ability. The 100BASE-T2 full duplex ability bits always reads as 0 to
indicate that the PHY does not support this technology.
Half-Duplex 100BASE-T2- Ability. The 100BASE-T2 half-duplex ability bit always reads as 0 to
indicate that the PHY does not support this technology.
Extended Status Support. The extended status support bit always reads as 0 to indicate that the
PHY does not provide extended status information in Register 0xF.
Unidirectional Ability. The unidirectional ability register always reads as 0 to indicate that the PHY
can only transmit data from the MII when it has determined that a valid link is established.
Management Preamble Suppression Ability. The management frame preamble suppression ability
bit always reads as 0 to indicate that the PHY is not able to receive management frames that are
not preceded by the preamble pattern.
0x0
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Data Sheet
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REGISTERS
Table 113. Bit Descriptions for MI_STATUS
Bits
Bit Name
Description
Reset
Access
5
MI_AN_COMPLETE
0x0
R
4
MI_REM_FLT
0x0
R LH
3
MI_AN_ABLE
0x1
R
2
MI_LINK_STAT_LAT
0x0
R LL
1
MI_JABBER_DET
0x0
R LH
0
MI_EXT_CAPABLE
Autonegotiation Complete. The autonegotiation complete bit indicates that the autonegotiation
process is completed and the PHY link is up. Mirrors AN_COMPLETE.
Remote Fault. The remote fault bit always reads as 0 as the PHY has no provision for remote fault
detection.
Autonegotiation Ability. The autonegotiation ability bit always reads as 1 indicating that the PHY has
the ability to perform autonegotiation. Mirrors AN_ABLE.
Link Status. This uses a latch low functionality as described in IEEE Standard 802.3 Subclause
45.2.7.20.5. If the link_status value is fail, this register remains cleared until the latching is cleared
when the register is read. Mirrors AN_LINK_STATUS.
MII Jabber Detect. The jabber detect bit always reads as 0 as the 10BASE-T1L PHY does not
incorporate a jabber detect function.
MII Extended Capability. The extended capability bit always reads as 1 indicating that the PHY
provides an extended set of capabilities that can be accessed through the extended register set.
The extended register set consists of all of the management registers except 0, 1, and 15.
0x1
R
PHY Identifier 1 Register
Address: 0x2, Reset: 0x0283, Name: MI_PHY_ID1
The PHY Identifier 1 address allows 16 bits of the OUI to be observed.
Table 114. Bit Descriptions for MI_PHY_ID1
Bits
Bit Name
Description
Reset
Access
[15:0]
MI_PHY_ID1
The PHY Identifier 1 address allows 16 bits of the OUI to be observed.
0x283
R
PHY Identifier 2 Register
Address: 0x3, Reset: 0xBC91, Name: MI_PHY_ID2
The PHY Identifier 2 address allows six bits of the OUI, the model number, and revision number to be observed.
Table 115. Bit Descriptions for MI_PHY_ID2
Bits
Bit Name
Description
Reset
Access
[15:10]
[9:4]
[3:0]
MI_PHY_ID2_OUI
MI_MODEL_NUM
MI_REV_NUM
OUI, Bits[7:2].
Model Number.
Revision Number.
0x2F
0x9
0x1
R
R
R
MMD Access Control Register
Address: 0xD, Reset: 0x0000, Name: MMD_ACCESS_CNTRL
This address corresponds to the MMD access control register specified in Clause 22.2.4.3.11 of IEEE Standard 802.3-2018.
Table 116. Bit Descriptions for MMD_ACCESS_CNTRL
Bits
Bit Name
Description
Reset
Access
[15:14]
MMD_ACR_FUNCTION
0x0
R/W
[13:5]
RESERVED
Function. The function register selects the type of MMD access on accesses to the MMD_DAR
register.
00: address.
01: data, no post increment.
10: data, post increment on reads and writes.
11: data, and post increment on writes only.
Reserved.
0x0
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Data Sheet
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REGISTERS
Table 116. Bit Descriptions for MMD_ACCESS_CNTRL
Bits
Bit Name
Description
Reset
Access
[4:0]
MMD_ACR_DEVAD
Device Address. The value in this register directs any accesses to the MMD_DAR register to the
selected MMD.
0x0
R/W
MMD Access Register
Address: 0xE, Reset: 0x0000, Name: MMD_ACCESS
This address corresponds to the MMD access address data register specified in Clause 22.2.4.3.12 of IEEE Standard 802.3-2018.
The MMD_ADDR_DATA register is used with the MMD_ACCESS_CNTRL register to provide access to the MMD address space using the
interface and mechanisms defined in Clause 22.2.4.
Table 117. Bit Descriptions for MMD_ACCESS
Bits
Bit Name
Description
Reset
Access
[15:0]
MMD_ACCESS
Access Address. This address corresponds to the MMD access address data register specified in
Clause 22.2.4.3.12 of IEEE Standard 802.3-2018.The MMD_ADDR_DATA register is used with the
MMD_ACCESS_CNTRL register to provide access to the MMD address space using the interface and
mechanisms defined in Clause 22.2.4.
0x0
R/W
PHY CLAUSE 45 REGISTER MAP
Table 118. PHY Clause 45 Register Summary
Device Address
Register Address
Name
Description
Reset
Access
0x01
0x01
0x01
0x01
0x0000
0x0001
0x0005
0x0006
PMA_PMD_CNTRL1
PMA_PMD_STAT1
PMA_PMD_DEVS_IN_PKG1
PMA_PMD_DEVS_IN_PKG2
0x0000
0x0002
0x008B
0xC000
R/W
R
R
R
0x01
0x01
0x01
0x01
0x01
0x01
0x01
0x01
0x01
0x01
0x0007
0x0008
0x0009
0x000B
0x0012
0x0834
0x08F6
0x08F7
0x08F8
0x8015
PMA_PMD_CNTRL2
PMA_PMD_STAT2
PMA_PMD_TX_DIS
PMA_PMD_EXT_ABILITY
PMA_PMD_BT1_ABILITY
PMA_PMD_BT1_CONTROL
B10L_PMA_CNTRL
B10L_PMA_STAT
B10L_TEST_MODE_CNTRL
CR_STBL_CHK_FOFFS_SAT_THR
0x003D
0x8301
0x0000
0x0800
0x0004
0x8002
0x0000
0x2800
0x0000
0x0008
R/W
R
R/W
R
R
R/W
R/W
R
R/W
R/W
0x01
0x81E7
SLV_FLTR_ECHO_ACQ_CR_KP
0x0400
R/W
0x01
0x01
0x03
0x03
0x03
0x03
0x03
0x03
0x03
0x8302
0x830B
0x0000
0x0001
0x0005
0x0006
0x0008
0x08E6
0x08E7
B10L_PMA_LINK_STAT
MSE_VAL
PCS_CNTRL1
PCS_STAT1
PCS_DEVS_IN_PKG1
PCS_DEVS_IN_PKG2
PCS_STAT2
B10L_PCS_CNTRL
B10L_PCS_STAT
PMA/PMD Control 1 Register.
PMA/PMD Status 1 Register.
PMA/PMD MMD Devices in Package 1.
PMA/PMD MMD Devices in Package 2
Register.
PMA/PMD Control 2 Register.
PMA/PMD Status 2.
PMA/PMD Transmit Disable Register.
PMA/PMD Extended Abilities Register.
BASE-T1 PMA/PMD Extended Ability Register.
BASE-T1 PMA/PMD Control Register.
10BASE-T1L PMA Control Register.
10BASE-T1L PMA Status Register.
10BASE-T1L Test Mode Control Register.
Frequency Offset Saturation Threshold for CR
Stability Check Register.
Slave IIR Filter Change Echo Acquisition Clock
Recovery Proportional Gain Register.
10BASE-T1L PMA Link Status Register.
Mean Squared Error (MSE) Value Register.
PCS Control 1 Register.
PCS Status 1 Register.
PCS MMD Devices in Package 1 Register.
PCS MMD Devices in Package 2 Register.
PCS Status 2 Register.
10BASE-T1L PCS Control Register.
10BASE-T1L PCS Status Register.
0x0000
0x0000
0x0000
0x0002
0x008B
0xC000
0x8000
0x0000
0x0000
R
R
R/W
R
R
R
R
R/W
R
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Data Sheet
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REGISTERS
Table 118. PHY Clause 45 Register Summary
Device Address
Register Address
Name
Description
Reset
Access
0x07
0x0005
AN_DEVS_IN_PKG1
0x008B
R
0x07
0x0006
AN_DEVS_IN_PKG2
0xC000
R
0x07
0x07
0x07
0x0200
0x0201
0x0202
AN_CONTROL
AN_STATUS
AN_ADV_ABILITY_L
0x1000
0x0008
0x0001
R/W
R
R/W
0x07
0x0203
AN_ADV_ABILITY_M
0x4000
R/W
0x07
0x0204
AN_ADV_ABILITY_H
0x0000
R/W
0x07
0x0205
AN_LP_ADV_ABILITY_L
0x0000
R
0x07
0x0206
AN_LP_ADV_ABILITY_M
0x0000
R
0x07
0x0207
AN_LP_ADV_ABILITY_H
0x0000
R
0x07
0x0208
AN_NEXT_PAGE_L
0x2001
R/W
0x07
0x0209
AN_NEXT_PAGE_M
0x0000
R/W
0x07
0x020A
AN_NEXT_PAGE_H
0x0000
R/W
0x07
0x020B
AN_LP_NEXT_PAGE_L
0x0000
R
0x07
0x020C
AN_LP_NEXT_PAGE_M
0x0000
R
0x07
0x020D
AN_LP_NEXT_PAGE_H
0x0000
R
0x07
0x07
0x07
0x07
0x07
0x1E
0x020E
0x020F
0x8000
0x8001
0x8030
0x0002
AN_B10_ADV_ABILITY
AN_B10_LP_ADV_ABILITY
AN_FRC_MODE_EN
AN_STATUS_EXTRA
AN_PHY_INST_STATUS
MMD1_DEV_ID1
0x8000
0x0000
0x0000
0x0000
0x0010
0x0283
R/W
R
R/W
R
R
R
0x1E
0x0003
MMD1_DEV_ID2
0xBC01
R
0x1E
0x0005
MMD1_DEVS_IN_PKG1
0x008B
R
0x1E
0x0006
MMD1_DEVS_IN_PKG2
0xC000
R
0x1E
0x1E
0x1E
0x1E
0x1E
0x1E
0x1E
0x0008
0x0010
0x0020
0x8810
0x8812
0x8814
0x8815
MMD1_STATUS
CRSM_IRQ_STATUS
CRSM_IRQ_MASK
CRSM_SFT_RST
CRSM_SFT_PD_CNTRL
CRSM_PHY_SUBSYS_RST
CRSM_MAC_IF_RST
AUTO-_NEGOTIATION MMD Devices in
Package 1 Register.
AUTO-_NEGOTIATION MMD Devices in
Package 2 Register.
BASE-T1 Autonegotiation Control Register.
BASE-T1 Autonegotiation Status Register.
BASE-T1 Autonegotiation Advertisement
Register, Bits[15:0].
BASE-T1 Autonegotiation Advertisement
Register, Bits[31:16].
BASE-T1 Autonegotiation Advertisement
Register, Bits[47:32].
BASE-T1 Autonegotiation Link Partner Base
Page Ability Register, Bits[15:0].
BASE-T1 Autonegotiation Link Partner Base
Page Ability Register, Bits[31:16].
BASE-T1 Autonegotiation Link Partner Base
Page Ability Register, Bits[47:32].
BASE-T1 Autonegotiation Next Page Transmit
Register, Bits[15:0]
BASE-T1 Autonegotiation Next Page Transmit
Register, Bits[31:16].
BASE-T1 Autonegotiation Next Page Transmit
Register, Bits[47:32].
BASE-T1 Autonegotiation Link Partner Next
Page Ability Register, Bits[15:0].
BASE-T1 Autonegotiation Link Partner Next
Page Ability Register, Bits[31:16].
BASE-T1 Autonegotiation Link Partner Next
Page Ability Register, Bits[47:32].
10BASE-T1 Autonegotiation Control Register.
10BASE-T1 Autonegotiation Status Register.
Autonegotiation Force Mode Enable Register.
Extra Autonegotiation Status Register.
PHY Instantaneous Status.
Vendor Specific MMD 1 Device Identifier High
Register.
Vendor Specific MMD 1 Device Identifier Low
Register.
Vendor Specific 1 MMD Devices in Package
Register.
Vendor Specific 1 MMD Devices in Package
Register.
Vendor Specific MMD 1 Status Register.
System Interrupt Status Register.
System Interrupt Mask Register.
Software Reset Register.
Software Power-Down Control Register.
PHY Subsystem Reset Register.
PHY MAC Interface Reset Register.
0x8000
0x1000
0x1FFE
0x0000
0x0000
0x0000
0x0000
R
R
R/W
R/W
R/W
R/W
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Data Sheet
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REGISTERS
Table 118. PHY Clause 45 Register Summary
Device Address
Register Address
Name
Description
Reset
Access
0x1E
0x1E
0x1E
0x1E
0x1E
0x1E
0x1E
0x1E
0x1E
0x1E
0x1F
0x8818
0x8819
0x882C
0x8C22
0x8C30
0x8C56
0x8C80
0x8C81
0x8C82
0x8C83
0x0002
CRSM_STAT
CRSM_PMG_CNTRL
CRSM_DIAG_CLK_CTRL
MGMT_PRT_PKG
MGMT_MDIO_CNTRL
DIGIO_PINMUX
LED0_BLINK_TIME_CNTRL
LED1_BLINK_TIME_CNTRL
LED_CNTRL
LED_POLARITY
MMD2_DEV_ID1
0x0000
0x0000
0x0002
0x0000
0x0000
0x00FE
0x3636
0x3636
0x8480
0x0000
0x0283
R
R/W
R/W
R
R/W
R/W
R/W
R/W
R/W
R/W
R
0x1F
0x0003
MMD2_DEV_ID2
0xBC91
R
0x1F
0x0005
MMD2_DEVS_IN_PKG1
0x008B
R
0x1F
0x0006
MMD2_DEVS_IN_PKG2
0xC000
R
0x1F
0x1F
0x1F
0x1F
0x1F
0x1F
0x1F
0x1F
0x1F
0x1F
0x1F
0x1F
0x1F
0x0008
0x0011
0x0021
0x8001
0x8004
0x8005
0x8008
0x8009
0x800A
0x800B
0x800C
0x800D
0x800E
MMD2_STATUS
PHY_SUBSYS_IRQ_STATUS
PHY_SUBSYS_IRQ_MASK
FC_EN
FC_IRQ_EN
FC_TX_SEL
RX_ERR_CNT
FC_FRM_CNT_H
FC_FRM_CNT_L
FC_LEN_ERR_CNT
FC_ALGN_ERR_CNT
FC_SYMB_ERR_CNT
FC_OSZ_CNT
0x8000
0x0000
0x2402
0x0001
0x0001
0x0000
0x0000
0x0000
0x0000
0x0000
0x0000
0x0000
0x0000
R
R
R/W
R/W
R/W
R/W
R
R
R
R
R
R
R
0x1F
0x800F
FC_USZ_CNT
0x0000
R
0x1F
0x8010
FC_ODD_CNT
0x0000
R
0x1F
0x8011
FC_ODD_PRE_CNT
0x0000
R
0x1F
0x1F
0x1F
0x1F
0x8013
0x8020
0x8021
0x8022
FC_FALSE_CARRIER_CNT
FG_EN
FG_CNTRL_RSTRT
FG_CONT_MODE_EN
0x0000
0x0000
0x0001
0x0000
R
R/W
R/W
R/W
0x1F
0x1F
0x1F
0x8023
0x8025
0x8026
FG_IRQ_EN
FG_FRM_LEN
FG_IFG_LEN
0x0000
0x006B
0x000C
R/W
R/W
R/W
0x1F
0x8027
FG_NFRM_H
System Status Register.
CRSM Power Management Control Register.
CRSM Diagnostics Clock Control.
Package Configuration Values Register.
MDIO Control Register.
Pin Mux Configuration 1 Register.
LED 0 On/Off Blink Time Register.
LED 1 On/Off Blink Time Register.
LED Control Register.
LED Polarity Register.
Vendor Specific MMD 2 Device Identifier High
Register.
Vendor Specific MMD 2 Device Identifier Low
Register.
Vendor Specific 2 MMD Devices in Package
Register.
Vendor Specific 2 MMD Devices in Package
Register.
Vendor Specific MMD 2 Status Register.
PHY Subsystem Interrupt Status Register.
PHY Subsystem Interrupt Mask Register.
Frame Checker Enable Register.
Frame Checker Interrupt Enable Register.
Frame Checker Transmit Select Register.
Receive Error Count Register.
Frame Checker Count High Register.
Frame Checker Count Low Register.
Frame Checker Length Error Count Register.
Frame Checker Alignment Error Count Register.
Frame Checker Symbol Error Count Register.
Frame Checker Oversized Frame Count
Register.
Frame Checker Undersized Frame Count
Register.
Frame Checker Odd Nibble Frame Count
Register.
Frame Checker Odd Preamble Packet Count
Register.
Frame Checker False Carrier Count Register.
Frame Generator Enable Register.
Frame Generator Control/Restart Register.
Frame Generator Continuous Mode Enable
Register.
Frame Generator Interrupt Enable Register.
Frame Generator Frame Length Register.
Frame Generator Interframe Gap Length
Register.
Frame Generator Number of Frames High
Register.
0x0000
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Data Sheet
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REGISTERS
Table 118. PHY Clause 45 Register Summary
Device Address
Register Address
Name
Description
Reset
Access
0x1F
0x8028
FG_NFRM_L
0x0100
R/W
0x1F
0x1F
0x8029
0x8055
FG_DONE
MAC_IF_LOOPBACK
0x0000
0x000A
R
R/W
0x1F
0x805A
MAC_IF_SOP_CNTRL
Frame Generator Number of Frames Low
Register.
Frame Generator Done Register.
MAC Interface Loopbacks Configuration
Register.
MAC Start Of Packet (SOP) Generation Control
Register.
0x001B
R/W
PMA/PMD Control 1 Register
Device Address: 0x01; Register Address: 0x0000, Reset: 0x0000, Name: PMA_PMD_CNTRL1
This address corresponds to the PMA/PMD Control Register 1 specified in Clause 45.2.1.1 of Standard 802.3. Note that the reset value of this
register is dependent on the hardware configuration pin settings.
Table 119. Bit Descriptions for PMA_PMD_CNTRL1
Bits
Bit Name
Description
Reset
Access
15
PMA_SFT_RST
0x0
R/W SC
[14:12]
11
RESERVED
PMA_SFT_PD
0x0
0x0
R
R/W
[10:1]
0
RESERVED
LB_PMA_LOC_EN
PMA Software Reset. The PMA software reset bit allows the chip to be reset. When this bit is set,
the chip fully initializes, almost equivalent to a hardware reset. This bit is self clearing and returns a
value of 1 when a reset is in progress. Otherwise, it returns a value of 0.
Reserved.
PMA Software Power-Down. The PMA software power-down register puts the chip in a lower power
mode. In this mode, most of the circuitry is switched off. However, MDIO access to all registers is
still possible. The default value for this register is configurable via the SWPD_EN pin, which allows
the chip to be held in power-down mode until an appropriate software initialization is performed.
Reserved.
Enables PMA Local Loopback. When this bit is set to 1, the PMA accepts data on the transmit path
and returns it on the receive path. When this bit is set to 0, the PMA works in normal mode.
0x0
0x0
R
R/W
PMA/PMD Status 1 Register
Device Address: 0x01; Register Address: 0x0001, Reset: 0x0002, Name: PMA_PMD_STAT1
This address corresponds to the PMA/PMD Status Register 1 specified in Clause 45.2.1.2 of Standard 802.3.
Table 120. Bit Descriptions for PMA_PMD_STAT1
Bits
Bit Name
Description
Reset
Access
[15:3]
2
RESERVED
PMA_LINK_STAT_OK_LL
0x0
0x0
R
R LL
1
0
PMA_SFT_PD_ABLE
RESERVED
Reserved.
PMA Link Status. When read as 1, this bit indicates that the link is up. When read as 0, it
indicates that the link has dropped since the last time the bit was read.
PMA Software Power-Down Able. Indicates that the PMA supports software power-down.
Reserved.
0x1
0x0
R
R
PMA/PMD MMD Devices in Package 1 Register
Device Address: 0x01; Register Address: 0x0005, Reset: 0x008B, Name: PMA_PMD_DEVS_IN_PKG1
Table 121. Bit Descriptions for PMA_PMD_DEVS_IN_PKG1
Bits
Bit Name
Description
Reset
Access
[15:0]
PMA_PMD_DEVS_IN_PKG1
PMA/PMD MMD Devices in Package. Clause 22 registers and PMA/PMD, PCS, and
autonegotiation MMDs are present.
0x8B
R
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Data Sheet
ADIN1110
REGISTERS
PMA/PMD MMD Devices in Package 2 Register
Device Address: 0x01; Register Address: 0x0006, Reset: 0xC000, Name: PMA_PMD_DEVS_IN_PKG2
Table 122. Bit Descriptions for PMA_PMD_DEVS_IN_PKG2
Bits
Bit Name
Description
[15:0]
PMA_PMD_DEVS_IN_PKG2
PMA/PMD MMD Devices in Package. Vendor Specific Device 1 and Vendor Specific 0xC000
Device 2 MMDs are present.
Reset
Access
R
PMA/PMD Control 2 Register
Device Address: 0x01; Register Address: 0x0007, Reset: 0x003D, Name: PMA_PMD_CNTRL2
Table 123. Bit Descriptions for PMA_PMD_CNTRL2
Bits
Bit Name
Description
Reset
Access
[15:7]
[6:0]
RESERVED
PMA_PMD_TYPE_SEL
Reserved.
PMA/PMD Type Selection. See IEEE Standard 802.3. PMA_PMD_TYPE_SEL is used
only when autonegotiation is disabled and forced link configuration mode is enabled. If
autonegotiation is enabled, the PHY type is determined by the autonegotiation process itself.
Note that for ADIN1110, the only valid value for this field is for BASE-T1 PMA/PMD.
0000000: TS_10GBASE_CX4_PMA_PMD.
0000001: TS_10GBASE_EW_PMA_PMD.
0000010: TS_10GBASE_LW_PMA_PMD.
0000011: TS_10GBASE_SW_PMA_PMD.
0000100: TS_10GBASE_LX4_PMA_PMD.
0000101: TS_10GBASE_ER_PMA_PMD.
0000110: TS_10GBASE_LR_PMA_PMD.
0000111: TS_10GBASE_SR_PMA_PMD.
0001000: TS_10GBASE_LRM_PMA_PMD.
0001001: TS_10GBASE_T_PMA.
0001010: TS_10GBASE_KX4_PMA_PMD.
0001011: TS_10GBASE_KR_PMA_PMD.
0001100: TS_1000BASE_T_PMA_PMD.
0001101: TS_1000BASE_KX_PMA_PMD.
0001110: TS_100BASE_TX_PMA_PMD.
0001111: TS_10BASE_T_PMA_PMD.
0010000: TS_10_1GBASE_PRX_D1.
0010001: TS_10_1GBASE_PRX_D2.
0010010: TS_10_1GBASE_PRX_D3.
0010011: TS_10GBASE_PR_D1.
0010100: TS_10GBASE_PR_D2.
0010101: TS_10GBASE_PR_D3.
0010110: TS_10_1GBASE_PRX_U1.
0010111: TS_10_1GBASE_PRX_U2.
0011000: TS_10_1GBASE_PRX_U3.
0011001: TS_10GBASE_PR_U1.
0011010: TS_10GBASE_PR_U3.
0011011: TS_RESERVED.
0011100: TS_10GBASE_PR_D4.
0011101: TS_10_1GBASE_PRX_D4.
0011110: TS_10GBASE_PR_U4.
0011111: TS_10_1GBASE_PRX_U4.
0x0
0x3D
R
R/W
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Data Sheet
ADIN1110
REGISTERS
Table 123. Bit Descriptions for PMA_PMD_CNTRL2
Bits
Bit Name
Description
Reset
Access
0100000: TS_40GBASE_KR4_PMA_PMD.
0100001: TS_40GBASE_CR4_PMA_PMD.
0100010: TS_40GBASE_SR4_PMA_PMD.
0100011: TS_40GBASE_LR4_PMA_PMD.
0100100: TS_40GBASE_FR_PMA_PMD.
0100101: TS_40GBASE_ER4_PMA_PMD.
0100110: TS_40GBASE_T_PMA.
0101000: TS_100GBASE_CR10_PMA_PMD.
0101001: TS_100GBASE_SR10_PMA_PMD.
0101010: TS_100GBASE_LR4_PMA_PMD.
0101011: TS_100GBASE_ER4_PMA_PMD.
0101100: TS_100GBASE_KP4_PMA_PMD.
0101101: TS_100GBASE_KR4_PMA_PMD.
0101110: TS_100GBASE_CR4_PMA_PMD.
0101111: TS_100GBASE_SR4_PMA_PMD.
0110000: TS_2_5GBASE_T_PMA.
0110001: TS_5GBASE_T_PMA.
0110010: TS_10GPASS_XR_D_PMA_PMD.
0110011: TS_10GPASS_XR_U_PMA_PMD.
0110100: TS_BASE_H_PMA_PMD.
0110101: TS_25GBASE_LR_PMA_PMD.
0110110: TS_25GBASE_ER_PMA_PMD.
0110111: TS_25GBASE_T_PMA.
0111000: TS_25GBASE_CR_OR_25GBASE_CR_S_PMA_PMD.
0111001: TS_25GBASE_KR_OR_25GBASE_KR_S_PMA_PMD.
0111010: TS_25GBASE_SR_PMA_PMD.
0111101: TS_BASE_T1_PMA_PMD.
1010011: TS_200GBASE_DR4_PMA_PMD.
1010100: TS_200GBASE_FR4_PMA_PMD.
1010101: TS_200GBASE_LR4_PMA_PMD.
1011001: TS_400GBASE_SR16_PMA_PMD.
1011010: TS_400GBASE_DR4_PMA_PMD.
1011011: TS_400GBASE_FR8_PMA_PMD.
1011100: TS_400GBASE_LR8_PMA_PMD.
PMA/PMD Status 2 Register
Device Address: 0x01; Register Address: 0x0008, Reset: 0x8301, Name: PMA_PMD_STAT2
Table 124. Bit Descriptions for PMA_PMD_STAT2
Bits
Bit Name
Description
Reset
Access
[15:14]
[13:10]
9
PMA_PMD_PRESENT
RESERVED
PMA_PMD_EXT_ABLE
0x2
0x0
0x1
R
R
R
8
[7:1]
0
PMA_PMD_TX_DIS_ABLE
RESERVED
LB_PMA_LOC_ABLE
PMA/PMD Present. Indicates that the PMA is present and responding.
Reserved.
PHY Extended Abilities Support. Indicates that the PHY supports extended abilities as
listed in PMA_PMD_EXT_ABILITY.
PMA/PMD Tx Disable. Indicates that the PMA supports transmit disable.
Reserved.
PMA Local Loopback Able. Indicates that the PMA supports local loopback.
0x1
0x0
0x1
R
R
R
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Data Sheet
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REGISTERS
PMA/PMD Transmit Disable Register
Device Address: 0x01; Register Address: 0x0009, Reset: 0x0000, Name: PMA_PMD_TX_DIS
This address corresponds to the PMD transmit disable register specified in Clause 45.2.1.8 of Standard 802.3.
Table 125. Bit Descriptions for PMA_PMD_TX_DIS
Bits
Bit Name
Description
Reset
Access
[15:1]
0
RESERVED
PMA_TX_DIS
Reserved.
PMD Transmit Disable. When this bit is set to 1, the PMD disables output on the transmit path. Otherwise,
the PMD enables output on the transmit path.
0x0
0x0
R
R/W
PMA/PMD Extended Abilities Register
Device Address: 0x01; Register Address: 0x000B, Reset: 0x0800, Name: PMA_PMD_EXT_ABILITY
PMA/PMD extended abilities.
Table 126. Bit Descriptions for PMA_PMD_EXT_ABILITY
Bits
Bit Name
Description
Reset
Access
[15:12]
11
RESERVED
PMA_PMD_BT1_ABLE
0x0
0x1
R
R
[10:0]
RESERVED
Reserved.
PHY Supports BASE-T1. Indicates that the PHY supports BASE-T1 extended abilities as
listed in PMA_PMD_BT1_ABILITY.
Reserved.
0x0
R
BASE-T1 PMA/PMD Extended Ability Register
Device Address: 0x01; Register Address: 0x0012, Reset: 0x0004, Name: PMA_PMD_BT1_ABILITY
This address corresponds to the BASE-T1 PMA/PMD extended ability register specified in Clause 45.2.1.16 of Standard 802.3. This register is
read only, and writes have no effect.
Table 127. Bit Descriptions for PMA_PMD_BT1_ABILITY
Bits
Bit Name
Description
Reset
Access
[15:4]
3
2
1
RESERVED
B10S_ABILITY
B10L_ABILITY
B1000_ABILITY
0x0
0x0
0x1
0x0
R
R
R
R
0
B100_ABILITY
Reserved.
10BASE-T1S Ability. This bit always reads as 0 because the PMA/PMD does not support 10BASE-T1S.
10BASE-T1L Ability. This bit always reads as 1 because the PMA/PMD supports 10BASE-T1L.
1000BASE-T1 Ability. This bit always reads as 0 because the PMA/PMD does not support 1000BASET1.
100BASE-T1 Ability. This bit always reads as 0 because the PMA/PMD does not support 100BASE-T1.
0x0
R
BASE-T1 PMA/PMD Control Register
Device Address: 0x01; Register Address: 0x0834, Reset: 0x8002, Name: PMA_PMD_BT1_CONTROL
This address corresponds to the BASE-T1 PMA/PMD control register specified in Clause 45.2.1.185 of Standard 802.3.
Table 128. Bit Descriptions for PMA_PMD_BT1_CONTROL
Bits
Bit Name
Description
Reset
Access
15
14
RESERVED
CFG_MST
0x1
Pin Dependent
R
R/W
[13:4]
RESERVED
Reserved.
Master and Slave Configuration. CFG_MST is used only when autonegotiation is disabled.
Otherwise, this value is determined by the autonegotiation process itself. When this bit is set as
1, the device is configured as master. Otherwise, the device is configured as slave.
Reserved.
0x0
R
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Data Sheet
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REGISTERS
Table 128. Bit Descriptions for PMA_PMD_BT1_CONTROL
Bits
Bit Name
Description
Reset
Access
[3:0]
BT1_TYPE_SEL
BASE-T1 Type Selection. See IEEE Standard 802.3 for the following control register bit
definitions (where X means don't care):
1XXX: reserved.
01XX: reserved.
0011: 10BASE-T1S.
0010: 10BASE-T1L.
0001: 1000BASE-T.
0000: 100BASE-T.
BT1_TYPE_SEL is used only when autonegotiation is disabled and forced link configuration
mode is enabled. If autonegotiation is enabled, the PHY type is determined by the
autonegotiation process itself. Note that for ADIN1110, the only valid value is for 10BASE-T1L.
0x2
R/W
10BASE-T1L PMA Control Register
Device Address: 0x01; Register Address: 0x08F6, Reset: 0x0000, Name: B10L_PMA_CNTRL
This address corresponds to the 10BASE-T1L PMA control register specified in Clause 45.2.1.186a of Standard 802.3cg.
Table 129. Bit Descriptions for B10L_PMA_CNTRL
Bits
Bit Name
Description
Reset
Access
15
14
RESERVED
B10L_TX_DIS_MODE_EN
0x0
0x0
R/W SC
R/W
13
12
RESERVED
B10L_TX_LVL_HI
0x0
Pin Dependent
R
R/W
11
10
[9:1]
0
RESERVED
B10L_EEE
RESERVED
B10L_LB_PMA_LOC_EN
Reserved.
10BASE-T1L Transmit Disable Mode. When this bit is set to 1, it disables output on
the transmit path. Otherwise, it enables output on the transmit path.
Reserved.
10BASE-T1L Transmit Voltage Amplitude Control. This configuration is only used
when autonegotiation is disabled. Otherwise, the configuration is decided by the
autonegotiation process. When this bit is set as 1, the device works in the 2.4 V p-p
operating mode. Otherwise, the device works in the 1.0 V p-p operating mode.
Reserved.
10BASE-T1L EEE Enable.
Reserved.
10BASE-T1L PMA Loopback. When this bit is set to 1, the PMA accepts data on the
transmit path and returns it on the receive path. When this bit is set to 0, the PMA
works in normal mode.
0x0
0x0
0x0
0x0
R/W
R/W
R
R/W
10BASE-T1L PMA Status Register
Device Address: 0x01; Register Address: 0x08F7, Reset: 0x2800, Name: B10L_PMA_STAT
This address corresponds to the 10BASE-T1L PMA status register specified in Clause 45.2.1.186b of Standard 802.3cg.
Table 130. Bit Descriptions for B10L_PMA_STAT
Bits
Bit Name
Description
Reset
Access
[15:14]
13
RESERVED
B10L_LB_PMA_LOC_ABLE
0x0
0x1
R
R
12
B10L_TX_LVL_HI_ABLE
Pin Dependent
R
11
B10L_PMA_SFT_PD_ABLE
0x1
R
10
B10L_EEE_ABLE
Reserved.
10BASE-T1L PMA Loopback Ability. This bit always reads as 1 because the
PMA has loopback ability
10BASE-T1L High Voltage Tx Ability. Indicates that the PHY supports
10BASE-T1L high voltage (2.4 V p-p) transmit level operating mode.
PMA Supports Power-Down. Indicates that the PMA supports software
power-down.
10BASE-T1L EEE Ability. Indicates if the PHY supports 10BASE-T1L EEE.
0x0
R
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Data Sheet
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Table 130. Bit Descriptions for B10L_PMA_STAT
Bits
Bit Name
Description
Reset
Access
[9:0]
RESERVED
Reserved.
0x0
R
10BASE-T1L Test Mode Control Register
Device Address: 0x01; Register Address: 0x08F8, Reset: 0x0000, Name: B10L_TEST_MODE_CNTRL
This address corresponds to the 10BASE-T1L PMA test mode control register specified in Clause 45.2.1.186c of Standard 802.3cg. The default
value of this register selects normal operation without management intervention as the initial state of the device.
Table 131. Bit Descriptions for B10L_TEST_MODE_CNTRL
Bits
Bit Name
Description
Reset
Access
[15:13]
B10L_TX_TEST_MODE
0x0
R/W
[12:0]
RESERVED
10BASE-T1L Transmitter Test Mode.
000: normal operation.
001: Test Mode 1—transmitter output voltage and timing jitter test mode. When Test Mode 1
is enabled, the PHY repeatedly transmits the data symbol sequence (+1, −1).
010: Test Mode 2—transmitter output droop test mode. When Test Mode 2 is enabled, the
PHY transmits ten +1 symbols followed by ten −1 symbols.
011: Test Mode 3—normal operation in idle mode. When Test Mode 3 is enabled, the PHY
transmits as in nontest operation and in the master data mode with data set to normal
interframe idle signals.
Reserved.
0x0
R
Frequency Offset Saturation Threshold for CR Stability Check Register
Device Address: 0x01; Register Address: 0x8015, Reset: 0x0008, Name: CR_STBL_CHK_FOFFS_SAT_THR
Table 132. Bit Descriptions for CR_STBL_CHK_FOFFS_SAT_THR
Bits
Bit Name
Description
Reset
Access
[15:11]
[10:0]
RESERVED
CR_STBL_CHK_FOFFS_SAT_THR
Reserved.
Frequency Offset Saturation Threshold for Clock Recovery (CR) Stability
Check.
0x0
0x8
R
R/W
Slave IIR Filter Change Echo Acquisition Clock Recovery Proportional Gain Register
Device Address: 0x01; Register Address: 0x81E7, Reset: 0x0400, Name: SLV_FLTR_ECHO_ACQ_CR_KP
Table 133. Bit Descriptions for SLV_FLTR_ECHO_ACQ_CR_KP
Bits
Bit Name
Description
Reset
Access
[15:0]
SLV_FLTR_ECHO_ACQ_CR_KP
Slave Infinite Impulse Response (IIR) Filter Change Echo Acquisition Clock
Recovery Proportional Gain.
0x400
R/W
10BASE-T1L PMA Link Status Register
Device Address: 0x01; Register Address: 0x8302, Reset: 0x0000, Name: B10L_PMA_LINK_STAT
This address can be read to determine the 10BASE-T1L PMA link status. Reading B10L_PMA_LINK_STAT clears the latching condition of
these bits.
Table 134. Bit Descriptions for B10L_PMA_LINK_STAT
Bits
Bit Name
Description
Reset
Access
[15:10]
RESERVED
Reserved.
0x0
R
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Table 134. Bit Descriptions for B10L_PMA_LINK_STAT
Bits
Bit Name
Description
Reset
Access
9
B10L_REM_RCVR_STAT_OK_LL
0x0
R LL
8
B10L_REM_RCVR_STAT_OK
0x0
R
7
B10L_LOC_RCVR_STAT_OK_LL
0x0
R LL
6
B10L_LOC_RCVR_STAT_OK
0x0
R
5
B10L_DSCR_STAT_OK_LL
0x0
R LL
4
B10L_DSCR_STAT_OK
0x0
R
[3:2]
1
RESERVED
B10L_LINK_STAT_OK_LL
0x0
0x0
R
R LL
0
B10L_LINK_STAT_OK
10BASE-T1L Remote Receiver Status OK Latch Low. Latched low version of
B10L_REM_RCVR_STAT_OK.
10BASE-T1L Remote Receiver Status OK. When read as 1, this bit indicates
that the remote receiver status is OK.
10BASE-T1L Local Receiver Status OK Latch Low. Latched low version of
B10L_LOC_RCVR_STAT_OK.
10BASE-T1L Local Receiver Status OK. When read as 1, this bit indicates that
the local receiver status is OK.
BASE-T1L Descrambler Status OK Latch Low. When read as 1, this bit indicates
that the descrambler status is OK.
10BASE-T1L Descrambler Status OK. When read as 1, this bit indicates that the
descrambler status is OK.
Reserved.
Link Status OK Latch Low. When read as 1, this bit indicates that the link status
is OK.
Link Status OK. When read as 1, this bit indicates that the link status is OK.
0x0
R
MSE Value Register
Device Address: 0x01; Register Address: 0x830B, Reset: 0x0000, Name: MSE_VAL
Table 135. Bit Descriptions for MSE_VAL
Bits
Bit Name
Description
Reset
Access
[15:0]
MSE_VAL
MSE Value. Note that the LSB weight is 2−18. When computing a signal-to-noise ratio (SNR) value, the mean
10BASE-T1L idle symbol power is 0.64422.
0x0
R
PCS Control 1 Register
Device Address: 0x03; Register Address: 0x0000, Reset: 0x0000, Name: PCS_CNTRL1
This address corresponds to the PCS Control Register 1 specified in Clause 45.2.3.1 of Standard 802.3.
Table 136. Bit Descriptions for PCS_CNTRL1
Bits
Bit Name
Description
Reset
Access
15
14
PCS_SFT_RST
LB_PCS_EN
0x0
0x0
R/W SC
R/W
[13:12]
11
[10:0]
RESERVED
PCS_SFT_PD
RESERVED
PCS Software Reset. Mirrors PMA_SFT_RST.
PCS Loopback Enable. When this bit is set to 1, the PCS accepts data on the transmit path and returns it
on the receive path. When this bit is set to 0, the PCS works in normal mode.
Reserved.
PCS Software Power-Down. Mirrors PMA_SFT_PD
Reserved.
0x0
0x0
0x0
R
R/W
R
PCS Status 1 Register
Device Address: 0x03; Register Address: 0x0001, Reset: 0x0002, Name: PCS_STAT1
Table 137. Bit Descriptions for PCS_STAT1
Bits
Bit Name
Description
Reset
Access
[15:2]
1
0
RESERVED
PCS_SFT_PD_ABLE
RESERVED
Reserved.
PCS Software Power-Down Able. Indicates that the PCS supports software power-down.
Reserved.
0x0
0x1
0x0
R
R
R
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PCS MMD Devices in Package 1 Register
Device Address: 0x03; Register Address: 0x0005, Reset: 0x008B, Name: PCS_DEVS_IN_PKG1
Table 138. Bit Descriptions for PCS_DEVS_IN_PKG1
Bits
Bit Name
Description
Reset
Access
[15:0]
PCS_DEVS_IN_PKG1
PCS MMD Devices in Package. Clause 22 registers and PMA/PMD, PCS, and autonegotiation
MMDs are present.
0x8B
R
PCS MMD Devices in Package 2 Register
Device Address: 0x03; Register Address: 0x0006, Reset: 0xC000, Name: PCS_DEVS_IN_PKG2
Vendor Specific Device 1 and Vendor Specific Device 2 MMDs are present.
Table 139. Bit Descriptions for PCS_DEVS_IN_PKG2
Bits
Bit Name
Description
Reset
[15:0]
PCS_DEVS_IN_PKG2
PCS MMD Devices in Package. Vendor Specific Device 1 and Vendor Specific Device 2 MMDs 0xC000
present
Access
R
PCS Status 2 Register
Device Address: 0x03; Register Address: 0x0008, Reset: 0x8000, Name: PCS_STAT2
Table 140. Bit Descriptions for PCS_STAT2
Bits
Bit Name
Description
Reset
Access
[15:14]
[13:0]
PCS_PRESENT
RESERVED
PCS Present. Indicates that the PCS is present and responding.
Reserved.
0x2
0x0
R
R
10BASE-T1L PCS Control Register
Device Address: 0x03; Register Address: 0x08E6, Reset: 0x0000, Name: B10L_PCS_CNTRL
This address corresponds to the 10BASE-T1L PCS control register specified in Clause 45.2.3.68a of Standard 802.3cg.
Table 141. Bit Descriptions for B10L_PCS_CNTRL
Bits
Bit Name
Description
Reset
Access
15
14
[13:0]
RESERVED
B10L_LB_PCS_EN
RESERVED
Reserved.
PCS Loopback Enable. When set to 1, this bit enables the 10BASE-T1L PCS loopback.
Reserved.
0x0
0x0
0x0
R/W SC
R/W
R
10BASE-T1L PCS Status Register
Device Address: 0x03; Register Address: 0x08E7, Reset: 0x0000, Name: B10L_PCS_STAT
This address corresponds to the 10BASE-T1L PCS status register specified in Clause 45.2.3.68b of Standard 802.3cg.
Table 142. Bit Descriptions for B10L_PCS_STAT
Bits
Bit Name
Description
Reset
Access
[15:3]
2
RESERVED
B10L_PCS_DSCR_STAT_OK_LL
0x0
0x0
R
R LL
[1:0]
RESERVED
Reserved.
PCS Descrambler Status. When read as 1, this bit indicates that the 10BASE-T1L
descrambler is locked. When read as 0, this bit indicates that the 10BASE-T1L
descrambler has unlocked since the last time the bit was read.
Reserved.
0x0
R
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REGISTERS
Autonegotiation MMD Devices in Package 1 Register
Device Address: 0x07; Register Address: 0x0005, Reset: 0x008B, Name: AN_DEVS_IN_PKG1
Clause 22 registers and PMA/PMD, PCS, and autonegotiation MMDs are present.
Table 143. Bit Descriptions for AN_DEVS_IN_PKG1
Bits
Bit Name
Description
Reset
Access
[15:0]
AN_DEVS_IN_PKG1
Autonegotiation MMD Devices in Package. Clause 22 registers and PMA/PMD, PCS, and
autonegotiation MMDs are present.
0x8B
R
Autonegotiation MMD Devices in Package 2 Register
Device Address: 0x07; Register Address: 0x0006, Reset: 0xC000, Name: AN_DEVS_IN_PKG2
Vendor Specific Device 1 and Vendor Specific Device 2 MMDs are present.
Table 144. Bit Descriptions for AN_DEVS_IN_PKG2
Bits
Bit Name
Description
Reset
Access
[15:0]
AN_DEVS_IN_PKG2
Autonegotiation MMD Devices in Package. Vendor Specific Device 1 and Vendor Specific
Device 2 MMDs are present.
0xC000
R
BASE-T1 Autonegotiation Control Register
Device Address: 0x07; Register Address: 0x0200, Reset: 0x1000, Name: AN_CONTROL
This address corresponds to the BASE-T1 autonegotiation control register specified in Clause 45.2.7.19 of Standard 802.3.
Table 145. Bit Descriptions for AN_CONTROL
Bits
Bit Name
Description
Reset
Access
[15:13]
12
RESERVED
AN_EN
0x0
0x1
R/W SC
R/W
[11:10]
9
RESERVED
AN_RESTART
0x0
0x0
R
R/W SC
[8:0]
RESERVED
Reserved.
Autonegotiation Enable. When this bit is set to 1, the autonegotiation is enabled. Autonegotiation is
enabled by default and it is strongly recommended that it is always enabled.
Reserved.
Autonegotiation Restart. Setting this bit to 1 restarts the autonegotiation process. This bit is self clearing,
and it returns a value of one until the autonegotiation process is initiated.
Reserved.
0x0
R
BASE-T1 Autonegotiation Status Register
Device Address: 0x07; Register Address: 0x0201, Reset: 0x0008, Name: AN_STATUS
This address corresponds to the BASE-T1 autonegotiation status register specified in Clause 45.2.7.20 of Standard 802.3.
Table 146. Bit Descriptions for AN_STATUS
Bits
Bit Name
Description
Reset
Access
[15:7]
6
RESERVED
AN_PAGE_RX
0x0
0x0
R
R LH
5
AN_COMPLETE
Reserved.
Page Received. This bit is set to indicate that a new link codeword is received and stored in
the AN_LP_ADV_ABILITY register or the AN_LP_NEXT_PAGE register. The contents of the
AN_LP_ADV_ABILITY are valid when this bit is set the first time during autonegotiation. This bit
resets to 0 on a read of the AN_STATUS register.
Autonegotiation Complete. When this bit is read as 1, the autonegotiation process is complete,
the PHY link is up, and the contents of the AN_ADV_ABILITY_x and AN_LP_ADV_ABILITY_x
registers are valid. This bit returns 0 if the autonegotiation is disabled, clearing the AN_EN bit.
0x0
R
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Table 146. Bit Descriptions for AN_STATUS
Bits
Bit Name
Description
Reset
Access
4
3
AN_REMOTE_FAULT
AN_ABLE
0x0
0x1
R LH
R
2
AN_LINK_STATUS
0x0
R LL
[1:0]
RESERVED
Autonegotiation Remote Fault. Remote fault set in base page received from link partner.
Autonegotiation Ability. When this bit is read as 1, it indicates that the PHY is able to perform
autonegotiation.
Link Status. When read as 1, this bit indicates that a valid link is established. If this bit reads 0, it
means that the link has failed since the last time it was read.
Reserved.
0x0
R
BASE-T1 Autonegotiation Advertisement Register, Bits[15:0]
Device Address: 0x07; Register Address: 0x0202, Reset: 0x0001, Name: AN_ADV_ABILITY_L
This address corresponds to the BASE-T1 autonegotiation advertisement register, Bits[15:0] specified in Clause 45.2.7.21 of Standard 802.3.
Table 147. Bit Descriptions for AN_ADV_ABILITY_L
Bits
Bit Name
Description
Reset
Access
15
AN_ADV_NEXT_PAGE_REQ
0x0
R/W
14
AN_ADV_ACK
0x0
R
13
12
AN_ADV_REMOTE_FAULT
AN_ADV_FORCE_MS
0x0
0x0
R/W
R/W
[11:10]
AN_ADV_PAUSE
0x0
R/W
[9:5]
[4:0]
RESERVED
AN_ADV_SELECTOR
Next Page Request. This bit indicates to the link partner that the PHY wants to send a
next page. See IEEE Standard 802.3 subclause 98.2.1.2.9.
Acknowledge (ACK). This bit indicates that the device has received the link codeword
of its link partner. See IEEE Standard 802.3 Subclause 98.2.1.2.8.
Remote Fault. See IEEE Standard 802.3 Subclause 98.2.1.2.7.
Force Master/slave Configuration. This bit allows the PHY to force its master/slave
configuration. When this bit is set as 0, the master/slave configuration is a preferred
mode. (The configuration in AN_ADV_MST is a preferred configuration.) If this bit
is set to 1, the master/slave configuration is a forced mode. (The configuration
in AN_ADV_MST is a forced configuration.) See IEEE Standard 802.3 Subclause
98.2.1.2.5 for more details.
Pause Ability. This bit field advertises support for asymmetric and symmetric pause
functions on full duplex links. See IEEE Standard 802.3 Subclause 98.2.1.2.6 for
more details.
Reserved.
Selector. The value of this field is fixed at 5'b00001, which is the IEEE 802.3 selector
value. See IEEE Standard 802.3 Subclause 98.2.1.2.1.
0x0
0x1
R
R
BASE-T1 Autonegotiation Advertisement Register, Bits[31:16]
Device Address: 0x07; Register Address: 0x0203, Reset: 0x4000, Name: AN_ADV_ABILITY_M
This address corresponds to the BASE-T1 autonegotiation advertisement register, Bits[31:16], specified in Clause 45.2.7.21 of Standard 802.3.
Table 148. Bit Descriptions for AN_ADV_ABILITY_M
Bits
Bit Name
Description
Reset
Access
15
14
[13:5]
4
RESERVED
AN_ADV_B10L
RESERVED
AN_ADV_MST
0x0
0x1
0x0
Pin Dependent
R
R/W
R
R/W
[3:0]
RESERVED
Reserved.
10BASE-T1L Ability. This bit indicates that the device is compatible with 10BASE-T1L.
Reserved.
Master/slave Configuration. This bit advertises the master/slave configuration, as follows: 0:
slave, 1: master. See also the AN_ADV_FORCE_MS bit, which determines whether this bit
expresses a preference or a forced value. See IEEE Standard 802.3 Subclause 98.2.1.2.3
(master/slave configuration is Bit 4 of the transmitted nonce field).
Reserved.
0x0
R
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BASE-T1 Autonegotiation Advertisement Register, Bits[47:32]
Device Address: 0x07; Register Address: 0x0204, Reset: 0x0000, Name: AN_ADV_ABILITY_H
This address corresponds to the BASE-T1 autonegotiation advertisement register, Bits[47:32], specified in Clause 45.2.7.21 of Standard 802.3.
Table 149. Bit Descriptions for AN_ADV_ABILITY_H
Bits
Bit Name
Description
Reset
Access
[15:14]
13
RESERVED
AN_ADV_B10L_TX_LVL_HI_ABL
0x0
Pin dependent
R
R/W
12
AN_ADV_B10L_TX_LVL_HI_REQ
Pin dependent
R/W
[11:0]
RESERVED
Reserved.
10BASE-T1L High Level Transmit Operating Mode Ability. This
bit advertises that the PHY is capable of transmitting in the
high level (2.4 V p-p) transmit operating mode. This bit is used
with AN_ADV_B10L_TX_LVL_HI_REQ to configure the 10BASET1L transmission level (2.4 V p-p or 1.0 V p-p). See the
AN_ADV_B10L_TX_LVL_HI_REQ bit for more details.
10BASE-T1L High Level Transmit Operating Mode Request. This bit
advertises that the PHY is requesting that high level (2.4 V p-p)
transmit operating mode be used. The transmit level is resolved as
follows:
If either PHY is not capable of high level transmission (and has
AN_ADV_B10L_TX_LVL_HI_ABL = 0), both PHYs must use the low
voltage (1.0 V p-p) transmit operating mode.
Otherwise, if either PHY requests high level transmission (and has
AN_ADV_B10L_TX_LVL_HI_REQ = 1), both PHYs must use the high
voltage (2.4 V p-p) transmit operating mode. See IEEE P802.cg
Subclause 146.6.4 for more details.
Reserved.
0x0
R
BASE-T1 Autonegotiation Link Partner Base Page Ability Register, Bits[15:0]
Device Address: 0x07; Register Address: 0x0205, Reset: 0x0000, Name: AN_LP_ADV_ABILITY_L
This address corresponds to the link partner's BASE-T1 autonegotiation base page ability register, Bits[15:0], specified in Clause
45.2.7.22 of Standard 802.3. Note that the value of the AN_LP_ADV_ABILITY_M and AN_LP_ADV_ABILITY_H registers is latched when
AN_LP_ADV_ABILITY_L is read.
Table 150. Bit Descriptions for AN_LP_ADV_ABILITY_L
Bits
Bit Name
Description
Reset
Access
15
AN_LP_ADV_NEXT_PAGE_REQ
0x0
R
14
AN_LP_ADV_ACK
0x0
R
13
12
AN_LP_ADV_REMOTE_FAULT
AN_LP_ADV_FORCE_MS
0x0
0x0
R
R
[11:10]
AN_LP_ADV_PAUSE
0x0
R
[9:5]
[4:0]
RESERVED
AN_LP_ADV_SELECTOR
Link Partner Next Page Request. This bit indicates that the link partner PHY
wants to send a next page. See IEEE Standard 802.3 Subclause 98.2.1.2.9.
Link Partner Acknowledge (ACK). This bit indicates that the device has received
the link codeword of its link partner. See IEEE Standard 802.3 Subclause
98.2.1.2.8.
Link Partner Remote Fault. See IEEE Standard 802.3 Subclause 98.2.1.2.7.
Link Partner Force Master/Slave Configuration. This bit reports the forced
master/slave configuration of the link partner, with values as follows. See IEEE
Standard 802.3 Subclause 98.2.1.2.5 for more details.
0: preferred mode (AN_LP_ADV_MST is a preferred configuration).
1: forced mode (AN_LP_ADV_MST is a forced configuration).
Link Partner Pause Ability. This bit field reports the support of the link partner
for asymmetric and symmetric pause functions on full duplex links. See IEEE
Standard 802.3 Subclause 98.2.1.2.6 for more details.
Reserved.
Link Partner Selector. The value of this field reads 00001, which is the IEEE
802.3 selector value. See IEEE Standard 802.3 Subclause 98.2.1.2.1.
0x0
0x0
R
R
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BASE-T1 Autonegotiation Link Partner Base Page Ability Register, Bits[31:16]
Device Address: 0x07; Register Address: 0x0206, Reset: 0x0000, Name: AN_LP_ADV_ABILITY_M
This address corresponds to the link partner's BASE-T1 autonegotiation base page ability register, Bits[31:16], specified in Clause 45.2.7.22 of
Standard 802.3. Note that the value of this register is latched when the AN_LP_ADV_ABILITY_L register is read. Reading this register returns
the latched value rather than the current value.
Table 151. Bit Descriptions for AN_LP_ADV_ABILITY_M
Bits
Bit Name
Description
Reset
Access
15
14
[13:8]
7
RESERVED
AN_LP_ADV_B10L
RESERVED
AN_LP_ADV_B1000
0x0
0x0
0x0
0x0
R
R
R
R
6
AN_LP_ADV_B10S_FD
0x0
R
5
4
AN_LP_ADV_B100
AN_LP_ADV_MST
0x0
0x0
R
R
[3:0]
RESERVED
Reserved.
Link Partner 10BASE-T1L Ability. This bit indicates if the link partner has 10BASE-T1L ability.
Reserved.
Link Partner 1000BASE-T1 Ability. This bit indicates if the link partner has 1000BASE-T1
ability.
Link Partner 10BASE-T1S Full Duplex Ability. This bit indicates if the link partner has 10BASET1S ability.
Link Partner 100BASE-T1 Ability. This bit indicates if the link partner has 100BASE-T1 ability.
Link Partner Master/Slave Configuration. This bit reports the master/slave configuration of the
link partner, as follows: 0: slave, 1: master. See also the AN_LP_ADV_FORCE_MS bit, which
determines whether this bit expresses a preference or a forced value. See IEEE Standard
802.3 Subclause 98.2.1.2.3 (master/slave configuration is Bit 4 of the transmitted nonce field).
Reserved.
0x0
R
BASE-T1 Autonegotiation Link Partner Base Page Ability Register, Bits[47:32]
Device Address: 0x07; Register Address: 0x0207, Reset: 0x0000, Name: AN_LP_ADV_ABILITY_H
This address corresponds to the link partner's BASE-T1 autonegotiation base page ability register, Bits[47:32], specified in Clause 45.2.7.22 of
Standard 802.3. Note that the value of this register is latched when the AN_LP_ADV_ABILITY_L register is read. Reading this register returns
the latched value rather than the current value.
Table 152. Bit Descriptions for AN_LP_ADV_ABILITY_H
Bits
Bit Name
Description
Reset
Access
15
14
RESERVED
AN_LP_ADV_B10L_EEE
0x0
0x0
R
R
13
AN_LP_ADV_B10L_TX_LVL_HI_ABL
0x0
R
12
AN_LP_ADV_B10L_TX_LVL_HI_REQ
0x0
R
11
AN_LP_ADV_B10S_HD
0x0
R
[10:0]
RESERVED
Reserved.
Link Partner 10BASE-T1L EEE Ability. This bit reports if the link partner is
capable of using 10BASE-T1L energy efficient Ethernet.
Link Partner 10BASE-T1L High Level Transmit Operating Mode Ability.
This bit reports whether the link partner is capable of transmitting
in the high level (2.4 V p-p) transmit operating mode. This bit
is used with AN_LP_ADV_B10L_TX_LVL_HI_REQ to configure the
10BASE-T1L transmission level (2.4 V p-p or 1.0 V p-p); see the
AN_ADV_B10L_TX_LVL_HI_REQ bit for more details.
Link Partner 10BASE-T1L High Level Transmit Operating Mode Request.
This bit reports whether the link partner is requesting that the
high level (2.4 V p-p) transmit operating mode be used. See the
AN_ADV_B10L_TX_LVL_HI_REQ bit for more details.
Link Partner 10BASE-T1S Half-Duplex Ability. This bit reports if the link
partner is capable of using 10BASE-T1S half duplex.
Reserved.
0x0
R
BASE-T1 Autonegotiation Next Page Transmit Register, Bits[15:0]
Device Address: 0x07; Register Address: 0x0208, Reset: 0x2001, Name: AN_NEXT_PAGE_L
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This address corresponds to the BASE-T1 autonegotiation next page transmit register, Bits[15:0], specified in Clause 45.2.7.23 of Standard
802.3. On power-up or autonegotiation reset, this register contains the default value, which represents a message page with the message code
set to null. Write AN_NEXT_PAGE_M and AN_NEXT_PAGE_H before AN_NEXT_PAGE_L.
Table 153. Bit Descriptions for AN_NEXT_PAGE_L
Bits
Bit Name
Description
Reset
Access
15
AN_NP_NEXT_PAGE_REQ
0x0
R/W
14
13
AN_NP_ACK
AN_NP_MESSAGE_PAGE
0x0
0x1
R
R/W
12
AN_NP_ACK2
0x0
R/W
11
AN_NP_TOGGLE
0x0
R
[10:0]
AN_NP_MESSAGE_CODE
Next Page Request. This bit indicates to the link partner that the PHY wants to send a
next page. See IEEE Standard 802.3 Subclause 98.2.1.2.9.
Next Page Acknowledge. See IEEE Standard 802.3 Subclause 98.2.1.2.8.
Next Page Encoding. Indicates encoding of next page, as follows:
0: unformatted next page.
1: message next page.
Acknowledge 2. Indicates whether the PHY can comply with the message. See IEEE
Standard 802.3 Subclause 28.2.3.4.6.
Toggle Bit. The Toggle bit is used to synchronize pages between the PHYS. This is
always read as 0 (the toggle bit is set automatically by the arbitration state machine).
Message/unformatted Code Field. For a message page (AN_NP_MESSAGE_PAGE = 1),
the valid values are defined in IEEE Standard 802.3.
1: null message.
5: organizationally unique identifier tagged message.
6: autonegotiation device identifier tag code.
0x1
R/W
BASE-T1 Autonegotiation Next Page Transmit Register, Bits[31:16]
Device Address: 0x07; Register Address: 0x0209, Reset: 0x0000, Name: AN_NEXT_PAGE_M
This address corresponds to the BASE-T1 autonegotiation next page transmit register, Bits[31:16], specified in Clause 45.2.7.23 of Standard
802.3. On power-up or autonegotiation reset, this register contains the default value, which represents a message page with the message code
set to null. Write AN_NEXT_PAGE_M and AN_NEXT_PAGE_H before AN_NEXT_PAGE_L.
Table 154. Bit Descriptions for AN_NEXT_PAGE_M
Bits
Bit Name
Description
Reset
Access
[15:0]
AN_NP_UNFORMATTED1
Unformatted Code Field 1.
0x0
R/W
BASE-T1 Autonegotiation Next Page Transmit Register, Bits[47:32]
Device Address: 0x07; Register Address: 0x020A, Reset: 0x0000, Name: AN_NEXT_PAGE_H
This address corresponds to the BASE-T1 autonegotiation next page transmit register, Bits[47:42], specified in Clause 45.2.7.23 of Standard
802.3. On power-up or autonegotiation reset, this register contains the default value, which represents a message page with the message code
set to null. Write AN_NEXT_PAGE_M and AN_NEXT_PAGE_H before AN_NEXT_PAGE_L.
Table 155. Bit Descriptions for AN_NEXT_PAGE_H
Bits
Bit Name
Description
Reset
Access
[15:0]
AN_NP_UNFORMATTED2
Unformatted Code Field 2.
0x0
R/W
BASE-T1 Autonegotiation Link Partner Next Page Ability Register, Bits[15:0]
Device Address: 0x07; Register Address: 0x020B, Reset: 0x0000, Name: AN_LP_NEXT_PAGE_L
This address corresponds to the BASE-T1 autonegotiation link partner's next page ability register, Bits[15:0], specified in Clause 45.2.7.24 of
Standard 802.3. The values of AN_LP_NEXT_PAGE_M and AN_LP_NEXT_PAGE_H are latched when this register is read.
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Table 156. Bit Descriptions for AN_LP_NEXT_PAGE_L
Bits
Bit Name
Description
Reset
Access
15
AN_LP_NP_NEXT_PAGE_REQ
0x0
R
14
AN_LP_NP_ACK
0x0
R
13
AN_LP_NP_MESSAGE_PAGE
0x0
R
12
11
[10:0]
AN_LP_NP_ACK2
AN_LP_NP_TOGGLE
AN_LP_NP_MESSAGE_CODE
Next Page Request. This bit indicates to the link partner that the PHY wants to send
a next page. See IEEE Standard 802.3 Subclause 98.2.1.2.9.
Link Partner Next Page Acknowledge. See IEEE Standard 802.3 Subclause
98.2.1.2.8.
Link Partner Next Page Encoding. Indicates encoding of link partner next page, as
follows:
0: unformatted next page.
1: message next page.
Link Partner Acknowledge 2. See AN_NP_ACK2 for more details.
Link Partner Toggle Bit. Link partner Toggle bit.
Link Partner Message/Unformatted Code Field. See AN_NP_MESSAGE_PAGE for
more details.
1: null message.
5: organizationally unique identifier tagged message.
6: autonegotiation device identifier tag code.
0x0
0x0
0x0
R
R
R
BASE-T1 Autonegotiation Link Partner Next Page Ability Register, Bits[31:16]
Device Address: 0x07; Register Address: 0x020C, Reset: 0x0000, Name: AN_LP_NEXT_PAGE_M
This address corresponds to the BASE-T1 autonegotiation next page ability register, Bits[31:16], of the link partner specified in Clause
45.2.7.24 of Standard 802.3. The values of this register are latched when AN_LP_NEXT_PAGE_L is read. Reading this register returns the
latched value rather than the current value.
Table 157. Bit Descriptions for AN_LP_NEXT_PAGE_M
Bits
Bit Name
Description
Reset
Access
[15:0]
AN_LP_NP_UNFORMATTED1
Link Partner Unformatted Code Field 1.
0x0
R
BASE-T1 Autonegotiation Link Partner Next Page Ability Register, Bits[47:32]
Device Address: 0x07; Register Address: 0x020D, Reset: 0x0000, Name: AN_LP_NEXT_PAGE_H
This address corresponds to the BASE-T1 autonegotiation link partner's next page ability register, Bits[47:32], specified in Clause 45.2.7.24 of
Standard 802.3. The values of this register are latched when AN_LP_NEXT_PAGE_L is read. Reading this register returns the latched value
rather than the current value.
Table 158. Bit Descriptions for AN_LP_NEXT_PAGE_H
Bits
Bit Name
Description
Reset
Access
[15:0]
AN_LP_NP_UNFORMATTED2
Link Partner Unformatted Code Field 2.
0x0
R
10BASE-T1 Autonegotiation Control Register
Device Address: 0x07; Register Address: 0x020E, Reset: 0x8000, Name: AN_B10_ADV_ABILITY
This address corresponds to the 10BASE-T1 autonegotiation control register specified in Clause 45.2.7.25 of Standard 802.3cg.
Table 159. Bit Descriptions for AN_B10_ADV_ABILITY
Bits
Bit Name
Description
Reset
Access
15
AN_B10_ADV_B10L
10BASE-T1L Ability. This is a duplicate of the AN_ADV_B10L
register.
0x1
R/W
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Table 159. Bit Descriptions for AN_B10_ADV_ABILITY
Bits
Bit Name
Description
Reset
Access
14
AN_B10_ADV_B10L_EEE
0x0
R
13
AN_B10_ADV_B10L_TX_LVL_HI_ABL
Pin Dependent
R/W
12
AN_B10_ADV_B10L_TX_LVL_HI_REQ
Pin Dependent
R/W
[11:0]
RESERVED
10BASE-T1L EEE Ability. This is a duplicate of the
AN_ADV_B10L_EEE register.
10BASE-T1L High Level Transmit Operating Mode Ability. This is
a duplicate of the AN_ADV_B10L_TX_LVL_HI_ABL register.
10BASE-T1L High Level Transmit Operating Mode Request. This
is a duplicate of the AN_ADV_B10L_TX_LVL_HI_REQ register.
Reserved.
0x0
R
10BASE-T1 Autonegotiation Status Register
Device Address: 0x07; Register Address: 0x020F, Reset: 0x0000, Name: AN_B10_LP_ADV_ABILITY
This address corresponds to the 10BASE-T1 autonegotiation status register specified in Clause 45.2.7.26 of Standard 802.3cg.
Table 160. Bit Descriptions for AN_B10_LP_ADV_ABILITY
Bits
Bit Name
Description
Reset
Access
15
AN_B10_LP_ADV_B10L
0x0
R
14
AN_B10_LP_ADV_B10L_EEE
0x0
R
13
AN_B10_LP_ADV_B10L_TX_LVL_HI_ABL
0x0
R
12
AN_B10_LP_ADV_B10L_TX_LVL_HI_REQ
0x0
R
[11:8]
7
RESERVED
AN_B10_LP_ADV_B10S_FD
0x0
0x0
R
R
6
AN_B10_LP_ADV_B10S_HD
0x0
R
[5:0]
RESERVED
10BASE-T1L Ability. This is a duplicate of the AN_LP_ADV_B10L
register.
10BASE-T1L EEE Ability. This is a duplicate of the
AN_LP_ADV_B10L_EEE register.
10BASE-T1L High Level Transmit Operating Mode Ability. This is a
duplicate of the AN_LP_ADV_B10L_TX_LVL_HI_ABL register.
10BASE-T1L High Level Transmit Operating Mode Request. This is
a duplicate of the AN_LP_ADV_B10L_TX_LVL_HI_REQ register.
Reserved.
Link Partner 10BASE-T1S Full Duplex Ability. This is a duplicate of
the AN_LP_ADV_B10S_FD register.
Link Partner 10BASE-T1S Half-Duplex Ability. This is a duplicate of
the AN_LP_ADV_B10S_HD register.
Reserved.
0x0
R
Autonegotiation Force Mode Enable Register
Device Address: 0x07; Register Address: 0x8000, Reset: 0x0000, Name: AN_FRC_MODE_EN
Note that the effect of this register is superseded by the AN_EN bit, which enables the autonegotiation process. If autonegotiation is disabled
(AN_EN = 0) and AN_FRC_MODE_EN is 1, forced mode is enabled.
Table 161. Bit Descriptions for AN_FRC_MODE_EN
Bits
Bit Name
Description
Reset
Access
[15:1]
0
RESERVED
AN_FRC_MODE_EN
Reserved.
Autonegotiation Forced Mode. Enables forced mode functionality.
0x0
0x0
R
R/W
Extra Autonegotiation Status Register
Device Address: 0x07; Register Address: 0x8001, Reset: 0x0000, Name: AN_STATUS_EXTRA
This register is provided in addition to AN_STATUS.
Table 162. Bit Descriptions for AN_STATUS_EXTRA
Bits
Bit Name
Description
Reset
Access
[15:11]
RESERVED
Reserved.
0x0
R
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Table 162. Bit Descriptions for AN_STATUS_EXTRA
Bits
Bit Name
Description
Reset
Access
10
9
AN_LP_NP_RX
AN_INC_LINK
0x0
0x0
R LH
R
[8:7]
AN_TX_LVL_RSLTN
0x0
R
[6:5]
AN_MS_CONFIG_RSLTN
0x0
R
[4:1]
AN_HCD_TECH
0x0
R
0
AN_LINK_GOOD
Next Page Request Received from Link Partner.
Incompatible Link Indication. This corresponds to the incompatible link state of IEEE
Standard 802.3 Subclause 98.5.1. Its value is set by the priority resolution function run on
entering the autonegotiation good check state.
Autonegotiation Tx Level Result. Transmit level high/low resolution result, determined as
per IEEE Standard 802.3cg Subclause 146.6.4. This is encoded as follows:
0: not run.
2: success, low transmit levels (1.0 V p-p) selected.
3: success, high transmit levels (2.4 V p-p) selected.
Master/Slave Resolution Result. Determined as per master/slave configuration of IEEE
Standard 802.3. This is encoded as follows:
0: not run.
1: configuration fault.
2: success, PHY is configured as slave.
3: success, PHY is configured as master.
Highest Common Denominator (HCD) PHY Technology. As selected by the priority
resolution function of IEEE Standard 802.3 Subclause 98.2.4.2. Consider all values that
are not shown to be reserved.
0: null (not run).
1: 10BASE-T1L.
Autonegotiation Complete Indication. This corresponds to the an_link_good state of IEEE
Standard 802.3 Subclause 98.5.1. This signal indicates completion of the autonegotiation
transmission, and that the enabled PHY technology is either bringing up its link or that it
has brought up its link. See also AN_COMPLETE, which is similar, but also indicates that
the PHY link is up.
0x0
R
PHY Instantaneous Status Register
Device Address: 0x07; Register Address: 0x8030, Reset: 0x0010, Name: AN_PHY_INST_STATUS
This register address provides access to instantaneous status indications. These values are not latched, and the set of indications returned
here are a consistent set, that is, a set of values in effect at the time the register address is read.
Table 163. Bit Descriptions for AN_PHY_INST_STATUS
Bits
Bit Name
Description
Reset
Access
[15:5]
4
RESERVED
IS_AN_TX_EN
0x0
0x1
R
R
3
IS_CFG_MST
0x0
R
2
IS_CFG_SLV
0x0
R
1
IS_TX_LVL_HI
0x0
R
0
IS_TX_LVL_LO
Reserved.
Autonegotiation Tx Enable Status. Autonegotiation transmit enable. This bit indicates that the
autonegotiation is active and controlling the transmitter, and arbitration has not yet reached the
autonegotiation (AN) good check state or the AN good state. That is, the link_control signals have not been
set to enable.
Master Status. If link_control = enable (for example, B10L_LINK_CTRL_EN = 1), this indicates whether the
PHY is operating as master (and not slave).
Slave Status. If link_control = enable (for example, B10L_LINK_CTRL_EN = 1), this indicates whether the
PHY is operating as slave (and not master).
Tx Level High Status. Indicates that the PHY is operating with high transmit levels (2.4 V), and not low
transmit levels (1.0 V).
Tx Level Low Status. Indicates that the PHY is operating with low transmit levels (1.0 V), and not low
transmit levels (2.4 V).
0x0
R
Vendor Specific MMD 1 Device Identifier High Register
Device Address: 0x1E; Register Address: 0x0002, Reset: 0x0283, Name: MMD1_DEV_ID1
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This address corresponds to the Vendor Specific MMD 1 device identifier register specified in Clause 45.2.11.1 of Standard 802.3 and allows 16
bits of the organizationally unique identifier (OUI) to be observed.
Table 164. Bit Descriptions for MMD1_DEV_ID1
Bits
Bit Name
Description
Reset
Access
[15:0]
MMD1_DEV_ID1
Organizationally Unique Identifier. Bits[3:18]
0x283
R
Vendor Specific MMD 1 Device Identifier Low Register
Device Address: 0x1E; Register Address: 0x0003, Reset: 0xBC91, Name: MMD1_DEV_ID2
This address corresponds to the Vendor Specific MMD 1 device identifier register specified in Clause 45.2.11.1 of Standard 802.3 and allows
six bits of the OUI along with the model number and revision number to be observed.
Table 165. Bit Descriptions for MMD1_DEV_ID2
Bits
Bit Name
Description
Reset
Access
[15:10]
[9:4]
[3:0]
MMD1_DEV_ID2_OUI
MMD1_MODEL_NUM
MMD1_REV_NUM
Organizationally Unique Identifier. Bits[19:24]
Model Number.
Revision Number.
0x2F
0x9
0x1
R
R
R
Vendor Specific 1 MMD Devices in Package Register
Device Address: 0x1E; Register Address: 0x0005, Reset: 0x008B, Name: MMD1_DEVS_IN_PKG1
Clause 22 registers and PMA/PMD, PCS, and autonegotiation MMDs are present.
Table 166. Bit Descriptions for MMD1_DEVS_IN_PKG1
Bits
Bit Name
Description
Reset
Access
[15:0]
MMD1_DEVS_IN_PKG1
Vendor Specific 1 MMD Devices in Package. Clause 22 registers and PMA/PMD, PCS, and
autonegotiation MMDs are present.
0x8B
R
Device Address: 0x1E; Register Address: 0x0006, Reset: 0xC000, Name: MMD1_DEVS_IN_PKG2
Vendor-specific device 1 and Vendor-specific device 2 MMDs present
Table 167. Bit Descriptions for MMD1_DEVS_IN_PKG2
Bits
Bit Name
Description
Reset
Access
[15:0]
MMD1_DEVS_IN_PKG2
Vendor Specific 1 MMD Devices in Package. Vendor Specific Device 1 and Vendor
Specific Device 2 MMDs are present.
0xC000
R
Vendor Specific MMD 1 Status Register
Device Address: 0x1E; Register Address: 0x0008, Reset: 0x8000, Name: MMD1_STATUS
This address corresponds to the Vendor Specific MMD 1 status register specified in Clause 45.2.11.2 of Standard 802.3.
Table 168. Bit Descriptions for MMD1_STATUS
Bits
Bit Name
Description
Reset
Access
[15:14]
MMD1_STATUS
0x2
R
[13:0]
RESERVED
Vendor Specific 1 MMD Status.
10: device responding at this address.
11: no device responding at this address.
01: no device responding at this address.
00: no device responding at this address.
Reserved.
0x0
R
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System Interrupt Status Register
Device Address: 0x1E; Register Address: 0x0010, Reset: 0x1000, Name: CRSM_IRQ_STATUS
This address can be used to check which interrupt requests have triggered since the last time it was read. Each bit goes high when the
associated event occurs and then latches high until it is unlatched by reading. The bits of CRSM_IRQ_STATUS go high even when the
associated interrupts are not enabled. A reserved interrupt being triggered indicates a fatal error in the system.
Table 169. Bit Descriptions for CRSM_IRQ_STATUS
Bits
Bit Name
Description
Reset
Access
15
[14:13]
12
[11:0]
CRSM_SW_IRQ_LH
RESERVED
CRSM_HRD_RST_IRQ_LH
RESERVED
Software Requested Interrupt Event.
Reserved.
Hardware Reset Interrupt.
Reserved.
0x0
0x0
0x1
0x0
R LH
R
R LH
R LH
System Interrupt Mask Register
Device Address: 0x1E; Register Address: 0x0020, Reset: 0x1FFE, Name: CRSM_IRQ_MASK
Controls whether or not the interrupt signal is asserted in response to various events.
Table 170. Bit Descriptions for CRSM_IRQ_MASK
Bits
Bit Name
Description
Reset
Access
15
CRSM_SW_IRQ_REQ
0x0
R/W SC
[14:13]
12
RESERVED
CRSM_HRD_RST_IRQ_EN
0x0
0x1
R
R/W
[11:0]
RESERVED
Software Interrupt Request. Software can set this bit to generate an interrupt for system
level testing. This bit always reads as 0 as it is self clearing.
Reserved.
Enable Hardware Reset Interrupt. Note that writing a 0 to this register does not mask
the interrupt since this register is initialized when a hardware reset occurs.
Reserved.
0xFFE
R/W
Reset
Access
Software Reset Register
Device Address: 0x1E; Register Address: 0x8810, Reset: 0x0000, Name: CRSM_SFT_RST
Table 171. Bit Descriptions for CRSM_SFT_RST
Bits
Bit Name
Description
[15:1]
0
RESERVED
CRSM_SFT_RST
Reserved.
0x0
Software Reset Register. The software reset bit allows the chip to be reset. When this bit is set, the chip 0x0
fully initializes, almost equivalent to a hardware reset.
R
R/W SC
Software Power-Down Control Register
Device Address: 0x1E; Register Address: 0x8812, Reset: 0x0000, Name: CRSM_SFT_PD_CNTRL
Table 172. Bit Descriptions for CRSM_SFT_PD_CNTRL
Bits
Bit Name
Description
Reset
Access
[15:1]
0
RESERVED
CRSM_SFT_PD
Reserved.
Software Power-Down. The software power-down register puts the chip in a lower power mode.
In this mode, most of the circuitry is switched off. However, MDIO access to all registers is still
possible. The default value for this register is configurable via the SWPD_EN pin, which allows
the chip to be held in power-down mode until an appropriate software initialization is performed.
0x0
Pin dependent
R
R/W
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PHY Subsystem Reset Register
Device Address: 0x1E; Register Address: 0x8814, Reset: 0x0000, Name: CRSM_PHY_SUBSYS_RST
Table 173. Bit Descriptions for CRSM_PHY_SUBSYS_RST
Bits
Bit Name
Description
Reset
Access
[15:1]
0
RESERVED
CRSM_PHY_SUBSYS_RST
Reserved.
PHY Subsystem Reset. The PHY subsystem reset register allows a managed subsystem
reset to be initiated. When the PHY subsystem is reset, normal operation resumes, and
the bit is self cleared.
0x0
0x0
R
R/W SC
PHY MAC Interface Reset Register
Device Address: 0x1E; Register Address: 0x8815, Reset: 0x0000, Name: CRSM_MAC_IF_RST
Table 174. Bit Descriptions for CRSM_MAC_IF_RST
Bits
Bit Name
Description
Reset
Access
[15:1]
0
RESERVED
CRSM_MAC_IF_RST
Reserved.
PHY MAC Interface Reset. The PHY MAC interface reset register allows a managed PHY MAC
interface reset to be initiated. When the PHY MAC interface is reset, normal operation resumes,
and the bit is self cleared.
0x0
0x0
R
R/W SC
System Status Register
Device Address: 0x1E; Register Address: 0x8818, Reset: 0x0000, Name: CRSM_STAT
Table 175. Bit Descriptions for CRSM_STAT
Bits
Bit Name
Description
Reset
Access
[15:2]
1
RESERVED
CRSM_SFT_PD_RDY
0x0
0x0
R
R
0
CRSM_SYS_RDY
Reserved.
Software Power-Down Status. This bit indicates that the system is in the software power-down
state.
System Ready. This bit indicates that the start-up sequence is complete and the system is ready
for normal operation.
0x0
R
CRSM Power Management Control Register
Device Address: 0x1E; Register Address: 0x8819, Reset: 0x0000, Name: CRSM_PMG_CNTRL
Table 176. Bit Descriptions for CRSM_PMG_CNTRL
Bits
Bit Name
Description
Reset
Access
[15:1]
0
RESERVED
CRSM_FRC_OSC_EN
Reserved.
Force Digital Boot Oscillator Clock Enable.
0x0
0x0
R
R/W
CRSM Diagnostics Clock Control Register
Device Address: 0x1E; Register Address: 0x882C, Reset: 0x0002, Name: CRSM_DIAG_CLK_CTRL
CRSM diagnostics clock control.
Table 177. Bit Descriptions for CRSM_DIAG_CLK_CTRL
Bits
Bit Name
Description
Reset
Access
[15:1]
0
RESERVED
CRSM_DIAG_CLK_EN
Reserved.
Enable the Diagnostics Clock.
0x1
0x0
R
R/W
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Package Configuration Values Register
Device Address: 0x1E; Register Address: 0x8C22, Reset: 0x0000, Name: MGMT_PRT_PKG
The MGMT_CFG_VAL address allows reading of the package configuration values.
Table 178. Bit Descriptions for MGMT_PRT_PKG
Bits
Bit Name
Description
Reset
Access
[15:6]
[5:0]
RESERVED
MGMT_PRT_PKG_VAL
Reserved.
Package Type. 0 = 40-lead LFCSP.
0x0
0x0
R
R
MDIO Control Register
Device Address: 0x1E; Register Address: 0x8C30, Reset: 0x0000, Name: MGMT_MDIO_CNTRL
Table 179. Bit Descriptions for MGMT_MDIO_CNTRL
Bits
Bit Name
Description
Reset
Access
[15:1]
0
RESERVED
MGMT_GRP_MDIO_EN
Reserved.
Enable MDIO PHY/Port Group Address Mode. In this mode, the PHY responds to any
write or address operation to the 5-bit PHY/Port Address 31 (decimal) regardless of its
own PHY/port address. This feature is only intended for initialization sequences in multiport
applications, must only be set in those cases, and cleared immediately after the initialization
is complete.
0x0
0x0
R
R/W
Pin Mux Configuration 1 Register
Device Address: 0x1E; Register Address: 0x8C56, Reset: 0x00FE, Name: DIGIO_PINMUX
Table 180. Bit Descriptions for DIGIO_PINMUX
Bits
Bit Name
Description
Reset
Access
[15:8]
[7:6]
RESERVED
DIGIO_TSTIMER_PINMUX
0x0
0x3
R
R/W
[5:4]
DIGIO_TSCAPT_PINMUX
0x3
R/W
[3:1]
DIGIO_LED1_PINMUX
0x7
R/W
0
DIGIO_LINK_ST_POLARITY
Reserved.
Pin Mux Select for TS_TIMER.
00: RXD_1.
01: LED_0.
10: INT.
11: TS_TIMER not assigned.
Pin Mux Select for TS_CAPT.
00: TXD_1.
01: LED_1.
10: MDIO.
Others: TS_CAPT not assigned.
Pin Mux Select for LED_1.
000: LED_1.
001: TX_ER.
010: TX_EN.
011: TX_CLK.
100: TXD_0.
101: TXD_2.
110: LINK_ST.
111: LED_1 output not enabled.
LINK_ST Polarity.
0x0
R/W
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Table 180. Bit Descriptions for DIGIO_PINMUX
Bits
Bit Name
Description
Reset
Access
0: assert high.
1: assert low.
LED_0 On/Off Blink Time Register
Device Address: 0x1E; Register Address: 0x8C80, Reset: 0x3636, Name: LED0_BLINK_TIME_CNTRL
LED on blink time = LED0_ON_N4MS × 4 ms.
LED off blink time = LED0_OFF_N4MS × 4 ms.
If LEDx_MODE = 0 and LEDx_FUNCTION is set to blink, the LED activity starts with an LED off sequence, followed by an LED on sequence,
and then repeats.
If LEDx_MODE = 1 and LEDx_FUNCTION is set to blink, the LED activity starts with an LED on sequence, followed by an LED off sequence,
and then repeats.
If LEDx_OFF_N4MS = LEDx_ON_N4MS = 0, this is a special case whereby the internal activity signal as selected by LEDx_FUNCTION can be
monitored live.
If LEDx_FUNCTION is programmed to a combination of a link and activity signal, the LED is on while the link is up and with no activity. The
LED switches off for either loss of link or receipt of activity.
If LEDx_FUNCTION is programmed to an activity signal, the LED is off with no activity. The LED switches on upon receipt of activity.
Table 181. Bit Descriptions for LED0_BLINK_TIME_CNTRL
Bits
Bit Name
Description
Reset
Access
[15:8]
LED0_ON_N4MS
0x36
R/W
[7:0]
LED0_OFF_N4MS
LED_0 On Blink Time. LED_0 on blink time is calculated by 4 ms × LED0_ON_N4MS bit field.
Recommended value is greater than 3.
LED_0 Off Blink Time. LED_0 off blink time is calculated by 4 ms × LED0_OFF_N4MS bit field.
Recommended value is greater than 3.
0x36
R/W
LED 1 On/Off Blink Time Register
Device Address: 0x1E; Register Address: 0x8C81, Reset: 0x3636, Name: LED1_BLINK_TIME_CNTRL
LED on blink time = LED1_ON_N4MS × 4 ms.
LED off blink time = LED1_OFF_N4MS × 4 ms.
If LEDx_MODE = 0 and LEDx_FUNCTION is set to blink, the LED activity starts with an LED off sequence followed by an LED on sequence,
and then repeats.
If LEDx_MODE = 1 and LEDx_FUNCTION is set to blink, the LED activity starts with an LED on sequence, followed by an LED Off sequence,
and then repeats.
If LEDx_OFF_N4MS = LEDx_ON_N4MS = 0, this is a special case whereby the internal activity signal as selected by LEDx_FUNCTION can be
monitored live.
If LEDx_FUNCTION is programmed to a combination of a link and activity signal, the LED is on while the link is up and with no activity. The
LED switches off for either loss of link or receipt of activity.
If LEDx_FUNCTION is programmed to an activity signal, the LED is off with no activity. The LED switches on upon receipt of activity.
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Table 182. Bit Descriptions for LED1_BLINK_TIME_CNTRL
Bits
Bit Name
Description
Reset
Access
[15:8]
LED1_ON_N4MS
0x36
R/W
[7:0]
LED1_OFF_N4MS
LED_1 On Blink Time. LED_1 on blink time is calculated by 4 ms × LED1_ON_N4MS bit field.
Recommended value is greater than 3.
LED_1 Off Blink Time. LED_1 off blink time is calculated by 4 ms × LED1_OFF_N4MS bit field.
Recommended value is greater than 3.
0x36
R/W
LED Control Register
Device Address: 0x1E; Register Address: 0x8C82, Reset: 0x8480, Name: LED_CNTRL
LED control register.
Table 183. Bit Descriptions for LED_CNTRL
Bits
Bit Name
Description
Reset
Access
15
LED1_EN
0x1
R/W
14
LED1_LINK_ST_QUALIFY
0x0
R/W
13
LED1_MODE
0x0
R/W
[12:8]
LED1_FUNCTION
LED 1 Enable. A disabled LED is off. An enabled LED can be on or blinking depending on
LED1_FUNCTION selection and activity.
Qualify Certain LED 1 Options with Link Status.
0: TX_LEVEL_2P4, TX_LEVEL_1P0, master, slave not qualified by link_status.
1: TX_LEVEL_2P4, TX_LEVEL_1P0, master, slave are qualified by link_status.
LED 1 Mode Selection.
0: LED Mode 1. If there is activity, blink at the rate defined by MMR LED1_BLINK_TIME_CNTRL.
1: LED Mode 2. The LED blink frequency is set depending on the level of activity. The activity level is graded
in steps of 10%, and the frequency of the LED adjusts accordingly. A higher activity level means a longer off
duration and shorter on duration. The activity level is reevaluated after a window period that varies between
640 ms and 1.5 sec.
LED_1 Pin Function. Determines the source activity for the LED_1 pin. The CLK25_REF, TX_TCLK, and
CLK_120MHZ options are clock out features with the LED controller bypassed. The waveform transmitted
off chip is dependent on the selected clock source frequency.
The following LED1_FUNCTION settings are not qualified with link_status: LED1_FUNCTION =
on, off, blink, INCOMPATIBLE_LINK_CFG, AN_LINK_GOOD, AN_COMPLETE, LOC_RCVR_STATUS,
REM_RCVR_STATUS, CLK25_REF, TX_TCLK, and CLK_120MHz.
The TX_LEVEL_2P4, TX_LEVEL_1P0, master, and slave options are optionally qualified by link_status and
this is controlled via the LED1_LINK_ST_QUALIFY MMR.
The TX_LEVEL_2P4, TX_LEVEL_1P0, master, slave, MSTR_SLV_FAULT, AN_LINK_GOOD,
AN_COMPLETE, and TS_TIMER options are considered status indicators and the LED controller is not
used. If the programmed signal is high, the LED is static on and if the programmed signal is low, the LED is
static off.
0: LINKUP_TXRX_ACTIVITY.
1: LINKUP_TX_ACTIVITY.
2: LINKUP_RX_ACTIVITY.
3: LINKUP_ONLY.
4: TXRX_ACTIVITY.
5: TX_ACTIVITY.
6: RX_ACTIVITY.
7: LINKUP_RX_ER.
8: LINKUP_RX_TX_ER.
9: RX_ER.
10: RX_TX_ER.
11: TX_SOP.
12: RX_SOP.
13: on.
14: off.
0x4
R/W
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Table 183. Bit Descriptions for LED_CNTRL
Bits
Bit Name
7
LED0_EN
6
LED0_LINK_ST_QUALIFY
5
LED0_MODE
[4:0]
LED0_FUNCTION
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Description
15: blink.
16: TX_LEVEL_2P4.
17: TX_LEVEL_1P0.
18: master.
19: slave.
20: INCOMPATIBLE_LINK_CFG.
21: AN_LINK_GOOD.
22: AN_COMPLETE.
23: TS_TIMER.
24: LOC_RCVR_STATUS.
25: REM_RCVR_STATUS.
26: CLK25_REF.
27: TX_TCLK.
28: CLK_120MHZ.
LED 0 Enable. A disabled LED is off. An enabled LED can be on or blinking depending on
LED0_FUNCTION selection and activity
Qualify Certain LED 0 Options with link_status.
0: TX_LEVEL_2P4, TX_LEVEL_1P0, master, slave not qualified by link_status.
1: TX_LEVEL_2P4, TX_LEVEL_1P0, master, slave are qualified by link_status.
LED 0 Mode Selection.
0: LED Mode 1. If activity, blink at the rate defined by MMR LED0_BLINK_TIME_CNTRL.
1: LED Mode 2. The LED blink frequency is set depending on the level of activity. The activity level is graded
in steps of 10%, and the frequency of the LED adjusts accordingly. A higher activity level means a longer off
duration and shorter on duration. The activity level is reevaluated after a window period that varies between
640 ms and 1.5 sec.
LED_0 Pin Function. Determines the source activity for the LED_0 pin.
The CLK25_REF, TX_TCLK, CLK_120MHZ options are clock out features with the LED controller bypassed.
The waveform transmitted off chip is dependent on the selected clock source frequency.
The following LED_FUNCTION settings are not qualified with link_status: LED_FUNCTION =
on, off, blink, INCOMPATIBLE_LINK_CFG, AN_LINK_GOOD, AN_COMPLETE, LOC_RCVR_STATUS,
REM_RCVR_STATUS, CLK25_REF, TX_TCLK and CLK_120MHz.
Options TX_LEVEL_2P4, TX_LEVEL_1P0, master, and slave are optionally qualified by link status and this
is controlled via the LED0_LINK_ST_QUALIFY MMR.
The TX_LEVEL_2P4, TX_LEVEL_1P0, master, slave, MSTR_SLV_FAULT, AN_LINK_GOOD,
AN_COMPLETE, and TS_TIMER. These options are considered status indicators and the LED controller is
not used. If the programmed signal is high, the LED is static on and if the programmed signal is low, the
LED is static off.
0: LINKUP_TXRX_ACTIVITY.
1: LINKUP_TX_ACTIVITY.
2: LINKUP_RX_ACTIVITY.
3: LINKUP_ONLY.
4: TXRX_ACTIVITY.
5: TX_ACTIVITY.
6: RX_ACTIVITY.
7: LINKUP_RX_ER.
8: LINKUP_RX_TX_ER.
9: RX_ER.
10: RX_TX_ER.
11: TX_SOP.
12: RX_SOP.
Reset
Access
0x1
R/W
0x0
R/W
0x0
R/W
0x0
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Data Sheet
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Table 183. Bit Descriptions for LED_CNTRL
Bits
Bit Name
Description
Reset
Access
13: on.
14: off.
15: blink.
16: TX_LEVEL_2P4.
17: TX_LEVEL_1P0.
18: master.
19: slave.
20: INCOMPATIBLE_LINK_CFG.
21: AN_LINK_GOOD.
22: AN_COMPLETE.
23: TS_TIMER.
24: LOC_RCVR_STATUS.
25: REM_RCVR_STATUS.
26: CLK25_REF.
27: TX_TCLK.
28: CLK_120MHZ.
LED Polarity Register
Device Address: 0x1E; Register Address: 0x8C83, Reset: 0x0000, Name: LED_POLARITY
Allows the LED polarity to be automatically sensed by the internal logic or allows reconfiguration by the user.
Table 184. Bit Descriptions for LED_POLARITY
Bits
Bit Name
Description
Reset
Access
[15:4]
[3:2]
RESERVED
LED1_POLARITY
0x0
0x0
R
R/W
[1:0]
LED0_POLARITY
Reserved.
LED 1 Polarity.
0: LED autosense. LED active high or low as per autosense.
1: LED active high.
2: LED active low.
LED 0 Polarity.
0: LED autosense. LED active high or low as per autosense.
1: LED active high.
2: LED active low.
0x0
R/W
Vendor Specific MMD 2 Device Identifier High Register
Device Address: 0x1F; Register Address: 0x0002, Reset: 0x0283, Name: MMD2_DEV_ID1
Table 185. Bit Descriptions for MMD2_DEV_ID1
Bits
Bit Name
Description
Reset
Access
[15:0]
MMD2_DEV_ID1
Vendor Specific 2 MMD Device Identifier.
0x283
R
Vendor Specific MMD 2 Device Identifier Low Register
Device Address: 0x1F; Register Address: 0x0003, Reset: 0xBC91, Name: MMD2_DEV_ID2
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Table 186. Bit Descriptions for MMD2_DEV_ID2
Bits
Bit Name
Description
Reset
Access
[15:10]
[9:4]
[3:0]
MMD2_DEV_ID2_OUI
MMD2_MODEL_NUM
MMD2_REV_NUM
OUI Bits.
Model Number.
Revision Number.
0x2F
0x9
0x1
R
R
R
Vendor Specific 2 MMD Devices in Package Register
Device Address: 0x1F; Register Address: 0x0005, Reset: 0x008B, Name: MMD2_DEVS_IN_PKG1
Clause 22 registers and PMA/PMD, PCS, and autonegotiation MMDs are present.
Table 187. Bit Descriptions for MMD2_DEVS_IN_PKG1
Bits
Bit Name
Description
Reset
Access
[15:0]
MMD2_DEVS_IN_PKG1
Vendor Specific 2 MMDs in Package 1. Clause 22 registers and PMA/PMD, PCS, and
autonegotiation MMDs are present.
0x8B
R
Device Address: 0x1F; Register Address: 0x0006, Reset: 0xC000, Name: MMD2_DEVS_IN_PKG2
Vendor Specific Device 1 and Vendor Specific Device 2 MMDs are present.
Table 188. Bit Descriptions for MMD2_DEVS_IN_PKG2
Bits
Bit Name
Description
Reset
Access
[15:0]
MMD2_DEVS_IN_PKG2
Vendor Specific 2 MMDs in Package 2. Vendor Specific 1 and Vendor Specific 2 MMDs
are present.
0xC000
R
Vendor Specific MMD 2 Status Register
Device Address: 0x1F; Register Address: 0x0008, Reset: 0x8000, Name: MMD2_STATUS
This address corresponds to the Vendor Specific MMD 2 status register.
Table 189. Bit Descriptions for MMD2_STATUS
Bits
Bit Name
Description
Reset
Access
[15:14]
MMD2_STATUS
0x2
R
[13:0]
RESERVED
Vendor specific 2 MMD Status.
10: device responding at this address.
11: no device responding at this address.
01: no device responding at this address.
00: no device responding at this address.
Reserved.
0x0
R
PHY Subsystem Interrupt Status Register
Device Address: 0x1F; Register Address: 0x0011, Reset: 0x0000, Name: PHY_SUBSYS_IRQ_STATUS
This address can be read to check which interrupt events have occurred since the last time it was read. Each bit goes high when the associated
event occurs and then latches high until it is unlatched by reading. The bits of PHY_SUBSYS_IRQ_STATUS go high even when the associated
bits in PHY_SUBSYS_IRQ_MASK are not set. A reserved interrupt being triggered indicates a fatal error in the system.
Table 190. Bit Descriptions for PHY_SUBSYS_IRQ_STATUS
Bits
Bit Name
Description
Reset
Access
15
14
RESERVED
MAC_IF_FC_FG_IRQ_LH
Reserved.
MAC Interface Frame Checker/Generator Interrupt.
0x0
0x0
R LH
R LH
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Data Sheet
ADIN1110
REGISTERS
Table 190. Bit Descriptions for PHY_SUBSYS_IRQ_STATUS
Bits
Bit Name
Description
Reset
Access
13
12
11
[10:2]
1
0
MAC_IF_EBUF_ERR_IRQ_LH
RESERVED
AN_STAT_CHNG_IRQ_LH
RESERVED
LINK_STAT_CHNG_LH
RESERVED
MAC Interface Buffers Overflow/Underflow Interrupt.
Reserved.
Autonegotiation Status Change Interrupt.
Reserved.
Link Status Change.
Reserved.
0x0
0x0
0x0
0x0
0x0
0x0
R LH
R LH
R LH
R LH
R LH
R LH
PHY Subsystem Interrupt Mask Register
Device Address: 0x1F; Register Address: 0x0021, Reset: 0x2402, Name: PHY_SUBSYS_IRQ_MASK
Controls whether or not the interrupt signal is asserted in response to various events.
Table 191. Bit Descriptions for PHY_SUBSYS_IRQ_MASK
Bits
Bit Name
Description
Reset
Access
15
14
13
12
11
[10:2]
1
0
RESERVED
MAC_IF_FC_FG_IRQ_EN
MAC_IF_EBUF_ERR_IRQ_EN
RESERVED
AN_STAT_CHNG_IRQ_EN
RESERVED
LINK_STAT_CHNG_IRQ_EN
RESERVED
Reserved.
Enable MAC Interface Frame Checker/Generator Interrupt.
Enable MAC Interface Buffers Overflow/Underflow Interrupt.
Reserved.
Enable Autonegotiation Status Change Interrupt.
Reserved.
Enable Link Status Change Interrupt.
Reserved.
0x0
0x0
0x1
0x0
0x0
0x100
0x1
0x0
R/W SC
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Frame Checker Enable Register
Device Address: 0x1F; Register Address: 0x8001, Reset: 0x0001, Name: FC_EN
This register is used to enable the frame checker. The frame checker analyzes the received frames from either the MAC interface or the PHY
(see the FC_TX_SEL register) to report the number of frames received, CRC errors, and various other frame errors. The frame checker frame
and error counter registers count these events.
Table 192. Bit Descriptions for FC_EN
Bits
Bit Name
Description
Reset
Access
[15:1]
0
RESERVED
FC_EN
Reserved.
Frame Checker Enable. Set to 1 to enable the frame checker.
0x0
0x1
R
R/W
Frame Checker Interrupt Enable Register
Device Address: 0x1F; Register Address: 0x8004, Reset: 0x0001, Name: FC_IRQ_EN
This register is used to enable the frame checker interrupt. An interrupt is generated when a receive error occurs. Enable the frame
checker/generator interrupt in the PHY_SUBSYS_IRQ_MASK register. Set the MAC_IF_FC_FG_IRQ_EN bit.
The status can be read via the MAC_IF_FC_FG_IRQ_LH bit in the PHY_SUBSYS_IRQ_STATUS register.
Table 193. Bit Descriptions for FC_IRQ_EN
Bits
Bit Name
Description
Reset
Access
[15:1]
0
RESERVED
FC_IRQ_EN
Reserved.
Frame Checker Interrupt Enable. When set, this bit enables the frame checker interrupt.
0x0
0x1
R
R/W
analog.com
Rev. 0 | 96 of 104
Data Sheet
ADIN1110
REGISTERS
Frame Checker Transmit Select Register
Device Address: 0x1F; Register Address: 0x8005, Reset: 0x0000, Name: FC_TX_SEL
This register is used to select the transmit side or receive side for frames to be checked. If set, frames received from the MAC interface to
be transmitted are checked. The frame checker can be used to verify that correct data is received over the MAC interface and is also useful
if remote loopback is enabled (see the MAC_IF_REM_LB_EN bit in the MAC_IF_LOOPBACK register) because it can be used to check the
received data after it is looped back at the MAC interface.
Table 194. Bit Descriptions for FC_TX_SEL
Bits
Bit Name
Description
Reset
Access
[15:1]
0
RESERVED
FC_TX_SEL
Reserved.
Frame Checker Transmit Select. When set, this bit indicates that the frame checker must check frames
received to be transmitted by the PHY.
1: check frames from the MAC interface to be transmitted by the PHY.
0: check frames received by the PHY from the remote end.
0x0
0x0
R
R/W
Receive Error Count Register
Device Address: 0x1F; Register Address: 0x8008, Reset: 0x0000, Name: RX_ERR_CNT
The receive error counter register is used to access the receive error counter associated with the frame checker in the PHY.
Table 195. Bit Descriptions for RX_ERR_CNT
Bits
Bit Name
Description
Reset
Access
[15:0]
RX_ERR_CNT
Receive Error Count. This is the receive error counter associated with the frame checker in the PHY. Note
that this bit is self clearing upon reading.
0x0
R SC
Frame Checker Count High Register
Device Address: 0x1F; Register Address: 0x8009, Reset: 0x0000, Name: FC_FRM_CNT_H
This register is a latched copy of Bits[31:16] of the 32-bit of the receive frame counter register. When the receive error counter (RX_ERR_CNT)
is read, the receive frame counter register is latched so that the error count and the receive frame count are synchronized.
Table 196. Bit Descriptions for FC_FRM_CNT_H
Bits
Bit Name
Description
Reset
Access
[15:0]
FC_FRM_CNT_H
Bits[31:16] of Latched Copy of the Number of Received Frames.
0x0
R
Frame Checker Count Low Register
Device Address: 0x1F; Register Address: 0x800A, Reset: 0x0000, Name: FC_FRM_CNT_L
This register is a latched copy of Bits[15:0] of the 32-bit receive frame counter register. When the receive error counter (RX_ERR_CNT) is read,
the receive frame counter register is latched so that the error count and receive frame count are synchronized.
Table 197. Bit Descriptions for FC_FRM_CNT_L
Bits
Bit Name
Description
Reset
Access
[15:0]
FC_FRM_CNT_L
Bits[15:0] of Latched Copy of the Number of Received Frames.
0x0
R
Frame Checker Length Error Count Register
Device Address: 0x1F; Register Address: 0x800B, Reset: 0x0000, Name: FC_LEN_ERR_CNT
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Rev. 0 | 97 of 104
Data Sheet
ADIN1110
REGISTERS
This register is a latched copy of the frame length error counter register. This register is a count of received frames with a length error status.
When the receive error counter (RX_ERR_CNT) is read, the frame length error counter register is latched, which ensures that the frame length
error count and receive frame count are synchronized.
Table 198. Bit Descriptions for FC_LEN_ERR_CNT
Bits
Bit Name
Description
Reset
Access
[15:0]
FC_LEN_ERR_CNT
Latched Copy of the Frame Length Error Counter.
0x0
R
Frame Checker Alignment Error Count Register
Device Address: 0x1F; Register Address: 0x800C, Reset: 0x0000, Name: FC_ALGN_ERR_CNT
This register is a latched copy of the frame alignment error counter register. This register is a count of received frames with an alignment error
status. When the receive error counter (RX_ERR_CNT) is read, the alignment error counter is latched, which ensures that the frame alignment
error count and the receive frame count are synchronized.
Table 199. Bit Descriptions for FC_ALGN_ERR_CNT
Bits
Bit Name
Description
Reset
Access
[15:0]
FC_ALGN_ERR_CNT
Latched Copy of the Frame Alignment Error Counter.
0x0
R
Frame Checker Symbol Error Count Register
Device Address: 0x1F; Register Address: 0x800D, Reset: 0x0000, Name: FC_SYMB_ERR_CNT
This register is a latched copy of the symbol error counter register. This register is a count of received frames with both RX_ER and RX_DV set.
When the receive error counter (RX_ERR_CNT) is read, the symbol error count is latched, which ensures that the symbol error count and the
frame receive count are synchronized.
Table 200. Bit Descriptions for FC_SYMB_ERR_CNT
Bits
Bit Name
Description
Reset
Access
[15:0]
FC_SYMB_ERR_CNT
Latched Copy of the Symbol Error Counter.
0x0
R
Frame Checker Oversized Frame Count Register
Device Address: 0x1F; Register Address: 0x800E, Reset: 0x0000, Name: FC_OSZ_CNT
This register is a latched copy of the oversized frame error counter register. This register is a count of receiver frames with a length greater than
specified in frame checker maximum frame size (FC_MAX_FRM_SIZE). When the receive error counter (RX_ERR_CNT) is read, the oversized
frame counter register is latched, which ensures that the oversized error count and the receive frame count are synchronized.
Table 201. Bit Descriptions for FC_OSZ_CNT
Bits
Bit Name
Description
Reset
Access
[15:0]
FC_OSZ_CNT
Latched copy of the Oversized Frame Error Counter.
0x0
R
Frame Checker Undersized Frame Count Register
Device Address: 0x1F; Register Address: 0x800F, Reset: 0x0000, Name: FC_USZ_CNT
This register is a latched copy of the undersized frame error counter register. This register is a count of received frames with less than 64 bytes.
When the receive error counter (RX_ERR_CNT) is read, the undersized frame error counter is latched, which ensures that the undersized
frame error count and the receive frame count are synchronized.
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Rev. 0 | 98 of 104
Data Sheet
ADIN1110
REGISTERS
Table 202. Bit Descriptions for FC_USZ_CNT
Bits
Bit Name
Description
Reset
Access
[15:0]
FC_USZ_CNT
Latched Copy of the Undersized Frame Error Counter.
0x0
R
Frame Checker Odd Nibble Frame Count Register
Device Address: 0x1F; Register Address: 0x8010, Reset: 0x0000, Name: FC_ODD_CNT
This register is a latched copy of the odd nibble frame register. This register is a count of received frames with an odd number of frames in the
frame. When the receive error counter (RX_ERR_CNT) is read, the odd nibble frame counter register is latched, which ensures that the odd
nibble frame count and the receive frame count are synchronized.
Table 203. Bit Descriptions for FC_ODD_CNT
Bits
Bit Name
Description
Reset
Access
[15:0]
FC_ODD_CNT
Latched Copy of the Odd Nibble Counter.
0x0
R
Frame Checker Odd Preamble Packet Count Register
Device Address: 0x1F; Register Address: 0x8011, Reset: 0x0000, Name: FC_ODD_PRE_CNT
This register is a latched copy of the odd preamble packet counter register. This register is a count of received packets with an odd number of
nibbles in the preamble. When the receive error counter (RX_ERR_CNT) is read, the odd preamble packet counter register is latched, which
ensures that the odd preamble packet count and the receive frame count are synchronized.
Table 204. Bit Descriptions for FC_ODD_PRE_CNT
Bits
Bit Name
Description
Reset
Access
[15:0]
FC_ODD_PRE_CNT
Latched Copy of the Odd Preamble Packet Counter.
0x0
R
Frame Checker False Carrier Count Register
Device Address: 0x1F; Register Address: 0x8013, Reset: 0x0000, Name: FC_FALSE_CARRIER_CNT
This register is a latched copy of the false carrier events counter register. This is a count of the number of times the bad SSD state is entered.
When the receive error counter (RX_CNT_ERR) is read, the false carrier events counter register is latched, which ensures that the false carrier
events count and the receive frame count are synchronized.
Table 205. Bit Descriptions for FC_FALSE_CARRIER_CNT
Bits
Bit Name
Description
Reset
Access
[15:0]
FC_FALSE_CARRIER_CNT
Latched Copy of the False Carrier Events Counter.
0x0
R
Frame Generator Enable Register
Device Address: 0x1F; Register Address: 0x8020, Reset: 0x0000, Name: FG_EN
This register is used to enable the frame generator. When the frame generator is enabled, the source of data for the PHY comes from the frame
generator and not the MAC interface. To use the frame generator, the diagnostic clock must also be enabled (DIAG_CLK_EN).
Table 206. Bit Descriptions for FG_EN
Bits
Bit Name
Description
Reset
Access
[15:1]
0
RESERVED
FG_EN
Reserved.
Frame Generator Enable.
0x0
0x0
R
R/W
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Rev. 0 | 99 of 104
Data Sheet
ADIN1110
REGISTERS
Frame Generator Control/Restart Register
Device Address: 0x1F; Register Address: 0x8021, Reset: 0x0001, Name: FG_CNTRL_RSTRT
This register controls the frame generator. The FG_CNTRL bit field specifies data field type used by the frame generator, for example, random
all zeros. The FG_RSTRT bit restarts the frame generator.
Table 207. Bit Descriptions for FG_CNTRL_RSTRT
Bits
Bit Name
Description
Reset
Access
[15:4]
3
[2:0]
RESERVED
FG_RSTRT
FG_CNTRL
Reserved.
Frame Generator Restart. When set, this bit restarts the frame generator. This bit is self clearing
Frame Generator Control.
000: no frames after completion of current frame.
001: random number data frame.
010: all zeros data frame.
011: all ones data frame.
100: alternative 0x55 data field.
101: data field decrementing from 255 (decimal) to 0.
0x0
0x0
0x1
R
R/W SC
R/W
Frame Generator Continuous Mode Enable Register
Device Address: 0x1F; Register Address: 0x8022, Reset: 0x0000, Name: FG_CONT_MODE_EN
This register is used to put the frame generator into continuous mode. The default mode of operation is burst mode, where the number of
frames generated is specified by the FG_NFRM_H and FG_NFRM_L registers.
Table 208. Bit Descriptions for FG_CONT_MODE_EN
Bits
Bit Name
Description
Reset
Access
[15:1]
0
RESERVED
FG_CONT_MODE_EN
Reserved.
Frame Generator Continuous Mode Enable. This bit is used to put the frame generator into
continuous mode or burst mode.
1: frame generator operates in continuous mode. In this mode, the frame generator keeps
generating frames indefinitely.
0: frame generator operates in burst mode. In this mode, the frame generator generates
a single burst of frames and then stops. The number of frames is determined by the
FG_NFRM_H and FG_NFRM_L registers.
0x0
0x0
R
R/W
Frame Generator Interrupt Enable Register
Device Address: 0x1F; Register Address: 0x8023, Reset: 0x0000, Name: FG_IRQ_EN
This register is used to enable the frame generator interrupt. An interrupt is generated when the requested number of frames is generated.
Enable the frame checker/generator interrupt in the PHY_SUBSYS_IRQ_MASK register. Set the MAC_IF_FC_FG_IRQ_EN bit.
The interrupt status can be read via the MAC_IF_FC_FG_IRQ_LH bit in the PHY_SUBSYS_IRQ_STATUS register.
Table 209. Bit Descriptions for FG_IRQ_EN
Bits
Bit Name
Description
Reset
Access
[15:1]
0
RESERVED
FG_IRQ_EN
Reserved.
Frame Generator Interrupt Enable. When set, this bit indicates that the frame generator must generate an
interrupt when it has transmitted the programmed number of frames.
1: enable the frame generator interrupt.
0: disable the frame generator interrupt.
0x0
0x0
R
R/W
analog.com
Rev. 0 | 100 of 104
Data Sheet
ADIN1110
REGISTERS
Frame Generator Frame Length Register
Device Address: 0x1F; Register Address: 0x8025, Reset: 0x006B, Name: FG_FRM_LEN
This register specifies the data field frame length in bytes. In addition to the data field, six bytes are added for the source address, six bytes
for the destination address, two bytes for the length field, and four bytes for the frame check sequence (FCS). The total length is the data field
length plus 18.
Table 210. Bit Descriptions for FG_FRM_LEN
Bits
Bit Name
Description
Reset
Access
[15:0]
FG_FRM_LEN
The Data Field Frame Length in Bytes.
0x6B
R/W
Frame Generator Interframe Gap Length Register
Device Address: 0x1F; Register Address: 0x8026, Reset: 0x000C, Name: FG_IFG_LEN
This register specifies the length in bytes of the interframe gap to be inserted between frames by the frame generator.
Table 211. Bit Descriptions for FG_IFG_LEN
Bits
Bit Name
Description
Reset
Access
[15:0]
FG_IFG_LEN
Frame Generator Interframe Gap Length. This register specifies the length in bytes of the interframe gap to
be inserted between frames by the frame generator.
0xC
R/W
Frame Generator Number of Frames High Register
Device Address: 0x1F; Register Address: 0x8027, Reset: 0x0000, Name: FG_NFRM_H
This register is Bits[31:16] of a 32-bit register that specifies the number of frames to be generated each time the frame generator is enabled or
restarted.
Table 212. Bit Descriptions for FG_NFRM_H
Bits
Bit Name
Description
Reset
Access
[15:0]
FG_NFRM_H
Bits[31:16] of the Number of Frames to be Generated.
0x0
R/W
Frame Generator Number of Frames Low Register
Device Address: 0x1F; Register Address: 0x8028, Reset: 0x0100, Name: FG_NFRM_L
This register is Bits[15:0] of a 32-bit register that specifies the number of frames to be generated each time the frame generator is enabled or
restarted.
Table 213. Bit Descriptions for FG_NFRM_L
Bits
Bit Name
Description
Reset
Access
[15:0]
FG_NFRM_L
Bits[15:0] of the Number of Frames to be Generated.
0x100
R/W
Frame Generator Done Register
Device Address: 0x1F; Register Address: 0x8029, Reset: 0x0000, Name: FG_DONE
This register is used to indicate that the frame generator has completed the generation of the number of frames requested in the FG_NFRM_H
and FG_NFRM_L registers.
Table 214. Bit Descriptions for FG_DONE
Bits
Bit Name
Description
Reset
Access
[15:1]
RESERVED
Reserved.
0x0
R
analog.com
Rev. 0 | 101 of 104
Data Sheet
ADIN1110
REGISTERS
Table 214. Bit Descriptions for FG_DONE
Bits
Bit Name
Description
Reset
Access
0
FG_DONE
Frame Generator Done. This bit reads as 1 to indicate that the generation of frames has completed. When set,
this bit goes high and it latches high until its unlatched by reading.
0x0
R LH
MAC Interface Loopbacks Configuration Register
Device Address: 0x1F; Register Address: 0x8055, Reset: 0x000A, Name: MAC_IF_LOOPBACK
MAC interface loopbacks configuration.
Table 215. Bit Descriptions for MAC_IF_LOOPBACK
Bits
Bit Name
Description
Reset
Access
[15:4]
3
RESERVED
MAC_IF_REM_LB_RX_SUP_EN
0x0
0x1
R
R/W
2
MAC_IF_REM_LB_EN
0x0
R/W
1
MAC_IF_LB_TX_SUP_EN
0x1
R/W
0
MAC_IF_LB_EN
Reserved.
Suppress RX Enable. Suppress receiver to the MAC when MAC_IF_REM_LB_EN
is set.
MAC Interface Remote Loopback Enable. Receive data is looped back to the
transmitter.
Suppress Transmission Enable. Suppress transmission to the PHY when
MAC_IF_LB_EN is set.
MAC Interface Loopback Enable. Transmit data is looped back to the receiver.
0x0
R/W
MAC Start of Packet (SOP) Generation Control Register
Device Address: 0x1F; Register Address: 0x805A, Reset: 0x001B, Name: MAC_IF_SOP_CNTRL
Table 216. Bit Descriptions for MAC_IF_SOP_CNTRL
Bits
Bit Name
Description
Reset
Access
[15:6]
5
4
3
2
RESERVED
MAC_IF_TX_SOP_LEN_CHK_EN
MAC_IF_TX_SOP_SFD_EN
MAC_IF_TX_SOP_DET_EN
MAC_IF_RX_SOP_LEN_CHK_EN
0x0
0x0
0x1
0x1
0x0
R
R/W
R/W
R/W
R/W
1
MAC_IF_RX_SOP_SFD_EN
0x1
R/W
0
MAC_IF_RX_SOP_DET_EN
Reserved.
Enable TX SOP Preamble Length Check.
Enable TX SOP Signal Indication on start of frame delimiter (SFD).
Enable the Generation of the TX SOP Indication Signal.
Enable RX SOP Preamble Length Check. If this bit is set and no SFD is received,
the RX SOP signal indication is set after eight bytes. Otherwise, the RX SOP is
not set if no SFD is received in the first eight bytes.
Enable RX SOP Signal Indication on SFD Reception. If both
MAC_IF_RX_SOP_DET_EN and MAC_IF_RX_SOP_SFD_EN are set, the RX
SOP signal is set when the SFD is received. Otherwise, the RX SOP is set when
RX_DV is set. The RX SOP signal remains set until the end of the frame.
Enable the Generation of the RX SOP Indication Signal.
0x1
R/W
analog.com
Rev. 0 | 102 of 104
Data Sheet
ADIN1110
PCB LAYOUT RECOMMENDATIONS
This section details the key areas of interest for the placement and
layout of the PHY and corresponding support components.
PACKAGE LAYOUT
The LFCSP has an exposed pad underneath the package that
must be soldered to the PCB ground for mechanical, electrical,
and thermal reasons. For thermal impedance performance and to
maximize heat removal, the use of a 4 × 4 array of thermal vias
beneath the exposed ground pad is recommended. The PCB land
pattern must incorporate the exposed ground pad with these vias
in the footprint. The EVAL-ADIN1110EBZ uses an array of 4 × 4
filled vias on a 1.00 mm grid arrangement. The via pad diameter
dimension is 0.02 inches (0.5015 mm).
COMPONENT PLACEMENT AND ROUTING
Prioritization of the critical traces and components helps simplify
the routing exercise. Place and orient the critical traces and components first to ensure an effective layout. The critical components
are the crystal and load capacitors, the CEXT_2 and DEXT_3
capacitors, and all bypass capacitors local to the ADIN1110 device.
Prioritize these components for placement and routing.
CRYSTAL PLACEMENT AND ROUTING
Particular attention is required on the crystal placement and routing
to ensure minimum current consumption, reduce stray capacitance,
and improve noise immunity.
Follow these recommendations:
►
►
►
►
►
PCB STACK
Follow these recommendations:
►
Follow these recommendations:
►
►
►
►
►
Place the decoupling capacitors as close as possible to their
respective input pin.
Minimize trace turns and use 45° corners.
Avoid traces crossing power planes on adjacent layers.
Avoid stubs.
Avoid vias on high speed signals. If vias are required, place
ground vias next to the signal vias to improve the return current
path.
analog.com
Place the crystal and its capacitors as close as possible to the
XTAL_I and XTAL_O pins.
Place the load capacitors close to each other.
Use a local GND plane (copper island) for the crystal and load
capacitor with a single point connection to the main GND.
Reduce parasitic capacitance by keeping the XTAL_I and
XTAL_O traces away from each other.
Adding a copper keep out on the layer beneath the crystal can
also reduce the parasitic capacitance.
►
►
►
►
Use a PCB stack with a minimum of 4 layers.
► Consider 6 layers or more with external layers used as ground
planes to improve EMI issues (optional).
Define copper layer thickness based on the application and
power requirements.
Use internal layers for power and ground planes.
Use external layers for signals.
Use via stitching to improve ground and reduce EMI. Stitching
pattern and via to via gaps to be defined based on the application.
Rev. 0 | 103 of 104
Data Sheet
ADIN1110
OUTLINE DIMENSIONS
Figure 30. 40-Lead Lead Frame Chip Scale Package [LFCSP]
6 mm × 6 mm Body and 0.75 mm Package Height
(CP-40-29)
Dimensions shown in millimeters
Updated: October 08, 2021
ORDERING GUIDE
Model1
Temperature Range
Package Description
Packing Quantity
Package Option
ADIN1110BCPZ
ADIN1110BCPZ-R7
ADIN1110CCPZ
ADIN1110CCPZ-R7
−40°C to +85°C
−40°C to +85°C
−40°C to +105°C
−40°C to +105°C
LFCSP:LEADFRM CHIP SCALE
LFCSP:LEADFRM CHIP SCALE
LFCSP:LEADFRM CHIP SCALE
LFCSP:LEADFRM CHIP SCALE
Tray, 490
Reel, 750
Tray, 490
Reel, 750
CP-40
CP-40
CP-40
CP-40
1
Z = RoHS Compliant Part.
©2021 Analog Devices, Inc. All rights reserved. Trademarks and
registered trademarks are the property of their respective owners.
One Analog Way, Wilmington, MA 01887-2356, U.S.A.
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