ADIN1200BCP32Z-R7

Data Sheet Robust, Industrial, Low Power, 10 Mbps and 100 Mbps Ethernet PHY ADIN1200 FEATURES GENERAL DESCRIPTION 10BASE-Te/100BASE-TX IEEE® 802.3TM compliant MII, RMII and RGMII MAC interfaces 100BASE-TX RGMII latency transmit: 0.5 × VDDIO1 >0.9 × VDDIO1 Note that the supply rail for the LED_0 pin is AVDD_3P3 rather than VDDIO. Therefore, pull up any pull-up resistor on the LED_0 pin to AVDD_3P3. Rev. 0 | Page 27 of 79 ADIN1200 Data Sheet Table 21. Hardware Configuration Pin Summary Configuration Function PHYAD_0 to PHYAD_3 Configuration Forced/Advertised PHY Speed, Software Power-Down Mode after Reset, Downspeed Enable, Energy Detect Power-Down Mode, Energy Efficient Ethernet Auto MDIX MAC Interface Selection 1 2 Functional Pin/Hardware Configuration Mnemonic1 RXD_3/PHYAD_3 RXD_2/PHYAD_2 RXD_1/PHYAD_1 RXD_0/PHYAD_0 LINK_ST/PHY_CFG1 LED_0/COL/TX_ER/PHY_CFG0 Pin Levels 2 2 2 2 4 4 Internal Pull-Down2 Yes Yes Yes Yes None None GP_CLK/RX_ER/MDIX_MODE 4 None RX_CTL/RX_DV/CRS_DV/MACIF_SEL1 RXC/RX_CLK/MACIF_SEL0 2 2 Yes Yes Default Configuration PHY Address 0x0 Unknown (external resistors are required) Unknown (external resistors are required) RGMII RXC/TXC 2 ns delay Hardware configuration pin is the last pin name in the pin mnemonic. The internal pull-down resistor has a typical value of 45 kΩ. Table 22. PHY Address Configuration PHY Address 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 PHYAD_3 Pin Low Low Low Low Low Low Low Low High High High High High High High High PHYAD_2 Pin Low Low Low Low High High High High Low Low Low Low High High High High Rev. 0 | Page 28 of 79 PHYAD_1 Pin Low Low High High Low Low High High Low Low High High Low Low High High PHYAD_0 Pin Low High Low High Low High Low High Low High Low High Low High Low High Data Sheet ADIN1200 Table 23. PHY Configuration Forced/Advertised Advertised Speeds (Autonegotiation Enabled) Forced Speed (Autonegotiation Disabled) 1 2 PHY Speed Configuration1 10 HD/FD and 100 HD/FD 10 HD/FD and 100 HD/FD 10 HD/FD and 100 HD/FD 10 FD and 100 FD 100 FD 10 FD 100 HD 100 FD Other Functions Enabled2 Downspeed, EDPD and EEE Software power-down mode after reset PHY_CFG1 MODE_4 MODE_1 MODE_3 MODE_4 MODE_4 MODE_1 MODE_2 MODE_3 PHY_CFG0 MODE_4 MODE_4 MODE_4 MODE_3 MODE_1 MODE_2 MODE_2 MODE_3 Row No. 1 2 3 4 5 6 7 8 HD means half duplex and FD means full duplex. If no function is listed in this column, only the PHY speed is configured using this row. PHY Configuration Software Power-Down After Reset The PHY_CFG1 and PHY_CFG0 hardware configuration pins are shared with the LINK_ST and LED_0 functional pins, respectively. These hardware configuration pins cover the following functions and can be configured according to Table 23: If the ADIN1200 is configured so that it does not enter software power-down mode after reset, the ADIN1200 attempts to bring up a link at the configured speeds and MDI/MDIX configuration after it exits reset. If the ADIN1200 is configured so that it enters software power-down mode after reset (Row 3), the ADIN1200 waits in software power-down mode until it is configured over the MDIO interface, at which point the PHY configuration can be set to exit software power-down by software. The ADIN1200 can also be put into software powerdown mode by setting the SFT_PD bit (MII_CONTROL register, Address 0x0000).      Forced/advertised PHY speed Software power-down mode after reset Downspeed enable Energy detect power-down (EDPD) mode EEE enable The PHY_CFG1 pin and PHY_CFG0 pin have no internal pullup resistors. Therefore, external resistors must be used to configure these functions. Forced/Advertised PHY Speed As shown in Table 23, it is possible to advertise all or a subset of PHY speed capabilities, set half duplex or full duplex mode, as well as enable or disable autonegotiation. Autonegotiation is enabled for the first five rows in Table 23, such as in the case of advertised speeds modes. It is also possible to configure forced speed modes where autonegotiation is disabled and the speed is forced (Row 6 to Row 8 of Table 23). Referring to Table 23, three of the PHY_CFG1 and PHY_CFG0 hardware configuration pin settings result in the same link speed configuration (Row 1, Row 2, and Row 3). However, Row 1 also enables three other functions, Row 2 does not enable any extra functions, and in Row 4, the ADIN1200 is configured to enter software power-down mode after reset. The enabling or disabling of autonegotiation and advertised speed settings can also be set using the standard IEEE registers, MII_CONTROL (Address 0x0000) and AUTONEG_ADV (Address 0x0004). Downspeed Configuration If downspeed is enabled, the PHY downspeeds to a lower speed after a number of attempts if it cannot link at the highest speed advertised. The use of downspeed requires autonegotiation to be enabled with multiple speeds advertised. The default operation of downspeed can be overwritten in software by writing to DN_ SPEED_TO_10_EN (PHY_CTRL_2 register, Address 0x0016, Bit 10), and NUM_SPEED_RETRY (PHY_CTRL_3 register, Address 0x0017, Bits[12:10]). Energy Detect Power-Down Configuration If energy detect power-down is enabled and no energy is detected at the MDI_x_x pins, the ADIN1200 enters a low power mode. Therefore, this mode saves power where there is no cable connected or the remote PHY is powered down. Energy Efficient Ethernet If EEE is enabled and also advertised by the remote PHY, the ADIN1200 can enter a low power mode (low power idle) when no data is being transmitted by either end. See the EEE, Low Power Idle Mode section for more details. Rev. 0 | Page 29 of 79 ADIN1200 Data Sheet Auto MDIX Configuration MAC Interface Selection Auto MDIX configuration mode is shared with the GP_CLK pin and can be configured according to Table 24. This pin does not have an internal pull-up resistor. Therefore, external resistors must be used to set the MDI/MDIX mode. The MAC interface selection is shared with the RX_CTL/ RX_DV/CRS_DV pin and RXC/RX_CLK pin, and can be configured according to Table 25. In RGMII mode, it is possible to enable a 2 ns delay on RXC only or on both RXC and TXC. The RX_CTL/RX_DV/CRS_DV and RXC/RX_CLK pins have weak internal pull-down resistors. Therefore, by default the ADIN1200 is configured in RGMII mode with a 2 ns delay on RXC and TXC. External resistors must be used to select any of the remaining MAC interface modes. Table 24. Auto MDIX Configuration Configuration Manual MDI Manual MDIX Auto MDIX, Prefer MDIX Auto MDIX, Prefer MDI MDIX_MODE MODE_1 MODE_2 MODE_3 MODE_4 If auto MDIX is enabled (MODE_3 or MODE_4), the ADIN1200 automatically determines if the MDI or MDIX configuration must be used. Otherwise, the ADIN1200 is forced to the chosen MDI or MDIX configuration. If enabling auto MDIX, the ADIN1200 supports auto MDIX with a preference for MDI or MDIX. This determines which MDI/ MDIX setting is first in the autocrossover algorithm. To achieve a faster MDI/MDIX resolution in some cases, set both PHYs to the same preferred configuration (MDI or MDIX) when a crossover cable is used, and to opposite preferred configurations if a straight through cable is used, which has the advantage of still being able to work with a mismatch of wiring and optimizes the time to resolve auto MDIX. The default operation of auto MDIX can be overwritten in software by writing to the AUTO_MDI_EN bit (PHY_ CTRL_1 register, Address 0x0012) and the MAN_MDIX bit (PHY_CTRL_1 register, Address 0x0012). The MAC interface selection can also be done via software (GE_ RGMII_CFG and GE_RMII_CFG registers) with the internal 2 ns delay configured via the GE_RGMII_RXLD_EN bit and GE_ RGMII_TXLD_EN bit within the GE_RGMII_CFG register (Address 0xFF23). Put the PHY in software power-down by setting the SFT_PD bit (MII_CONTROL register, Address 0x0000) before any changes are made to the MAC interface configuration registers. Because RMII mode requires a 50 MHz reference clock, do not use software to configure the MAC interface to RMII. Table 25. MAC Interface Selection MAC Interface Selection RGMII RXC/TXC 2 ns Delay RGMII RXC Only, 2 ns Delay MII RMII Rev. 0 | Page 30 of 79 MACIF_SEL1 Low High Low High MACIF_SEL0 Low Low High High Data Sheet ADIN1200 ON-CHIP DIAGNOSTICS loopback at the end of the cable. The signal processing is adjusted so that the transmitted signal is not cancelled. Setting the LB_ EXT_EN bit (PHY_CTRL_STATUS_1 register, Address 0x0013) enables external cable loopback. LOOPBACK MODES The PHY core provides several loopback modes: all digital loopback, MII loopback, external cable loopback, line driver loopback, and remote loopback (see Figure 28). These loopback modes test and verify various functional blocks within the PHY. The use of frame generators and frame checkers allow completely self contained in-circuit testing of the digital and analog data paths within the PHY core. Line Driver Loopback For line driver loopback, leave the MDI_x_x pins open-circuit, thereby transmitting into an unterminated connector or cable. The PHY can then operate by receiving the reflection from its own transmission. This provides similar capabilities to the external cable loopback without the need to create any wire shorts by unplugging the cable. Setting the LB_LD_SEL bit (PHY_CTRL_ STATUS_1 register, Address 0x0013) selects line driver loopback. The loopback bit (MII_CONTROL register, Address 0x0000, Bit 14) also must be set to enable line driver loopback. All Digital Loopback The default loopback mode is all digital loopback mode. This loops the data within the PHY at the analog/digital boundary to check for proper operation of the PHY, but does not require the external analog components, connections, or analog supplies to be accurate. In all digital loopback mode, it is possible to also transmit to the MDI_x_x pins, which can be useful for transmit testing. By default, the LB_ALL_DIG_SEL bit (PHY_CTRL_ STATUS_1 register, Address 0x0013) is set, which selects all digital loopback mode and the LB_TX_SUP bit (Bit 6 within the PHY_CTRL_STATUS_1 register) is also set, which suppresses the transmission of the signal to the MDI pins. Setting the PHY_ CTRL_STATUS_1 register to a value of 0x1001 selects digital loopback with transmission to the MDI_x_x pins. The loopback bit (MII_CONTROL register, Address 0x0000, Bit 14) must also be set to enable all digital loopback mode. Remote Loopback Remote loopback requires a link with a remote PHY and to loop the data received from the remote PHY back to the remote PHY. This linking allows a remote PHY to verify a complete link by ensuring that the PHY receives the proper data. Setting the PHY_CTRL_STATUS_1 register to a value of 0x0241 selects remote loopback where the data received by the PHY is also sent to the MAC. Setting the LB_TX_SUP bit within the PHY_ CTRL_STATUS register, which sets the register value to 0x0341, selects remote loopback, where the data received by the PHY is not sent to the MAC. For this type of loopback, do not set the loopback bit (MII_CONTROL register, Address 0x0000, Bit 14). External Cable Loopback External cable loopback verifies the whole analog and digital path, including the external components and cable. This requires that Pair 0 and Pair 1 are shorted together to provide an analog TRANSMITTER SUPRESSION REMOTE LOOPBACK FRAME GENERATOR MAC PHY DIGITAL PHY AFE RECEIVER SUPPRESSION RJ45 LINE DRIVER LOOPBACK FRAME CHECKER ALL DIGITAL LOOPBACK Figure 28. Loopback Modes Rev. 0 | Page 31 of 79 EXTERNAL CABLE LOOPBACK 21561-031 MAC INTERFACE ADIN1200 Data Sheet The frame checker counts the number of CRC errors and these are reported in the receive error counter register (RX_ERR_CNT register, Address 0x0014). To ensure synchronization between the frame checker error counter and frame checker frame counters, all of the counters are latched when the receive error counter register is read. Therefore, when using the frame checker, read the receive error counter first, and then read all other frame counters and error counters. A latched copy of the receive frame counter register is available in the FC_FRM_CNT_H register and FC_FRM_CNT_L register (Address 0x940A and Address 0x940B, respectively). FRAME GENERATOR AND CHECKER The ADIN1200 can be configured to generate frames and to check received frames (see Figure 29). The frame generator and checker can be used independently to just generate frames or just check frames or can be used together to simultaneously generate frames and check frames. If frames are looped back at the remote end, the frame checker can be used to check frames generated by the ADIN1200. When the frame generator is enabled, the source of data for the PHY comes from the frame generator and not the MAC interface. To use the frame generator, the diagnostic clock must also be enabled (DIAG_CLK_EN bit, PHY_CTRL_1 register, Address 0x0012). In addition to CRC errors, the frame checker counts frame length errors, frame alignment errors, symbol errors, oversized frame errors, and undersized frame errors. In addition to the received frames, the frame checker counts frames with an odd number of nibbles in the frame in 100BASE-TX mode or 10BASE-Te mode, and counts frames with an odd number of nibbles in the preamble in 100BASE-TX mode. The frame checker also counts frames with a noninteger number of nibbles in 10BASE-Te mode and the number of false carrier events, which is a count of the number of times the bad start of stream delimiter (SSD) state is entered. The frame generator control registers configure the type of frames to be sent (random data, all 1s), the frame length, and the number of frames to be generated. The generation of the requested frames starts by enabling the frame generator (set the FG_EN bit, Address 0x9415). When the generation of the frames is completed, the frame generator done bit is set (FG_DONE bit, Address 0x941E). The frame checker is enabled using the frame checker enable bit (FC_EN bit, Address 0x9403). The frame checker can be configured to check and analyze received frames from either the MAC interface or the PHY, which is configured using the frame checker transmit select bit (FC_TX_SEL bit, Address 0x9407). The frame checker reports the number of frames received, cyclic redundancy check (CRC) errors, and various other frame errors. The frame checker frame counter register and frame checker error counter register count these events. Frame Generator and Checker Used with Remote Loopback with Two PHYs Using two PHY devices, the user can configure a convenient self contained validation of the PHY to PHY connection. Figure 29 shows an overview of how each PHY is configured. An external Ethernet cable is connected between both devices, and PHY 1 is generating frames using the frame generator. PHY 2 has remote loopback enabled on the MAC side. The frames issued by PHY 1 are sent through the cable, through the PHY 2 signal chain returned by PHY 2 remote loopback, back again through the Ethernet cable, and checked by the PHY 1 frame checker. PHY 1 MAC INTERFACE FRAME GENERATOR FRAME CHECKER PHY DIGITAL PHY AFE RJ45 MAGNETICS EXTERNAL CABLE LOOPBACK PHY 2 FRAME CHECKER PHY DIGITAL PHY AFE RJ45 MAGNETICS Figure 29. Remote Loopback Used Across Two PHYs for Self Check Purposes Rev. 0 | Page 32 of 79 21561-032 MAC INTERFACE Data Sheet ADIN1200 CABLE DIAGNOSTICS ENHANCED LINK DETECTION The ADIN1200 has on-chip cable diagnostics capabilities. This cable analysis can be used to detect cable impairments that may be preventing the establishment of the link speed or degrading performance and can be performed both when the link is up or when the link is down. The ADIN1200 supports enhanced link detection, which is early detection and indication of link loss. This is a feature where the received signal is monitored, and if a significant number of consecutive samples of the signal are not as expected, early indication of link down is indicated. The ADIN1200 can simultaneously monitor for a significant number of consecutive 0s, a significant number of consecutive 1s, or a significant number of consecutive invalid levels. Each time a 100BASE-TX link is brought up the ADIN1200 reports an estimate of the cable length based on the signal processing. This can be read in the cable diagnostics cable length estimate register (CDIAG_CBL_LEN_EST register, Address 0xBA25). This estimate is not available for a 10BASE-Te link. A polarity inversion on each pair is reported in the pair polarity inversion register bits (PHY_2_STATUS register, Address 0x001F, Bits[13:10]) and the B_10_POL_INV bit (PHY_STATUS_1 register, Address 0x001A). Pair swaps are reported in the pair swap register bit (PAIR_01_SWAP bit, Address 0x001A). When the link is up, the signal quality on each pair is indicated in the mean square error register for each pair (MSE_A register, Address 0x8402). When the link is down, the ADIN1200 can run cable fault detection using time domain reflectometry (TDR). By transmitting pulses and analyzing the reflections, the PHY can detect cable faults like opens, shorts, cross pair shorts, and the distance to the nearest fault. The PHY can also determine that the pair is well terminated and does not have any faults. Put the remote PHY in a power-down state or disconnect the PHY to run cable fault detection because remote PHY link pulses can interfere with the analysis of the reflected pulses and can return a pair busy result. The cable fault detection is automatically run on the two pairs looking at all combinations of pair faults by first putting the PHY in standby (clear the LINK_EN bit, PHY_CTRL_3 register, Address 0x0017) and then enabling the diagnostic clock (set the DIAG_CLK_EN bit, PHY_CTRL_1 register, Address 0x0012). Cable diagnostics can then be run (set the CDIAG_RUN bit in the CDIAG_RUN register, Address 0xBA1B). The results are reported for each pair in the cable diagnostics results registers, CDIAG_DTLD_RSLTS_0, CDIAG_DTLD_RSLTS_1, Addresses 0xBA1D and Address 0xBA1E). The distance to the first fault for each pair is reported in the cable fault distance registers, CDIAG_FLT_DIST_0, CDIAG_FLT_DIST_1, Addresses 0xBA21 and Addresses 0xBA22. If enhanced link detection is enabled, the ADIN1200 typically reacts to a break in the cable within 10 μs and indicates link down via the LINK_ST pin. If enhanced link detection is not enabled, the ADIN1200 follows the IEEE standard, and in 100BASE-TX, it can take more than either 350 ms or 750 ms. Enhanced link detection is enabled for 100BASE-TX via the enhanced link detection 100BASE-TX enable register bits (FLD_EN register, Address 0x8E27, Bit 5, Bit 3, and Bit 1). The latched status of the enhanced link detection function can be read via the enhanced link detection status bit, FAST_ LINK_DOWN_LAT (Address 0x8E38). START OF PACKET INDICATION The ADIN1200 includes the detection and indication of the start of packets (SOP) on the transmit and receive side to support IEEE 1588 time stamp controls and give the MAC more accurate timing information. The transmit and receive SOP indication can be made available at any of the following pins under software configuration: GP_CLK, LINK_ST, INT_N, and LED_0 using the following override control registers:     GE_IO_GP_CLK_OR_CNTRL bits, Address 0xFF3D GE_IO_GP_OUT_OR_CNTRL bits, Address 0xFF3E GE_IO_INT_N_OR_CNTRL bits, Address 0xFF3F GE_IO_LED_A_OR_CNTRL bits, Address 0xFF41 The detection of the transmit SOP is done after internal PHY FIFO. Therefore, there is a fixed delay between the SOP indication at the pin to the actual SOP at the MDI_x_x pins. Start of packet indication is enabled via the SOP transmit and receive enables, (set the SOP_TX_EN bit, and the SOP_RX_EN bit, Address 0x9428). The SOP is asserted by default on the first byte or nibble of the frame. The SOP can be configured to be asserted when the start frame delimitator (SFD) is detected in the frame by setting the SOP SFD enable bit (SOP_SFD_EN, Address 0x9428). Rev. 0 | Page 33 of 79 ADIN1200 Data Sheet The SOP indication, by default, is asserted for the duration of the frame. The SOP can be configured to be asserted for a programmable number of cycles. This is configured by setting the SOP N-cycle enable bit (SOP_NCYC_EN, Address 0x9428), and the number of cycles in this case is configured via the SOP N by 8 minus 1 cycles register (SOP_N_8_CYC_M_1_D_EN register, Address 0x9428, Bits[6:4]). The ADIN1200 start of packet detection and indication circuit includes the ability to delay each of the SOP transmit and receive indications by a programmable number of clock cycles. The purpose of this on the receive side is to support MAC interfaces with long latency so that the received frame SOP indication is not asserted before the MAC receives the frame. The purpose of this on the transmit side is to align the transmit SOP indication assertion close to the reference point set on the MDI_x_x pins (so that the time stamping point does not have to be adjusted at the MAC/switch side). There are programmable registers for the delays for 100BASE-TX mode, and 10BASE-T mode for transmit and receive. These are programmed via the SOP_RX_DEL register and SOP_TX_DEL register, Address 0x9429 and Address 0x942A, respectively. Rev. 0 | Page 34 of 79 Data Sheet ADIN1200 APPLICATIONS INFORMATION SYSTEM OVERVIEW REM SWITCH, fido5200 The ADIN1200 is a low power, single-port 10 Mbps/100 Mbps Ethernet transceiver with low latency specifications primarily designed for industrial Ethernet applications. Figure 30 shows a basic system block diagram with the fido5200 REM switch. Note that the MAC Interface section must be consulted for specific information on each MAC interface configuration mode. The fido5200 is a REM switch (programmable IEEE 802.3 10 Mbps/100 Mbps Ethernet Internet Protocol Version 6 (IPv6) and Internet Protocol Version 4 (IPv4)) that supports any Layer 2 or Layer 3 protocol. The switch can be personalized to support the desired protocol by firmware that is downloaded from a host processor. The fido5200 is configurable to support the following protocols: EtherCAT, PROFINET real time (RT) and isochronous real time (IRT), EtherNet/IP with and without device level ring (DLR), Modbus TCP, and POWERLINK. 3.3V 1.2V REGULATOR ADIN1200 PHY ADDRESS 1 HOST CONTROLLER HOST INTERFACE TIMERS fido5200 REM SWITCH PORT #1 MII MAC INTERFACE PHY AFE MANAGEMENT INTERFACE CLOCKING, POWER, LED ADIN1200 PHY ADDRESS 3 CLOCKING PORT 2 MII MAC INTERFACE MDIO PORT #1 MII MAC INTERFACE PHY AFE MANAGEMENT INTERFACE CLOCKING, POWER, LED MDI INTERFACE RJ45 TRAFFO Figure 30. Simplified Typical Application Block Diagram Rev. 0 | Page 35 of 79 RJ45 TRAFFO 21561-029 PORT 1 MII MAC INTERFACE MDI INTERFACE ADIN1200 Data Sheet MDIX Configuration DETAILED OVERVIEW OF fido5200 AND ADIN1200 Figure 31 shows more detail of the interconnection of the ADIN1200 and the fido5200. Some details are simplified. PHY Address The ADIN1200 has four PHY address pins. These pins are shared with the RXD_3 pin to the RXD_0 pin and are two-level configuration pins, providing the ability to configure 16 PHY addresses. In the ADIN1200, there are weak internal pull-down resistors on all PHYAD_x pins. In this application, to configure the ADIN1200 devices with differing addresses, external pull-up resistors are added to PHYAD_0 for one PHY and to PHYAD_0 (Address = 0x1) and PHYAD_1 for the second PHY (Address = 0x3). External resistors can also be added to PHYAD_2 and PHYAD_3 to pull them down externally. Review whether there is any circuitry hanging off these pins that may affect the expected PHY address setting. The MDI configuration is determined by the MDIX_MODE pin which is a shared function. This pin does not have an internal pull up. It is a multilevel sense pin and, therefore, four voltage level options for its configuration and must be configured with external resistors. For this configuration, the MDIX_MODE pins have external pull-up and pull-down resistors (value as listed in Table 20). Therefore, the auto MDIX mode is selected as shown in Table 26. This enables the device to automatically detect the appropriate MDI or MDIX configuration suited to the link partner. Table 26. Auto MDIX Configuration Configuration Manual MDI Manual MDIX Auto MDIX; Prefer MDIX Auto MDIX; Prefer MDI MDIX_MODE MODE_1 MODE_2 MODE_3 MODE_4 POWER SUPPLY MAC Interface The MAC interface selection is shared with the RX_CTL/RX_DV/ CRS_DV/MACIF_SEL1 pin and the RXC/RX_CLK/MACIF_ SEL0 pin and can be configured according to Table 25. To configure a MII interface, the MACIF_SEL1 = MODE_1 by pulling it to ground, while MACIF_SEL0 = MODE_4 by pulling it to VDDIO. Speed Configuration The PHY configuration pins are also shared pins. They have no internal pull-up resistors. Therefore, external resistors must be used to configure the appropriate function. These pins are multilevel sense pins, allowing four distinct voltage levels to be configured to provide a wider range of configuration, as discussed in the PHY Configuration section. The power supply requirements for the fido5200 and the ADIN1200 are two supply rails: a common 3.3 V rail shared with the switch and the PHYs and a 1.2 V rail for the switch. The ADIN1200 operates from a minimum of one power supply rail. The AVDD_3P3 is the 3.3 V analog power supply input for the PHY MDI interface, analog circuitry, XTAL oscillator, DLL, RESET_N, and LED circuitry. VDDIO enables the MDIO and MAC interface voltage supply to be configured independently of the other circuitry on the ADIN1200. VDDIO can be supplied from 1.8 V to 3.3 V. All devices must have local decoupling as close to the pins as possible. In Figure 31, PHY_CFG1 has an external pull-down resistor, configuring MODE_1 (0 V), while the PHY_CFG0 has a pullup resistor, configuring MODE_4 (3.3 V). This setup configures the PHY for autonegotiation with 10 HD/FD and 100 HD/FD advertised speeds, as shown in Table 23. When connected to a link partner, the device brings up a link with the highest common speed. The value of the resistors are as shown in Table 20. Rev. 0 | Page 36 of 79 Data Sheet 1.2V ADIN1200 3.3V PHY HARDWARE CONFIGURATION PULL-UP/DOWN VCC+1V2 MDI INTERFACE VCC+3V3 P1_ACTIVITY LE SIZE_32 LDO_CAP MDI_0_P P1_COL LED_0/COL/TX_ER/PHY_CFG0 P1_CRS INT_N/CRS P1_RXDV WE AVDD_3P3 LINK_ST/PHY_CFG1 P1_LINK_STATUS MBS VDDIO TO HOST CONTROLLER MDI_0_N RXC/RX_CLK/MACIF_SEL0 3.3V OE PORT 1 INT0 TO INT2 P1_RXD0 P1_RXD1 P1_RXD2 P1_RXD3 P1_TXCLK A02 TO A05 HOST INTERFACE 32 D00 TO D31 RXD_0/PHYAD_0 RXD_1/PHYAD_1 RXD_2/PHYAD_2 RXD_3/PHYAD_3 MII MAC INTERFACE P1_TXEN ADIN1200 10M/100MB ETHERNET PHY PHY ADDRESS 1 TXC/TX_CLK P1_TXD0 TX_CTL/TX_EN TXD_0 P1_TXD1 P1_TXD2 TXD_1 TXD_2 P1_TXD3 TXD_3 RESET_N 4 CLKOUT FROM HOST CONTROLLER REXT 3.01kΩ GP_CLK/RX_ER/MDIX_MODE RESET MANAGEMENT INTERFACE (HOST CONTROLLER) MDIO MDC XTAL_I/CLK_IN/REF_CLK XTAL_O TIMER 0 – 7 XTAL0 fido5200 REM SWITCH 3.3V MDI INTERFACE P2_ACTIVITY VDDIO TO HOST CONTROLLER P2_LINK_STATUS AVDD_3P3 LDO_CAP LINK_ST/PHY_CFG1 P2_COL LED_0/COL/TX_ER/PHY_CFG0 P2_CRS INT_N/CRS P2_RXDV MDI_0_P MDI_0_N RJ45 MDI_1_P MDI_1_N TRAFFO RX_CTL/RX_DV/CRS_DV/MACIFSEL1 P2_RXCLK RXC/RX_CLK/MACIF_SEL0 3.3V PORT 2 P2_RXD0 P2_RXD1 P2_RXD2 P2_RXD3 P2_TXCLK RXD_0/PHYAD_0 RXD_1/PHYAD_1 RXD_2/PHYAD_2 RXD_3/PHYAD_3 MII MAC INTERFACE ADIN1200 10M/100MB ETHERNET PHY PHY ADDRESS 3 MANAGEMENT INTERFACE (HOST CONTROLLER) MDIO MDC TXC/TX_CLK P2_TXEN TX_CTL/TX_EN P2_TXD0 TXD_0 P2_TXD1 TXD_1 P2_TXD2 TXD_2 P2_TXD3 TXD_3 GP_CLK/RX_ER/MDIX_MODE RESET_N FROM HOST CONTROLLER REXT 3.01kΩ XTAL_I/CLK_IN/REF_CLK PHY HARDWARE CONFIGURATION PULL-UP/DOWN XTAL_O Figure 31. Detailed Block Diagram of the fido5200 with Two ADIN1200 PHYs Rev. 0 | Page 37 of 79 21561-101 4 TRAFFO RX_CTL/RX_DV/CRS_DV/MACIFSEL1 P1_RXCLK CS 3 RJ45 MDI_1_P MDI_1_N ADIN1200 Data Sheet COMPONENT RECOMMENDATIONS Crystal The typical connection for an external crystal (XTAL) is shown in Figure 32. To ensure minimum current consumption and to minimize stray capacitances, make connections between the crystal, capacitors, and ground as close to the ADIN1200 as possible. Consult individual crystal vendors for recommended load information and crystal performance specifications. 25MHz ADIN1200 21561-035 XTAL_O 12pF XTAL_I 12pF Figure 32. Crystal Oscillator Connection External Clock Input If using a single-ended reference clock on XTAL_I/CLK_IN/ REF_CLK, leave XTAL_O open-circuit. This clock must be a unipolar 2.5 V, 25 MHz sinewave or square-wave signal. The CLK_IN can also be driven by a 1.8 V square wave signal. When using the RMII MAC interface, a 50 MHz reference clock (REF_CLK) is required. This clock can be sourced from the MAC or from an external source. The magnetics can be discrete or integrated and there are strengths and weaknesses to both. Choosing the discrete option typically occupies more board space, but gives more freedom in terms of layout, tends to be cheaper than integrated magnetics, and offers better performance overall. The integrated approach is a combined RJ45 connector jack with the magnetics built in, which provides a more compact solution due to fewer components and, in applications where space is at a premium, condenses the required footprint, but tends to cost more. Magnetics cores tend to be smaller and closer to each other, which can compromise EMC performance, increase the likelihood of crosstalk, and have impacts on performance by increasing losses and introducing nonlinear distortion. For optimum performance, a discrete transformer with integrated common-mode choke is recommended for use with the ADIN1200 PHY. The common-mode choke is important because it attenuates any common-mode signals picked up by the twisted pair cable from the environment, improving the signal-to-noise ratio of the system. Transformers with an autotransformer stage following the common-mode choke provide additional attenuation of common-mode noise. The ADIN1200 transmit drivers are voltage mode with on-chip terminations. Therefore, connect each of the center tap pins on the transformer on the ADIN1200 side separately to ground through a 0.1 μF capacitor. 0.1µF 75Ω 0.001µF ADIN1200 XTAL_O HX1260NL TX+ MDI_0_P MDI_0_N MDI_1_P MDI_1_N RJ45 1 TX– Figure 33. External Clock Connection TRANSFORMER1 Magnetics 1ONLY ONE CHANNEL SHOWN Galvanic isolation is necessary between any two point to point communication nodes in applications using the Ethernet protocol to transmit/receive data to protect against faults and transients, and achieve the best electromagnetic compatibility performance. Magnetic coupling between the PHY and the RJ45 is the most common way of achieving this isolation. 21561-037 ADIN1200 21561-036 XTAL_I PHY1 MCT Figure 34. Isolation Using Discrete Magnetics, Only One Channel Shown, Each Channel has Separate Components to Ground The key considerations for the magnetics are outlined in Table 27. Table 27. Magnetics Selection Parameter Turns Ratio Open-Circuit Inductance Insertion loss Rev. 0 | Page 38 of 79 Value 1CT:1CT 350 μH −1 dB Conditions Min: 100 mV, 100 kHz, 8 mA Max: 0 MHz to 100 MHz Data Sheet ADIN1200 The following simplified system level power solutions show three recommended arrangements for powering the ADIN1200 PHY and companion two-port switch (note that depending on the choice of the two-port switch, there may be differing power supply requirements to what is shown). POWER REQUIREMENTS The ADIN1200 has the following two power supply domains and requires a minimum of one supply source: SUPPLY DECOUPLING It is recommended to decouple each of the AVDD_3P3 and VDDIO supply pins with 0.1 μF in parallel with 0.01 μF capacitors to ground. Place decoupling capacitors as close to the relevant pins as possible and ensure that the capacitor ground is routed directly into the plane. There are no power supply sequencing requirements around the order of power being applied to the device. See the Power-Up Timing section for more details. 3.3V ADP51331 DUAL, 800mA BUCK REGULATOR VOUT1 VOUT2 1.8V 0.9V AVDD_3P3 VDDIO ADIN1200 PORT 1 TWO-PORT SWITCH 10Mbps/100Mbps PORT 2 10Mbps/100Mbps ETHERNET PHY AVDD_3P3 VDDIO ADIN1200 10Mbps/100Mbps ETHERNET PHY 21561-039  AVDD_3P3 is the 3.3 V analog power supply input for the PHY MDI interface, analog circuitry, crystal oscillator, DLL, RESET_N, and LED circuitry. VDDIO enables the MDIO and MAC interface voltage supply to be configured independently of the other circuitry on the ADIN1200. 1ALTERNATIVES ARE ADP5023 OR ADP5024 (WITH LDO CHANNEL). Figure 35. Recommended Power Solution for 3.3 V with RGMII Operating at VDDIO = 1.8 V 24V ADP24412 36V, 1A BUCK REGULATOR 5V ADP51331 DUAL, 800mA BUCK REGULATOR VOUT1 VOUT2 3.3V 1.2V AVDD_3P3 VDDIO ADIN1200 PORT 1 fido5200 TWO-PORT SWITCH 10Mbps/100Mbps PORT 2 1ALTERNATIVES 2ALTERNATIVES 10Mbps/100Mbps ETHERNET PHY AVDD_3P3 VDDIO ADIN1200 10Mbps/100Mbps ETHERNET PHY ARE ADP5023 OR ADP5024 (WITH LDO CHANNEL). ARE ADP2443, 3A CAPABLE. 21561-040  Figure 36. Recommended Power Solution with 24 V System Power, with fido5200, Where MII Is Operating at VDDIO = 3.3 V Rev. 0 | Page 39 of 79 ADIN1200 Data Sheet 3.3V/ 2.5V/ 1.8V 3.3V 0.1µF 0.01µF 0.1µF 0.01µF VDDIO AVDD_3P3 0.1µF 0.01µF 0.1µF 0.01µF AVDD_3P3 ADIN1200 LDO_CAP 0.1µF Figure 37. Supply Decoupling Overview Rev. 0 | Page 40 of 79 21561-042 VDDIO Data Sheet ADIN1200 REGISTER SUMMARY The MII management interface provides a 2-wire serial interface between a host processor or MAC and the ADIN1200 allowing access to control and status information in the subsystem and PHY core management registers. The interface is compatible with both IEEE Standard 802.3 Clause 22 and Clause 45 management frame structures. The device supplements the registers specified in IEEE Standard 802.3 with an additional set of registers that are accessed indirectly. These registers are referred to as extended management interface (EMI) registers. The EMI registers can be accessed using the interface specified under Clause 45. However, for systems that do not support this interface, an alternative access mechanism is provided using the interface specified under Clause 22. The PHY Core Register Summary section and the Subsystem Register Summary section list the PHY core and subsystem registers. PHY CORE REGISTER SUMMARY The PHY core registers are made up of the following three register groupings:    0x0000 to 0x000F, IEEE standard registers 0x0010 to 0x001F, vendor specific registers PHY core EMI registers at Device Address 0x1E The IEEE standard registers and vendor specific registers are accessed using Clause 22 access, and the EMI registers are accessed using Clause 45 access. The ADIN1200 supports the IEEE Clause 45 MDIO manageable device (MMD) registers associated with EEE. These registers are all remapped to the Device Address 0x1E. Therefore, they are available at the same device address as the rest of the PHY extended management registers. For systems that do not support the interface specified under Clause 45, the EMI registers can be accessed using Clause 22 access via Register 0x0010 and Register 0x0011. The default value of some of the registers are determined by the value of the hardware configuration pins, which are read just after the RESET_N pin is deasserted (see the Hardware Configuration Pins section). This allows the default operation of the ADIN1200 to be configured in unmanaged applications. The default values in Table 28 assume the ADIN1200 is configured as follows:       Auto MDIX, prefer MDI Autonegotiation enabled All speeds advertised EEE, energy detect power-down, and downspeed disabled ADIN1200 is not configured to enter software power-down after reset RGMII MAC interface selected with 2 ns internal delay on RXC and TXC Table 28. PHY Core Register Summary Address 0x0000 0x0001 0x0002 0x0003 0x0004 0x0005 0x0006 0x0007 0x0008 0x000A 0x000F 0x0010 0x0011 0x0012 0x0013 0x0014 0x0015 0x0016 0x0017 0x0018 0x0019 0x001A 0x001B 0x001C 0x001D Name MII_CONTROL MII_STATUS PHY_ID_1 PHY_ID_2 AUTONEG_ADV LP_ABILITY AUTONEG_EXP TX_NEXT_PAGE LP_RX_NEXT_PAGE MSTR_SLV_STATUS EXT_STATUS EXT_REG_PTR EXT_REG_DATA PHY_CTRL_1 PHY_CTRL_STATUS_1 RX_ERR_CNT PHY_CTRL_STATUS_2 PHY_CTRL_2 PHY_CTRL_3 IRQ_MASK IRQ_STATUS PHY_STATUS_1 LED_CTRL_1 LED_CTRL_2 LED_CTRL_3 Description MII Control Register. MII Status Register. PHY Identifier 1 Register. PHY Identifier 2 Register. Autonegotiation Advertisement Register. Autonegotiation Link Partner Base Page Ability Register. Autonegotiation Expansion Register. Autonegotiation Next Page Transmit Register. Autonegotiation Link Partner Received Next Page Register. Master Slave Status Register. Extended Status Register. Extended Register Pointer Register. Extended Register Data Register. PHY Control 1 Register. PHY Control Status 1 Register. Receive Error Count Register. PHY Control Status 2 Register. PHY Control 2 Register. PHY Control 3 Register. Interrupt Mask Register. Interrupt Status Register. PHY Status 1 Register. LED Control 1 Register. LED Control 2 Register. LED Control 3 Register. Rev. 0 | Page 41 of 79 Reset 0x1000 0x7949 0x0282 0xBC20 0x01E1 0x0000 0x0064 0x2001 0x0000 0x0000 0x0000 0x0000 0x0000 0x0002 0x1041 0x0000 0x0000 0x0308 0x3048 0x0000 0x0000 0x0300 0x0001 0x210A 0x1855 Access R/W R R R R/W R R R/W R R R R/W R/W R/W R/W R R/W R/W R/W R/W R R R/W R/W R/W ADIN1200 Address 0x001D 0x001F 0x8000 0x8001 0x8002 0x8008 0x8402 0x8E27 0x8E38 0x9400 0x9401 0x9403 0x9406 0x9407 0x9408 0x940A 0x940B 0x940C 0x940D 0x940E 0x940F 0x9410 0x9411 0x9412 0x9413 0x9414 0x9415 0x9416 0x9417 0x9418 0x941A 0x941B 0x941C 0x941D 0x941E 0x9427 0x9428 0x9429 0x942A 0x9602 0xA000 0xB403 0xB412 0xB413 0xBA1B 0xBA1C 0xBA1D 0xBA1E 0xBA21 0xBA22 0xBA25 0xBC00 Name LED_CTRL_3 PHY_STATUS_2 EEE_CAPABILITY EEE_ADV EEE_LP_ABILITY EEE_RSLVD MSE_A FLD_EN FLD_STAT_LAT RX_MII_CLK_STOP_EN PCS_STATUS_1 FC_EN FC_IRQ_EN FC_TX_SEL FC_MAX_FRM_SIZE FC_FRM_CNT_H FC_FRM_CNT_L FC_LEN_ERR_CNT FC_ALGN_ERR_CNT FC_SYMB_ERR_CNT FC_OSZ_CNT FC_USZ_CNT FC_ODD_CNT FC_ODD_PRE_CNT FC_DRIBBLE_BITS_CNT FC_FALSE_CARRIER_CNT FG_EN FG_CNTRL_RSTRT FG_CONT_MODE_EN FG_IRQ_EN FG_FRM_LEN FG_IFG_LEN FG_NFRM_H FG_NFRM_L FG_DONE FIFO_SYNC SOP_CTRL SOP_RX_DEL SOP_TX_DEL DPTH_MII_BYTE LPI_WAKE_ERR_CNT B_10_E_EN B_10_TX_TST_MODE B_100_TX_TST_MODE CDIAG_RUN CDIAG_XPAIR_DIS CDIAG_DTLD_RSLTS_0 CDIAG_DTLD_RSLTS_1 CDIAG_FLT_DIST_0 CDIAG_FLT_DIST_1 CDIAG_CBL_LEN_EST LED_PUL_STR_DUR Data Sheet Description LED Control 3 Register. PHY Status 2 Register. Energy Efficient Ethernet Capability Register. Energy Efficient Ethernet Advertisement Register. Energy Efficient Ethernet Link Partner Ability Register. Energy Efficient Ethernet Resolved Register. Mean Square Error A Register. Enhanced Link Detection Enable Register. Enhanced Link Detection Latched Status Register. Receive MII Clock Stop Enable Register. Physical Coding Sublayer (PCS) Status 1 Register. Frame Checker Enable Register. Frame Checker Interrupt Enable Register. Frame Checker Transmit Select Register. Frame Checker Maximum Frame Size Register. Frame Checker Count High Register. Frame Checker Count Low Register. Frame Checker Length Error Count Register. Frame Checker Alignment Error Count Register. Frame Checker Symbol Error Counter Register. Frame Checker Oversized Frame Count Register. Frame Checker Undersized Frame Count Register. Frame Checker Odd Nibble Frame Count Register. Frame Checker Odd Preamble Packet Count Register. Frame Checker Dribble Bits Frame Count Register. Frame Checker False Carrier Count Register. Frame Generator Enable Register. Frame Generator Control and Restart Register. Frame Generator Continuous Mode Enable Register. Frame Generator Interrupt Enable Register. Frame Generator Frame Length Register. Frame Generator Interframe Gap Length Register. Frame Generator Number of Frames High Register. Frame Generator Number of Frames Low Register. Frame Generator Done Register. FIFO Sync Register. Start of Packet Control Register. Start of Packet Receive Detection Delay Register. Start of Packet Transmit Detection Delay Register. Control of FIFO Depth for MII Modes Register. LPI Wake Error Count Register. Base 10e Enable Register. 10BASE-T Transmit Test Mode Register. 100BASE-TX Transmit Test Mode Register. Run Automated Cable Diagnostics Register. Cable Diagnostics Cross Pair Fault Checking Disable Register. Cable Diagnostics Results 0 Register. Cable Diagnostics Results 1 Register. Cable Diagnostics Fault Distance Pair 0 Register. Cable Diagnostics Fault Distance Pair 1 Register. Cable Diagnostics Cable Length Estimate Register. LED Pulse Stretching Duration Register. Rev. 0 | Page 42 of 79 Reset 0x1855 0x03FC 0x0006 0x0000 0x0000 0x0000 0x0000 0x003D 0x0000 0x0400 0x0040 0x0001 0x0001 0x0000 0x05F2 0x0000 0x0000 0x0000 0x0000 0x0000 0x0000 0x0000 0x0000 0x0000 0x0000 0x0000 0x0000 0x0001 0x0000 0x0000 0x006B 0x000C 0x0000 0x0100 0x0000 0x0000 0x0034 0x0000 0x0000 0x0001 0x0000 0x0001 0x0000 0x0000 0x0000 0x0000 0x0000 0x0000 0x00FF 0x00FF 0x00FF 0x0011 Access R/W R R R/W R R R R/W R R/W R R/W R/W R/W R/W R R R R R R R R R R R R/W R/W R/W R/W R/W R/W R/W R/W R R/W R/W R/W R/W R/W R R/W R/W R/W R/W R/W R R R R R R/W Data Sheet ADIN1200 PHY CORE REGISTER DETAILS MII Control Register Address: 0x0000, Reset: 0x1000, Name: MII_CONTROL This address corresponds to the MII control register specified in Clause 22.2.4.1 of Standard 802.3. Note that the default reset value of this register is dependent on the hardware configuration pins settings. Table 29. Bit Descriptions for MII_CONTROL Bits 15 Bit Name SFT_RST 14 LOOPBACK 13 SPEED_SEL_LSB 12 AUTONEG_EN 11 SFT_PD 10 ISOLATE 9 RESTART_ANEG 8 DPLX_MODE 7 COLTEST 6 SPEED_SEL_MSB 5 UNIDIR_EN [4:0] RESERVED Description Software Reset Bit. Note that this bit is self clearing. When the reset operation is complete, this bit returns to 1'b0. 1: PHY reset. 0: normal operation. Enable/Disable Loopback Mode. 1: enable loopback mode. 0: disable loopback mode. The speed selection MSB and LSB register bits are used to configure the link speed. Note that the default value of this register bit is configurable via the hardware configuration pins. This allows the default operation of the PHY to be configured in unmanaged applications. 11: reserved. 10: reserved. 01: 100 Mbps. 00: 10 Mbps. The autonegotiation enable bit is used to enable/disable autonegotiation. Note that the default value of this register bit is configurable via the hardware configuration pins. This allows the default operation of the PHY to be configured in unmanaged applications. 1: enable autonegotiation process. 0: disable autonegotiation process. Software Power-Down Bit. Note that the default value of this register bit is configurable via the hardware configuration pins. The PHY can be held in reset until initialized by the software. 1: software power-down. 0: normal operation. Isolate Bit. 1: electrically isolate PHY from MAC interface by setting MAC interface pins to tristate (even if active). 0: normal operation. Restart Autonegotiation Bit. Note that this bit is self clearing. When the autonegotiation process is restarted, this bit returns to 1'b0. 1: restart the autonegotiation process. 0: normal operation. Duplex Mode Bit. 1: full duplex. 0: half duplex. Collision Test Bit. 1: enable collision signal test. 0: disable collision signal test. See SPEED_SEL_LSB Bit Description. 11: reserved. 10: reserved. 01: 100 Mbps. 00: 10 Mbps. The unidirectional enable register bit is read only and always reads as 1'b0. Transmission from the media independent interface is only enabled when the PHY has determined that a valid link has been established. Reserved. Rev. 0 | Page 43 of 79 Reset 0x0 Access R/W 0x0 R/W 0x0 R/W 0x1 R/W 0x0 R/W 0x0 R/W 0x0 R/W 0x0 R/W 0x0 R/W 0x0 R/W 0x0 R 0x0 R ADIN1200 Data Sheet MII Status Register Address: 0x0001, Reset: 0x7949, Name: MII_STATUS This address corresponds to the MII status register specified in Clause 22.2.4.2 of IEEE Standard 802.3. Table 30. Bit Descriptions for MII_STATUS Bits 15 Bit Name T_4_SPRT 14 FD_100_SPRT 13 HD_100_SPRT 12 FD_10_SPRT 11 HD_10_SPRT 10 FD_T_2_SPRT 9 HD_T_2_SPRT 8 EXT_STAT_SPRT 7 UNIDIR_ABLE 6 MF_PREAM_SUP_ABLE 5 AUTONEG_DONE 4 REM_FLT_LAT 3 AUTONEG_ABLE 2 LINK_STAT_LAT 1 JABBER_DET_LAT 0 EXT_CAPABLE Description The 100BASE-T4 ability bit always reads as 1'b0 because the PHY does not support 100BASE-T4. The 100BASE-TX full duplex ability bit always reads as 1'b1 because the PHY supports 100BASE-TX full duplex. The 100BASE-TX half duplex ability bit always reads as 1'b1 because the PHY supports 100BASE-TX half duplex. The 10BASE-T full duplex ability bit always reads as 1'b1 because the PHY supports 10BASE-T full duplex. The 10BASE-T half duplex ability bit always reads as 1'b1 because the PHY supports 10BASE-T half duplex. The 100BASE-T2 full duplex ability bit always reads as 1'b0 because the PHY does not support 100BASE-T2. The 100BASE-T2 half duplex ability bit always reads as 1'b0 because the PHY does not support 100BASE-T2. The extended status support bit always reads as 1'b1, indicating that the PHY provides extended status information in Register 0x000F. When zero, the unidirectional ability register bit indicates that the PHY can only transmit data from the media independent interface when it has determined that a valid link has been established. This bit always reads as 1'b0. Management Frame Preamble Suppression Ability Bit. This always reads as 1'b1 because the PHY accepts management frames with preamble suppressed. Autonegotiation Complete Bit. 1: autonegotiation process completed. 0: autonegotiation process not completed. Remote Fault Bit. When this bit goes high, it latches high until it is unlatched by reading. 1: remote fault condition detected. 0: no remote fault condition detected. Autonegotiation Ability Bit. This bit always reads as 1'b1. 1: PHY is able to perform autonegotiation. 0: PHY is not able to perform autonegotiation. Link Status Bit. If the link subsequently drops, this bit latches low until it is unlatched by reading. 1: link is up. 0: link is down. Jabber Detect Bit. When this bit goes high, it latches high until it is unlatched by reading. 1: jabber condition detected. 0: no jabber condition detected. The extended capability bit always reads as 1'b1 because the PHY provides an extended set of capabilities. Rev. 0 | Page 44 of 79 Reset 0x0 Access R 0x1 R 0x1 R 0x1 R 0x1 R 0x0 R 0x0 R 0x1 R 0x0 R 0x1 R 0x0 R 0x0 R 0x1 R 0x0 R 0x0 R 0x1 R Data Sheet ADIN1200 PHY Identifier 1 Register Address: 0x0002, Reset: 0x0283, Name: PHY_ID_1 This address corresponds to the MII status register specified in Clause 22.2.4.3.1 of IEEE Standard 802.3 and allows 16 bits of the organizationally unique identifier (OUI) to be observed. Table 31. Bit Descriptions for PHY_ID_1 Bits [15:0] Bit Name PHY_ID_1 Description Organizationally Unique Identifier Bits[3:18]. Reset 0x283 Access R PHY Identifier 2 Register Address: 0x0003, Reset: 0xBC20, Name: PHY_ID_2 This address corresponds to the MII status register specified in Clause 22.2.4.3.1 of IEEE Standard 802.3 and allows 6 bits of the OUI along with the model number and revision number to be observed. Table 32. Bit Descriptions for PHY_ID_2 Bits [15:10] [9:4] [3:0] Bit Name PHY_ID_2_OUI MODEL_NUM REV_NUM Description Organizationally Unique Identifier Bits[19:24]. Manufacturer Model Number. Manufacturer Revision Number. Reset 0x2F 0x2 0x0 Access R R R Autonegotiation Advertisement Register Address: 0x0004, Reset: 0x01E1, Name: AUTONEG_ADV This address corresponds to the autonegotiation advertisement register specified in Clause 28.2.4.1.3 of IEEE Standard 802.3. Note that the default reset value of this register is dependent on the hardware configuration pins settings. Table 33. Bit Descriptions for AUTONEG_ADV Bits 15 Bit Name NEXT_PAGE_ADV 14 13 RESERVED REM_FLT_ADV 12 EXT_NEXT_PAGE_ADV 11 APAUSE_ADV 10 PAUSE_ADV 9 T_4_ADV 8 FD_100_ADV Description Next page exchange occurs after the base link code words have been exchanged. Next page exchange consists of using the normal autonegotiation arbitration process to send next page messages. Next page transmission ends when both ends of a link segment set their next page bits to Logic 0, indicating that neither has anything additional to transmit. Reserved. The remote fault bit provides a standard transport mechanism for the transmission of simple fault information. The extended next page bit indicates that the local device supports transmission of extended next pages. The use of extended next page is orthogonal to the negotiated data rate, medium, or link technology. The technology ability field is a 7-bit wide field (Bits[11:5] within this register) containing information indicating supported technologies specific to the selector field value. This bit is to advertise asymmetric pause operation for full duplex links. The technology ability field is a 7-bit wide field (Bits[11:5] within this register) containing information indicating supported technologies specific to the selector field value. This bit is to advertise pause operation for full duplex links. The technology ability field is a 7-bit wide field (Bits[11:5] within this register) containing information indicating supported technologies specific to the selector field value. This bit is to advertise 100BASE-T4 and always reads as 1'b0 because this technology is not supported. The technology ability field is a 7-bit wide field (Bits[11:5] within this register) containing information indicating supported technologies specific to the selector field value. This bit is to advertise 100BASE-TX full duplex. Note that the default value of this register bit is configurable via the hardware configuration pins, which allows the default operation of the PHY to be configured in unmanaged applications. Rev. 0 | Page 45 of 79 Reset 0x0 Access R/W 0x0 0x0 R R/W 0x0 R/W 0x0 R/W 0x0 R/W 0x0 R 0x1 R/W ADIN1200 Bits 7 Bit Name HD_100_ADV 6 FD_10_ADV 5 HD_10_ADV [4:0] SELECTOR_ADV Data Sheet Description The technology ability field is a 7-bit wide field (Bits[11:5] within this register) containing information indicating supported technologies specific to the selector field value. This bit is to advertise 100BASE-TX half duplex. Note that the default value of this register bit is configurable via the hardware configuration pins, which allows the default operation of the PHY to be configured in unmanaged applications. The technology ability field is a 7-bit wide field (Bits[11:5] within this register) containing information indicating supported technologies specific to the selector field value. This bit is to advertise 10BASE-T full duplex. Note that the default value of this register bit is configurable via the hardware configuration pins, which allows the default operation of the PHY to be configured in unmanaged applications. The technology ability field is a 7-bit wide field (Bits[11:5] within this register) containing information indicating supported technologies specific to the selector field value. This bit is to advertise 10BASE-T half duplex. Note that the default value of this register bit is configurable via the hardware configuration pins, which allows the default operation of the PHY to be configured in unmanaged applications. Selector field is a 5-bit wide field, encoding 32 possible messages. This field always reads as 1'b1, indicating that the PHY only supports IEEE Standard 802.3. Reset 0x1 Access R/W 0x1 R/W 0x1 R/W 0x1 R/W Reset 0x0 Access R 0x0 R 0x0 R 0x0 R 0x0 R 0x0 R 0x0 R 0x0 R 0x0 R 0x0 R Autonegotiation Link Partner Base Page Ability Register Address: 0x0005, Reset: 0x0000, Name: LP_ABILITY This address corresponds to the link partner ability register specified in Clause 28.2.4.1.4 of IEEE Standard 802.3. Table 34. Bit Descriptions for LP_ABILITY Bits 15 Bit Name LP_NEXT_PAGE 14 LP_ACK 13 LP_REM_FLT 12 LP_EXT_NEXT_PAGE_ABLE 11 LP_APAUSE_ABLE 10 LP_PAUSE_ABLE 9 LP_T_4_ABLE 8 LP_FD_100_ABLE 7 LP_HD_100_ABLE 6 LP_FD_10_ABLE Description Link Partner Next Page Bit. Next page exchange occurs after the base link code words have been exchanged. Next page exchange consists of using the normal autonegotiation arbitration process to send next page messages. Next page transmission ends when both ends of a link segment set their next page bits to Logic 0, indicating that neither has anything additional to transmit. This bit is used by the internal handshaking in autonegotiation and must be ignored. 1: link partner has successfully received its link code word. 0: link partner has not received its link code word. The link partner remote fault bit provides a standard transport mechanism for the transmission of simple fault information. The link partner extended next page bit indicates that the link partner supports transmission of extended next page. The use of extended next page is orthogonal to the negotiated data rate, medium, or link technology. The technology ability field is a 7-bit wide field (Bits[11:5] within this register) containing information indicating supported technologies specific to the selector field value. This bit indicates that the link partner advertises asymmetric pause operation for full duplex links. The technology ability field is a 7-bit wide field (Bits[11:5] within this register) containing information indicating supported technologies specific to the selector field value. This bit indicates that the link partner advertises pause operation for full duplex links. The technology ability field is a 7-bit wide field (Bits[11:5] within this register) containing information indicating supported technologies specific to the selector field value. This bit indicates that the link partner advertises 100BASE-T4. The technology ability field is a 7-bit wide field (Bits[11:5] within this register) containing information indicating supported technologies specific to the selector field value. This bit indicates that the link partner advertises 100BASE-TX full duplex. The technology ability field is a 7-bit wide field (Bits[11:5] within this register) containing information indicating supported technologies specific to the selector field value. This bit indicates that the link partner advertises 100BASE-TX half duplex. The technology ability field is a 7-bit wide field (Bits[11:5] within this register) containing information indicating supported technologies specific to the selector field value. This bit indicates that the link partner advertises 10BASE-T full duplex. Rev. 0 | Page 46 of 79 Data Sheet Bits 5 Bit Name LP_HD_10_ABLE [4:0] LP_SELECTOR ADIN1200 Description The technology ability field is a 7-bit wide field (Bits[11:5] within this register) containing information indicating supported technologies specific to the selector field value. This bit indicates that the link partner advertises 10BASE-T half duplex. Link Partner Selector Field. This is a 5-bit wide field, encoding 32 possible messages. The value 0x1 indicates IEEE Standard 802.3. Reset 0x0 Access R 0x0 R Reset 0x0 0x1 Access R R 0x1 R 0x0 R 0x0 R 0x1 R 0x0 R 0x0 R Autonegotiation Expansion Register Address: 0x0006, Reset: 0x0064, Name: AUTONEG_EXP This address corresponds to the autonegotiation expansion register specified in Clause 28.2.4.1.5 of IEEE Standard 802.3. Table 35. Bit Descriptions for AUTONEG_EXP Bits [15:7] 6 Bit Name RESERVED RX_NP_LOC_ABLE 5 RX_NP_LOC 4 PAR_DET_FLT 3 LP_NP_ABLE 2 NP_ABLE 1 PAGE_RX_LAT 0 LP_AUTONEG_ABLE Description Reserved. The received next page location ability bit always reads as 1'b1 because received next pages are stored in Register 0x0008. 1: received next page storage location is specified by Bit 5 (RX_NP_LOC). 0: received next page storage location is not specified by Bit 5 (RX_NP_LOC). The received next page location bit always reads as 1'b1. 1: link partner next pages are stored in Register 0x0008. 0: link partner next pages are stored in Register 0x0005. Parallel Detection Fault Bit. When this bit goes high, it latches high until it is unlatched by reading. 1: a fault has been detected via the parallel detection function. 0: a fault has not been detected via the parallel detection function. Link Partner Next Page Ability Bit. 1: link partner is next page capable. 0: link partner is not next page capable. The next page ability bit always reads as 1'b1, indicating that the PHY supports next pages. 1: local device is next page capable. 0: local device is not next page capable. Page Received Bit. When this bit goes high, it latches high until it is unlatched by reading. 1: a new page has been received. 0: a new page has not been received. Link Partner Autonegotiation Ability Bit. 1: link partner is autonegotiation capable. 0: link partner is not autonegotiation capable. Autonegotiation Next Page Transmit Register Address: 0x0007, Reset: 0x2001, Name: TX_NEXT_PAGE This address corresponds to the autonegotiation next page transmit register specified in Clause 28.2.4.1.6 of IEEE Standard 802.3. Table 36. Bit Descriptions for TX_NEXT_PAGE Bits 15 Bit Name NP_NEXT_PAGE 14 13 RESERVED NP_MSG_PAGE 12 NP_ACK_2 11 NP_TOGGLE Description Next page (NP) is used by the next page function to indicate that additional next page(s) follow. Otherwise, this is the last next page to be transmitted. Reserved. Message page (MP) is used by the next page function to indicate that this is a message page. Otherwise, this is an unformatted page. Acknowledge 2 (Ack2) is used by the next page function to indicate that a device has the ability to comply with the message. Toggle (T) is used by the arbitration function to ensure synchronization with the link partner during next page exchange. This bit always takes the opposite value of the toggle bit in the previously exchanged link code word. Rev. 0 | Page 47 of 79 Reset 0x0 Access R/W 0x0 0x1 R R/W 0x0 R/W 0x0 R ADIN1200 Bits [10:0] Bit Name NP_CODE Data Sheet Description Message code field is an 11-bit wide field, encoding 2048 possible messages. If the message page bit is set to Logic 0, the bit encoding of the link code word is interpreted as an unformatted page. Reset 0x1 Access R/W Autonegotiation Link Partner Received Next Page Register Address: 0x0008, Reset: 0x0000, Name: LP_RX_NEXT_PAGE This address corresponds to the autonegotiation link partner received next page register specified in Clause 28.2.4.1.7 of IEEE Standard 802.3. Table 37. Bit Descriptions for LP_RX_NEXT_PAGE Bits 15 Bit Name LP_NP_NEXT_PAGE 14 LP_NP_ACK 13 LP_NP_MSG_PAGE 12 LP_NP_ACK_2 11 LP_NP_TOGGLE [10:0] LP_NP_CODE Description Link partner next page (NP) is used by the next page function to indicate that the link partner sends additional next page(s). Otherwise, this is the last next page to be transmitted. This bit is used by the internal handshaking in autonegotiation and must be ignored. 1: link partner has successfully received its link code word. 0: link partner has not received its link code word. Link partner message page (MP) is used by the next page function to indicate that this is a message page. Otherwise, this is an unformatted page. Acknowledge 2 (Ack2) is used by the next page function to indicate that the link partner has the ability to comply with the message. Link partner toggle (T) is used by the arbitration function to ensure synchronization with the link partner during the next page exchange. This bit always takes the opposite value of the toggle bit in the previously exchanged link code word. Link partner message code field is an 11-bit wide field, encoding 2048 possible messages. If the message page bit is set to Logic 0, the bit encoding of the link code word is interpreted as an unformatted page. Reset 0x0 Access R 0x0 R 0x0 R 0x0 R 0x0 R 0x0 R Master Slave Status Register Address: 0x000A, Reset: 0x0000, Name: MSTR_SLV_STATUS This address corresponds to the master slave status register specified in Clause 40.5.1.1 of IEEE Standard 802.3. Table 38. Bit Descriptions for MSTR_SLV_STATUS Bits [15:14] 13 Bit Name RESERVED LOC_RCVR_STATUS 12 REM_RCVR_STATUS 11 LP_FD_1000_ABLE 10 LP_HD_1000_ABLE [9:8] [7:0] RESERVED IDLE_ERR_CNT Description Reserved. Local Receiver Status Bit. Defined by the value of LOC_RCVR_STATUS, as described in Clause 40.4.5.1 of IEEE Standard 802.3. 1: local receiver okay (LOC_RCVR_STATUS = okay). 0: local receiver not okay (LOC_RCVR_STATUS = not okay). Remote Receiver Status Bit. Defined by the value of REM_RCVR_STATUS as, described in Clause 40.4.5.1 of IEEE Standard 802.3. 1: remote receiver okay (REM_RCVR_STATUS = okay). 0: remote receiver not okay (REM_RCVR_STATUS = not okay). Link Partner 1000BASE-T Full Duplex Ability Bit. This bit is guaranteed to be valid only when the PAGE_RX_LAT bit (Register 0x0006, Bit 1) has been set to 1. 1: link partner is capable of 1000BASE-T full duplex. 0: link partner is not capable of 1000BASE-T full duplex. Link Partner 1000BASE-T Half Duplex Ability Bit. This bit is guaranteed to be valid only when the PAGE_RX_LAT bit (6.1) has been set to 1. 1: link partner is capable of 1000BASE-T half duplex. 0: link partner is not capable of 1000BASE-T half duplex. Reserved. These idle error count bits contain a cumulative count of the errors detected when the receiver is receiving idles. See Clause 40.5.1.1 of IEEE Standard 802.3 for more details. Rev. 0 | Page 48 of 79 Reset 0x0 0x0 Access R R 0x0 R 0x0 R 0x0 R 0x0 0x0 R R Data Sheet ADIN1200 Extended Status Register Address: 0x000F, Reset: 0x0000, Name: EXT_STATUS This address corresponds to the extended status register specified in Clause 22.2.4.4 of IEEE Standard 802.3. Table 39. Bit Descriptions for EXT_STATUS Bits 15 14 13 12 [11:0] Bit Name FD_1000_X_SPRT HD_1000_X_SPRT FD_1000_SPRT HD_1000_SPRT RESERVED Description This bit is always zero because the PHY does not support full duplex 1000BASE-X. This bit is always zero because the PHY does not support half duplex 1000BASE-X. This bit is always zero because the PHY does not support full duplex 1000BASE-T. This bit is always zero because the PHY does not support half duplex 1000BASE-T. Reserved. Reset 0x0 0x0 0x0 0x0 0x0 Access R R R R R Extended Register Pointer Register Address: 0x0010, Reset: 0x0000, Name: EXT_REG_PTR The extended register pointer and extended register data registers provide a mechanism to access the indirect access address map via directly accessible registers for cases where the station management does not support Clause 45. Table 40. Bit Descriptions for EXT_REG_PTR Bits [15:0] Bit Name EXT_REG_PTR Description The extended register pointer and extended register data registers provide an indirect mechanism to access EMI registers using normal Clause 22 access for cases where the station management does not support Clause 45. Write the 16-bit register address into the EXT_REG_PTR register. The EMI register can be read or written by reading or writing the EXT_REG_DATA register. An EMI register can be directly accessed using Clause 45 access. Reset 0x0 Access R/W Extended Register Data Register Address: 0x0011, Reset: 0x0000, Name: EXT_REG_DATA The extended register pointer and extended register data registers provide a mechanism to access the indirect access address map via directly accessible registers for cases where the station management does not support Clause 45. Table 41. Bit Descriptions for EXT_REG_DATA Bits [15:0] Bit Name EXT_REG_DATA Description The extended register pointer and extended register data registers provide an indirect mechanism to access EMI registers using normal Clause 22 access for cases where the station management does not support Clause 45. See Table 40 for further details. Reset 0x0 Access R/W PHY Control 1 Register Address: 0x0012, Reset: 0x0002, Name: PHY_CTRL_1 This register provides access to various PHY control register bits, in particular for diagnostic clocking control and MDI crossover. Table 42. Bit Descriptions for PHY_CTRL_1 Bits [15:11] 10 Bit Name RESERVED AUTO_MDI_EN Description Reserved. The automatic MDI/MDIX resolution enable register bit allows the automatic cable crossover feature of the PHY to be controlled. Note that the default value of this register bit is configurable via a hardware configuration pin, which allows the default operation of the PHY to be configured in unmanaged applications. 1: enable auto MDI/MDIX. Prefer MDI if MAN_MDIX is 1'b0 and prefer MDIX if MAN_MDIX is 1'b1. 0: disable auto MDI/MDIX. Rev. 0 | Page 49 of 79 Reset 0x0 0x0 Access R R/W ADIN1200 Bits 9 Bit Name MAN_MDIX [8:3] 2 RESERVED DIAG_CLK_EN [1:0] RESERVED Data Sheet Description When this bit is set and the AUTO_MDI_EN bit is clear, the PHY operates in the MDIX configuration. In this configuration, no crossover is implemented and the logical pairs of the PCS correspond to the physical pairs of the AFE. When this bit is clear and the AUTO_MDI_EN bit is clear, the PHY operates in the MDI configuration and crossovers the pairs. If the AUTO_MDI_EN bit is set, the MAN_MDIX bit determines the MDI or MDIX preference option. 1: operate in MDIX configuration. 0: operate in MDI configuration. Reserved. Enable PHY Diagnostics Clock. This clock is required for certain diagnostic functions within the PHY, for example, the frame generator/checker. 1: enable PHY diagnostics clock. 0: disable PHY diagnostics clock. Reserved. Reset 0x0 Access R/W 0x0 0x0 R R/W 0x2 R/W Reset 0x0 0x1 Access R/W R/W 0x0 0x0 R R/W 0x0 R/W 0x0 0x0 R/W R/W 0x1 0x0 0x1 R/W R R/W Reset 0x0 Access R PHY Control Status 1 Register Address: 0x0013, Reset: 0x1041, Name: PHY_CTRL_STATUS_1 This register provides access to PHY loopback control bits. Table 43. Bit Descriptions for PHY_CTRL_STATUS_1 Bits [15:13] 12 Bit Name RESERVED LB_ALL_DIG_SEL 11 10 RESERVED LB_LD_SEL 9 LB_REMOTE_EN 8 7 ISOLATE_RX LB_EXT_EN 6 [5:1] 0 LB_TX_SUP RESERVED LB_MII_LS_OK Description Reserved. Setting this bit selects all digital loopback. This loops the data within the PHY at the analog/ digital boundary so that data received on the MAC interface TXD_x pins is looped back to the RXD_x pins. This requires the IEEE loopback bit (Register 0x0000, Bit 14) to be set. Reserved. Setting this bit selects line driver loopback. If this register bit is set, every time the loopback bit is set the PHY enters line driver loopback mode. In line driver loopback mode, leave the MDI pins open to create a large impedance mismatch. The PHY can then operate by receiving the reflection from its own transmission. Setting this bit enables remote loopback. This requires a link up with a remote PHY and it loops the data received from the remote PHY back to the remote PHY using all of the digital and analog circuitry of the PHY. Setting this bit suppresses data being sent to the MAC during loopback. Setting this bit enables external cable loopback. This requires an external cable with Pair 0 and Pair 1 and Pair 2 and Pair 3 shorted together to provide an analog loopback at the end of the cable. All of the digital and analog circuitry of the PHY and the signal processing is adjusted so that the transmitted signal is not cancelled. The IEEE loopback bit (Register 0x0000, Bit 14) must not be set. Setting this bit suppresses the transmit signal at the MDI pins in all digital loopback. Reserved. Setting this bit sets the link status signal to okay during MII loopback. Receive Error Count Register Address: 0x0014, Reset: 0x0000, Name: RX_ERR_CNT The receive error counter register is used to access the receive error counter associated with the frame checker in the PHY. Table 44. Bit Descriptions for RX_ERR_CNT Bits [15:0] Bit Name RX_ERR_CNT Description This is the receive error counter associated with the frame checker in the PHY. Note that this bit is self clearing upon reading. Rev. 0 | Page 50 of 79 Data Sheet ADIN1200 PHY Control Status 2 Register Address: 0x0015, Reset: 0x0000, Name: PHY_CTRL_STATUS_2 This register provides access to various PHY control and status registers, in particular autonegotiation controls and energy detect powerdown control and status bits. Table 45. Bit Descriptions for PHY_CTRL_STATUS_2 Bits [15:4] 3 Bit Name RESERVED NRG_PD_EN 2 NRG_PD_TX_EN 1 PHY_IN_NRG_PD 0 RESERVED Description Reserved. Setting this bit enables energy detect power-down. If there is no signal energy detected for a number of seconds, the PHY enters energy detect power-down mode. Note that the default value of this register bit is configurable via the hardware configuration pins. This allows the default operation of the PHY to be configured in unmanaged applications. 1: enable energy detect power-down mode. 0: disable energy detect power-down mode. When this bit is set, the PHY periodically wakes up when in energy detect power-down and transmits a number of pulses. This is to avoid a lock up situation where the PHYs on both ends of the line are in energy detect power-down mode. Note that the default value of this register bit is configurable via the hardware configuration pins. This allows the default operation of the PHY to be configured in unmanaged applications. 1: enable periodic transmission of the pulse while in energy detect power-down mode. 0: disable periodic transmission of the pulse while in energy detect power-down mode. This status bit indicates that the PHY is in energy detect power-down mode. 1: PHY is in energy detect power-down mode. 0: PHY is not in energy detect power-down mode. Reserved. Reset 0x0 0x0 Access R R/W 0x0 R/W 0x0 R 0x0 R/W PHY Control 2 Register Address: 0x0016, Reset: 0x0308, Name: PHY_CTRL_2 This register provides access to various PHY control registers, for control of clocking, group MDIO access, and autonegotiation. Table 46. Bit Descriptions for PHY_CTRL_2 Bits [15:11] 10 Bit Name RESERVED DN_SPEED_TO_10_EN [9:7] 6 RESERVED GROUP_MDIO_EN [5:0] RESERVED Description Reserved. Setting this bit enables downspeed to 10BASE-T. Note that autonegotiation must also be enabled. If the PHY is unable to bring a link up at a high speed, it automatically drops down to 10BASE-T (assuming this speed has been advertised) if necessary. 1: enable downspeed to 10BASE-T. 0: disable downspeed to 10BASE-T. Reserved. The group MDIO enable register bit may be used to place the PHY in group MDIO mode. In this mode, the PHY responds to any write or address operation to PHY address 5'd31 as if it was an access to its own PHY address. It is recommended that this bit be set only when performing specific sequences and then be cleared again. Reserved. Rev. 0 | Page 51 of 79 Reset 0x0 0x0 Access R/W R/W 0x6 0x0 R/W R/W 0x8 R/W ADIN1200 Data Sheet PHY Control 3 Register Address: 0x0017, Reset: 0x3048, Name: PHY_CTRL_3 This register provides access to PHY control register bits for link enable and autonegotiation controls. Table 47. Bit Descriptions for PHY_CTRL_3 Bits [15:14] 13 Bit Name RESERVED LINK_EN [12:10] NUM_SPEED_RETRY [9:0] RESERVED Description Reserved. Setting this bit enables linking. If linking is disabled, the PHY enters the standby state and does not attempt to bring up links. The standby state can be used to run diagnostics, including cable diagnostics. 1: enable linking. 0: disable linking. If downspeed is enabled, this register bit specifies the number of retries the PHY must attempt to bring up a link at the advertised speed before advertising a lower speed. By default, the PHY attempts to bring up a link 5 times (4 retries) before downspeeding. Reserved. Reset 0x0 0x1 Access R R/W 0x4 R/W 0x48 R/W Reset 0x0 0x0 Access R/W R/W 0x0 R/W 0x0 R/W 0x0 R/W 0x0 R/W 0x0 R/W 0x0 R/W 0x0 R/W 0x0 R/W 0x0 R/W Interrupt Mask Register Address: 0x0018, Reset: 0x0000, Name: IRQ_MASK The interrupt mask register allows interrupts to be masked or unmasked. Table 48. Bit Descriptions for IRQ_MASK Bits [15:11] 10 Bit Name RESERVED CBL_DIAG_IRQ_EN 9 MDIO_SYNC_IRQ_EN 8 AN_STAT_CHNG_IRQ_EN 7 FC_FG_IRQ_EN 6 PAGE_RX_IRQ_EN 5 IDLE_ERR_CNT_IRQ_EN 4 FIFO_OU_IRQ_EN 3 RX_STAT_CHNG_IRQ_EN 2 LNK_STAT_CHNG_IRQ_EN 1 SPEED_CHNG_IRQ_EN Description Reserved. Cable Diagnostics Interrupt Enable Bit. 1: enable cable diagnostics interrupt. 0: disable cable diagnostics interrupt. MDIO Synchronization Lost Interrupt Enable Bit. 1: enable MDIO synchronization lost interrupt. 0: disable MDIO synchronization lost interrupt. Autonegotiation Status Changed Interrupt Enable Bit. 1: enable autonegotiation status changed interrupt. 0: disable autonegotiation status changed interrupt. Frame checker/generator interrupt enable bit. 1: enable interrupt. 0: disable changed interrupt. Autonegotiation Page Received Interrupt Enable Bit. 1: enable autonegotiation page received interrupt. 0: disable autonegotiation page received interrupt. Idle Error Counter Saturated Interrupt Enable Bit. 1: enable idle error counter saturated interrupt. 0: disable idle error counter saturated interrupt. MAC Interface FIFO Overflow/Underflow Interrupt Enable Bit. 1: enable MAC interface FIFO overflow/underflow interrupt. 0: disable MAC interface FIFO overflow/underflow interrupt. Receive Status Changed Interrupt Enable Bit. 1: enable receive status changed interrupt. 0: disable receive status changed interrupt. Link Status Changed Interrupt Enable Bit. 1: enable link status changed interrupt. 0: disable link status changed interrupt. Speed Changed Interrupt Enable Bit. 1: enable speed changed interrupt. 0: disable speed changed interrupt. Rev. 0 | Page 52 of 79 Data Sheet Bits 0 Bit Name HW_IRQ_EN ADIN1200 Description When set, this enables the hardware interrupt pin, INT_N, and INT_N is asserted when an interrupt is generated. 1: enable the hardware interrupt pin, INT_N. 0: disable the hardware interrupt pin, INT_N. Reset 0x0 Access R/W Interrupt Status Register Address: 0x0019, Reset: 0x0000, Name: IRQ_STATUS The interrupt status register is used to check which interrupts have triggered since the last time it was read. Each bit goes high when the associated interrupt triggers and then latches high until it is unlatched by reading (note that reading any of the bits in this register unlatches all of the bits in the register). The bits of IRQ_STATUS go high even when the associated interrupts are not enabled. However, only bits associated with enabled interrupts are considered when generating the IRQ_PENDING indication. Table 49. Bit Descriptions for IRQ_STATUS Bits [15:11] 10 Bit Name RESERVED CBL_DIAG_IRQ_STAT 9 MDIO_SYNC_IRQ_STAT 8 AN_STAT_CHNG_IRQ_STAT 7 FC_FG_IRQ_STAT 6 PAGE_RX_IRQ_STAT 5 IDLE_ERR_CNT_IRQ_STAT 4 FIFO_OU_IRQ_STAT 3 RX_STAT_CHNG_IRQ_STAT 2 LNK_STAT_CHNG_IRQ_STAT 1 SPEED_CHNG_IRQ_STAT 0 IRQ_PENDING Description Reserved. If the cable diagnostics interrupt status bit is 1, this indicates that the associated interrupt triggered since last read. Note that when this bit goes high, it latches high until it is unlatched by reading. If the MDIO synchronization lost interrupt status bit is 1, this indicates that the associated interrupt triggered since last read. Note that when this bit goes high, it latches high until it is unlatched by reading. If the autonegotiation status changed interrupt status bit is 1, this indicates that the associated interrupt triggered since last read. Note that when this bit goes high, it latches high until it is unlatched by reading. If the frame checker/generator interrupt status bit is 1, this indicates that the associated interrupt triggered since last read. Note that when this bit goes high, it latches high until it is unlatched by reading. If the autonegotiation page received interrupt status bit is 1, this indicates that the associated interrupt triggered since last read. Note that when this bit goes high, it latches high until it is unlatched by reading. If the idle error counter saturated interrupt status bit is 1, this indicates that the associated interrupt triggered since last read. Note that when this bit goes high, it latches high until it is unlatched by reading. If the MAC interface RGMII transmit FIFO overflow/underflow interrupt status bit is 1, this indicates that the associated interrupt triggered since last read. Note that when this bit goes high, it latches high until it is unlatched by reading. If the receive status changed interrupt status bit is 1, this indicates that the associated interrupt triggered since last read. Note that when this bit goes high, it latches high until it is unlatched by reading. If the link status changed interrupt status bit is 1, this indicates that the associated interrupt triggered since last read. Note that when this bit goes high, it latches high until it is unlatched by reading. If the speed changed interrupt status bit is 1, this indicates that the associated interrupt triggered since last read. Note that when this bit goes high, it latches high until it is unlatched by reading. If the interrupt pending status bit is 1, this indicates that an interrupt has occurred and is pending. Note that when this bit goes high, it latches high until it is unlatched by reading. Rev. 0 | Page 53 of 79 Reset 0x0 0x0 Access R R 0x0 R 0x0 R 0x0 R 0x0 R 0x0 R 0x0 R 0x0 R 0x0 R 0x0 R 0x0 R ADIN1200 Data Sheet PHY Status 1 Register Address: 0x001A, Reset: 0x0300, Name: PHY_STATUS_1 This register provides access to various PHY status registers. Table 50. Bit Descriptions for PHY_STATUS_1 Bits 15 Bit Name PHY_IN_STNDBY 14 13 Reserved PAR_DET_FLT_STAT 12 AUTONEG_STAT 11 10 [9:7] PAIR_01_SWAP B_10_POL_INV HCD_TECH 6 5 4 3 2 1 LINK_STAT TX_EN_STAT RX_DV_STAT COL_STAT AUTONEG_SUP LP_PAUSE_ADV 0 LP_APAUSE_ADV Description A 1 indicates that the PHY is in standby state and does not attempt to bring up links. The standby state can be used to run diagnostics, including cable diagnostics. Reserved Parallel Detection Fault Status Bit. A 1 indicates that a fault has occurred in the parallel detection process. This bit is a copy of PAR_DET_FLT, (AUTONEG_EXP register, Address 0x0006). Reading the PAR_DET_FLT_STAT bit does not clear PAR_DET_FLT. Autonegotiation Status Bit. A 1 indicates that autonegotiation has completed. This bit is a copy of AUTONEG_DONE (MII_STATUS register, Address 0x0001). Reading the AUTONEG_STAT bit does not clear AUTONEG_DONE. A 1 indicates that Pair 0 and Pair 1 have been swapped. A 1 indicates that the polarity of the 10BASE-T signal has been inverted. This field indicates the resolved technology after the link is established. 111: reserved. 110: reserved. 101: reserved 100: reserved 011: speed resolved to 100BASE-TX full duplex. 010: speed resolved to 100BASE-TX half duplex. 001: speed resolved to 10BASE-T full duplex. 000: speed resolved to 10BASE-T half duplex. A 1 indicates that a link is up. A 1 indicates that transmit enable (TX_EN) is asserted. A 1 indicates that receive data valid (RX_DV) is asserted. A 1 indicates that collision is asserted. A 1 indicates that both the local and remote PHYs support autonegotiation. A 1 indicates that the link partner has advertised pause. The link partner pause advertisement bit indicates that the link partner advertised support for pause operation on full duplex links. This bit provides the same information as LP_PAUSE_ABLE. A 1 indicates that the link partner has advertised asymmetric pause. The link partner asymmetric pause advertisement bit indicates that the link partner advertised support for asymmetric pause operation on full duplex links. This bit provides the same information as LP_APAUSE_ABLE. Rev. 0 | Page 54 of 79 Reset 0x0 Access R 0x0 0x0 R R 0x0 R 0x0 0x0 0x6 R R R 0x0 0x0 0x0 0x0 0x0 0x0 R R R R R R 0x0 R Data Sheet ADIN1200 LED Control 1 Register Address: 0x001B, Reset: 0x0001, Name: LED_CTRL_1 This register provides access to various PHY LED control register bits. Table 51. Bit Descriptions for LED_CTRL_1 Bits [15:11] 10 Bit Name RESERVED LED_A_EXT_CFG_EN [9:8] [7:4] RESERVED LED_PAT_PAUSE_DUR [3:2] LED_PUL_STR_DUR_SEL 1 LED_OE_N 0 LED_PUL_STR_EN Description Reserved. Enable Extended Configuration Set for LED_0 Pin. Also see LED_CTRL_2 register, Address 0x001C, Bits[3:0]. 1: enable extended configuration set for LED_0 pin. 0: disable extended configuration set for LED_0 pin. Reserved. Internal LED Pattern Pause Duration for LED_0. After the blink pattern is driven out to the LED_0 pin, the last bit is held for a duration specified by the LED pattern pause duration register field. This duration is the value of LED tick duration (for example, the time for each bit) multiplied by the value of the LED pattern pause duration register field. Also see the LED_PAT register field (LED_CTRL_3 register, Address 0x001D, Bits[7:0]) and the LED_PAT_TICK_DUR register field (LED_CTRL_3 register, Address 0x001D, Bits[13:8]). The default blink is a 0.5 sec on and 0.5 sec off pattern. This bit field selects the duration of the pulse stretching. 11: user-programmable. In this case, the duration of the pulse stretching is programmable by the LED_PUL_STR_DUR register (Address 0xBC00, Bits[5:0]). 10: 102 ms. 01: 64 ms. 00: 32 ms. LED Active Low Output Enable Register Bit. 1: disable LED outputs. 0: enable LED outputs. Setting this bit enables pulse stretching for transmit, receive, or collision LED events so that very short duration events are visible. The LED pulse stretching enable register indicates that the PHY must stretch any pulses indicating transmit, receive, or collision. Without stretching, these pulses may be too short to cause an LED to light. Reset 0x0 0x0 Access R/W R/W 0x0 0x0 R R/W 0x0 R/W 0x0 R/W 0x1 R/W Reset 0x210 0xA Access R/W R/W LED Control 2 Register Address: 0x001C, Reset: 0x210A, Name: LED_CTRL_2 This register provides access to various PHY LED control register bits. Table 52. Bit Descriptions for LED_CTRL_2 Bits [15:4] [3:0] Bit Name RESERVED LED_A_CFG Description Reserved. LED_0 configuration is made up of five bits. These four bits, Bits[3:0], are the LSBs and Bit 4 is from LED_A_EXT_CFG_EN (LED_CTRL_1 register, Address 0x001B). The combination of the five bits configures LED_0, selecting one of 32 possible configuration functions according to the following settings. The default setting is 01010 (on if link up and blink on activity). 11111: on if 10BASE-Te link, blink if 100BASE-TX link. 11110: on if 10BASE-Te link. 11101: on if 100BASE-TX link, blink if 10BASE-Te link. 11100: on if 100BASE-TX link 11011: blink if 10BASE-Te link. 11010: blink if transmit. 11001: blink on activity. 11000: reserved. 10111: reserved. 10110: reserved. 10101: reserved. Rev. 0 | Page 55 of 79 ADIN1200 Bits Bit Name Data Sheet Description 10100: reserved. 10011: on if 100BASE-TX link, blink on activity. 10010: on if 10BASE-Te link, blink on activity. 10001: reserved. 10000: on if 10BASE-Te or 100BASE-TX link. 01111: off. 01110: on. 01101: blink. 01100: on if full duplex link, blink on collision. 01011: on if link, blink if receiving. 01010: on if link, blink on activity. 01001: on if collision. 01000: on if full duplex link. 00111: on if activity (transmitting or receiving). 00110: on if receiving. 00101: on if transmitting. 00100: on if link up. 00011: blink if 100BASE-TX. 00010: reserved. 00001: reserved. 00000: reserved. Reset Access Reset 0x0 Access R/W 0x18 R/W 0x55 R/W LED Control 3 Register Address: 0x001D, Reset: 0x1855, Name: LED_CTRL_3 This register provides access to various PHY LED control register bits. Table 53. Bit Descriptions for LED_CTRL_3 Bits [15:14] Bit Name LED_PAT_SEL [13:8] LED_PAT_TICK_DUR [7:0] LED_PAT Description The LED_PAT_SEL bit field is always 2'b00, allowing the user to program the LED_0 blink pattern via the LED_PAT, LED_PAT_TICK_DUR, and LED_PAT_PAUSE_DUR bit fields. 11: reserved. 10: reserved. 01: reserved. 00: read/write access to LED_0 blink pattern registers. Each bit in the blink pattern bit field (LED_PAT) is driven to the corresponding LED pin and held for the duration specified in this 6-bit LED pattern duration bit field. The duration is the value of this register plus 1 multiplied by 8, for example, 8 ms, 16 ms, … 504 ms. The value 63 has a special meaning of 1 ms tick duration. Also see the LED_PAT_PAUSE_DUR bit field (LED_CTRL_1 register, Address 0x001B). The default blink is a 0.5 sec on and 0.5 sec off pattern. The internal LED pattern for LED_0 can be read or written via this field. The LED_PAT_SEL field selects which set of internal blink pattern registers for LED_0 is accessed. The default value of the LED pattern is 0x55 and is, therefore, an alternating 0/1 pattern (LED_CTRL_1 register, Address 0x001B). The default blink is a 0.5 sec on and 0.5 sec off pattern. Rev. 0 | Page 56 of 79 Data Sheet ADIN1200 PHY Status 2 Register Address: 0x001F, Reset: 0x03FC, Name: PHY_STATUS_2 This register provides access to various PHY status register bits. Table 54. Bit Descriptions for PHY_STATUS_2 Bits [15:12] 11 10 [9:0] Bit Name RESERVED PAIR_1_POL_INV PAIR_0_POL_INV RESERVED Description Reserved. A 1 indicates that the polarity on Pair 1 has been inverted. A 1 indicates that the polarity on Pair 0 has been inverted. Reserved. Reset 0x0 0x0 0x0 0x1FE Access R R R R Energy Efficient Ethernet Capability Register Address: 0x8000, Reset: 0x0006, Name: EEE_CAPABILITY This address corresponds to the EEE capability register specified in Clause 45.2.3.9 of IEEE Standard 802.3, which, in the IEEE standard, is at MMD Register Address 3.20. This register is used to indicate the capability of the PCS to support EEE functions for each PHY type. Table 55. Bit Descriptions for EEE_CAPABILITY Bits [15:7] 6 Bit Name RESERVED EEE_10_G_KR_SPRT 5 EEE_10_G_KX_4_SPRT 4 EEE_1000_KX_SPRT 3 EEE_10_G_SPRT 2 EEE_1000_SPRT 1 EEE_100_SPRT 0 RESERVED Description Reserved. The 10GBASE-KR EEE capability bit always reads as 1'b0. 1: EEE is supported for 10GBASE-KR. 0: EEE is not supported for 10GBASE-KR. The 10GBASE-KX4 EEE capability bit always reads as 1'b0. 1: EEE is supported for 10GBASE-KX4. 0: EEE is not supported for 10GBASE-KX4. The 1000BASE-KX EEE capability bit always reads as 1'b0. 1: EEE is supported for 1000BASE-KX. 0: EEE is not supported for 1000BASE-KX. The 10GBASE-T EEE capability bit always reads as 1'b0. 1: EEE is supported for 10GBASE-T. 0: EEE is not supported for 10GBASE-T. The 1000BASE-T EEE capability bit always reads as 1'b1. 1: EEE is supported for 1000BASE-T. 0: EEE is not supported for 1000BASE-T. The 100BASE-TX EEE capability bit always reads as 1'b1. 1: EEE is supported for 100BASE-TX. 0: EEE is not supported for 100BASE-TX. Reserved. Reset 0x0 0x0 Access R R 0x0 R 0x0 R 0x0 R 0x1 R 0x1 R 0x0 R Energy Efficient Ethernet Advertisement Register Address: 0x8001, Reset: 0x0000, Name: EEE_ADV This address corresponds to the EEE advertisement register specified in Clause 45.2.7.13 of Standard 802.3, which, in the IEEE standard, is at MMD Register Address 7.60. This register is used to define the EEE advertisement during autonegotiation. The reset value of this register is 0x0000 except where the hardware configuration pins are set to enable EEE. In this case, the reset value is 0x0006. Table 56. Bit Descriptions for EEE_ADV Bits [15:7] 6 Bit Name RESERVED EEE_10_G_KR_ADV Description Reserved. The 10GBASE-KR EEE advertisement bit always reads as 1'b0. 1: advertise that the 10GBASE-KR has EEE capability. 0: do not advertise that the 10GBASE-KR has EEE capability. Rev. 0 | Page 57 of 79 Reset 0x0 0x0 Access R R ADIN1200 Bits 5 Bit Name EEE_10_G_KX_4_ADV 4 EEE_1000_KX_ADV 3 EEE_10_G_ADV 2 EEE_1000_ADV 1 EEE_100_ADV 0 RESERVED Data Sheet Description The 10GBASE-KX4 EEE advertisement bit always reads as 1'b0. 1: advertise that the 10GBASE-KX4 has EEE capability. 0: do not advertise that the 10GBASE-KX4 has EEE capability. The 1000BASE-KX EEE advertisement bit always reads as 1'b0. 1: advertise that the 1000BASE-KX has EEE capability. 0: do not advertise that the 1000BASE-KX has EEE capability. The 10GBASE-T EEE advertisement bit always reads as 1'b0. 1: advertise that the 10GBASE-T has EEE capability. 0: do not advertise that the 10GBASE-T has EEE capability. The 1000BASE-T EEE advertisement register bit always reads as 1'b0. 1: advertise that the 1000BASE-T has EEE capability. 0: do not advertise that the 1000BASE-T has EEE capability. The default value of the 100BASE-TX EEE advertisement register bit is dependent on the hardware configuration pins settings. When EEE is enabled by these pins, the default value is 1'b1 and when disabled, the default value is 1'b0. 1: advertise that the 100BASE-TX has EEE capability. 0: do not advertise that the 100BASE-TX has EEE capability. Reserved. Reset 0x0 Access R 0x0 R 0x0 R 0x0 R/W 0x0 R/W 0x0 R Energy Efficient Ethernet Link Partner Ability Register Address: 0x8002, Reset: 0x0000, Name: EEE_LP_ABILITY This address corresponds to the EEE link partner ability register specified in Clause 45.2.7.14 of Standard 802.3, which, in the IEEE standard, is at MMD Register Address 7.61. This register reflects the EEE advertisement of the link partner during autonegotiation. Table 57. Bit Descriptions for EEE_LP_ABILITY Bits [15:7] 6 Bit Name RESERVED LP_EEE_10_G_KR_ABLE 5 LP_EEE_10_G_KX_4_ABLE 4 LP_EEE_1000_KX_ABLE 3 LP_EEE_10_G_ABLE 2 LP_EEE_1000_ABLE 1 LP_EEE_100_ABLE 0 RESERVED Description Reserved. Link Partner 10GBASE-KR EEE Ability Bit. 1: link partner is advertising EEE capability for 10GBASE-KR. 0: link partner is not advertising EEE capability for 10GBASE-KR. Link Partner 10GBASE-KX4 EEE Ability Bit. 1: link partner is advertising EEE capability for 10GBASE-KX4. 0: link partner is not advertising EEE capability for 10GBASE-KX4. Link Partner 1000BASE-KX EEE Ability Bit. 1: link partner is advertising EEE capability for 1000BASE-KX. 0: link partner is not advertising EEE capability for 1000BASE-KX. Link Partner 10GBASE-T EEE Ability Bit. 1: link partner is advertising EEE capability for 10GBASE-T. 0: link partner is not advertising EEE capability for 10GBASE-T. Link Partner 1000BASE-T EEE Ability Bit. 1: link partner is advertising EEE capability for 1000BASE-T. 0: link partner is not advertising EEE capability for 1000BASE-T. Link Partner 100BASE-TX EEE Ability Bit. 1: link partner is advertising EEE capability for 100BASE-TX. 0: link partner is not advertising EEE capability for 100BASE-TX. Reserved. Rev. 0 | Page 58 of 79 Reset 0x0 0x0 Access R R 0x0 R 0x0 R 0x0 R 0x0 R 0x0 R 0x0 R Data Sheet ADIN1200 Energy Efficient Ethernet Resolved Register Address: 0x8008, Reset: 0x0000, Name: EEE_RSLVD This register indicates whether or not the resolved technology after the link has been established is EEE capable. Table 58. Bit Descriptions for EEE_RSLVD Bits [15:1] 0 Bit Name RESERVED EEE_RSLVD Description Reserved. This bit indicates that the resolved technology after the link has been established is EEE capable. This is a vendor specific register bit. 1: resolved technology is EEE capable. Reset 0x0 0x0 Access R R Reset 0x0 0x0 Access R R Mean Square Error A Register Address: 0x8402, Reset: 0x0000, Name: MSE_A This register is an indication of signal quality and is a measure of the mean square error on Dimension A. Table 59. Bit Descriptions for MSE_A Bits [15:8] [7:0] Bit Name RESERVED MSE_A Description Reserved. This register is an indication of signal quality when a 100BASE-TX link is up and is a measure of the mean square error on Dimension A. Enhanced Link Detection Enable Register Address: 0x8E27, Reset: 0x003D, Name: FLD_EN This register controls the enables for the enhanced link detection function. This is early detection and indication of link loss. Table 60. Bit Descriptions for FLD_EN Bits [15:8] 7 6 5 Bit Name RESERVED FLD_PCS_ERR_B_100_EN RESERVED FLD_SLCR_OUT_STUCK_B_100_EN 4 3 RESERVED FLD_SLCR_IN_ZDET_B_100_EN 2 1 RESERVED FLD_SLCR_IN_INVLD_B_100_EN 0 RESERVED Description Reserved. Enhanced link detection PCS receive error detection enable for 100BASE-TX. Reserved. Enhanced link detection PMA slicer output stuck at detection enable for 100BASE-TX. Reserved. Enhanced link detection PMA slicer input zero detection enable for 100BASE-TX. Reserved. Enhanced link detection PMA slicer input invalid level detection enable for 100BASE-TX. Enabled when set high. Reserved. Reset 0x0 0x0 0x0 0x1 Access R R/W R/W R/W 0x1 0x1 R/W R/W 0x1 0x0 R/W R/W 0x1 R/W Enhanced Link Detection Latched Status Register Address: 0x8E38, Reset: 0x0000, Name: FLD_STAT_LAT This register is the latched status for the enhanced link detection function. This bit is latched until the start of the next link-up, when it is cleared. Table 61. Bit Descriptions for FLD_STAT_LAT Bits [15:14] 13 [12:0] Bit Name RESERVED FAST_LINK_DOWN_LAT RESERVED Description Reserved. Main Enhanced Link Detection Latched Indication. Reserved. Rev. 0 | Page 59 of 79 Reset 0x0 0x0 0x0 Access R R R ADIN1200 Data Sheet Receive MII Clock Stop Enable Register Address: 0x9400, Reset: 0x0400, Name: RX_MII_CLK_STOP_EN This register contains the clock stop enable bit specified in Clause 45.2.3.1.4 of IEEE Standard 802.3, which, in the IEEE standard, is at MMD Register Address 3.0, Bit 10. Table 62. Bit Descriptions for RX_MII_CLK_STOP_EN Bits [15:11] 10 Bit Name RESERVED RX_MII_CLK_STOP_EN [9:0] RESERVED Description Reserved. If this bit is set, the PHY may stop the receive MII clock while it is signaling low power enable (LPI). Otherwise, it keeps the clock active. 1: the PHY may stop the clock during LPI. 0: clock not stoppable. Reserved. Reset 0x0 0x1 Access R R/W 0x0 R PCS Status 1 Register Address: 0x9401, Reset: 0x0040, Name: PCS_STATUS_1 The bits contained in this register correspond to the bits in the PCS Status 1 register specified in Clause 45.2.3.2 of IEEE Standard 802.3, which, in the IEEE standard, is at MMD Register Address 3.1, Bits[11:8] and Bit 6. Table 63. Bit Descriptions for PCS_STATUS_1 Bits [15:12] 11 Bit Name RESERVED TX_LPI_RCVD 10 RX_LPI_RCVD 9 TX_LPI 8 RX_LPI 7 6 RESERVED TX_MII_CLK_STOP_CPBL [5:0] RESERVED Description Reserved. The transmit LPI received bit is a latched version of TX_LPI. When this bit goes high, it latches high until it is unlatched by reading. 1: transmit PCS has received LPI. 0: LPI not received. The receive LPI received bit is a latched version of RX_LPI. When this bit goes high, it latches high until it is unlatched by reading. 1: receive PCS has received LPI. 0: LPI not received. Transmit LPI Bit. 1: transmit PCS is currently receiving LPI. 0: PCS is not currently receiving LPI. Receive LPI Bit. 1: receive PCS is currently receiving LPI. 0: PCS is not currently receiving LPI. Reserved. The transmit MII clock stop capable bit always reads as 1'b1. 1: the MAC may stop the clock during LPI. 0: clock not stoppable. Reserved. Rev. 0 | Page 60 of 79 Reset 0x0 0x0 Access R R 0x0 R 0x0 R 0x0 R 0x0 0x1 R R 0x0 R Data Sheet ADIN1200 Frame Checker Enable Register Address: 0x9403, Reset: 0x0001, Name: FC_EN This register is used to enable the frame checker. The frame checker analyzes the received frames from either the MAC interface or the PHY (see the FC_TX_SEL register, Address 0x9407, Bit 0) to report the number of frames received, CRC errors, and various other frame errors. The frame checker frame and error counter registers count these events. Table 64. Bit Descriptions for FC_EN Bits [15:1] 0 Bit Name RESERVED FC_EN Description Reserved. When set, this bit enables the frame checker. Reset 0x0 0x1 Access R R/W Frame Checker Interrupt Enable Register Address: 0x9406, Reset: 0x0001, Name: FC_IRQ_EN This register is used to enable the frame checker interrupt. An interrupt is generated when a receive error occurs. Enable the frame checker/generator interrupt in the interrupt mask register. Set the FC_FG_IRQ_EN bit (IRQ_MASK register, Address 0x0018). The interrupt status can be read via the FC_FG_IRQ_STAT bit (IRQ_STATUS register, Address 0x0019). Table 65. Bit Descriptions for FC_IRQ_EN Bits [15:1] 0 Bit Name RESERVED FC_IRQ_EN Description Reserved. When set, this bit enables the frame checker interrupt. Reset 0x0 0x1 Access R R/W Frame Checker Transmit Select Register Address: 0x9407, Reset: 0x0000, Name: FC_TX_SEL This register is used to select the transmit side or receive side for frames to be checked. If set, frames received on the MAC interface to be transmitted are checked. The frame checker can be used to verify that correct data is received over the MAC interface and is also useful if remote loopback is enabled (set the LB_REMOTE_EN bit the in PHY_CTRL_STATUS_1 register, Address 0x0013, Bit 9) because it can be used to check the received data after it is looped back at the MAC interface. Table 66. Bit Descriptions for FC_TX_SEL Bits [15:1] 0 Bit Name RESERVED FC_TX_SEL Description Reserved. When set, this bit indicates that the frame checker must check frames received to be transmitted by the PHY. 1: check frames from the MAC interface to be transmitted by the PHY. 0: check frames received by the PHY from the remote end. Reset 0x0 0x0 Access R R/W Reset 0x5F2 Access R/W Frame Checker Maximum Frame Size Register Address: 0x9408, Reset: 0x05F2, Name: FC_MAX_FRM_SIZE This register specifies the maximum frame size. Frames longer than this size are counted as oversized frames. Table 67. Bit Descriptions for FC_MAX_FRM_SIZE Bits [15:0] Bit Name FC_MAX_FRM_SIZE Description This bit field specifies the max frame size. Received frames that are longer than this are counted as oversized frames. Note that this frame length excludes the preamble and start frame delimiter. Rev. 0 | Page 61 of 79 ADIN1200 Data Sheet Frame Checker Count High Register Address: 0x940A, Reset: 0x0000, Name: FC_FRM_CNT_H This register is a latched copy of Bits[31:16] of the 32-bit receive frame counter register. When the receive error counter (RX_ERR_CNT register, Address 0x0014) is read, the receive frame counter register is latched. A copy of the receive frame counter register is latched when recant is read so that the error count and receive frame count are synchronized. Table 68. Bit Descriptions for FC_FRM_CNT_H Bits [15:0] Bit Name FC_FRM_CNT_H Description Bits[31:16] of Latched Copy of the Number of Received Frames. Reset 0x0 Access R Frame Checker Count Low Register Address: 0x940B, Reset: 0x0000, Name: FC_FRM_CNT_L This register is a latched copy of Bits[15:0] of the 32-bit receive frame counter register. When the receive error counter (RX_ERR_CNT register, Address 0x0014) is read, the receive frame counter register is latched. A copy of the receive frame counter register is latched when RX_ERR_CNT is read so that the error count and receive frame count are synchronized. Table 69. Bit Descriptions for FC_FRM_CNT_L Bits [15:0] Bit Name FC_FRM_CNT_L Description Bits[15:0] of Latched Copy of the Number of Received Frames. Reset 0x0 Access R Frame Checker Length Error Count Register Address: 0x940C, Reset: 0x0000, Name: FC_LEN_ERR_CNT This register is a latched copy of the frame length error counter register. This register is a count of received frames with a length error status. When the receive error counter (RX_ERR_CNT register, Address 0x0014) is read, the frame length error counter register is latched, which ensures that the frame length error count and receive frame count are synchronized. Table 70. Bit Descriptions for FC_LEN_ERR_CNT Bits [15:0] Bit Name FC_LEN_ERR_CNT Description Latched Copy of the Frame Length Error Counter. Reset 0x0 Access R Frame Checker Alignment Error Count Register Address: 0x940D, Reset: 0x0000, Name: FC_ALGN_ERR_CNT This register is a latched copy of the frame alignment error counter register. This register is a count of received frames with an alignment error status. When the receive error counter (RX_ERR_CNT register, Address 0x0014) is read, the alignment error counter register is latched, which ensures that the frame alignment error count and receive frame count are synchronized. Table 71. Bit Descriptions for FC_ALGN_ERR_CNT Bits [15:0] Bit Name FC_ALGN_ERR_CNT Description Latched Copy of the Frame Alignment Error Counter. Reset 0x0 Access R Frame Checker Symbol Error Counter Register Address: 0x940E, Reset: 0x0000, Name: FC_SYMB_ERR_CNT This register is a latched copy of the symbol error counter register. This register is a count of received frames with both RX_ER and RX_DV set. When the receive error counter (RX_ERR_CNT register, Address 0x0014) is read, the symbol error counter register is latched, which ensures that the symbol error count and receive frame count are synchronized. Table 72. Bit Descriptions for FC_SYMB_ERR_CNT Bits [15:0] Bit Name FC_SYMB_ERR_CNT Description Latched Copy of the Symbol Error Counter. Rev. 0 | Page 62 of 79 Reset 0x0 Access R Data Sheet ADIN1200 Frame Checker Oversized Frame Count Register Address: 0x940F, Reset: 0x0000, Name: FC_OSZ_CNT This register is a latched copy of the oversized frame error counter register. This register is a count of received frames with a length greater than specified in frame checker maximum frame size (FC_MAX_FRM_SIZE register, Address 0x9407). When the receive error counter (RX_ERR_CNT register, Address 0x0014) is read, the oversized frame error counter register is latched, which ensures that the oversized frame error count and receive frame count are synchronized. Table 73. Bit Descriptions for FC_OSZ_CNT Bits [15:0] Bit Name FC_OSZ_CNT Description Latched Copy of the Oversized Frame Error Counter. Reset 0x0 Access R Frame Checker Undersized Frame Count Register Address: 0x9410, Reset: 0x0000, Name: FC_USZ_CNT This register is a latched copy of the undersized frame error counter register. This register is a count of received frames with a length less than 64 bytes. When the receive error counter (RX_ERR_CNT register, Address 0x0014) is read, the undersized frame error counter register is latched, which ensures that the undersized frame error count and receive frame count are synchronized. Table 74. Bit Descriptions for FC_USZ_CNT Bits [15:0] Bit Name FC_USZ_CNT Description Latched Copy of the Undersized Frame Error Counter. Reset 0x0 Access R Frame Checker Odd Nibble Frame Count Register Address: 0x9411, Reset: 0x0000, Name: FC_ODD_CNT This register is a latched copy of the odd nibble frame counter register. This register is a count of received frames with an odd number of nibbles in the frame in 100BASE-TX or 10BASE-T mode. When the receive error counter (RX_ERR_CNT register, Address 0x0014) is read, the odd nibble frame counter register is latched, which ensures that the odd nibble frame count and receive frame count are synchronized. Table 75. Bit Descriptions for FC_ODD_CNT Bits [15:0] Bit Name FC_ODD_CNT Description Latched Copy of the Odd Nibble Counter. Reset 0x0 Access R Frame Checker Odd Preamble Packet Count Register Address: 0x9412, Reset: 0x0000, Name: FC_ODD_PRE_CNT This register is a latched copy of the odd preamble packet counter register. This register is a count of received frames with an odd number of nibbles in the preamble in 100BASE-TX mode. When the receive error counter (RX_ERR_CNT register, Address 0x0014) is read, the odd preamble packet counter register is latched, which ensures that the odd preamble packet count and receive frame count are synchronized. Table 76. Bit Descriptions for FC_ODD_PRE_CNT Bits [15:0] Bit Name FC_ODD_PRE_CNT Description Latched Copy of the Odd Preamble Packet Counter. Reset 0x0 Access R Frame Checker Dribble Bits Frame Count Register Address: 0x9413, Reset: 0x0000, Name: FC_DRIBBLE_BITS_CNT This register is a latched copy of the dribble bits frame counter register. This register is a count of received frames with a noninteger number of nibbles in 10BASE-T mode. When the receive error counter (RX_ERR_CNT register, Address 0x0014) is read, the dribble bits frame counter register is latched, which ensures that the dribble bits frame count and receive frame count are synchronized. Table 77. Bit Descriptions for FC_DRIBBLE_BITS_CNT Bits [15:0] Bit Name FC_DRIBBLE_BITS_CNT Description Latched Copy of the Dribble Bits Frame Counter. Rev. 0 | Page 63 of 79 Reset 0x0 Access R ADIN1200 Data Sheet Frame Checker False Carrier Count Register Address: 0x9414, Reset: 0x0000, Name: FC_FALSE_CARRIER_CNT This register is a latched copy of the false carrier events counter register. This is a count of the number of times the bad SSD state is entered. When the receive error counter (RX_ERR_CNT register, Address 0x0014) is read, the false carrier events counter register is latched, which ensures that the false carrier events count and receive frame count are synchronized. Table 78. Bit Descriptions for FC_FALSE_CARRIER_CNT Bits [15:0] Bit Name FC_FALSE_CARRIER_CNT Description Latched Copy of the False Carrier Events Counter. Reset 0x0 Access R Frame Generator Enable Register Address: 0x9415, Reset: 0x0000, Name: FG_EN This register is used to enable the frame generator. When the frame generator is enabled, the source of data for the PHY comes from the frame generator and not the MAC interface. To use the frame generator, the diagnostic clock must also be enabled. Set the DIAG_CLK_EN bit (PHY_CTRL_1 register, Address 0x0012, Bit 2). Table 79. Bit Descriptions for FG_EN Bits [15:1] 0 Bit Name RESERVED FG_EN Description Reserved. When set, this bit enables the built in frame generator. Reset 0x0 0x0 Access R R/W Frame Generator Control and Restart Register Address: 0x9416, Reset: 0x0001, Name: FG_CNTRL_RSTRT This register provides frame generator control and restart functions. Table 80. Bit Descriptions for FG_CNTRL_RSTRT Bits [15:4] 3 [2:0] Bit Name RESERVED FG_RSTRT FG_CNTRL Description Reserved. When set, this bit restarts the frame generator. This bit is self clearing. This bit field controls the frame generator in accordance with the following encoding: 111: reserved. 110: reserved. 101: data field decrementing from 255 (decimal) to 0. 100: alternative 0x55 in the MAC client data frame field. 011: all ones in the MAC client data frame field. 010: all zeros in the MAC client data frame field. 001: random number in the MAC client data frame field. 000: no frames after completion of current frame. Rev. 0 | Page 64 of 79 Reset 0x0 0x0 0x1 Access R R/W R/W Data Sheet ADIN1200 Frame Generator Continuous Mode Enable Register Address: 0x9417, Reset: 0x0000, Name: FG_CONT_MODE_EN This register is used to put the frame generator into continuous mode. The default mode of operation is burst mode, where the number of frames generated is specified by the FG_NFRM_H register and FG_NFRM_L register (Address 0x941C and Address 0x941D). Table 81. Bit Descriptions for FG_CONT_MODE_EN Bits [15:1] 0 Bit Name RESERVED FG_CONT_MODE_EN Description Reserved. This bit is used to put the frame generator into continuous mode or burst mode. 1: frame generator operates in continuous mode. In this mode, the frame generator keeps generating frames indefinitely. 0: frame generator operates in burst mode. In this mode, the frame generator generates a single burst of frames and then stops. The number of frames in the burst is determined by the FG_NFRM_H register and FG_NFRM_L register. Reset 0x0 0x0 Access R R/W Frame Generator Interrupt Enable Register Address: 0x9418, Reset: 0x0000, Name: FG_IRQ_EN This register is used to enable the frame generator interrupt. An interrupt is generated when the requested number of frames has been generated. Enable the frame checker/generator interrupt in the IRQ_MASK register. Set the FC_FG_IRQ_EN bit (Address 0x0018, Bit 7). The interrupt status can be read via the IRQ_STATUS register, FC_FG_IRQ_STAT bit (Address 0x0019, Bit 7). Table 82. Bit Descriptions for FG_IRQ_EN Bits [15:1] 0 Bit Name RESERVED FG_IRQ_EN Description Reserved. When set, this bit indicates that the frame generator must generate an interrupt when it has transmitted the programmed number of frames. 1: enable the frame generator interrupt. 0: disable the frame generator interrupt. Reset 0x0 0x0 Access R R/W Frame Generator Frame Length Register Address: 0x941A, Reset: 0x006B, Name: FG_FRM_LEN This register specifies the MAC client data field frame length in bytes. In addition to the data field, 6 bytes are added for the source address, 6 bytes for the destination address, 2 bytes for the length field, and 4 bytes for the frame check sequence (FCS). The total frame length is the data field length plus 18. Table 83. Bit Descriptions for FG_FRM_LEN Bits [15:0] Bit Name FG_FRM_LEN Description The Data Field Frame Length in Bytes. Reset 0x6B Access R/W Frame Generator Interframe Gap Register Address: 0x941B, Reset: 0x000C, Name: FG_IFG_LEN This register specifies the length in bytes of the interframe gap to be inserted between frames by the frame generator. Table 84. Bit Descriptions for FG_IFG_LEN Bits [15:8] [7:0] Bit Name RESERVED FG_IFG_LEN Description Reserved. Interframe gap length in bytes Rev. 0 | Page 65 of 79 Reset 0x0 0xC Access R R/W ADIN1200 Data Sheet Frame Generator Number of Frames High Register Address: 0x941C, Reset: 0x0000, Name: FG_NFRM_H This register is Bits[31:16] of a 32-bit register that specifics the number of frames to be generated each time the frame generator is enabled or restarted. Table 85. Bit Descriptions for FG_NFRM_H Bits [15:0] Bit Name FG_NFRM_H Description Bits[31:16] of the Number of Frames to be Generated. Reset 0x0 Access R/W Frame Generator Number of Frames Low Register Address: 0x941D, Reset: 0x0100, Name: FG_NFRM_L This register is Bits[15:0] of a 32-bit register that specifics the number of frames to be generated each time the frame generator is enabled or restarted. Table 86. Bit Descriptions for FG_NFRM_L Bits [15:0] Bit Name FG_NFRM_L Description Bits[15:0] of the Number of Frames to be Generated. Reset 0x100 Access R/W Frame Generator Done Register Address: 0x941E, Reset: 0x0000, Name: FG_DONE This register is used to indicate that the frame generator has completed the generation of the number of frames requested in the FG_NFRM_H register and FG_NFRM_L register (Address 0x941C and Address 0x941D, respectively). Table 87. Bit Descriptions for FG_DONE Bits [15:1] 0 Bit Name RESERVED FG_DONE Description Reserved. This bit reads as 1'b1 to indicate that the generation of frames has completed. When set, this bit goes high and it latches high until it is unlatched by reading. Reset 0x0 0x0 Access R R Reset 0x0 0x0 Access R R/W FIFO_SYNC Register Address: 0x9427, Reset: 0x0000, Name: FIFO_SYNC When set, the transmit FIFO is configured for synchronous operation to minimize latency. Table 88. Bit Descriptions for FIFO_SYNC Bits [15:1] 0 Bit Name RESERVED FIFO_SYNC Description Reserved. FIFO_SYNC. When set, the transmit FIFO is configured for synchronous operation to minimize latency. Rev. 0 | Page 66 of 79 Data Sheet ADIN1200 Start of Packet Control Register Address: 0x9428, Reset: 0x0034, Name: SOP_CTRL This register controls the start of packet (SOP) detection for IEEE 1588 time stamp controls. Table 89. Bit Descriptions for SOP_CTRL Bits [15:7] [6:4] Bit Name RESERVED SOP_N_8_CYCM_1 3 SOP_NCYC_EN 2 SOP_SFD_EN 1 0 SOP_RX_EN SOP_TX_EN Description Reserved. When the SOP_NCYC_EN bit is set, the SOP_N_8_CYCM_1 bit field specifies the number of cycles of the MII RX_CLK clock that the transmit and receive SOP indications remain asserted. Add 1 to the value specified and then multiply by 8 to get the number of cycles. Note that the SOP indications are always deasserted at the end of the frame. When this bit is set, the duration of the transmit and receive SOP indications are defined by the SOP_N_8_CYCM_1 bit field. Otherwise, the SOP indications are set for the duration of the frame. When this bit is set, SFD detection is enabled, so that the SOP signals are asserted when the SFD in the frame is detected. If this register bit is cleared, the SOP signals are asserted on the first byte or nibble of the frame. Note that if this signal is changed while packets are being transmitted or received, the SOP signals may be wrongly asserted. Therefore, only change the signal while the link is down or when SOP_TX_EN and SOP_RX_EN are cleared. When set, this bit enables the generation of SOP detection for received frames. When set, this bit enables the generation of SOP detection for transmitted frames. To minimize the SOP indication variation, the detection is done after the transmit FIFO for modes in which the transmit FIFO is used. Reset 0x0 0x3 Access R R/W 0x0 R/W 0x1 R/W 0x0 0x0 R/W R/W Reset 0x0 Access R/W 0x0 R/W 0x0 R/W Reset 0x0 0x0 Access R R/W 0x0 R/W 0x0 R/W Start of Packet Receive Detection Delay Register Address: 0x9429, Reset: 0x0000, Name: SOP_RX_DEL This register controls the receive side SOP detection delay. Table 90. Bit Descriptions for SOP_RX_DEL Bits [15:11] Bit Name SOP_RX_10_DEL_NCYC [10:6] SOP_RX_100_DEL_NCYC [5:0] Reserved Description This register field specifies the number of cycles of the MII RX_CLK clock to delay the received frames SOP indication for 10BASE-T links. This register field specifies the number of cycles of the MII RX_CLK clock to delay the received frames SOP indication for 100BASE-TX links. Reserved. Start of Packet Transmit Detection Delay Register Address: 0x942A, Reset: 0x0000, Name: SOP_TX_DEL This register controls the transmit side SOP detection delay. Table 91. Bit Descriptions for SOP_TX_DEL Bits [15:13] [12:8] Bit Name RESERVED SOP_TX_10_DEL_N_8_NS [7:4] SOP_TX_100_DEL_N_8_NS [3:0] Reserved Description Reserved. This bit field specifies the number of 8 ns periods to delay the transmitted frames SOP indication for 10BASE-T links. To align the transmit SOP indication assertion close to the reference point set on the MDI pins, set this register to 5'd20. This bit field specifies the number of 8 ns periods to delay the transmitted frames SOP indication for 100BASE-TX links. To align the transmit SOP indication assertion close to the reference point set on the MDI pins, set this register to 4'd0. Reserved Rev. 0 | Page 67 of 79 ADIN1200 Data Sheet Control of FIFO Depth for MII Modes Register Address: 0x9602, Reset: 0x0001, Name: DPTH_MII_BYTE FIFO depth in bytes in MII modes. Table 92. Bit Descriptions for DPTH_MII_BYTE Bits [15:1] 0 Bit Name RESERVED DPTH_MII_BYTE Description Reserved. Applies to MII modes for 10 Mbps and 100 Mbps. When set, the FIFO depth is in bytes. When zero, the FIFO depth is in nibbles. The default value of this bit is 1. Therefore, the FIFO prefill is set in bytes. In MII mode, because the interface is nibble based, the internal prefill in the transmit FIFO is larger and, therefore, the latency is longer. Reset 0x0 0x1 Access R R/W LPI Wake Error Count Register Address: 0xA000, Reset: 0x0000, Name: LPI_WAKE_ERR_CNT This address corresponds to the EEE wake error counter register specified in Clause 45.2.3.10 of IEEE Standard 802.3, which in the IEEE standard is at MMD Register Address 3.22. Table 93. Bit Descriptions for LPI_WAKE_ERR_CNT Bits [15:0] Bit Name LPI_WAKE_ERR_CNT Description This bit field counts wake time faults where the PHY fails to complete its normal wake sequence within the time required. This field self clears upon reading. Reset 0x0 Access R Base 10e Enable Register Address: 0xB403, Reset: 0x0001, Name: B_10_E_EN When set, this register enables 10BASE-Te operation. 10BASE-Te is a variant of 10BASE-T that transmits at a lower voltage level. Table 94. Bit Descriptions for B_10_E_EN Bits [15:1] 0 Bit Name RESERVED B_10_E_EN Description Reserved. 10BASE-Te. When set, this bit enables 10BASE-Te operation, this is the default operation of the device. 10BASE-Te is a variant of 10BASE-T that transmits at a lower voltage level. Reset 0x0 0x1 Access R R/W Reset 0x0 0x0 Access R R/W 10BASE-T Transmit Test Mode Register Address: 0xB412, Reset: 0x0000, Name: B_10_TX_TST_MODE This register provides the ability to transmit a 10BASE-T test signal. Table 95. Bit Descriptions for B_10_TX_TST_MODE Bits [15:3] [2:0] Bit Name RESERVED B_10_TX_TST_MODE Description Reserved. The PHY provides the ability to transmit a 10BASE-T test signal consisting of either a 5 MHz or a 10 MHz square wave. 111: reserved. 110: reserved. 101: reserved. 100: transmit 5 MHz square wave on Dimension 1. 011: transmit 5 MHz square wave on Dimension 0. 010: transmit 10 MHz square wave on Dimension 1. 001: transmit 10 MHz square wave on Dimension 0. 000: 10BASE-T test mode disabled. Rev. 0 | Page 68 of 79 Data Sheet ADIN1200 100BASE-TX Transmit Test Mode Register Address: 0xB413, Reset: 0x0000, Name: B_100_TX_TST_MODE This register provides the ability to transmit a 100BASE-TX test signal. Table 96. Bit Descriptions for B_100_TX_TST_MODE Bits [15:3] [2:0] Bit Name RESERVED B_100_TX_TST_MODE Description Reserved. The PHY provides the ability to transmit a 100BASE-TX test signal that cycles continuously through the valid MLT3 signal levels: zero, positive, zero, and negative. Each transmit level can be held for either 16 ns (short dwell time) or 112 ns (long dwell time). The MLT3 transmit test waveform with a 16 ns dwell time measures duty cycle distortion, as specified in Clause 9.1.8 of ANSI Standard X3.263. The MLT3 transmit test waveform with a 112 ns dwell time measures waveform overshoot, amplitude symmetry, and rise/fall times, as specified in Clauses 9.1.3, 9.1.4, and 9.1.6 of ANSI Standard X3.263. 111: reserved. 110: reserved. 101: reserved. 100: transmit MLT3 test waveform, 112 ns dwell time on Dimension 1. 011: transmit MLT3 test waveform, 112 ns dwell time on Dimension 0. 010: transmit MLT3 test waveform, 16 ns dwell time on Dimension 1. 001: transmit MLT3 test waveform, 16 ns dwell time on Dimension 0. 000: 100BASE-TX test mode disabled. Reset 0x0 0x0 Access R R/W Run Automated Cable Diagnostics Register Address: 0xBA1B, Reset: 0x0000, Name: CDIAG_RUN This register is used to start the automated running of cable diagnostics and to return results in the cable diagnostic results registers. Table 97. Bit Descriptions for CDIAG_RUN Bits [15:1] 0 Bit Name RESERVED CDIAG_RUN Description Reserved. When set, this bit starts an automatic cable diagnostics run. Run this bit with the PHY in standby. Clear the LINK_EN bit (PHY_CTRL_3 register, Address 0x0017, Bit 13). This bit self clears when the cable diagnostics are completed. Reset 0x0 0x0 Access R R/W Cable Diagnostics Cross Pair Fault Checking Disable Register Address: 0xBA1C, Reset: 0x0000, Name: CDIAG_XPAIR_DIS This register allows the checking of cross pair faults in the cable diagnostics to be disabled. Table 98. Bit Descriptions for CDIAG_XPAIR_DIS Bits [15:1] 0 Bit Name RESERVED CDIAG_XPAIR_DIS Description Reserved. When set, this bit disables cross pair fault checking. 1: disable cross pair fault checking. 0: enable cross pair fault checking. Rev. 0 | Page 69 of 79 Reset 0x0 0x0 Access R R/W ADIN1200 Data Sheet Cable Diagnostics Results 0 Register Address: 0xBA1D, Reset: 0x0000, Name: CDIAG_DTLD_RSLTS_0 This register provides cable diagnostics results for Pair 0. Table 99. Bit Descriptions for CdiagDtldRslts0 Bits [15:11] 10 Bit Name RESERVED CDIAG_RSLT_0_BSY [9:8] 7 RESERVED CDIAG_RSLT_0_XSIM_1 6 [5:4] 3 2 1 0 CDIAG_RSLT_0_SIM RESERVED CDIAG_RSLT_0_XSHRT_1 CDIAG_RSLT_0_SHRT CDIAG_RSLT_0_OPN CDIAG_RSLT_0_GD Description Reserved. When set, this bit indicates that Pair 0 is busy. This bit indicates that there was unknown activity on Pair 0 during cable diagnostics. Reserved. When set, this bit indicates that there is a significant impedance cross pair short between Pair 0 and Pair 1. When set, this bit indicates that there is a significant impedance mismatch on Pair 0. Reserved. When set, this bit indicates that there is a cross pair short between Pair 0 and Pair 1. When set, this bit indicates that there is a short on Pair 0. When set, this bit indicates that there is an open on Pair 0. When set, this bit indicates that Pair 0 is well terminated. Reset 0x0 0x0 Access R R 0x0 0x0 R R 0x0 0x0 0x0 0x0 0x0 0x0 R R R R R R Reset 0x0 0x0 Access R R 0x0 0x0 R R 0x0 0x0 0x0 0x0 0x0 0x0 R R R R R R Reset 0x0 0xFF Access R R Cable Diagnostics Results 1 Register Address: 0xBA1E, Reset: 0x0000, Name: CDIAG_DTLD_RSLTS_1 This register provides cable diagnostics results for Pair 1. Table 100. Bit Descriptions for CDIAG_DTLD_RSLTS_1 Bits [15:11] 10 Bit Name RESERVED CDIAG_RSLT_1_BSY [9:8] 7 RESERVED CDIAG_RSLT_1_XSIM_0 6 [5:4] 3 2 1 0 CDIAG_RSLT_1_SIM RESERVED CDIAG_RSLT_1_XSHRT_0 CDIAG_RSLT_1_SHRT CDIAG_RSLT_1_OPN CDIAG_RSLT_1_GD Description Reserved. When set, this bit indicates Pair 1 is busy. This bit indicates that there was unknown activity on Pair 1 during cable diagnostics. Reserved. When set, this bit indicates that there is a significant impedance cross pair short between Pair 1 and Pair 0. When set, this bit indicates that there is a significant impedance mismatch on Pair 1. Reserved. When set, this bit indicates that there is a cross pair short between Pair 1 and Pair 0. When set, this bit indicates that there is a short on Pair 1. When set, this bit indicates that there is an open on Pair 1. When set, this bit indicates that Pair 1 is well terminated. Cable Diagnostics Fault Distance Pair 0 Register Address: 0xBA21, Reset: 0x00FF, Name: CDIAG_FLT_DIST_0 This register provides the distance to the first fault on Pair 0. Table 101. Bit Descriptions for CDIAG_FLT_DIST_0 Bits [15:8] [7:0] Bit Name RESERVED CDIAG_FLT_DIST_0 Description Reserved. This bit field provides the distance to the first fault on Pair 0 in meters. A value of 0xFF indicates an unknown result. Rev. 0 | Page 70 of 79 Data Sheet ADIN1200 Cable Diagnostics Fault Distance Pair 1 Register Address: 0xBA22, Reset: 0x00FF, Name: CDIAG_FLT_DIST_1 This register provides the distance to the first fault on Pair 1. Table 102. Bit Descriptions for CDIAG_FLT_DIST_1 Bits [15:8] [7:0] Bit Name RESERVED CDIAG_FLT_DIST_1 Description Reserved. This bit field provides the distance to the first fault on Pair 1 in meters. A value of 0xFF indicates an unknown result. Reset 0x0 0xFF Access R R Cable Diagnostics Cable Length Estimate Register Address: 0xBA25, Reset: 0x00FF, Name: CDIAG_CBL_LEN_EST This register provides an estimate of the cable length in meters based on the signal processing and is estimated during link establishment for 100BASE-TX. Table 103. Bit Descriptions for CDIAG_CBL_LEN_EST Bits [15:8] [7:0] Bit Name RESERVED CDIAG_CBL_LEN_EST Description Reserved. This bit field provides a cable length estimate in meters. A value of 0xFF indicates an unknown result. Reset 0x0 0xFF Access R R LED Pulse Stretching Duration Register Address: 0xBC00, Reset: 0x0011, Name: LED_PUL_STR_DUR When the LED_PUL_STR_DUR_SEL bit field in the LED_CTRL_1 register (Address 0x001B, Bits[3:2]) is set to 2'b11, the LED_PUL_STR_DUR register determines the LED pulse stretching duration. Table 104. Bit Descriptions for LED_PUL_STR_DUR Bits [15:6] [5:0] Bit Name RESERVED LED_PUL_STR_DUR Description Reserved. When the LED_PUL_STR_DUR_SEL bit field in the LED_CTRL_1 register (Address 0x001B, Bits[3:2]) is set to 2'b11, the LED_PUL_STR_DUR bit field determines the LED pulse stretching duration. Multiply the value specified by 8 to determine the duration in milliseconds. Reset 0x0 0x11 Access R R/W SUBSYSTEM REGISTER SUMMARY The subsystem registers are accessible at Device Address 0x1E using Clause 45 access. For systems that do not support the interface specified under Clause 45, these registers can be accessed using Clause 22 access via Register 0x0010 and Register 0x0011. The default value of some of the registers are determined by the value of the hardware configuration pins, which are read just after the RESET_N pin is deasserted (see Hardware Configuration Pins section) so that the default operation of the ADIN1200 can be configured in unmanaged applications. The default values in the registers listed in Table 105 assume that the ADIN1200 is configured with autonegotiation enabled, all speeds advertised, and the ADIN1200 is not configured to enter software power-down after reset. Table 105. Subsystem Register Summary Address 0xFF0C 0xFF0D 0xFF1F 0xFF23 0xFF24 0xFF26 0xFF3C 0xFF3D 0xFF3E 0xFF3F 0xFF41 Name GE_SFT_RST GE_SFT_RST_CFG_EN GE_CLK_CFG GE_RGMII_CFG GE_RMII_CFG GE_PHY_BASE_CFG GE_LNK_STAT_INV_EN GE_IO_GP_CLK_OR_CNTRL GE_IO_GP_OUT_OR_CNTRL GE_IO_INT_N_OR_CNTRL GE_IO_LED_A_OR_CNTRL Description Subsystem Software Reset Register. Subsystem Software Reset Configuration Enable Register. Subsystem Clock Configuration Register. Subsystem RGMII Configuration Register. Subsystem RMII Configuration Register. Subsystem PHY Base Configuration Register. Subsystem Link Status Invert Enable Register. Subsystem GP_CLK Pin Override Control Register. Subsystem LINK_ST Pin Override Control Register. Subsystem INT_N Pin Override Control Register. Subsystem LED_0 Pin Override Control Register. Rev. 0 | Page 71 of 79 Reset 0x0000 0x0000 0x0000 0x0E07 0x0116 0x0C86 0x0000 0x0000 0x0000 0x0000 0x0000 Access R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W ADIN1200 Data Sheet SUBSYSTEM REGISTER DETAILS Subsystem Software Reset Register Address: 0xFF0C, Reset: 0x0000, Name: GE_SFT_RST The soft reset register is used to reset the subsystem. Table 106. Bit Descriptions for GE_SFT_RST Bits [15:1] 0 Bit Name RESERVED GE_SFT_RST Description Reserved. The subsystem can be reset by setting GE_SFT_RST to 1. The subsystem behavior depends on the setting of the GE_SFT_RST_CFG_EN register. When the GE_SFT_RST_CFG_EN bit is set, the subsystem requests a new set of hardware configuration pin settings from the chip during the software reset sequence. When GE_SFT_RST_CFG_EN is clear, the previously stored hardware configuration pin settings are reloaded into the corresponding management registers. Reset 0x0 0x0 Access R R/W Subsystem Software Reset Configuration Enable Register Address: 0xFF0D, Reset: 0x0000, Name: GE_SFT_RST_CFG_EN In the event of a software reset using the GE_SFT_RST bit, the subsystem behavior depends on the setting of this register bit. Table 107. Bit Descriptions for GE_SFT_RST_CFG_EN Bits [15:1] 0 Bit Name RESERVED GE_SFT_RST_CFG_EN Description Reserved. In the event of a subsystem software reset using the GE_SFT_RST bit, the subsystem behavior depends on the setting of the GE_SFT_RST_CFG_EN bit. 1: when the GE_SFT_RST_CFG_EN bit is set, the subsystem requests a new set of hardware configuration pin settings from the chip during the software reset sequence. 0: when GE_SFT_RST_CFG_EN is clear, the previously stored hardware configuration pin settings are reloaded into the corresponding management registers. Reset 0x0 0x0 Access R R/W Reset 0x0 0x0 Access R R/W 0x0 0x0 0x0 R/W R/W R/W 0x0 R/W 0x0 R/W Subsystem Clock Configuration Register Address: 0xFF1F, Reset: 0x0000, Name: GE_CLK_CFG This register allows the subsystem output clock configuration to be controlled. Table 108. Bit Descriptions for GE_CLK_CFG Bits [15:6] 5 Bit Name RESERVED GE_CLK_RCVR_125_EN 4 3 2 GE_CLK_FREE_125_EN RESERVED GE_CLK_HRT_RCVR_EN 1 GE_CLK_HRT_FREE_EN 0 GE_CLK_25_EN Description Reserved. When this bit is set, the125 MHz PHY recovered clock (or PLL clock) is driven at the GP_CLK pin. When this bit is set, the 125 MHz PHY free running clock is driven at the GP_CLK pin. Reserved. The PHY provides a digital recovered heartbeat clock. This clock is sourced from either the 25 MHz reference clock or the 125 MHz recovered clock depending on the mode that the PHY is in and on the settings of certain registers. Setting GE_CLK_HRT_RCVR_EN causes the subsystem to request the chip to drive the digital recovered heartbeat clock at the GP_CLK pin. The PHY provides a digital free running heartbeat clock. This clock is sourced either from the 25 MHz reference clock or the 125 MHz free running clock depending on the mode that the PHY is in and on the settings of certain registers. Setting GE_CLK_HRT_FREE_EN causes the subsystem to request the chip to drive the digital free running heartbeat clock at the GP_CLK pin. When this bit is set, the 25 MHz reference clock from the crystal oscillator is driven at the GP_CLK pin (having been processed through the digital block). Rev. 0 | Page 72 of 79 Data Sheet ADIN1200 Subsystem RGMII Configuration Register Address: 0xFF23, Reset: 0x0E07, Name: GE_RGMII_CFG This register allows the MAC interface RGMII configuration to be controlled. Table 109. Bit Descriptions for GE_RGMII_CFG Bits [15:11] 10 Bit Name RESERVED GE_RGMII_100_LOW_LTNCY_EN 9 GE_RGMII_10_LOW_LTNCY_EN [8:6] GE_RGMII_RX_SEL [5:3] GE_RGMII_GTX_SEL 2 GE_RGMII_RX_ID_EN 1 GE_RGMII_TX_ID_EN 0 GE_RGMII_EN Description Reserved. Enable/Disable Low RGMII Latency for 100BASE-TX. 1: enable low RGMII latency for 100BASE-TX. 0: disable low RGMII latency for 100BASE-TX. Enable/Disable Low RGMII Latency for 10BASE-T. 1: enable low RGMII latency for 10BASE-T. 0: disable low RGMII latency for 10BASE-T. This field allows the RGMII receive clock delay to be specified in terms of the data link layer (DLL) unit delay (tU = 200 ps). 111: 10 × tU + 400 ps. 110: 9 × tU + 400 ps. 101: reserved. 100: reserved. 011: reserved. 010: 7 × tU + 400 ps. 001: 6 × tU + 400 ps. 000: 8 × tU + 400 ps. This field allows the RGMII transmit clock delay to be specified in terms of the DLL unit delay (tU = 200 ps). 111: 10 × tU + 400 ps. 110: 9 × tU + 400 ps. 101: reserved. 100: reserved. 011: reserved. 010: 7 × tU + 400 ps. 001: 6 × tU + 400 ps. 000: 8 × tU + 400 ps. Enable/disable receive clock internal 2 ns delay in RGMII mode. Note that the default value of this bit is configurable via hardware configuration pins. This allows the default operation of the PHY to be configured in unmanaged applications. 1: enable receive clock internal 2 ns delay in RGMII mode. 0: disable receive clock internal 2 ns delay in RGMII mode. Enable/disable transmit clock internal 2 ns delay in RGMII mode. Note that the default value of this bit is configurable via hardware configuration pins. This allows the default operation of the PHY to be configured in unmanaged applications. 1: enable transmit clock internal 2 ns delay in RGMII mode. 0: disable transmit clock internal 2 ns delay in RGMII mode. This bit selects the RGMII MAC interface mode. Note that the default value of this bit is configurable via hardware configuration pins. This allows the default operation of the PHY to be configured in unmanaged applications. Rev. 0 | Page 73 of 79 Reset 0x1 0x1 Access R R/W 0x1 R/W 0x0 R/W 0x0 R/W 0x1 R/W 0x1 R/W 0x1 R/W ADIN1200 Data Sheet Subsystem RMII Configuration Register Address: 0xFF24, Reset: 0x0116, Name: GE_RMII_CFG This register allows the MAC interface RMII configuration to be controlled. Table 110. Bit Descriptions for GE_RMII_CFG Bits [15:8] 7 [6:4] Bit Name RESERVED GE_RMII_FIFO_RST GE_RMII_FIFO_DPTH 3 GE_RMII_TXD_CHK_EN 2 GE_RMII_CRS_EN 1 GE_RMII_BAD_SSD_RX_ER_EN 0 GE_RMII_EN Description Reserved. This bit allows the RMII FIFO to be reset. This field allows the RMII receive FIFO depth to be selected. 111: reserved. 110: reserved. 101: ± 24 bits. 100: ± 20 bits. 011: ± 16 bits. 010: ± 12 bits. 001: ± 8 bits. 000: ± 4 bits. This bit determines whether or not the TXD_0 pin and TXD_1 pin are monitored to detect the start of a frame. This bit allows connecting the RMII receive CRS_DV to the RMII TX_EN signal. This allows a receive to transmit RMII pin loopback for media converter applications. This is something that it is not supported in the RMII specification. This bit determines whether or not CRS is encoded in the CRS_DV output signal. This allows a receive to transmit RMII pin loopback for media converter applications. This is something that it is not supported in the RMII specification. This bit determines whether or not the RX_ER output signal is asserted when a false carrier (bad SSD) is detected. When cleared, RX_ER is only asserted in case of a symbol error during a frame. This bit selects the RMII MAC interface mode. Note that the default value of this register bit is configurable via hardware configuration pins. This allows the default operation of the PHY to be configured in unmanaged applications. As RMII mode requires a 50 MHz reference clock, the RMII interface must be configured from the hardware configuration pins and not from software. Reset 0x1 0x0 0x1 Access R R/W R/W 0x0 R/W 0x1 R/W 0x1 R/W 0x0 R/W Subsystem PHY Base Configuration Register Address: 0xFF26, Reset: 0x0C86, Name: GE_PHY_BASE_CFG This subsystem register allows the enhanced link detection function of the PHY to be configured for 100BASE. Each time a PHY core software reset is issued, the PHY resets its registers and the enhanced link detection 100BASE-TX enable register bits (within the FLD_EN register, Address 0x8E27). The default value of the enhanced link detection 100BASE-T enable register bits (within the FLD_EN register) are set via the GE_FLD_100_EN_CFG bit within this register. If the value of any of these enable configuration bits are changed, the corresponding enhanced link detection 100BASE-TX enable register bit in the PHY only change after a PHY software reset. Table 111. Bit Descriptions for GE_PHY_BASE_CFG Bits [15:13] 12 11 10 Bit Name RESERVED RESERVED RESERVED GE_FLD_100_EN_CFG [9:4] 3 [2:0] RESERVED GE_PHY_SFT_PD_CFG RESERVED Description Reserved. Reserved. Reserved. When this bit is set, the enhanced link detection functionality is enabled when the PHY establishes a 100BASE-TX link. Reserved. When this bit is set, the PHY enters software power-down on exit from reset. Reserved. Rev. 0 | Page 74 of 79 Reset 0x0 0x0 0x1 0x1 Access R R/W R/W R/W 0x8 0x0 0x6 R/W R/W R/W Data Sheet ADIN1200 Subsystem Link Status Invert Enable Register Address: 0xFF3C, Reset: 0x0000, Name: GE_LNK_STAT_INV_EN This register allows the link status output signal on the LINK_ST pin to be inverted, meaning that link up is indicated by setting LINK_ST low. Table 112. Bit Descriptions for GE_LNK_STAT_INV_EN Bits [15:1] 0 Bit Name RESERVED GE_LNK_STAT_INV_EN Description Reserved. When set to 1, this bit enables the link status output signal on the LINK_ST pin to be inverted, meaning that link up is indicated by setting LINK_ST low. Reset 0x0 0x0 Access R R/W Reset 0x0 0x0 Access R R/W Reset 0x0 0x0 Access R R/W Subsystem GP_CLK Pin Override Control Register Address: 0xFF3D, Reset: 0x0000, Name: GE_IO_GP_CLK_OR_CNTRL This register allows the default function of the GP_CLK pin to be overridden. Table 113. Bit Descriptions for GE_IO_GP_CLK_OR_CNTRL Bits [15:3] [2:0] Bit Name RESERVED GE_IO_GP_CLK_OR_CNTRL Description Reserved. This bit field allows the default function of the GP_CLK pin to be overridden. 111: PHY clock selected by the registers in the GE_CLK_CFG register. 110: RX_ER. 101: COL. 100: CRS. 011: receive start of packet indication. 010: transmit start of packet indication. 001: link status. 000: default function. The default function is RX_ER when the PHY is configured for MII or RMII MAC interface. In all other cases, the default function is GP_CLK. Subsystem LINK_ST Pin Override Control Register Address: 0xFF3E, Reset: 0x0000, Name: GE_IO_GP_OUT_OR_CNTRL This register allows the default function of the LINK_ST pin to be overridden. Table 114. Bit Descriptions for GE_IO_GP_OUT_OR_CNTRL Bits [15:3] [2:0] Bit Name RESERVED GE_IO_GP_OUT_OR_CNTRL Description Reserved. This bit field allows the default function of the LINK_ST pin to be overridden. 111: link status. 110: reserved. 101: COL. 100: CRS. 011: receive start of packet indication. 010: transmit start of packet indication. 001: link status. 000: default function, link status. Rev. 0 | Page 75 of 79 ADIN1200 Data Sheet Subsystem INT_N Pin Override Control Register Address: 0xFF3F, Reset: 0x0000, Name: GE_IO_INT_N_OR_CNTRL This register allows the default function of the INT_N pin to be overridden. Table 115. Bit Descriptions for GE_IO_INT_N_OR_CNTRL Bits [15:3] [2:0] Bit Name RESERVED GE_IO_INT_N_OR_CNTRL Description Reserved. This bit field allows the default function of the INT_N pin to be overridden. 111: INT_N. 110: TX_ER. 101: COL. 100: CRS. 011: receive start of packet indication. 010: transmit start of packet indication. 001: link status. 000: default function, INT_N. The default function when configured for MII MAC interface with EEE advertisement disabled from hardware pin configuration is CRS. In all other cases, the pin function is INT_N. Reset 0x0 0x0 Access R R/W Reset 0x0 0x0 Access R R/W Subsystem LED_0 Pin Override Control Register Address: 0xFF41, Reset: 0x0000, Name: GE_IO_LED_A_OR_CNTRL This register allows the default function of the LED_0 pin to be overridden. Table 116. Bit Descriptions for GE_IO_LED_A_OR_CNTRL Bits [15:4] [3:0] Bit Name RESERVED GE_IO_LED_A_OR_CNTRL Description Reserved. This bit field allows the default function of the LED_0 pin to be overridden. 1111: LED_0. 1110: LED_0. 1101: LED_0. 1100: LED_0. 1011: LED_0. 1010: LED_0. 1001: reserved. 1000: reserved. 0111: LED_0. 0110: TX_ER. 0101: COL. 0100: CRS. 0011: receive start of packet indication. 0010: transmit start of packet indication. 0001: link status. 0000: default function, LED_0. When configured for MII MAC interface with EEE advertisement disabled from the hardware configuration pins, the default function is COL. When configured for MII MAC interface with EEE advertisement enabled from the hardware pin configuration, the default function is TX_ER. In all other cases, the default is LED_0. Rev. 0 | Page 76 of 79 Data Sheet ADIN1200 PCB LAYOUT RECOMMENDATIONS PHY PACKAGE LAYOUT The LFCSP has an exposed pad underneath the package that must be soldered to the PCB ground for mechanical and thermal reasons. For thermal impedance performance and to maximize heat removal, use of a 4 × 4 array of thermal vias beneath the exposed ground pad is recommended. There are also two keepout areas on the top and bottom of the exposed pad. The PCB land pattern must incorporate the exposed ground pad with vias and these two keepout areas in the footprint. No PCB traces or vias can be used in either of the keepout areas. The EVAL-ADIN1200FMCZ uses an array of 4 × 4 vias on a 0.75 mm grid arrangement, as shown in Figure 38. The via pad diameter dimension is 0.018 in. (0.4572 mm) and the finished drill hole diameter is 0.012 in. (0.3048 mm). MDI, DIFFERENTIAL PAIR ROUTING The MDI interface runs from the ADIN1200 PHY to the transformer, and from there to the RJ45 connector. Traces running from the MDI_x_x pins of the ADIN1200 to the magnetics must be on the same side of the board, kept as short as possible (ideally less than 1 in. in length), and individual trace impedance of these tracks kept below 50 Ω, with differential impedance of 100 Ω for each pair. The same recommendations apply for traces running from the magnetics to the RJ45 connector. Keep impedances constant throughout because any discontinuities may affect signal integrity. Each pair must be routed together, trace widths kept the same throughout, trace lengths kept equal where possible, and avoid any right angles on these traces (use curves in traces or 45° angles). Avoid stubs on all signal traces. Where possible, route traces on the same layer. Route traces over a continuous reference plane with no interruptions to reduce inductance. Where possible, ensure a solid return path underneath all signal traces. Avoid routing signal traces across plane splits. TRACES RUN PARALLEL THROUGHOUT AVOID STUBS AVOID CROSSING POWER OR GND PLANES GROUND OR POWER GROUND OR POWER 21561-044 This is an overview of the key areas of interest during placement and layout of the PHY and corresponding support components. Take care when routing high speed interface signals to maximize signal performance and ensure optimum EMC performance, with a view to ensure critical signal traces are kept as short as possible to minimize noise coupling. Figure 39. Things to Avoid When Routing Differential Pairs KEEPOUT 21561-043 MAC INTERFACE PINS Keep trace lengths as short as possible. Route traces with an impedance of 50 Ω to ground. Figure 38. Exposed Pad Via Array on EVAL-ADIN1200FMCZ COMPONENT PLACEMENT POWER AND GROUND PLANES Prioritization of the critical traces and components helps simplify the routing exercise. Place and orient the critical traces and components first to ensure an effective layout with minimal turns, vias, and crossing traces. For an Ethernet PHY layout, the important components are the crystal and load capacitors, the transformer on the MDI lines, and all bypass capacitors local to the device. Prioritize these components and the routing to them. Keep the PHY chip at least 1 in. away from the edge of the board. The following sections provide more detail for each of the areas. From a PCB layout point of view, it is important to place the decoupling capacitors as close as possible to the power and GND pins to minimize the inductance. Crystal Placement and Routing For optimal EMC performance, it is recommended to use a metal shielded RJ45 connector with the shield connected to chassis ground. There must be an isolation gap between the chassis ground and the PHY IC ground with consistent isolation across all layers. To ensure minimum current consumption and to minimize stray capacitances, make connections between the crystal, capacitors, and ground as close to the ADIN1200 as possible. Magnetics Placement Magnetics Module Grounding A split ground plane under the transformer minimizes noise coupling across the transformer and between adjacent coils within. Ensure a physical separation of the ground planes underneath the transformer. Make the width of this separation at least 100 mil. RJ45 Module Grounding Orient the magnetics and RJ45 in line with the MDI_x_x pins from the PHY chip. Rev. 0 | Page 77 of 79 ADIN1200 Data Sheet LAYOUT GUIDELINES FOR LFCSP PACKAGE The LFCSP package has an exposed pad that must be soldered to a metal plate on the PCB for mechanical reasons and to GND. The package also has two keepout areas to the top and bottom of the exposed pad. No PCB traces or vias can be used in these areas. For thermal impedance performance, use of a JEDEC 2S2P board with a 4 × 4 array of thermal vias beneath the exposed GND pad is required. Rev. 0 | Page 78 of 79 Data Sheet ADIN1200 OUTLINE DIMENSIONS DETAIL A (JEDEC 95) 5.10 5.00 SQ 4.90 0.016 REF 0.30 0.25 0.20 0.50 BSC PIN 1 INDIC ATOR AREA OPTIONS (SEE DETAIL A) 2.80 2.70 2.60 1 2.90 2.80 SQ 2.70 3.50 REF EXPOSED PAD 8 17 TOP VIEW 0.80 0.75 0.70 END VIEW PKG-005911 SEATING PLANE 0.50 0.40 0.30 0.25 0.15 0.05 32 25 24 16 0.05 MAX 0.02 NOM COPLANARITY 0.08 0.203 REF 9 BOTTOM VIEW 2.37 2.27 2.17 0.09 REF FOR PROPER CONNECTION OF THE EXPOSED PAD, REFER TO THE PIN CONFIGURATION AND FUNCTION DESCRIPTIONS SECTION OF THIS DATA SHEET. COMPLIANT TO JEDEC STANDARDS MO-220-WHHD-2 08-01-2018-A PIN 1 INDICATOR AREA Figure 40. 32-Lead Lead Frame Chip Scale Package [LFCSP] 5 mm × 5 mm Body and 0.75 mm Package Height (CP-32-31) Dimensions shown in millimeters ORDERING GUIDE Model1 ADIN1200CCP32Z ADIN1200CCP32Z-R7 ADIN1200BCP32Z ADIN1200BCP32Z-R7 EVAL-ADIN1200FMCZ 1 Temperature Range −40°C to +105°C −40°C to +105°C −40°C to +85°C −40°C to +85°C Package Description 32-Lead Lead Frame Chip Scale Package 32-Lead Lead Frame Chip Scale Package 32-Lead Lead Frame Chip Scale Package 32-Lead Lead Frame Chip Scale Package Evaluation Board Z = RoHS Compliant Part. ©2019 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. D21561-0-11/19(0) Rev. 0 | Page 79 of 79 Package Option CP-32-31 CP-32-31 CP-32-31 CP-32-31