±450°/Sec Precision Angular Rate Sensor
ADIS16136
Data Sheet
FEATURES
GENERAL DESCRIPTION
Digital gyroscope system, ±450°/sec measurement range
In-run bias stability, 4°/hour
Autonomous operation and data collection
No external configuration commands required
Start-up time: 180 ms; sleep mode recovery: 2.5 ms
Factory calibrated sensitivity and bias
Calibration temperature range: −40°C to +70°C
SPI-compatible serial interface
Wide bandwidth: 380 Hz
Embedded temperature sensor
Programmable operation and control
Automatic and manual bias correction controls
Digital filters: Bartlett FIR, average/decimation
Internal sample rate: up to 2048 SPS
Digital I/O: data ready, alarm indicator, general-purpose
Alarms for condition monitoring
Sleep mode for power management
Enable input sync operation
Single-supply operation: 4.75 V to 5.25 V
2000 g shock survivability
Operating temperature range: −40°C to +85°C
The ADIS16136 iSensor® is a high performance, digital gyroscope
sensing system that operates autonomously and requires no
user configuration to produce accurate rate sensing data. It
provides performance advantages with its low noise density,
wide bandwidth, and excellent in-run bias stability, which enable
applications such as platform control, navigation, robotics, and
medical instrumentation.
This sensor system combines industry leading iMEMS® technology
with signal conditioning that optimizes dynamic performance. The
factory calibration characterizes the entire sensor signal chain for
sensitivity and bias over a temperature range of −40°C to +70°C. As
a result, each ADIS16136 has its own unique correction formulas
to produce accurate measurements upon installation. For some
systems, the factory calibration eliminates the need for system
level calibration and greatly simplifies it for others.
The ADIS16136 provides data at rates of up to 2048 SPS and
offers an averaging/decimation filter structure for optimizing
noise/bandwidth trade-offs. The serial peripheral interface (SPI)
and user register structure provide easy access to configuration
controls and calibrated sensor data for embedded processor
platforms.
APPLICATIONS
The 36 mm × 44 mm × 14 mm package provides four holes for
simple mechanical attachment, using M2 (or 2-56 standard size)
machine screws along with a standard 24-pin, dual row, 1 mm
pitch connector that supports electrical attachment to a printed
circuit board (PCB) or cable system.
Precision instrumentation
Platform stabilization and control
Industrial vehicle navigation
Downhole instrumentation
Robotics
FUNCTIONAL BLOCK DIAGRAM
DIO1 DIO2 DIO3 DIO4/CLKIN RST
I/O
ALARMS
MEMS
SENSOR
CONTROLLER
POWER
MANAGEMENT
USER
CONTROL
REGISTERS
CS
TEMP
SENSOR
CLOCK
SPI
PORT
CALIBRATION
OUTPUT
DATA
REGISTERS
FILTER
ADIS16136
GND
SCLK
DIN
DOUT
10249-001
SELF-TEST
VDD
Figure 1.
Rev. D
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ADIS16136
Data Sheet
TABLE OF CONTENTS
Features .............................................................................................. 1
Automatic Bias Correction (Autonull) .................................... 13
Applications ....................................................................................... 1
Manual Bias Correction ............................................................ 13
General Description ......................................................................... 1
Alarms .............................................................................................. 14
Functional Block Diagram .............................................................. 1
Static Alarm Use ......................................................................... 14
Revision History ............................................................................... 2
Dynamic Alarm Use .................................................................. 14
Specifications..................................................................................... 3
Alarm Reporting ........................................................................ 14
Timing Specifications .................................................................. 4
System Controls .............................................................................. 15
Absolute Maximum Ratings ....................................................... 5
Global Commands ..................................................................... 15
ESD Caution .................................................................................. 5
Memory Management ............................................................... 15
Pin Configuration and Function Descriptions ............................. 6
General-Purpose Input/Output................................................ 15
Typical Performance Characteristics ............................................. 7
Automatic Self Test..................................................................... 16
Theory of Operation ........................................................................ 8
Power Management.................................................................... 16
Reading Sensor Data .................................................................... 8
Status ............................................................................................ 16
Output Data Registers.................................................................. 9
Product Identification................................................................ 17
Device Configuration .................................................................. 9
Applications Information .............................................................. 18
User Registers .................................................................................. 10
Power Supply Considerations ................................................... 18
Digital Processing Configuration ................................................. 11
Prototype Interface Board ......................................................... 18
Internal Sample Rate .................................................................. 11
Installation Tips .......................................................................... 19
Input Clock Configuration........................................................ 11
Packaging and Ordering Information ......................................... 20
Digital Filtering ........................................................................... 11
Outline Dimensions ................................................................... 20
Averaging/Decimation Filter .................................................... 12
Ordering Guide .......................................................................... 20
Calibration ....................................................................................... 13
REVISION HISTORY
2/14—Rev. C to Rev. D
Changes to Features Section............................................................ 1
Changes to Table 1 ............................................................................ 3
Changes to Table 5 ............................................................................ 6
9/13—Rev. B to Rev. C
Changes to Prototype Interface Board Section, Figure 22,
and Figure 23 ................................................................................... 18
2/13—Rev. A to Rev. B
Changes to Table 1 ............................................................................ 3
Changes to Table 4 ............................................................................ 5
Changes to Table 31 and Automatic Self Test Section ............... 16
11/11—Rev. 0 to Rev. A
Changes to Functional Times Parameters, Table 1 ...................... 3
10/11—Revision 0: Initial Version
Rev. D | Page 2 of 20
Data Sheet
ADIS16136
SPECIFICATIONS
TA = 25°C, VDD = 5.0 V, angular rate = 0°/sec, dynamic range = ±450°/sec, ±1 g, unless otherwise noted.
Table 1.
Parameter
GYROSCOPES
Dynamic Range
Sensitivity
Repeatability 1
Sensitivity Temperature Coefficient
Nonlinearity
Bias Repeatability1, 2
Bias Temperature Coefficient
In-Run Bias Stability
Angular Random Walk
Linear Acceleration Effect on Bias
Bias Voltage Sensitivity
Misalignment
Output Noise
Rate Noise Density
3 dB Bandwidth
Sensor Resonant Frequency
LOGIC INPUTS 3
Input High Voltage, VIH
Input Low Voltage, VIL
Logic 1 Input Current, IIH
Logic 0 Input Current, IIL
All Pins Except RST
RST Pin
Input Capacitance, CIN
DIGITAL OUTPUTS3
Output High Voltage, VOH
Output Low Voltage, VOL
FLASH MEMORY
Data Retention4
FUNCTIONAL TIMES 5
Power-On Start-Up Time
Reset Recovery Time
Sleep Mode Recovery Time
Flash Memory Update
Flash Memory Self Test
Automatic Sensor Self Test Time
SAMPLE RATE
Test Conditions/Comments
Internal Sample Rate Accuracy
SMPL_PRD = 0x000F
SMPL_PRD = 0x0000
Operating voltage range, VDD
SMPL_PRD = 0x001F
Sleep mode
Input Sync Clock Range
POWER SUPPLY
Power Supply Current
Min
Typ
±450
Max
Unit
±480
±35
±0.01
±0.15
±0.00125
4
0.167
0.017
±0.08
±1.0
0.11
0.00357
380
17.5
20
°/sec
°/sec/LSB
%
ppm/°C
% of FS
°/sec
°/sec/°C
°/hr
°/√hr
°/sec/g
°/sec/V
Degrees
°/sec rms
°/sec/√Hz rms
Hz
kHz
±0.2
0.8
±1
V
V
µA
7.139x10−5
GYRO_OUT, GYRO_OUT2 (24 bits)
−40°C ≤ TA ≤ +70°C
−40°C ≤ TA ≤ +70°C, 1 σ
Best fit straight line, ±400°/sec
−40°C ≤ TA ≤ +70°C, 1 σ
−40°C ≤ TA ≤ +70°C, 1 σ
25°C, SMPL_PRD = 0x000F
1 σ, 25°C
1σ
VDD = 4.75 V to 5.25 V, 1 σ
Axis-to-frame (package)
No filtering
f = 25 Hz, no filtering
±1
15.5
2.0
VIH = 3.3 V
VIL = 0 V
40
80
10
ISOURCE = 1.6 mA
ISINK = 1.6 mA
Endurance 4
TJ = 85°C
Time until data is available
2.4
0.4
10,000
20
245
128
2.5
72
21
245
SMPL_PRD ≠ 0x0000
6806
1
60
680 6
4.75
5.0
120
1.4
2048
±3
2048
5.25
μA
μA
pF
V
V
Cycles
Years
ms
ms
ms
ms
ms
ms
SPS
%
Hz
V
mA
mA
The Repeatability specifications represent analytical projections, which are based off of the following drift contributions and conditions: temperature hysteresis (−40°C
to +70°C), electronics drift (High-Temperature Operating Life test: +85°C, 500 hours), drift from temperature cycling (JESD22, Method A104-C, Method N, 500 cycles,
−40°C to +85°C), rate random walk (10 year projection), and broadband noise
2
Bias repeatability describes a long-term behavior, over a variety of conditions. Short-term repeatability is related to the in-run bias stability and noise density specifications.
3
The digital I/O signals are driven by an internal 3.3 V supply, and the inputs are 5 V tolerant.
4
JEDEC Standard 22, Method A117. Endurance measured at −40°C, +25°C, +85°C, and +125°C.
5
These times do not include thermal settling and internal filter response times, which may affect overall accuracy.
6
The sync input clock and internal sampling clock function below the specified minimum value, at reduced performance levels.
Rev. D | Page 3 of 20
ADIS16136
Data Sheet
TIMING SPECIFICATIONS
TA = 25°C, VDD = 5 V, unless otherwise noted.
Table 2.
Parameter
fSCLK
tSTALL
tREADRATE
tCS
Description
Serial clock
Stall period between data, see Figure 3
Read rate
Chip select to clock edge
tDAV
tDSU
tDHD
tSCLKR, tSCLKF
tDR, tDF
tSFS
t1
t2
t3
tx
DOUT valid after SCLK edge
DIN setup time before SCLK rising edge
DIN hold time after SCLK rising edge
SCLK rise and fall times
DOUT rise and fall times
CS high after SCLK edge
Input sync positive pulse width
Input sync to data ready output
Input sync period
Input sync low time
1
Normal Mode
Typ
Max
2.5
Min 1
0.01
15
25
48.8
Unit
MHz
µs
µs
ns
25
ns
ns
ns
ns
ns
ns
µs
µs
µs
µs
24.4
48.8
5
5
12.5
12.5
0
5
300
488
100
Guaranteed by design and characterization but not tested in production.
Timing Diagrams
CS
tCS
tSFS
1
2
3
4
5
6
15
16
SCLK
tDAV
MSB
DB14
DB13
tDSU
DIN
R/W
A6
DB12
DB11
A4
A3
DB10
DB2
DB1
LSB
tDHD
A5
D2
A2
D1
10249-002
DOUT
LSB
Figure 2. SPI Timing and Sequence
tREADRATE
tSTALL
10249-003
CS
SCLK
Figure 3. Stall Time and Data Rate
t3
t2
t1
tX
10249-004
SYNC
CLOCK (CLKIN)
DATA
READY
Figure 4. Input Clock Timing Diagram
Rev. D | Page 4 of 20
Data Sheet
ADIS16136
ABSOLUTE MAXIMUM RATINGS
Stresses above those listed under Absolute Maximum Ratings
may cause permanent damage to the device. This is a stress
rating only; functional operation of the device at these or any
other conditions above those indicated in the operational
section of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect
device reliability.
Table 3.
Parameter
Acceleration
Any Axis, Unpowered
Any Axis, Powered
VDD to GND
Digital Input Voltage to GND
Digital Output Voltage to GND
Operating Temperature Range
Storage Temperature Range
1
Rating
2000 g
2000 g
−0.3 V to +6.0 V
−0.3 V to +5.3 V
−0.3 V to VDD + 0.3 V
−40°C to +85°C
−65°C to +125°C1, 2
Table 4. Package Characteristics
Extended exposure to temperatures outside the specified temperature
range of −40°C to +105°C can adversely affect the accuracy of the factory
calibration. For best accuracy, store the devices within the specified
operating range of −40°C to +105°C.
2
Although the device is capable of withstanding short term exposure to
150°C, long-term exposure threatens internal mechanical integrity.
Package Type
24-Lead Module with Connector
Interface
ESD CAUTION
Rev. D | Page 5 of 20
θJA
15.7
θJC
1.48
Device
Weight
31 g
ADIS16136
Data Sheet
PIN CONFIGURATION AND FUNCTION DESCRIPTIONS
ADIS16136
24 22 20 18 16 14 12 10
8
6
4
2
23 21 19 17 15 13 11
7
5
3
1
9
NOTES
1. PINS ARE NOT VISIBLE FROM THIS VIEW. THE PIN ASSIGNMENTS
SHOWN REPRESENT THE MATING CONNECTOR ASSIGNMENTS.
2. USE SAMTEC CLM-112-02 OR EQUIVALENT.
10249-005
TOP VIEW
Figure 5. Mating Connector Pin Assignments
RATE
AXIS
POSITIVE
ROTATION
DIRECTION
10249-006
+
Figure 6. Axial Orientation (Bottom Side Facing Up)
Table 5. Pin Function Descriptions
Pin No.
1
2
3
4
5
6
7
8
9
10, 11, 12
13, 14, 15
16 to 24
1
Mnemonic
DIO3
DIO4/CLKIN
SCLK
DOUT
DIN
CS
DIO1
RST
DIO2
VDD
GND
DNC
Type 1
I/O
I
I
O
I
I
I/O
I
I/O
S
S
N/A
Description
Configurable Digital Input/Output.
Configurable Digital Input/Output/Clock Input
SPI Serial Clock.
SPI Data Output. Clocks output on SCLK falling edge.
SPI Data Input. Clocks input on SCLK rising edge.
SPI Chip Select.
Configurable Digital Input/Output.
Reset.
Configurable Digital Input/Output.
Power Supply.
Power Ground.
Do Not Connect. Do not connect to these pins.
I/O is input/output, I is input, O is output, S is supply, N/A is not applicable.
Rev. D | Page 6 of 20
Data Sheet
ADIS16136
TYPICAL PERFORMANCE CHARACTERISTICS
0.20
+1σ
AVERAGE
–1σ
INITIAL BIAS ERROR = ±0.1°
BIAS TEMPERATURE COEFFICIENT = ±0.00125°/sec/°C
0.15
OFFSET ERROR (°/sec)
ROOT ALLAN VARIANCE (°/Hr)
100
10
0.10
0.05
0
–0.05
–0.10
0.1
1
10
100
1000
10000
TAU (Seconds)
–0.20
–40 –30 –20 –10
10249-025
1
0.01
Figure 7. Root Allan Variance, 5 V, 25°C, 1024 SPS
SENSITIVITY ERROR (%)
INITIAL SENSITIVITY ERROR = ±0.35%
SENSITIVITIY TEMPC = ±25ppm/°C
0
–0.20
5
15
25
35
45
55
65
75
TEMPERATURE (°C)
10249-026
–0.40
–5
20
30
40
50
60
70
Figure 9. Offset (Bias) Error vs. Temperature, −40°C to +75°C to −40°C
0.40
–0.60
–45 –35 –25 –15
10
TEMPERATURE (°C)
0.60
0.20
0
10249-027
–0.15
Figure 8. Sensitivity Error vs. Temperature, −40°C to +75°C to −40°C
Rev. D | Page 7 of 20
ADIS16136
Data Sheet
THEORY OF OPERATION
Table 7. Generic Master Processor SPI Settings
The ADIS16136 is an autonomous system that requires no user
initialization. As soon as it has a valid power supply, it initializes
and starts sampling, processing, and loading sensor data into
the output registers. After each sample cycle concludes, DIO1
pulses high. The SPI interface enables simple integration with
many embedded processor platforms, as shown in Figure 10
(electrical connection) and Table 6 (processor pin names and
functions).
11
A single register read requires two 16-bit SPI cycles. The first
cycle requests the contents of a register using the bit assignments
in Figure 13. Then, the register contents follow on DOUT during
the second sequence. Figure 11 includes three single register reads
in succession. In this example, the process starts with Pin 5,
DIN = 0x0600, to request the contents of the GYRO_OUT
register and follows with 0x0400 to request the contents of the
GYRO_OUT2 register and with 0x0200 to request the contents
of the TEMP_OUT register. Full duplex operation enables processors to use the same 16-bit SPI cycle to read data from DOUT
while requesting the next set of data on the DIN pin. Figure 12
provides an example of the four SPI signals when reading
GYRO_OUT in a repeating pattern.
12
ADIS16136
SS
6
CS
SCLK
3
SCLK
MOSI
5
DIN
MISO
4
DOUT
IRQ
7
DIO1
13
14
15
Figure 10. Electrical Connection Diagram
Table 6. Generic Master Processor Pin Names and Functions
Pin Name
SS
IRQ
MOSI
MISO
SCLK
Function
Slave select
Interrupt request
Master output, slave input
Master input, slave output
Serial clock
DIN
0x0600
DOUT
0x0400
0x0200
GYRO_OUT
GYRO_OUT2
TEMP_OUT
Figure 11. SPI Read Example
CS
The ADIS16136 SPI interface supports full duplex serial
communication (simultaneous transmit and receive) and uses
the bit sequence shown in Figure 13. Table 7 provides a list of
the most common settings that require attention to initialize a
processor serial port for the ADIS16136 SPI interface.
SCLK
DIN
DIN = 0000 0110 0000 0000 = 0x0600
DOUT
DOUT = 1111 1001 1101 1010 = 0xF9DA = –1574 LSBs = –29.765°/sec
Figure 12. SPI Read Example, Second 16-Bit Sequence
CS
DIN
R/W
D15
A6
A5
A4
A3
A2
A1
A0
DC7
DC6
DC5
DC4
DC3
DC2
DC1
DC0
D14
D13
D12
D11
D10
D9
D8
D7
D6
D5
D4
D3
D2
D1
D0
R/W
D15
A6
A5
D14
D13
NOTES
1. DOUT BITS ARE PRODUCED ONLY WHEN THE PREVIOUS 16-BIT DIN SEQUENCE STARTS WITH R/W = 0.
2. WHEN CS IS HIGH, DOUT IS IN A THREE-STATE, HIGH-IMPEDANCE MODE, WHICH ALLOWS MULTIFUNCTIONAL USE OF THE LINE
FOR OTHER DEVICES.
Figure 13. SPI Communication Bit Sequence
Rev. D | Page 8 of 20
10249-013
SCLK
DOUT
10249-011
SYSTEM
PROCESSOR
SPI MASTER
READING SENSOR DATA
5V
10
Description
ADIS16136 operates as a slave
Maximum serial clock rate
CPOL = 1 (polarity), CPHA = 1 (phase)
Bit sequence
Shift register/data length
10249-012
I/O LINES ARE COMPATIBLE WITH
3.3V OR 5V LOGIC LEVELS
10249-010
VDD
Processor Setting
Master
SCLK Rate ≤ 2 MHz
SPI Mode 3
MSB First Mode
16-Bit Mode
Data Sheet
ADIS16136
OUTPUT DATA REGISTERS
Table 12. TEMP_OUT Bit Descriptions
Table 8. Output Data Register Formats
Bits
[15:0]
Measurement
Internal temperature
Gyroscope, lower 16 bits
Gyroscope, upper 16 bits
Table 13. Temperature, Twos Complement Format
Rotation Rate (Gyroscope)
GYRO_OUT is the primary register for gyroscope output data
and uses 16-bit twos complement format for its data. Table 9
provides the numerical format, and Table 10 provides several
examples for converting digital data into °/sec.
Table 9. GYRO_OUT Bit Descriptions
Bits
[15:0]
Description
Gyroscope data; twos complement, 0.018275°/sec per
LSB, 0°/sec = 0x0000
Table 10. GYRO_OUT, Twos Complement Format
Rotation Rate
+450°/sec
+0.03655°/sec
+0.018275°/sec
0°/sec
−0.018275°/sec
−0.03655°/sec
−450°/sec
Decimal
+24,623
+2
+1
0
−1
−2
−24,623
Hex
0x602F
0x0002
0x0001
0x0000
0xFFFF
0xFFFE
0x9FD1
Binary
0110 0000 0010 1111
0000 0000 0000 0010
0000 0000 0000 0001
0000 0000 0000 0000
1111 1111 1111 1111
1111 1111 1111 1110
1001 1111 1101 0001
The GYRO_OUT2 register (see Table 11) captures the bit growth
associated with the decimation and FIR filters that are shown in
Figure 18 using a MSB justified format. The bit growth starts
with the MSB (GYRO_OUT2[15]), is equal to the decimation
rate setting in DEC_RATE[4:0] (see Table 18), and grows in the
LSB direction as the decimation rate increases. See Figure 14 for
more details.
Table 11. GYRO_OUT2 Bit Descriptions
Description
Rotation rate data; resolution enhancement bits
D
GYROSCOPE DATA
15
GYRO_OUT
BIT WEIGHT =
D = DEC_RATE[4:0]
NOT USED
0 15
GYRO_OUT2
0.018275 °/sec
LSB = GYRO_OUT2[16-D]
LSB
2D
0
10249-014
Bits
[15:0]
Temperature
+85°C
+0.021394°C
+0.010697°C
0°C
−0.010697 °C
−0.021394°C
−40°C
Decimal
+7946
+2
+1
0
−1
−2
−3739
Hex
0x1F0A
0x0002
0x0001
0x0000
0xFFFF
0xFFFE
0xF165
Binary
0001 1111 0000 1010
0000 0000 0000 0010
0000 0000 0000 0001
0000 0000 0000 0000
1111 1111 1111 1111
1111 1111 1111 1110
1111 0001 0110 0101
DEVICE CONFIGURATION
The control registers listed in Table 14 provide a variety of user
configuration options. The SPI provides access to these registers,
one byte at a time, using the bit assignments shown in Figure 13.
Each register has 16 bits, wherein Bits[7:0] represent the lower
address and Bits[15:8] represent the upper address.
Figure 15 provides an example of writing 0x03 to Address 0x22
(DEC_RATE[7:0]), using Pin 5, DIN = 0xA203. This example
reduces the sample rate by a factor of 8 (see Table 16).
CS
SCLK
DIN
DIN = 1010 0010 0000 0011 = 0xA203, WRITES 0x03 TO ADDRESS 0x22
10249-015
Address
0x02
0x04
0x06
Figure 15. SPI Sequence for Setting the Decimate Rate to 8 (DIN = 0xA203)
Dual Memory Structure
Writing configuration data to a control register updates its SRAM
contents, which are volatile. After optimizing each relevant control
register setting in a system, set GLOB_CMD[3] = 1 (DIN =
0xA808) to backup these settings in the nonvolatile flash memory.
The flash back up process requires a valid power supply level for
the entire 72 ms process time. Table 14 provides a user register
memory map that includes a column of flash backup information.
A “yes” in this column indicates that a register has a mirror location
in flash and, when backed up properly, automatically restores itself
during startup or after a reset. Figure 16 provides a diagram of the
dual memory structure that is used to manage operation and store
critical user settings.
MANUAL
FLASH
BACKUP
Figure 14. Gyroscope Output Format, DEC_RATE[4:0] > 0
Internal Temperature
The TEMP_OUT register (see Table 12) provides an internal
temperature measurement that can be useful for observing
relative temperature changes in the environment. Table 13
provides several coding examples for converting the 16-bit
twos complement number into units for temperature (°C).
NONVOLATILE
FLASH MEMORY
VOLATILE
SRAM
(NO SPI ACCESS)
SPI ACCESS
START-UP
RESET
Figure 16. SRAM and Flash Memory Diagram
Rev. D | Page 9 of 20
10249-016
Register
TEMP_OUT
GYRO_OUT2
GYRO_OUT
Description
Temperature data; twos complement, 0.010697°C per
LSB, 0°C = 0x0000
ADIS16136
Data Sheet
USER REGISTERS
Table 14. User Register Memory Map
Name
FLASH_CNT
TEMP_OUT
GYRO_OUT2
GYRO_OUT
GYRO_OFF2
GYRO_OFF
Reserved
ALM_MAG1
ALM_MAG2
ALM_SMPL1
ALM_SMPL2
ALM_CTRL
GPIO_CTRL
MSC_CTRL
SMPL_PRD
AVG_CNT
DEC_RATE
SLP_CTRL
DIAG_STAT
GLOB_CMD
Reserved
LOT_ID1
LOT_ID2
LOT_ID3
PROD_ID
SERIAL_NUM
1
2
R/W
R
R
R
R
R/W
R/W
N/A 2
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
W
R
W
N/A2
R
R
R
R
R
Flash Backup
Yes
No
No
No
Yes
Yes
N/A2
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
No
No
N/A2
Yes
Yes
Yes
Yes
Yes
Address 1
0x00
0x02
0x04
0x06
0x08
0x0A
0x0C to 0x0F
0x10
0x12
0x14
0x16
0x18
0x1A
0x1C
0x1E
0x20
0x22
0x24
0x26
0x28
0x2A to 0x31
0x32
0x34
0x36
0x38
0x3A
Default
N/A2
N/A2
N/A2
N/A2
0x0000
0x0000
N/A2
0x0000
0x0000
0x0000
0x0000
0x0000
0x0000
0x0006
0x001F
0x0000
0x0000
0x0000
0x0000
0x0000
N/A2
N/A2
N/A2
N/A2
0x3F08
N/A2
Register Description
Flash memory write count
Output, temperature (internal)
Output, gyroscope, lower 16 bits
Output, gyroscope, upper 16 bits
Gyroscope bias correction, lower 16 bits
Gyroscope bias correction, upper 16 bits
Reserved
Alarm 1 trigger setting
Alarm 2 trigger setting
Alarm 1 sample period
Alarm 2 sample period
Alarm configuration
Auxiliary digital input/output control
Miscellaneous control: data ready, self test
Internal sample period (rate) control
Digital filter control
Decimation rate setting
Sleep mode control
System status
System command
Reserved
Lot Identification Code 1
Lot Identification Code 2
Lot Identification Code 3
Product ID, binary number for 16,136
Serial number
Bit Descriptions
Table 30
Table 12
Table 11
Table 9
Table 21
Table 20
Table 23
Table 24
Table 25
Table 25
Table 26
Table 32
Table 31
Table 16
Table 17
Table 18
Table 33
Table 34
Table 29
Table 36
Table 36
Table 36
Table 35
Table 37
Each register contains two bytes. The address column in this table only offers the address of the lower byte. Add 1 to it to calculate the address of the upper byte.
N/A means not applicable.
Rev. D | Page 10 of 20
Data Sheet
ADIS16136
DIGITAL PROCESSING CONFIGURATION
Figure 18 provides a block diagram for the sampling and digital
filter stages inside the ADIS16136. Table 15 provides a summary
of registers for sample rate and filter control.
Table 15. Digital Processing Registers
Description
Sample rate control
Digital filtering and range control
Decimation rate setting
INTERNAL SAMPLE RATE
The SMPL_PRD register in Table 16 provides a programmable
control for the internal sample rate. Use the following formula
to calculate the decimal number for the code to write into this
register:
SMPL _ PRD =
DIGITAL FILTERING
The AVG_CNT register (see Table 17) provides user controls
for the low-pass filter. This filter contains two cascaded averaging
filters that provide a Bartlett window FIR filter response (see
Figure 18). For example, set AVG_CNT[7:0] = 0x04 (DIN =
0xA004) to set each stage to 16 taps. When used with the default
sample rate of 1024 SPS, this establishes a −3 dB bandwidth of
approximately 24 Hz for this filter.
0
32,768
− 1; fS ≤ 2048 SPS
(fS )
–20
The factory default setting for SMPL_PRD sets the internal
sample rate to a rate of 1024 SPS; the minimum setting for the
SMPL_PRD register is 0x000F, which results in an internal
sample rate of 2048 SPS.
–40
–80
–100
Table 16. SMPL_PRD Bit Descriptions
Bits
[15:0]
–60
Description (Default = 0x001F)
Clock setting bits; sets fS in Figure 18
N=2
N=4
N = 16
N = 64
–120
–140
0.001
0.01
0.1
1
FREQUENCY (f/fS)
Figure 17. Bartlett Window FIR Filter Frequency Response
Table 17. AVG_CNT Bit Descriptions
Bits
[15:3]
[2:0]
Rev. D | Page 11 of 20
Description (Default = 0x0000)
Don’t care
Binary; B variable in Figure 18; maximum = 110 (6)
10249-017
Address
0x1E
0x20
0x22
Set SMPL_PRD = 0x0000 (DIN = 0x9F00, then DIN = 0x9E00)
to disable the internal clock and enable DIO4/CLKIN as a clock
input pin.
MAGNITUDE (dB)
Register Name
SMPL_PRD
AVG_CNT
DEC_RATE
INPUT CLOCK CONFIGURATION
ADIS16136
Data Sheet
AVERAGING/DECIMATION FILTER
The DEC_RATE register (see Table 18) provides user control
for the final filter stage (see Figure 18), which averages and
decimates the output data. For systems that value lower sample
rates, this filter stage provides an opportunity to lower the sample
rate while maintaining optimal bias stability performance. The
−3 dB bandwidth of this filter stage is approximately one half
the output data rate. For example, set DEC_RATE[7:0] = 0x04
(DIN = 0xA204) to reduce the sample rate by a factor of 16.
Table 18. DEC_RATE Bit Descriptions
Bits
[15:5]
[4:0]
Description (Default = 0x0000)
Don’t care
Binary; D variable in Figure 18; maximum = 10000 (16)
÷ND
410Hz
1595Hz
–3dB BANDWIDTH = 380Hz
32,768
SP + 1
SP ≥ 15
SP = SMPL_PRD
fS =
CLOCK
fS
B = AVG_CNT[2:0]
NB = 2B
NT = 2NB – 1
NT = TOTAL NUMBER OF TAPS
D = DEC_RATE[4:0]
ND = 2D
ND = NUMBER OF TAPS
ND = DATA RATE DIVISOR
CLKIN
Figure 18. Sampling and Frequency Response Block Diagram
Rev. D | Page 12 of 20
10249-018
MEMS
GYRO
When the factory default 1024 SPS sample rate is used, this
decimation setting reduces the output data rate to 64 SPS and
the sensor bandwidth to approximately 32 Hz.
Data Sheet
ADIS16136
CALIBRATION
The Allan variance curve shown in Figure 7 provides a trade-off
between bias accuracy and averaging time. The DEC_RATE
register provides a user control for averaging time when using
the ABC function. Set DEC_RATE[7:0] = 0x10 (DIN = 0xA210),
which sets the decimation rate to 65,536 (216) and provides an
averaging time of 64 seconds (65,536 ÷ 1024 SPS) for this function.
Next, set GLOB_CMD[0] = 1 (DIN = 0xA801), and keep the
platform stable for at least 65 seconds while the gyroscope bias
data accumulates.
The ADIS16136 factory calibration produces correction
formulas for the gyroscope and programs them into the flash
memory. Table 19 contains a list of user control registers that
provide an opportunity for user optimization after installation.
Figure 19 illustrates the summing function of the sensor’s offset
correction register.
Table 19. Registers for User Calibration
MEMS
GYRO
Address
0x08
0x0A
0x28
ADC
Description
Gyroscope bias
Gyroscope bias
Bias correction command
FACTORY
CALIBRATION
AND
FILTERING
GYRO_OUT GYRO_OUT2
10249-019
Register
GYRO_OFF2
GYRO_OFF
GLOB_CMD
GYRO_OFF GYRO_OFF2
Figure 19. Gyroscope Bias Calibration User Controls
The factory calibration addresses initial and temperature
dependent bias errors in the gyroscopes, but some environmental conditions, such as temperature cycling and mechanical
stress on the package, can cause bias shifts in MEMS gyroscope
structures. For systems that value absolute bias accuracy, there
are two options for optimizing absolute bias accuracy: autonull
and manual correction.
AUTOMATIC BIAS CORRECTION (AUTONULL)
Set GLOB_CMD[0] = 1 (DIN = 0xA801) to start the automatic
bias correction (ABC) function, which uses the following
internal sequence to calibrate each gyroscope for bias error:
1.
2.
3.
4.
5.
Wait for a complete output data cycle to complete, which
includes the entire average and decimation time in
DEC_RATE.
Read the output registers of the gyroscope.
Multiply the measurement by −1 to change its polarity.
Write the final value into the offset registers.
Update the flash memory.
After this completes, the ADIS16136 automatically updates the
flash memory. When the ABC function starts, the SPI is not active.
The only way to interrupt the ABC function is to remove power
or initiate a hardware reset using the RST pin. When using
DEC_RATE = 0x0010, the 1 σ accuracy for this correction is
approximately 0.001°/sec for the gyroscope correction factor.
See Table 29 for more information on GLOB_CMD.
MANUAL BIAS CORRECTION
The GYRO_OFF and GYRO_OFF2 registers (see Table 20 and
Table 21) provide a bias adjustment function for the output of
each sensor. GYRO_OFF has the same format as GYRO_OUT,
and GYRO_OFF2 has the same format as GYRO_OUT2.
Table 20. GYRO_OFF Bit Descriptions
Bits
[15:0]
Description (Default = 0x0000)
Gyroscope offset correction; twos complement,
0.018275°/sec per LSB
Table 21. GYRO_OFF2 Bit Descriptions
Bits
[15:0]
Description (Default = 0x0000)
Gyroscope offset correction, finer resolution; uses
same format as GYRO_OUT2 (see Table 11)
Restoring Factory Calibration
Set GLOB_CMD[1] = 1 (DIN = 0xA802) to execute the factory
calibration restore function. This function resets each user
calibration register to 0x0000, resets all sensor data to 0, and
automatically updates the flash memory within 72 ms. See
Table 29 for more information on GLOB_CMD.
Rev. D | Page 13 of 20
ADIS16136
Data Sheet
ALARMS
The alarm function provides monitoring for two independent
conditions. Table 22 contains a list of registers that provide
configuration and control inputs for the alarm function.
Table 26. ALM_CTRL Bit Descriptions
Bits
[15:12]
Table 22. Registers for Alarm Configuration
Register
ALM_MAG1
ALM_MAG2
ALM_SMPL1
ALM_SMPL2
ALM_CTRL
Address
0x10
0x12
0x14
0x16
0x18
Description
Alarm 1, trigger setting
Alarm 2, trigger setting
Alarm 1, sample period
Alarm 2, sample period
Alarm configuration
[11:8]
7
The ALM_CTRL register (see Table 26) provides data source
selection (Bits[15:8]), static/dynamic setting for each alarm
(Bits[7:6]), trigger polarity (Bits[5:4]), data source filtering
(Bit 3), and an alarm indicator signal (Bits[2:0]).
6
5
4
STATIC ALARM USE
3
The static alarms setting compares the data source selection
(ALM_CTRL[15:8]) with the values in the ALM_MAGx
registers in Table 23 and Table 24. The data format in these
registers matches the format of the data selection in
ALM_CTRL[15:8]. ALM_CTRL[5:4] provide polarity
settings. See Table 27 for a static alarm configuration
example.
2
1
0
Description (Default = 0x0000)
Alarm 2 source selection
0000 = disable
0001 = GYRO_OUT (does not include GYRO_OUT2)
0010 = TEMP_OUT
0011 = DIAG_STAT
Alarm 1 source selection (same as Alarm 2)
Rate-of-change enable for Alarm 2
(1 = rate of change, 0 = static level)
Rate-of-change enable for Alarm 1
(1 = rate of change, 0 = static level)
Comparison polarity for Alarm 2
(1 specifies >ALM_MAG2, 0 specifies ALM_MAG1, 0 specifies ALM_MAG2
Alarm 1: static; GYRO_OUT < ALM_MAG1
use filtered data source for comparison
DIO2 output indicator, positive polarity
ALM_MAG2 = 0x0AAF, (+50°/sec)
ALM_MAG1 = 0x0AAF, (+50°/sec)
ALM_SMPL2[7:0] = 0x66, (102 samples)
Data Sheet
ADIS16136
SYSTEM CONTROLS
The ADIS16136 provides a number of system level controls for
managing its operation using the registers listed in Table 28.
600
Description
General-purpose I/O control
Self test, calibration, data ready
Sleep mode control
Error flags
Single command functions
Lot Identification Code 1
Lot Identification Code 2
Lot Identification Code 3
Product identification
Serial number
450
300
150
0
30
40
55
70
85
100
125
JUNCTION TEMPERATURE (°C)
135
150
10249-113
Address
0x1A
0x1C
0x24
0x26
0x28
0x32
0x34
0x36
0x38
0x3A
RETENTION (Years)
Table 28. System Tool Registers
Register Name
GPIO_CTRL
MSC_CTRL
SLP_CTRL
DIAG_STAT
GLOB_CMD
LOT_ID1
LOT_ID2
LOT_ID3
PROD_ID
SERIAL_NUM
Figure 20. Flash Memory Retention
GLOBAL COMMANDS
Checksum Test
The GLOB_CMD register (see Table 29) provides trigger
bits for several operations. Write 1 to the appropriate bit in
GLOB_CMD to start a function. After the function completes,
the bit restores to 0.
Set MSC_CTRL[11] = 1 (DIN = 0x9D08) to perform a checksum
verification of the internal program memory. This takes a summation of the internal program memory and compares it with the
original summation value for the same locations (from factory
configuration). Check the results in the DIAG_STAT register
(see Table 34). DIAG_STAT[6] = 0 if the sum matches the
correct value and 1 if it does not. Make sure that the power
supply is within specification for the entire 21 ms that this
function takes to complete.
Software Reset
Set GLOB_CMD[7] = 1 (DIN = 0xA880) to reset the operation,
which removes all data, initializes all registers from their flash
settings, and starts data collection. This function provides a
firmware alternative to the RST line (see Table 5, Pin 8).
Table 29. GLOB_CMD Bit Descriptions
Bits
[15:8]
7
[6:4]
3
2
1
0
1
2
Description (Default = 0x0000)
Not used
Software reset
Not used
Flash update
Not used
Factory calibration restore
Automatic bias correction
Execution Time1
N/A
70 ms
N/A
70 ms
N/A
71 ms
N/A2
N/A in this column means not applicable.
Execution time is based on SMPL_PRD and DEC_RATE settings. This starts
at the next data ready pulse, restarts the decimation cycle, and then writes
to the flash (70 ms) after completing a decimation cycle. With respect to
Figure 18, the decimation cycle time = ND ÷ fS.
MEMORY MANAGEMENT
The data retention of the flash memory depends on the temperature, as shown in Figure 20. The FLASH_CNT register (see
Table 30) provides a 16-bit counter that helps track the number
of write cycles to the nonvolatile flash memory, which helps the
user manage against the endurance rating. The flash updates
every time any of the following bits are set to 1: GLOB_CMD[3],
GLOB_CMD[1], and GLOB_ CMD[0].
Table 30. FLASH_CNT Bit Descriptions
Bits
[15:0]
Description)
Binary counter; number of flash updates
GENERAL-PURPOSE INPUT/OUTPUT
There are four general-purpose I/O lines, DIO1, DIO2, DIO3,
and DIO4/CLKIN that provide a number of useful functions. The
MSC_CTRL[2:0] bits (see Table 31) control the data ready configuration and have the highest priority for setting either DIO1 or DIO2
(but not both). The ALM_CTRL[2:0] control bits (see Table 26)
provide the alarm indicator configuration control and have the
second highest priority for DIO1 or DIO2. When DIO1 and DIO2
are not in use as either data ready or alarm indicator signals, the
GPIO_CTRL register (see Table 32) provides the control and data
bits for them, together with the DIO3 and DIO4 lines.
Data Ready Input/Output Indicator
The factory default setting for MSC_CTRL[2:0] is 110, which
configures DIO1 as a positive data ready indicator signal. A
common option for this function is MSC_CTRL[2:0] = 100
(DIN = 0x9C04), which changes data ready to a negative
polarity for processors that provide only negative triggered
interrupt pins. The pulse width is between 100 μs and 200 μs
over all conditions.
Example Input/Output Configuration
For example, set GPIO_CTRL[7:0] = 0x02 (DIN = 0x9A02)
to set DIO1 as an input and DIO2 as an output. Then, set
GPIO_CTRL[15:8] = 0x02 (DIN = 0x9B02) to set DIO2 in a
high output state. Monitor DIO1 by reading GPIO_CTRL[8]
(DIN = 0x1B00).
Rev. D | Page 15 of 20
ADIS16136
Data Sheet
Table 31. MSC_CTRL Bit Descriptions
POWER MANAGEMENT
Bits
[15:12]
11
The SLP_CTRL register (see Table 33) provides two different
sleep modes for system level management: normal and timed.
Set SLP_CTRL[7:0] = 0xFF (DIN = 0xA4FF) to start normal
sleep mode. To awaken the device from sleep mode, use one of
the following options to restore normal operation: assert CS from
high to low, pulse RST low, then high again, or cycle the power. Use
SLP_CTRL[7:0] to put the device into sleep mode for a specified
period. For example, SLP_CTRL[7:0] = 0x64 (DIN = 0xA464)
puts the ADIS16136 to sleep for 50 sec.
10
[9:8]
7
[6:3]
2
1
0
Description (Default = 0x0006)
Not used
Memory test (cleared upon completion)
(1 = enabled, 0 = disabled)
Automatic self test (cleared upon completion)
(1 = enabled, 0 = disabled)
Do not use, always set both bits to zero.
Disable sensor compensation
(1 = disable compensation, 0 = enable compensation)
Not used
Data ready enable
(1 = enabled, 0 = disabled)
Data ready polarity
(1 = active high, 0 = active low)
Data ready line select
(1 = DIO2, 0 = DIO1)
Table 32. GPIO_CTRL Bit Descriptions
Bits
[15:12]
11
10
9
8
[7:4]
3
2
1
0
Description (Default = 0x0000)
Don’t care
General-Purpose I/O Line 4 (DIO4) data level
General-Purpose I/O Line 3 (DIO3) data level
General-Purpose I/O Line 2 (DIO2) data level
General-Purpose I/O Line 1 (DIO1) data level
Don’t care
General-Purpose I/O Line 2 (DIO2) direction control
(1 = output, 0 = input)
General-Purpose I/O Line 1 (DIO1) direction control
(1 = output, 0 = input)
General-Purpose I/O Line 2 (DIO2) direction control
(1 = output, 0 = input)
General-Purpose I/O Line 1 (DIO1) direction control
(1 = output, 0 = input)
AUTOMATIC SELF TEST
The MSC_CTRL bits (see Table 31) provide an automatic self
test function that helps verify the mechanical integrity of the
MEMS structure, along with the basic function of the signal
processing circuit. When enabled, the self test applies an
electrostatic force to MEMS structure, which causes it to move
in a manner that simulates its response to actual rotation. Set
MSC_CTRL[10] = 1 (DIN = 0x9D04) to run the automatic self
test routine, which reports a pass/fail result in DIAG_STAT[5].
MSC_CTRL[10] resets itself to 0 after completing this routine.
This process takes approximately 245 ms.
Table 33. SLP_CTRL Bit Descriptions
Bits
[15:8]
[7:0]
Description
Not used
0xFF: normal sleep mode
0x00 to 0xFE: programmable sleep time bits; 0.5 sec/LSB
STATUS
The DIAG_STAT register (see Table 34) provides error flags for
a number of functions. Each flag uses a 1 to indicate an error
condition and a 0 to indicate a normal condition. Reading this
register provides access to the status of each flag and resets all of
the bits to 0 for monitoring future operation. If the error
condition remains, the error flag returns to 1 at the conclusion
of the next sample cycle. The SPI communication error flag in
DIAG_STAT[3] indicates that the number of SCLKs in a SPI
sequence did not equal a multiple of 16 SCLKs.
Table 34. DIAG_STAT Bit Descriptions
Bits
[15:10]
9
8
7
6
5
4
3
2
[1:0]
Rev. D | Page 16 of 20
Description (Default = 0x0000)
Not used
Alarm 2 status (1 = active, 0 = inactive)
Alarm 1 status (1 = active, 0 = inactive)
Not used
Flash test, checksum flag (1 = fail, 0 = pass)
Self test diagnostic error flag (1 = fail, 0 = pass)
Sensor over range (1 = over range, 0 = normal)
SPI communication failure (1 = fail, 0 = pass)
Flash update failure (1 = fail, 0 = pass)
Not used
Data Sheet
ADIS16136
PRODUCT IDENTIFICATION
Table 35. PROD_ID Bit Descriptions
The PROD_ID register (see Table 35) contains 0x3F08, which is
the hexadecimal equivalent of 16,136. The LOT_ID1, LOT_ID2,
and LOT_ID3 registers (see Table 36) provide manufacturing
lot information. The SERIAL_NUM register (see Table 37) contains a binary number that represents the serial number on the
device label and is lot specific.
Bits
[15:0]
Description
Product identification = 0x3F08 (16,136)
Table 36. LOT_ID1, LOT_ID2, LOT_ID3 Bit Descriptions
Bits
[15:0]
Description
Lot identification, binary code
Table 37. SERIAL_NUM Bit Descriptions
Bits
[15:14]
[13:0]
Rev. D | Page 17 of 20
Description
Not used
Serial number, 1 to 9999 (0x270F)
ADIS16136
Data Sheet
APPLICATIONS INFORMATION
POWER SUPPLY CONSIDERATIONS
The ADIS16136 includes 12 µF of capacitance across the VDD
and GND pins. This capacitance presents low input impedance
for power supplies that have fast rise times. The internal power
regulator waits for a valid input supply voltage, and then goes
through a start-up process that draws an elevated current
(~400 mA) for approximately 1.5 ms. This transient current
occurs approximately 125 ms after VDD reaches a valid level.
This regulation circuit also provides a constant power load,
which results in a load that has a negative dynamic resistance.
Figure 21 provides a graphical relationship between the supply
current and voltage for systems that need to account for this
type of load when designing supply feedback loops.
125
Figure 22 provides the top level view of the interface board.
Install the ADIS16136AMLZ onto this board using the silk
pattern as an orientation guide. Figure 23 provides the pin
assignments for J1 that match the ADIS16136AMLZ pin functions,
which are listed in Table 5. The ADIS16136 does not require
external capacitors for normal operation; therefore, the interface
printed circuit board (PCB) does not use the C1 and C2 pads.
iSensor
ADIS16136
MOUNTING
HOLES
–40˚C
+25˚C
+85˚C
CURRENT (mA)
120
115
4.80
4.85
4.90
4.95
5.00
5.05
5.10
5.15
SUPPLY VOLTAGE (V)
5.20
5.25
Figure 21. Supply Current vs Supply Voltage
PROTOTYPE INTERFACE BOARD
The ADIS16IMU1/PCBZ (sold separately) provides a breakout
board function for the ADIS16136AMLZ. This interface PCB
provides larger connectors than the ADIS16136AMLZ, which
results in a simpler connection with a SPI-compatible processor
board. It also provides four tapped M2 holes for attachment of
the ADIS16136AMLZ to the breakout board and four holes
(machine screw size M2.5 or No. 4) for mounting the breakout
board to a solid structure. J1 is dual-row, 2 mm (pitch)
connector that works with 1 mm ribbon cable systems.
Rev. D | Page 18 of 20
Figure 22. Physical Diagram for the ADIS16IMU1/PCBZ
J1
RST
1
2
SCLK
CS
3
4
DOUT
DNC
5
6
DIN
GND
7
8
GND
GND
9
10
VDD
VDD
11
12
VDD
DIO1
13
14
DIO2
DIO3
15
16
DIO4
10249-021
105
4.75
10249-119
10249-020
110
Figure 23. J1 Pin Assignments
Data Sheet
ADIS16136
INSTALLATION TIPS
31.200 BSC
15.600 BSC
2x 0.560 BSC
ALIGNMENT HOLES
FOR MATING SOCKET
39.60 BSC
19.800 BSC
17.520
2.280
4x 2.500 BSC
10249-022
Figure 24 and Figure 25 provide the mechanical design information used for the ADIS16IMU1/PCBZ. Use these figures
when implementing a connector-down approach, where the
mating connector and the ADIS16136AMLZ are on the same
surface. When designing a connector-up system, use the mounting
holes shown in Figure 24 as a guide in designing the bulkhead
mounting system, and use Figure 25 as a guide in developing the
mating connector interface on a flexible circuit or other connector
system. The mating connector pattern in Figure 25 assumes the
use of the Samtec CLM-112-02 series of connectors.
5.00 BSC
5.00 BSC
Figure 24. Suggested Mounting Hole Locations, Connector Down
0.4334 [11.0]
0.019685
[0.5000]
(TYP)
0.0240 [0.610]
0.054 [1.37]
0.022±
DIA (TYP)
0.022 DIA THRU HOLE (TYP)
NONPLATED
NONPLATED THRU HOLE
THRU HOLE 2×
0.0394 [1.00]
Figure 25. Suggested Layout and Mechanical Design for the Mating Connector
Rev. D | Page 19 of 20
10249-023
0.0394 [1.00] 0.1800
[4.57]
ADIS16136
Data Sheet
PACKAGING AND ORDERING INFORMATION
OUTLINE DIMENSIONS
35.854
35.600
35.346
31.350
31.200
31.050
15.700
15.600
15.500
2.200
TYP
2.400 THRU HOLE
(4 PLACES)
44.254
44.000
43.746
17.670
17.520
17.370
39.750
39.600
39.450
19.900
19.800
19.700
TOP VIEW
14.054
13.800
13.546
2.200 TYP
END VIEW
3.27
3.07
2.87
0.30 BSC SQ
(PIN SIZE)
010908-A
1.00 BSC
(LEAD PITCH)
5.50 BSC
Figure 26. 24-Lead Module with Connector Interface
(ML-24-3)
Dimensions shown in millimeters
ORDERING GUIDE
Model 1
ADIS16136AMLZ
1
Temperature Range
−40°C to +85°C
Package Description
24-Lead Module with Connector Interface
Z = RoHS Compliant Part.
©2011–2014 Analog Devices, Inc. All rights reserved. Trademarks and
registered trademarks are the property of their respective owners.
D10249-0-2/14(D)
Rev. D | Page 20 of 20
Package Option
ML-24-3
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