High Accuracy, Dual-Axis
Digital Inclinometer and Accelerometer
ADIS16209
Data Sheet
FEATURES
FUNCTIONAL BLOCK DIAGRAM
AUX
ADC
AUX
DAC VREF
ADIS16209
TEMPERATURE
SENSOR
DUAL-AXIS
ACCELEROMETER
CALIBRATION
AND
DIGITAL
PROCESSING
SIGNAL
CONDITIONING
AND
CONVERSION
CS
SCLK
SPI
PORT
DIN
DIGITAL
CONTROL
SELF-TEST
DOUT
VDD
POWER
MANAGEMENT
ALARMS
AUXILIARY
I/O
GND
RST
DIO1 DIO2
07096-001
Dual-mode inclinometer system
Dual-axis, horizontal operation, ±90°
Single-axis, vertical operation, ±180°
High accuracy, 0.1°
Digital inclination data, 0.025° resolution
Digital acceleration data, 0.244 mg resolution
±1.7 g accelerometer measurement range
Digital temperature sensor output
Digitally controlled bias calibration
Digitally controlled sample rate
Digitally controlled frequency response
Dual alarm settings with rate/threshold limits
Auxiliary digital I/O
Digitally activated self-test
Digitally activated low power mode
SPI-compatible serial interface
Auxiliary 12-bit ADC input and DAC output
Single-supply operation: 3.0 V to 3.6 V
3500 g powered shock survivability
Figure 1.
APPLICATIONS
Platform control, stabilization, and alignment
Tilt sensing, inclinometers, leveling
Motion/position measurement
Monitor/alarm devices (security, medical, safety)
Navigation
GENERAL DESCRIPTION
The ADIS16209 is a high accuracy, digital inclinometer that
accommodates both single-axis (±180°) and dual-axis (±90°)
operation. The standard supply voltage (3.3 V) and serial
peripheral interface (SPI) enable simple integration into most
industrial system designs. A simple internal register structure
handles all output data and configuration features. This
includes access to the following output data: calibrated
acceleration, accurate incline angles, power supply, internal
temperature, auxiliary analog and digital input signals,
diagnostic error flags, and programmable alarm conditions.
Rev. H
Configurable operating parameters include sample rate,
power management, digital filtering, auxiliary analog and
digital output, offset/null adjustment, and self-test for sensor
mechanical structure.
The ADIS16209 is available in a 9.2 mm × 9.2 mm × 3.9 mm
LGA package that operates over a temperature range of −40°C
to +125°C. It can be attached using standard RoHS-compliant
solder reflow processes.
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ADIS16209
Data Sheet
TABLE OF CONTENTS
Features .............................................................................................. 1
Introduction ................................................................................ 12
Applications ....................................................................................... 1
Register Structure ....................................................................... 12
Functional Block Diagram .............................................................. 1
SPI................................................................................................. 12
General Description ......................................................................... 1
Reading Sensor Data .................................................................. 12
Revision History ............................................................................... 2
Device Configuration ................................................................ 12
Specifications..................................................................................... 4
Output Data Registers................................................................ 15
Timing Specifications .................................................................. 6
Operation Control Registers ..................................................... 17
Timing Diagrams.......................................................................... 6
Calibration Registers .................................................................. 20
Absolute Maximum Ratings ............................................................ 7
Alarm Registers .......................................................................... 20
Thermal Resistance ...................................................................... 7
Applications Information .............................................................. 22
ESD Caution .................................................................................. 7
Power Supply Considerations ................................................... 22
Pin Configuration and Function Descriptions ............................. 8
Assembly...................................................................................... 22
Recommended Pad Geometry.................................................... 8
Interface Board ........................................................................... 23
Typical Performance Characteristics ............................................. 9
X-Ray Sensitivity ........................................................................ 23
Theory of Operation ...................................................................... 11
Outline Dimensions ....................................................................... 24
Basic Operation............................................................................... 12
Ordering Guide .......................................................................... 24
REVISION HISTORY
3/2019—Rev. G to Rev. H
Added Endnote 1, Table 1; Renumbered Sequentially ................ 5
Deleted Figure 20; Renumbered Sequentially............................. 11
Changes to Basic Operation Section ............................................ 12
Added Introduction Section, Register Structure Section,
Figure 20, SPI Section, Figure 21, Reading Sensor Data Section,
Figure 22, Figure 23, and Device Configuration Section .......... 12
Added Table 6 and Table 7; Renumbered Sequentially ............. 12
Added Figure 24, Memory Structure Section, Figure 25, and
Figure 26 .......................................................................................... 13
Moved Table 8 ................................................................................. 14
Changes to Global Commands Section ....................................... 19
Change to the Power Supply Considerations Section................ 22
Added X-Ray Sensitivity Section .................................................. 23
Changes to Ordering Guide .......................................................... 24
8/2018—Rev. F to Rev. G
Change to Note 5, Table 1 ................................................................ 4
Changes to Accelerometers Section ............................................. 12
Change to Digital Filtering Section .............................................. 14
Changes to Global Commands Section ....................................... 16
Changes to Assembly Section ....................................................... 19
Added Figure 23; Renumbered Sequentially .............................. 19
5/2017—Rev. E to Rev. F
Changes to Figure 3 and Figure 4 ....................................................5
Change to Basic Operation Section ............................................. 11
1/2015—Rev. D to Rev. E
Changes to Power Supply Considerations Section and
Assembly Section ............................................................................ 19
Deleted VDD Ramp Rate Requirements Section and Transient
Current Demand from ADIS16209 Section ............................... 19
Added Power-On Reset Function Section .................................. 19
Changes to Figure 23...................................................................... 20
6/2014—Rev. C to Rev. D
Changes to Table 2.............................................................................5
Changes to Table 26 and Self-Test Section .................................. 15
Changes to Status Section.............................................................. 18
Added Power Supply Considerations Section ............................ 19
7/2012—Rev. B to Rev. C
Changes to Endnote 5 in Table 1 .....................................................4
Changed Digital Input/Output Voltage to GND Maximum
Rating from 5.5 V to 5.3 V ...............................................................6
Added 0x40 to 0x49 and 0x4A Addresses to Table 6 ................. 11
Changes to Output Data Registers Section ................................ 12
Changes to Digital Filtering Section ............................................ 14
Changes to Self-Test Section ......................................................... 15
Added Applications Information Section ................................... 18
Updated Outline Dimensions ....................................................... 19
Rev. H | Page 2 of 24
Data Sheet
ADIS16209
8/2009—Rev. A to Rev. B
Changes to Features Section ............................................................ 1
Changes to Input Low Voltage, VINL, Parameter, Table 1 .......... 4
Changes to Figure 18 and Figure 19 .............................................10
Changes to Table 7, Table 8, and Table 10 ....................................12
Updated Outline Dimensions ........................................................16
Changes to Ordering Guide ...........................................................16
7/2008—Rev. 0 to Rev. A
Changes to Figure 19 ...................................................................... 10
Changes to Table 21 ........................................................................ 15
3/2008—Revision 0: Initial Version
Rev. H | Page 3 of 24
ADIS16209
Data Sheet
SPECIFICATIONS
TA = 25°C, VDD = 3.3 V, tilt = 0°, unless otherwise noted.
Table 1.
Parameter
HORIZONTAL INCLINE
Input Range
Relative Accuracy 1
Sensitivity
VERTICAL ROTATION
Input Range
Relative Accuracy
Sensitivity
ACCELEROMETER
Input Range 2
Nonlinearity2
Alignment Error
Cross Axis Sensitivity
Sensitivity
ACCELEROMETER NOISE PERFORMANCE
Output Noise
Noise Density
ACCELEROMETER FREQUENCY RESPONSE
Sensor Bandwidth
Sensor Resonant Frequency
ACCELEROMETER SELF-TEST STATE 3
Output Change When Active
TEMPERATURE SENSOR
Output at 25°C
Scale Factor
ADC INPUT
Resolution
Integral Nonlinearity (INL)
Differential Nonlinearity (DNL)
Offset Error
Gain Error
Input Range
Input Capacitance
ON-CHIP VOLTAGE REFERENCE
Accuracy
Reference Temperature Coefficient
Output Impedance
DAC OUTPUT
Resolution
Relative Accuracy
Differential Nonlinearity
Offset Error
Gain Error
Output Range
Output Impedance
Output Settling Time
Test Conditions
Each axis
Min
Typ
±90
±0.1
0.025
±30° from horizon, AVG_CNT = 0x08
±30° from horizon
Rotational plane within ±30° of vertical
−180
360° of rotation
−40°C to +85°C
Each axis
25°C
Percentage of full scale
X sensor to Y sensor
−40°C to +85°C, VDD = 3.0 V to 3.6 V
+180
±1.7
0.243
706
±0.1
±0.1
±2
0.244
±0.2
0.245
g
%
Degrees
%
mg/LSB
mg rms
mg/√Hz rms
50
5.5
Hz
kHz
1343
1973
LSB
1278
−0.47
LSB
°C/LSB
12
±2
±1
±4
±2
±40
70
Bits
LSB
LSB
LSB
LSB
V
pF
V
mV
ppm/°C
Ω
12
4
1
±5
±0.5
0 to 2.5
2
10
Bits
LSB
LSB
mV
%
V
Ω
µs
2.5
20
2.5
At 25°C
Degrees
Degrees
°/LSB
1.7
0.19
0
During acquisition
Unit
Degrees
Degrees
°/LSB
±0.25
0.025
AVG_CNT = 0x00
AVG_CNT = 0x00
At 25°C
Max
−10
+10
5 kΩ/100 pF to GND
For Code 101 to Code 4095
Rev. H | Page 4 of 24
Data Sheet
Parameter
LOGIC INPUTS
Input High Voltage, VINH
Input Low Voltage, VINL
Logic 1 Input High Current, IINH
Logic 0 Input Low Current, IINL
All Except RST
RST 4
Input Capacitance, CIN
DIGITAL OUTPUTS
Output High Voltage, VOH
Output Low Voltage, VOL
SLEEP TIMER
Timeout Period 5
START-UP TIME 6
Power-On
Reset Recovery
Sleep Mode Recovery
FLASH MEMORY
Endurance 7
Data Retention 8
CONVERSION RATE SETTING
POWER SUPPLY
Operating Voltage Range
Power Supply Current
ADIS16209
Test Conditions
Min
Typ
Max
Unit
±0.2
0.8
±10
V
V
µA
2.0
VIH = 3.3 V
VIL = 0 V
−40
−1
10
ISOURCE = 1.6 mA
ISINK = 1.6 mA
−60
2.4
0.5
Time until data is available
Fast mode, SMPL_PRD ≤ 0x07
Normal mode, SMPL_PRD ≥ 0x08
Fast mode, SMPL_PRD ≤ 0x07
Normal mode, SMPL_PRD ≥ 0x08
3.0
Normal mode, SMPL_PRD ≥ 0x08
Fast mode, SMPL_PRD ≤ 0x07
Sleep mode, −40°C to +85°C
0.4
V
V
128
Seconds
150
190
30
70
2.5
20,000
20
1.04
TJ = 85°C
3.3
11
36
140
μA
mA
pF
ms
ms
ms
ms
ms
2731
Cycles
Years
SPS
3.6
14
42
350
V
mA
mA
µA
X-ray exposure may degrade this performance metric.
Guaranteed by iMEMS® packaged part testing, design, and/or characterization.
3
Self-test response changes as the square of VDD.
4
The RST pin has an internal pull-up.
5
Guaranteed by design.
6
The times presented in this section represent the time it takes to start producing data in the output registers, after the minimum VDD reaches 3.0 V. They do not
represent the settling time of the internal filters.
Note that for the default SENS_AVG and AVG_CNT settings, the typical settling time is ~1.28 seconds. For faster settling times, reduce the AVG_CNT and SMPL_PRD
settings. Note that the trade-off associated with faster settling times is noise and power.
7
Endurance is qualified as per JEDEC Standard 22 Method A117 and measured at −40°C, +25°C, +85°C, and +125°C.
8
Retention lifetime equivalent at junction temperature (TJ) 55°C as per JEDEC Standard 22 Method A117. Retention lifetime decreases with junction temperature.
1
2
Rev. H | Page 5 of 24
ADIS16209
Data Sheet
TIMING SPECIFICATIONS
TA = 25°C, VDD = 3.3 V, tilt = 0°, unless otherwise noted.
Table 2.
Parameter
fSCLK
Description
Fast mode, SMPL_PRD ≤ 0x07 (fS ≥ 546 Hz) 2
Normal mode, SMPL_PRD ≥ 0x08 (fS ≤ 482 Hz)2
Chip select period, fast mode, SMPL_PRD ≤ 0x07 (fS ≥ 546 Hz)2
Chip select period, normal mode, SMPL_PRD ≥ 0x08 (fS ≤ 482 Hz)2
Chip select period, fast mode, SMPL_PRD ≤ 0x07 (fS ≥ 546 Hz)2
Chip select period, normal mode, SMPL_PRD ≥ 0x08 (fS ≤ 482 Hz)2
Chip select to clock edge
Data output valid after SCLK edge
Data input setup time before SCLK rising edge
Data input hold time after SCLK rising edge
Data output fall time
Data output rise time
CS high after SCLK edge
tDATARATE
tSTALL
tCS
tDAV
tDSU
tDHD
tDF
tDR
tSFS
1
2
Min 1
0.01
0.01
32
42
10
12
48.8
Typ
Max
2.5
1.0
Unit
MHz
MHz
μs
μs
μs
μs
ns
ns
ns
ns
ns
ns
ns
100
24.4
48.8
5
5
12.5
12.5
5
Guaranteed by design, not tested.
Note that fS means internal sample rate.
TIMING DIAGRAMS
tDATARATE
tSTALL
CS
07096-002
SCLK
tSTALL = tDATARATE – 16/fSCLK
Figure 2. SPI Chip Select Timing
CS
tCS
tSFS
1
2
3
4
5
6
15
16
SCLK
tDAV
DB14
MSB
DB13
tDSU
DIN
W/R
DB12
DB11
A4
A3
DB10
DB2
DB1
LSB
tDHD
A6
A5
D1
D2
A2
07096-003
DOUT
LSB
Figure 3. SPI Timing
(Utilizing SPI Settings Typically Identified as Phase = 1, Polarity = 1)
DATA FRAME
CS
SCLK
W/R
A6
WRITE = 1
READ = 0
A5
A4
A3
A2
A1
REGISTER ADDRESS
A0
DC7
DC6
DC5 DC4
DC3
DC2
DC1
DATA FOR WRITE COMMANDS
DON’T CARE FOR READ COMMANDS
Figure 4. DIN Bit Sequence
Rev. H | Page 6 of 24
DC0
07096-004
DIN
Data Sheet
ADIS16209
ABSOLUTE MAXIMUM RATINGS
THERMAL RESISTANCE
Table 3.
Parameter
Acceleration (Any Axis, Unpowered)
Acceleration (Any Axis, Powered)
VDD to GND
Digital Input/Output Voltage to GND
Analog Inputs to GND
Analog Inputs to GND
Operating Temperature Range
Storage Temperature Range
Table 4. Package Characteristics
Rating
3500 g
3500 g
−0.3 V to +7.0 V
−0.3 V to +5.3 V
−0.3 to VDD + 0.3 V
−0.3 to VDD + 0.3 V
−40°C to +125°C
−65°C to +150°C
Package Type
16-Terminal LGA
ESD CAUTION
Stresses at or above those listed under Absolute Maximum
Ratings may cause permanent damage to the product. This is a
stress rating only; functional operation of the product at these
or any other conditions above those indicated in the operational
section of this specification is not implied. Operation beyond
the maximum operating conditions for extended periods may
affect product reliability.
Rev. H | Page 7 of 24
θJA
250°C/W
θJC
25°C/W
Device Weight
0.6 g
ADIS16209
Data Sheet
AUX ADC
VDD
16
VREF
GND
PIN CONFIGURATION AND FUNCTION DESCRIPTIONS
15
14
13
12
11
5
6
7
8
DIO2
DNC
DNC
TOP
LOOK THROUGH
VIEW
(Not to Scale)
DNC
RST
NOTES
1. DNC = DO NOT CONNECT TO THIS PIN.
2. THIS IS NOT AN ACTUAL TOP VIEW, BECAUSE THE PINS ARE NOT VISIBLE FROM THE TOP. THIS IS
A LAYOUT VIEW THAT REPRESENTS THE PIN CONFIGURATION IF THE PACKAGE IS LOOKED
THROUGH FROM THE TOP. THIS CONFIGURATION IS PROVIDED FOR PCB LAYOUT PURPOSES.
07096-005
ADIS16209
DIO1
3
CS
DNC
PIN 1
INDICATOR
2
DIN
4
DOUT
AUX DAC
10
AX
9
SCLK
1
AY
Figure 5. Pin Configuration
Table 5. Pin Function Descriptions
Pin No.
1
2
3
4
5, 6
7, 8, 10, 11
9
12
13
14
15
16
1
Mnemonic
SCLK
DOUT
DIN
CS
DIO1, DIO2
DNC
RST
AUX DAC
VDD
AUX ADC
VREF
GND
Type 1
I
O
I
I
I/O
N/A
I
O
S
I
O
S
Description
SPI, Serial Clock.
SPI, Data Output.
SPI, Data Input.
SPI, Chip Select.
Digital Input/Output Pins.
Do not connect to this pin.
Reset, Active Low.
Auxiliary DAC Output.
Power Supply, 3.3 V.
Auxiliary ADC Input.
Precision Reference.
Ground.
S = supply; O = output; I = input.
RECOMMENDED PAD GEOMETRY
2.6955
8×
4.1865
8×
0.670
12×
8.373
2×
5.391
4×
1.127
16×
9.2mm × 9.2mm STACKED LGA PACKAGE
Figure 6. Example of a Pad Layout
Rev. H | Page 8 of 24
07096-006
0.500
16×
Data Sheet
ADIS16209
TYPICAL PERFORMANCE CHARACTERISTICS
0.25
0.20
0.20
MAXIMUM
INCLINE
ERROR
0.15
0.15
0.10
ERROR (Degrees)
0.05
0
–0.05
–0.10
0
–0.05
–0.10
–0.15
–0.15
–0.20
–30
–20
–10
0
10
20
30
40
INCLINATION ANGLE (Degrees)
–0.25
07096-018
–0.20
–40
0.05
0
100
200
300
400
ROTATIONAL ANGLE (Degrees)
07096-021
ERROR (Degrees)
0.10
Figure 10. Vertical Mode Rotational Error (Eight Parts), 25°C, 3.3 V
Figure 7. Horizontal Inclination Error (Eight Parts), Autonull at Horizontal
Position, Stable Temperature, 3.3 V
0.3
0.3
0.2
0.2
0.1
ERROR (Degrees)
ERROR (Degrees)
0.1
0
–0.1
0
–0.1
–0.2
–0.3
–0.2
–20
0
20
40
60
80
TEMPERATURE (°C)
100
–0.5
–60
–40
–20
0
20
40
60
80
TEMPERATURE (°C)
Figure 8. Maximum Incline Error Over a ±30° Incline Range (Eight Parts) Over
Temperature, Autonull at Horizontal Position, 25°C, 3.3 V
100
07096-022
–40
07096-019
–0.3
–60
–0.4
Figure 11. Vertical Mode Error (Eight Parts) vs. Temperature, 0° to 360°, 3.3 V
0.3
0.15
0.2
0.10
0.1
ERROR (Degrees)
0
–0.05
–0.10
–0.1
–0.2
–0.3
–0.15
–0.4
3.0
3.3
SUPPLY VOLTAGE (V)
3.6
–0.5
07096-020
–0.20
0
3.0
3.3
SUPPLY VOLTAGE (V)
Figure 9. Maximum Incline Error Over a ±30° Incline Range (Eight Parts) Over
Supply Voltage, Autonull Horizontal Position, 25°C, 3.3 V
3.6
07096-023
ERROR (Degrees)
0.05
Figure 12. Vertical Mode Error (Eight Parts) vs. Supply Voltage, 0° to 360°, 25°C
Rev. H | Page 9 of 24
ADIS16209
Data Sheet
3.5
VDD = 3.0V, 3.3V, 3.6V
TEMP = –40°C, +25°C, +85°C
3.0
25
2.5
ERROR (Degrees)
20
15
10
5
1.5
0.5
0
–0.38
–0.26
–0.14
–0.02
0.10
0.22
0.34
0.46
SENSITIVITY ERROR (%)
VDD = 3.0V, 3.3V, 3.6V
TEMP = –40°C, +25°C, +85°C
18
16
14
12
10
8
6
4
–6.0
–4.4
–2.8
–1.2
0.4
2.0
3.6
5.2
BIAS ERROR (mg)
07096-014
2
0
10
20
30
40
50
60
70
OFF-VERTICAL TILT (Degrees)
Figure 15. Error vs. Off-Vertical Tilt, 25°C, 3.3 V
Figure 13. Accelerometer Output Sensitivity Error Distribution
20
0
Figure 14. Accelerometer Output Bias Error Distribution
Rev. H | Page 10 of 24
80
90
07096-015
0
–0.50
PERCENTAGE OF POPULATION (%)
2.0
1.0
07096-013
PERCENTAGE OF POPULATION (%)
30
Data Sheet
ADIS16209
THEORY OF OPERATION
The ADIS16209 tilt sensing system uses gravity as its only
stimulus, and a MEMS accelerometer as its sensing element.
MEMS accelerometers typically employ a tiny, spring-loaded
structure that is interlaced with a fixed pick-off finger structure.
The spring constant of the floating structure determines how
far it moves when subjected to a force. This structure responds
to dynamic forces associated with acceleration and to static
forces, such as gravity.
θx
GRAVITY = 1g
HORIZON
Figure 16. Single-Axis Tilt Theory Diagram
θx
θx
HORIZON
Figure 17. Dual-Axis Tilt Theory Diagram
1
5
4
8
1 16
13
12
13
8
4
XINCL_OUT = 0°
YINCL_OUT = 0°
16
9 12
8 9
5
07096-008
ax
9
5
0° ≤ XINCL_OUT ≤ 90°
YINCL_OUT = 0°
07096-011
4
ay
0° TILT
LEVEL PLANE
13
12
07096-007
θx
Figure 16 and Figure 17 illustrate how the accelerometer
responds to gravity, according to its orientation, with respect
to gravity. Figure 16 displays the configuration for the incline
angle outputs, and Figure 17 displays the configuration used
for the rotational angle position. This configuration provides
greater measurement range than a single axis. The ADIS16209
incorporates the signal processing circuit that converts acceleration into an incline angle, and it corrects for several known
error sources that would otherwise degrade the accuracy level.
1 16
ax
XINCL_OUT = 0°
0° ≤ YINCL_OUT ≤ 90°
16209
0°
+30°
+90°
+120°
+180°
–150°
–90°
–60°
XACCL_OUT
–1g
–0.866g
0g
0.5g
+1g
+0.866g
0g
–0.5g
YACCL_OUT
0g
+0.5g
+1g
+0.866g
0g
–0.5g
–1g
–0.866g
ROT_OUT
NOTES
1. ROT_OUT = 180° IS 1 LSB DIFFERENT THAN ROT_OUT = –179.975°.
Figure 19. Vertical Angle Orientation
Rev. H | Page 11 of 24
07096-012
16209
1g
9
20
16
9
20
16
9
20
16
16209
16209
GRAVITY
9
20
16
Figure 18. Horizontal Incline Angle Orientation
ADIS16209
Data Sheet
BASIC OPERATION
INTRODUCTION
Table 7. Generic Master Processor SPI Settings
When using the factory default configuration for all user
configurable control registers, the ADIS16209 initializes itself
and automatically starts a continuous process of sampling,
processing, and loading calibrated incline angle and acceleration
data into the output registers.
Processor Setting
Master
SCLK ≤ 2.5 MHz
All communication between the ADIS16209 and an external
processor involves either reading the contents of an output
register or writing configuration (or command) information to
a control register (see Figure 20). The output data registers
include the latest sensor data, error flags, and identification
information. The control registers include sample rate, filtering,
calibration, self-test, input/output line operation, and error flags.
Each user accessible register has two bytes (upper and lower),
each of which has a unique address. See Table 8 for a detailed
list of all user registers, along with the corresponding addresses.
SENSOR
SIGNAL
PROCESSING
OUTPUT
REGISTERS
TEMPERATURE
SENSOR
CONTROLLER
CONTROL
REGISTERS
07096-220
SPI
DUAL-AXIS
ACCELEROMETER
SCLK ≤ 1 MHz1
SPI Mode 3
MSB First Mode
16-Bit Mode
READING SENSOR DATA
Reading a single register requires two 16-bit cycles on the SPI:
one to request the contents of a register and another to receive
those contents. The 16-bit command code (see Figure 26) for a
read request on the SPI has three parts: the read bit (R/W = 0),
either address of the register, [A6:A0], and eight don’t care bits,
[DC7:DC0]. Figure 22 shows an example that includes two
register reads in succession. This example starts with DIN =
0x0C00 to request the contents of the XINCL_OUT register and
follows with 0x0E00 to request the contents of the YINCL_OUT
register. The sequence in Figure 22 also shows full duplex mode
of operation, which means that the ADIS16465 can receive
requests on DIN while also transmitting data out on DOUT
within the same 16-bit SPI cycle.
Figure 20. Basic Operation of the ADIS16209
DIN
0x0C00
0x0E00
NEXT
ADDRESS
XINCL_OUT
YINCL_OUT
SPI
The SPI provides access to the user registers (see Table 8).
Figure 21 shows the most common connections between the
ADIS16209 and a SPI master device, which is often an
embedded processor that has an SPI-compatible interface.
SCLK
Figure 22. SPI Read Example
Figure 23 shows an example of the four SPI signals when
reading the PROD_ID register in a repeating pattern. This
pattern can be helpful when troubleshooting the SPI interface
setup and communications because the signals are the same for
each 16-bit sequence, except during the first cycle.
SCK
DIN
MOSI
DOUT
MISO
CS
SCLK
DIN
Figure 21. Electrical Connection Diagram
DOUT = 0011 1111 0101 0001 = 0x3F51 (16209)
Table 6. Generic SPI Master Pin Mnemonics and Functions
Mnemonic
SS
SCLK
MOSI
MISO
DIN = 0100 1010 0000 0000 = 0x4A00
DOUT
07096-223
CS
EMBEDDED
PROCESSOR/
DSP/FPGA
SS
07096-009
ADIS16209
DOUT
07096-222
REGISTER STRUCTURE
Description
ADIS16209 operates as slave
Maximum serial clock rate
SMPL_PRD < 0x08
Maximum serial clock rate
SMPL_PRD ≥ 0x08
CPOL = 1 (polarity), CPHA = 1 (phase)
Bit sequence, see Figure 26 for coding
Shift register and data length
Figure 23. SPI Signal Pattern, Repeating Read of the PROD_ID Register
DEVICE CONFIGURATION
Function
Slave select
Serial clock
Master output, slave input
Master input, slave output
Embedded processors typically use control registers to configure
serial ports for communicating with SPI slave devices, such as
the ADIS16209. Table 7 provides a list of common settings that
describe the SPI protocol of the ADIS16209. The initialization
routine of the master processor typically establishes these settings
using firmware commands to write them to the control registers.
Each configuration register contains 16 bits (two bytes).
Bits[7:0] contain the low byte, and Bits[15:8] contain the high
byte of each register. Each byte has its own unique address in
the user register map (see Table 8). Updating the contents of a
register requires writing to both bytes in the following
sequence: low byte first, high byte second. The only exception to
this requirement is when writing to the COMMAND register.
When using this register to trigger a command, only write to
the low byte to trigger the command. Writing to the high byte
after triggering a command can interrupt the operation, which
the low byte triggers.
Rev. H | Page 12 of 24
Data Sheet
ADIS16209
update the settings in the flash memory bank. The manual flash
memory update command (Register COMMAND, Bit 3, see
Table 31) provides a convenient method for saving all of these
settings to the flash memory bank at one time. A yes in the
Flash Backup column of Table 8 identifies the registers that have
storage support in the flash memory bank.
There are three parts to coding an SPI command (see Figure 26)
that write a new byte of data to a register: the write bit (R/W = 1),
the address of the byte, [A6:A0], and the new data for that
location, [DC7:DC0]. Figure 24 shows a coding example for
writing 0x0001 to the SMPL_PRD register (see Table 24). In
Figure 24, the 0xB601 command writes 0x01 to Address 0x36
(lower byte) and the 0xB700 command writes 0x00 to
Address 0x37 (upper byte).
MANUAL
FLASH
BACKUP
CS
NONVOLATILE
FLASH MEMORY
VOLATILE
SRAM
SCLK
(NO SPI ACCESS)
SPI ACCESS
0xB700
07096-225
0xB601
07096-224
DIN
START-UP
RESET
Figure 25. SRAM and Flash Memory Diagram
Figure 24. SPI Sequence for Writing 0x0001 to the SMPL_PRD Register
Memory Structure
Figure 25 shows a functional diagram for the memory structure
of the ADIS16209. The flash memory bank contains the
operational code, unit specific calibration coefficients, and user
configuration settings. During initialization (power application
or reset recover), this information loads from the flash memory
into the static random access memory (SRAM), which supports
all normal operation, including register access through the SPI
port. Writing to a configuration register using the SPI updates
the SRAM location of the register but does not automatically
CS
DIN
DOUT
R/W
D15
A6
A5
A4
A3
A2
A1
A0
DC7
DC6
DC5
DC4
D14
D13
D12
D11
D10
D9
D8
D7
D6
D5
D4
DC3 DC2
D3
D2
DC1
DC0
D1
D0
R/W
D15
A6
A5
D14
D13
NOTES
1. DOUT BITS ARE PRODUCED ONLY WHEN THE PREVIOUS 16-BIT DIN SEQUENCE STARTS WITH R/W = 0.
2. WHEN CS IS HIGH, DOUT IS IN A THREE-STATE, HIGH IMPEDANCE MODE, WHICH ALLOWS MULTIFUNCTIONAL USE OF THE LINE
FOR OTHER DEVICES.
Figure 26. SPI Communication Bit Sequence
Rev. H | Page 13 of 24
07096-226
SCLK
ADIS16209
Data Sheet
Table 8. User Register Map
Name
ENDURANCE
SUPPLY_OUT
XACCL_OUT
YACCL_OUT
AUX_ADC
TEMP_OUT
XINCL_OUT
YINCL_OUT
ROT_OUT
XACCL_NULL
YACCL_NULL
XINCL_NULL
YINCL_NULL
ROT_NULL
R/W
R
R
R
R
R
R
R
R
R
R/W
R/W
R/W
R/W
R/W
Flash Backup
Yes
No
No
No
No
No
No
No
No
Yes
Yes
Yes
Yes
Yes
ALM_MAG1
ALM_MAG2
ALM_SMPL1
ALM_SMPL2
ALM_CTRL
R/W
R/W
R/W
R/W
R/W
AUX_DAC
GPIO_CTRL
MSC_CTRL
SMPL_PRD
AVG_CNT
SLP_CNT
STATUS
COMMAND
R/W
R/W
R/W
R/W
R/W
W
R
W
PROD_ID
R
Yes
Yes
Yes
Yes
Yes
No
No
No
No
Yes
Yes
Yes
No
No
No
Yes
Address
0x00
0x02
0x04
0x06
0x08
0x0A
0x0C
0x0E
0x10
0x12
0x14
0x16
0x18
0x1A
0x1C to 0x1F
0x20
0x22
0x24
0x26
0x28
0x2A to 0x2F
0x30
0x32
0x34
0x36
0x38
0x3A
0x3C
0x3E
0x40 to 0x49
0x4A
Size (Bytes)
2
2
2
2
2
2
2
2
2
2
2
2
2
2
4
2
2
2
2
2
6
2
2
2
2
2
2
2
2
10
2
Function
Diagnostics, flash write counter (16-bit binary)
Output, power supply
Output, x-axis acceleration
Output, y-axis acceleration
Output, auxiliary ADC
Output, temperature
Output, ±90° x-axis inclination
Output, ±90° y-axis inclination
Output, ±180° vertical rotational position
Calibration, x-axis acceleration offset null
Calibration, y-axis acceleration offset null
Calibration, x-axis inclination offset null
Calibration, y-axis inclination offset null
Calibration, vertical rotation offset null
Reserved, do not write to these locations
Alarm 1, amplitude threshold
Alarm 2, amplitude threshold
Alarm 1, sample period
Alarm 2, sample period
Alarm, source control register
Reserved
Auxiliary DAC data
Operation, digital I/O configuration and data
Operation, data-ready and self-test control
Operation, sample rate configuration
Operation, filter configuration
Operation, sleep mode control
Diagnostics, system status register
Operation, system command register
Reserved
Product identification = 0x3F51
Rev. H | Page 14 of 24
Reference
Table 20
Table 10
Table 11
Table 22
Table 18
Table 13
Table 14
Table 16
Table 32
Table 32
Table 33
Table 33
Table 33
Table 34
Table 34
Table 35
Table 35
Table 36
Table 30
Table 29
Table 28
Table 24
Table 26
Table 25
Table 37
Table 31
N/A
Data Sheet
ADIS16209
OUTPUT DATA REGISTERS
Table 9 provides the data configuration for each output data
register in the ADIS16209. Starting with the MSB of the upper
byte, each output data register has the following bit sequence:
new data (ND) flag, error/alarm (EA) flag, followed by 14 data
bits. The data bits are LSB justified, and in the case of the 12-bit
data formats, the remaining two bits are not used. The ND flag
indicates that unread data resides in the output data registers.
This flag clears and returns to 0 during an output register read
sequence. It returns to 1 after the next internal sample update
cycle completes. The EA flag indicates an error condition. The
STATUS register contains all of the error flags and provides the
ability to investigate the root cause.
Table 9. Output Data Register Formats
Register
SUPPLY_OUT
XACCL_OUT
YACCL_OUT
AUX_ADC
TEMP_OUT
XINCL_OUT2
YINCL_OUT2
ROT_OUT3
Bits
14
14
14
12
12
14
14
14
Format
Binary, 3.3 V = 0x2A3D
Twos complement
Twos complement
Binary, 2 V = 0x0CCC
Binary, 25°C = 0x04FE
Twos complement
Twos complement
Twos complement
Scale1
0.30518 mV
0.24414 mg
0.24414 mg
0.6105 mV
−0.47°C
0.025°
0.025°
0.025°
1
Scale denotes quantity per LSB.
2
Range is −90° to +90°.
3
Range is −179.975° to +180°.
Accelerometers
The accelerometers respond to both static (gravity) and
dynamic acceleration using the polarity shown in Figure 27.
AY
0° TILT
LEVEL PLANE
1 16
AX
13
12
5
Table 10. XACCL_OUT (Base Address = 0x04), Read Only
Bits
15
14
[13:0]
Bits
15
14
[13:0]
Description
New data bit = 1, when register contains un-read data
Error/alarm = 1, when STATUS ≠ 0x0000
y-axis accelerometer output data, twos complement,
1 LSB = 0.24414 mg, 0 g = 0x0000
Table 12. Accelerometer Data Format Examples
Acceleration (g)
+1.7
+1.0
+0.00048828
+0.00024414
0
−0.00024414
−0.00048828
−1.0
−1.7
8 9
XINCL_OUT = 0°
YINCL_OUT = 0°
Description
New data bit = 1, when register contains un-read data
Error/alarm = 1, when STATUS ≠ 0x0000
x-axis accelerometer output data, twos complement,
1 LSB = 0.24414 mg, 0 g = 0x0000
Table 11. YACCL_OUT (Base Address = 0x06), Read Only
07096-024
4
The XACCL_OUT (see Table 10) and YACCL_OUT (see
Table 11) registers provide access to acceleration data for each
axis. For example, set DIN = 0x0400 to request data from the
x-axis register on the next 16-bit SPI sequence. After reading
the contents of one of these registers, mask off the upper two
bits, convert the remaining 14-bit, twos complement number
into a decimal equivalent, and then multiply that number by
0.024414 to convert the measurement into units of acceleration
(mg). Table 12 provides several examples of this data format.
Figure 27. Accelerometer Polarity
Rev. H | Page 15 of 24
Decimal
+6,963
+4,096
+2
+1
0
−1
−2
−4096
−27,853
Hex
0x1B33
0x1000
0x0002
0x0001
0x0000
0x3FFF
0xFFFE
0x3000
0xE4CD
Binary
xx01 1011 0011 0011
xx01 0000 0000 0000
xx00 0000 0000 0010
xx00 0000 0000 0001
xx00 0000 0000 0000
xx11 1111 1111 1111
xx11 1111 1111 1110
xx11 0000 0000 0000
xx10 0100 1100 1101
ADIS16209
Data Sheet
Horizontal Incline Angle
Table 17. Vertical Incline Angle Data Format Examples
The XINCL_OUT (see Table 13) and YINCL_OUT (see
Table 14) registers provide access to acceleration data for each
axis. For example, set DIN = 0x0400 to request data from the
x-axis register on the next 16-bit SPI sequence. After reading
the contents of one of these registers, mask off the upper two
bits, convert the remaining 14-bit, twos complement number
into a decimal equivalent, and then multiply that number by
0.025 to convert the measurement into units of angle (°).
Table 15 provides several examples of this data format.
Internal Temperature
Table 13. XINCL_OUT (Base Address = 0x0C), Read Only
Bits
15
14
[13:0]
Description
New data bit = 1, when register contains un-read data
Error/alarm = 1, when STATUS ≠ 0x0000
x-axis inclinometer output data, twos complement,
0° = 0x0000, 1 LSB = 0.025°/LSB, ±90° range
Table 14. YINCL_OUT (Base Address = 0x0E), Read Only
Bits
15
14
[13:0]
Description
New data bit = 1, when register contains un-read data
Error/alarm = 1, when STATUS ≠ 0x0000
y-axis inclinometer output data, twos complement,
0° = 0x0000, 1 LSB = 0.025°/LSB, ±90° range
Table 15. Horizontal Incline Angle Data Format Examples
Orientation
+90° − 0.025°
+0.05°
+0.025°
0°
−0.025°
−0.05°
−90°
Decimal
+3,599
+2
+1
0
−1
−2
−3,600
Hex
0x0E0F
0x0002
0x0001
0x0000
0x3FFF
0x3FFE
0x31F1
Binary
0000 1110 0000 1111
xx00 0000 0000 0010
xx00 0000 0000 0001
xx00 0000 0000 0000
xx11 1111 1111 1111
xx11 1111 1111 1110
xx11 0001 1111 0001
Orientation
+180° − 0.025°
+0.05°
+0.025°
0°
−0.025°
−0.05°
−180°
Decimal
+7,199
+2
+1
0
−1
−2
−7,200
Hex
0x1C1F
0x0002
0x0001
0x0000
0x3FFF
0x3FFE
0x23E0
Binary
xx01 1100 0001 1111
xx00 0000 0000 0010
xx00 0000 0000 0001
xx00 0000 0000 0000
xx11 1111 1111 1111
xx11 1111 1111 1110
xx10 0011 1110 0000
The TEMP_OUT register (see Table 18) provides access to an
internal temperature measurement. Set DIN = 0x0A00 to
request the contents of this register. Mask off the upper four
bits, then convert the remaining 12-bit binary number into a
decimal equivalent, subtract 1278, multiply it by −0.47 and add
25 to convert this number into °C. See Table 19 for examples of
this format. Note that this internal temperature measurement
provides an indicator of condition changes, not an absolute
measurement of conditions outside of the package.
Table 18. TEMP_OUT (Base Address = 0x0A), Read Only
Bits
[15:0]
Description
Internal temperature data, binary format,
sensitivity = −0.47°/LSB, 25°C = 1278 LSB = 0x04FE
Table 19. Internal Temperature Data Format Examples
Temperature (°C)
+125
25 + 0.47
+25
25 − 0.047
0
−40
LSB
1065
1277
1278
1279
1331
1416
Hex
0x0429
0x04FD
0x04FE
0x04FF
0x0533
0x0588
Binary
xxxx 0100 0010 1001
xxxx 0100 1111 1101
xxxx 0100 1111 1110
xxxx 0100 1111 1111
xxxx 0101 0011 0011
xxxx 0101 1000 1000
Vertical Incline Angle
Power Supply
The ROT_OUT register (see Table 16) provides access to incline
angle data for each axis. For example, set DIN = 0x1000 to
request data from this register on the next 16-bit SPI sequence.
After reading the contents of one of these registers, mask off the
upper two bits, convert the remaining 14-bit, twos complement
number into a decimal equivalent, and then multiply that
number by 0.025 to convert the measurement into units of
angle (°). Table 17 provides several examples of this data format.
The SUPPLY_OUT register (see Table 20) provides a digital
measurement for the supply voltage on the VDD pins (see
Figure 5). Set DIN = 0x0200 to request the contents of this
register. See Table 21 for examples of this data format.
Table 16. ROT_OUT (Base Address = 0x10), Read Only
Bits
15
14
[13:0]
Description
New data bit = 1, when register contains un-read data
Error/alarm = 1, when STATUS ≠ 0x0000
Vertical inclinometer output data, twos complement,
0° = 0x0000, 1 LSB = 0.025°/LSB, ±180° range
Table 20. SUPPLY_OUT (Base Address = 0x02), Read Only
Bits
15
14
[15:0]
Description
New data bit = 1, when register contains un-read data
Error/alarm = 1, when STATUS ≠ 0x0000
Power supply measurement data, binary format,
1 LSB = 0.00030518 V, 0 V = 0x0000
Table 21. Power Supply Data Format Examples
Supply Level (V)
3.6
3.3 + 0.00030518
3.3
3.3 − 0.00030518
3.0
Rev. H | Page 16 of 24
LSB
11,796
10,814
10,813
10,812
9,830
Hex
0x2E14
0x2A3E
0x2A3D
0x2A3C
0x2666
Binary
xx10 1110 0001 0100
xx10 1010 0011 1110
xx10 1010 0011 1101
xx10 1010 0011 1100
xx10 0110 0110 0110
Data Sheet
ADIS16209
Auxiliary ADC
Table 25. SLP_CNT Bit Descriptions
The AUX_ADC register (see Table 22) provides a digital
measurement for the AUX_ADC input pin (see Figure 5).
Set DIN = 0x0800 to request the contents of this register.
See Table 23 for examples of this data format.
Bit
15:8
7:0
Table 22. AUX_ADC (Base Address = 0x08), Read Only
Bits
15
14
[13:12]
[15:0]
Description
New data bit = 1, when register contains un-read data
Error/alarm = 1, when STATUS ≠ 0x0000
Not used
Auxiliary ADC data, binary format,
1 LSB = 0.0006105 V, 0 V = 0x0000
Table 23. Auxiliary ADC Data Format Examples
Supply Level (V)
2.5
0.001221
0.0006105
0
LSB
4095
2
1
0
Hex
0xFFF
0x002
0x001
0x000
Binary
xxxx 1111 1111 1111
xxxx 0000 0000 0010
xxxx 0000 0000 0001
xxxx 0000 0000 0000
OPERATION CONTROL REGISTERS
Internal Sample Rate
The SMPL_PRD register controls the ADIS16209 internal sample
rate and has two parts: a selectable time base and a multiplier. The
following relationship produces the sample rate:
Description
Not used
Data bits, 0.5 seconds/LSB
For example, writing 0x08 to the SLP_CNT register places the
ADIS16209 into sleep mode for 4 sec. The only way to stop this
process is to remove power or reset the device.
Digital Filtering
The AVG_CNT register controls the moving average digital filter,
which determines the size of the moving average filter in eight
power-of-two step sizes (that is, 2M = 1, 2, 4, 16, 32, 64, 128, and
256). Filter setup requires one simple step: write the appropriate
M factor to the assigned bits in the AVG_CNT register. Note
that the default settings for AVG_CNT and SMPL_PRD provide
the best accuracy but require approximately 1.28 seconds
to settle.
Table 26. AVG_CNT Bit Descriptions
Bit
15:4
3:0
Description
(Default = 0x0008)
Not used
Power-of-two step size, maximum binary value = 1000
The following equation offers a frequency response relationship
for this filter:
HA( f )
tS = tB × NS + 122.07 μs
sin( N f t S )
N sin( f t S )
20
Table 24. SMPL_PRD Bit Descriptions
Description
(Default = 0x0014)
Not used
Time base (tB): 0 = 244.14 μs, 1 = 7.568 ms
Increment setting (NS)
An example calculation of the default sample period follows:
SMPL_PRD = 0x01, B7 − B0 = 00000001
N=4
0
N = 128
MAGNITUDE (dB)
Bit
15:8
7
6:0
(Default = 0x0000)
B7 = 0 → tB = 244.14 μs, B6 … B0 = 000000001 → NS = 1
N = 16
–20
–40
–60
–80
tS = tB × NS + 122.07 μs = 244.14 × 1 + 122.07 = 366.21 μs
The sample rate setting has a direct impact on the SPI data
rate capability. For sample rates ≥546 SPS, the SPI SCLK can
run at a rate up to 2.5 MHz. For sample rates or < M C ?
where:
NDS is the number of samples in ALM_SMPLx.
y(n) is the sampled output data.
MC is the magnitude for comparison in ALM_MAGx.
> or < is determined by the MSB in ALM_MAGx.
Table 34. ALM_MAG1/ALM_MAG2 Bit Designations
Bit
15
14
13:0
Description
(Default = 0x0000)
Comparison polarity: 1 = greater than, 0 = less than
Not used
Data bits, matches format of trigger source selection
Table 35. ALM_SMPL1/ALM_SMPL2 Bit Designations
Bit
15:8
7:0
Description
(Default = 0x0001)
Not used
Data bits: number of samples (both 0x00 and 0x01 = 1)
Table 36. ALM_CTRL Bit Descriptions
Bit
15:12
Value
0000
0001
0010
0011
0100
0101
0110
0111
1000
11:8
7
6
5
4
3
2
1
0
1
Description
(Default = 0x0000)
Trigger source, Alarm 2
Disabled
Power supply
X-acceleration
Y-acceleration
Auxiliary ADC
Temperature sensor
X-axis incline angle
Y-axis incline angle
Rotational position
Trigger source, Alarm 1, same as Bits[15:12]
Not used
Alarm 2 rate-of-change control: 1 = enabled
Alarm 1 rate-of-change control: 1 = enabled
Alarm 2 filter: 1 = filtered data, 0 = no filter1
Alarm 1 filter: 1 = filtered data, 0 = no filter1
Alarm indicator, using DIO1/DIO2: 1 = enabled
Alarm indicator polarity: 1 = active high
Alarm indicator line select: 1 = DIO2, 0 = DIO1
Incline and vertical angles always use filtered data in this comparison.
Rev. H | Page 20 of 24
Data Sheet
ADIS16209
Status
Table 37. STATUS Bit Descriptions
The STATUS register provides a series of error flags that
provide indicator functions for common system-level issues.
After reading the contents of this register, set COMMAND[4] =
1 (DIN = 0xBE10) to reset all of its flags to zero.
Bit
15:10
9
8
7:6
5
4
3
2
1
0
Rev. H | Page 21 of 24
Description
(Default = 0x0000)
Not used
Alarm 2 status:
1 = active, 0 = inactive
Alarm 1 status:
1 = active, 0 = inactive
Not used
Self-test diagnostic error flag:
1 = error condition, 0 = normal operation
Not used
SPI communications failure:
1 = error condition, 0 = normal operation
Flash update failed:
1 = error condition, 0 = normal operation
Power supply greater than 3.625 V:
1 > 3.625 V, 0 ≤ 3.625 V (normal)
Power supply less than 2.975 V:
1 < 2.975 V, 0 ≥ 2.975 V (normal)
ADIS16209
Data Sheet
APPLICATIONS INFORMATION
POWER SUPPLY CONSIDERATIONS
Filter Settling
The ADIS16209 is a precision sensing system that uses an
embedded processor for critical interface and signal processing
functions. Supporting this processor requires a low impedance
power supply, which can manage transient current demands that
happen during normal operation, as well as during the start-up
process. Transient current demands start when the voltage on
the VDD pin reaches ~2.1 V. Therefore, it is important for the
voltage on the VDD pin to reach 3 V as quickly as possible.
Linear VDD ramp profiles that reach 3 V in 100 µs provide
reliable results when used in conjunction with design practices
that support low dynamic source impedance. The ADP1712 is
a linear regulator that can support the recommended ramp profile.
See the ADIS1620x/21x/22x Power Regulator Suggestion page
for a reference design for using this regulator with the ADIS16209.
The SMPL_PRD and AVG_CNT settings have a direct impact
on the filter settling during turn-on. For example, when using
the default settings for these filters, the SUPPLY_OUT register
takes approximately 1.28 seconds to settle. During this time, the
SUPPLY_OUT register experiences a linear rise (assuming that
VDD is stable and greater than 3.0 V) and the low-voltage flag
(STATUS[0]) is low. When the SUPPLY_OUT register reaches a
value that exceeds 2.975 V, the STATUS[0] flag automatically
lowers.
Power-On-Reset Function
The ADIS16209 has a power-on-reset (POR) function that
triggers a reset if the voltage on the VDD pin fails to transition
between 2.35 V and 2.7 V within 128 ms.
Transient Current from VDD Ramp Rate
Because the ADIS16209 contains 2 μF of decoupling capacitance
on VDD and some systems may use additional filtering
capacitance, the VDD ramp rate will have a direct impact on
initial transient current requirements. Use this formula to
estimate the transient current, associated with a particular
capacitance (C) and VDD ramp rate (dV/dt).
When developing a process flow for installing ADIS16209
devices on PCBs, see the JEDEC standard document J-STD020C for reflow temperature profile and processing information.
The ADIS16209 can use the Sn-Pb eutectic process and the Pbfree eutectic process from this standard, with one exception: the
peak temperature exposure is 240°C. For a more complete list of
assembly process suggestion, see the ADIS162xx LGA Assembly
Guidelines page at the Engineer Zone/MEMS Community website.
Figure 29 provides an example pad layout for the location of the
ADIS16209 on a printed circuit board (PCB).
dt
1.178 BSC
(8 PLCS)
0.670 BSC
(12 PLCS)
7.873 BSC
(2 PLCS)
1.127 BSC
(16 PLCS)
For example, if VDD transitions from 0 V to +3.3 V in 33 µs,
dV/dt is equal to 100000V/S (3.3 V/33 µs). When charging the
internal 2 µF capacitor (no external capacitance), the charging
current for this ramps rate is 200 mA, during the 33 µs ramp time.
This relationship provides a tool for evaluating the initial charging
currents against the current limit thresholds of system power
supplies, which can cause power supply interruptions and the
appearance of failed start-ups. This may also be important for
maintaining surge current ratings of any series elements as well
Rev. H | Page 22 of 24
0.500 BSC
(16 PLCS)
Figure 29. Example Pad Layout
07096-123
i (t ) = C dV
ASSEMBLY
ADIS16209
1.100
Data Sheet
INTERFACE BOARD
The ADIS16209/PCBZ provides the ADIS16209 function on a
1.2 inch × 1.3 inch PCB, which simplifies the connection to an
existing processor system. The four mounting holes accommodate
either M2 (2 mm) or Type 2-56 machine screws. These boards
are made of IS410 material and are 0.063 inches thick. The second
level assembly uses a SAC305-compatible solder composition
(Pb-free), which has a presolder reflow thickness of approximately
0.005 inches. The pad pattern on the ADIS16209/PCBZ matches
that shown in Figure 31. J1 and J2 are dual-row, 2 mm (pitch)
connectors that work with a number of ribbon cable systems,
including 3M Part Number 152212-0100-GB (ribbon-crimp
connector) and 3M Part Number 3625/12 (ribbon cable).
1.050
2 × 0.925
C1
4 × Ø0.087
M2×0.4
2 × 0.000
0.150
6
2
7
8
3
9
10
4
6
10
1
4
2
3
13
11
12
16
RST
ADC
SCLK
DAC
CS
DIO2
DOUT
DIO1
DIN
DNC
DNC
VDD
DNC
GND
VREF
DNC
C1
1µF
J2
14
12
6
5
7
10
8
11
15
1
3
11
Figure 31. PCB Assembly View and Dimensions
12
X-RAY SENSITIVITY
10
7
Exposure to high dose rate X-rays, such as those in production
systems that inspect solder joints in electronic assemblies, may
affect accelerometer bias errors. For optimal performance, avoid
exposing the ADIS16209 to this type of inspection.
9
8
10
4
8
5
9
2
5
07096-025
7
07096-026
5
ADIS16209
9
0.865
1
2 × 0.900
J1
4
0.035
2 × 0.000
2
3
0.200
1
12
U1
iSensor
J1/J2 PIN NUMBERS
11
J2
J1
2 × 0.673
Figure 30. Electrical Schematic
Rev. H | Page 23 of 24
ADIS16209
Data Sheet
OUTLINE DIMENSIONS
5.391
BSC
(4×)
2.6955
BSC
(8×)
9.35
9.20 SQ
9.05
13
PIN 1
INDICATOR
1.000 BSC
(16×)
16
12
1
8.373
BSC
(2×)
0.797 BSC
(12×)
9
4
8
0.200
MIN
(ALL SIDES)
TOP VIEW
5
BOTTOM VIEW
0.373 BSC
(16×)
5.00
TYP
121409-C
3.90
MAX
SIDE VIEW
Figure 32. 16-Terminal Stacked Land Grid Array [LGA]
(CC-16-2)
Dimensions shown in millimeters
ORDERING GUIDE
Model 1
ADIS16209CCCZ
ADIS16209/PCBZ
EVAL-ADIS2Z
1
Temperature Range
−40°C to +125°C
Package Description
16-Terminal Stacked Land Grid Array [LGA]
Evaluation Board
Evaluation System
Z = RoHS Compliant Part.
©2008–2019 Analog Devices, Inc. All rights reserved. Trademarks and
registered trademarks are the property of their respective owners.
D07096-0-3/19(H)
Rev. H | Page 24 of 24
Package Option
CC-16-2
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