Digital Triaxial Vibration Sensor
with FFT Analysis and Storage
ADIS16227
Data Sheet
GENERAL DESCRIPTION
Frequency domain triaxial vibration sensor
Digital acceleration data, ± 70 g measurement range
Digital range settings: 1 g, 5 g, 20 g, 70 g
Sample rate: 100.2 kHz, 4 decimation filter settings
FFT, 512 point, real valued, all three axes (x, y, z)
Windowing options: rectangular, Hanning, flat top
Programmable FFT averaging, up to 256 averages
Storage, 16 FFT records on all three axes (x, y, z)
Programmable alarms, 6 spectral bands
2-level settings for warning and fault definition
Adjustable response delay to reduce false alarms
Trigger modes: SPI command, timer, external trigger
Multirecord capture for selected filter settings
Manual capture mode for time-domain data collection
Internal self-test with status flags
Digital temperature and power supply measurements
2 auxiliary digital I/Os
SPI-compatible serial interface
Serial number and device ID
Single-supply operation: 3.15 V to 3.6 V
Operating temperature range: −40°C to +125°C
15 mm × 15 mm × 15 mm aluminum package, flex connector
The ADIS16227 iSensor® is a complete vibration sensing system
that combines wide bandwidth, triaxial acceleration sensing with
advanced time domain and frequency domain signal processing.
Time domain signal processing includes a programmable decimation
filter and selectable windowing function. Frequency domain
processing includes a 512 point, real-valued FFT for each axis,
along with FFT averaging, which reduces the noise floor variation
for finer resolution. The 16-record FFT storage system offers
users the ability to track changes over time and to capture FFTs
with multiple decimation filter settings.
TE
FEATURES
B
SO
LE
The 22 kHz sensor resonance and 100.2 kSPS sample rate
provide a frequency response that is suitable for machine-health
applications. The aluminum core provides excellent mechanical
coupling to the MEMS acceleration sensors. An internal clock
drives the data sampling and signal processing system during all
operations, which eliminates the need for an external clock
source. The data capture function has three modes that offer
several options to meet the needs of many different applications.
APPLICATIONS
Vibration analysis
Condition monitoring
Machine health
Instrumentation, diagnostics
Safety shutoff sensing
The SPI and data buffer structure provide convenient access
to wide bandwidth sensor data. The ADIS16227 also offers a
digital temperature sensor and digital power supply measurements.
The ADIS16227 is available in a 15 mm × 15 mm × 15 mm module
with a threaded hole for stud mounting with a 10-32 UNF screw.
The dual-row, 1 mm, 14-pin, flexible connector enables simple
user interface and installation. The ADIS16227 is footprint and
pin-for-pin compatible with the ADIS16223. It has an extended
operating temperature range of −40°C to +125°C.
O
FUNCTIONAL BLOCK DIAGRAM
DIO1 DIO2 RST
INPUT/
OUTPUT
ADIS16227
VDD
ALARMS
POWER
MANAGEMENT
GND
CS
TRIAXIAL
MEMS
SENSOR
CONTROL
REGISTERS
CONTROLLER
SCLK
SPI
PORT
TEMP
SENSOR
ADC
CAPTURE
BUFFER
FILTER
WINDOW
FFT
DIN
DOUT
09425-001
SUPPLY
RECORD
STORAGE
OUTPUT
REGISTERS
Figure 1.
Rev. B
Information furnished by Analog Devices is believed to be accurate and reliable. However, no
responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other
rights of third parties that may result from its use. Specifications subject to change without notice. No
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
Trademarks and registered trademarks are the property of their respective owners.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700
www.analog.com
Fax: 781.461.3113 ©2010–2012 Analog Devices, Inc. All rights reserved.
ADIS16227
Data Sheet
TABLE OF CONTENTS
Spectral Alarms............................................................................... 13
Applications ....................................................................................... 1
Alarm Definition ........................................................................ 13
General Description ......................................................................... 1
Alarm Indicator Signals ............................................................. 14
Functional Block Diagram .............................................................. 1
Alarm Flags and Conditions ..................................................... 15
Revision History ............................................................................... 2
Alarm Status ................................................................................ 15
Specifications..................................................................................... 3
Worst-Condition Monitoring ................................................... 15
Timing Specifications .................................................................. 4
Reading Output Data ..................................................................... 16
Absolute Maximum Ratings............................................................ 5
Reading Data from the Data Buffer ......................................... 16
ESD Caution .................................................................................. 5
Accessing FFT Record Data ...................................................... 16
Pin Configuration and Function Descriptions ............................. 6
Data Format ................................................................................ 16
Theory of Operation ........................................................................ 7
Power Supply/Temperature ....................................................... 17
Sensing Element ........................................................................... 7
FFT Event Header ...................................................................... 17
Signal Processing .......................................................................... 7
System Tools .................................................................................... 18
User Interface ................................................................................ 7
Global Commands ..................................................................... 18
LE
TE
Features .............................................................................................. 1
Status/Error Flags ....................................................................... 18
SPI Write Commands .................................................................. 8
Operation Managment .............................................................. 18
SPI Read Commands ................................................................... 8
Input/Output Functions ............................................................ 19
Data Recording and Signal Processing ........................................ 10
Self-Test ....................................................................................... 19
Recording Modes........................................................................ 10
Flash Memory Management ..................................................... 20
B
SO
Basic Operation................................................................................. 8
Recording Times......................................................................... 10
Device Identification.................................................................. 20
Power-Down ............................................................................... 11
Applications Information .............................................................. 21
Record Storage Mode ................................................................. 11
Mounting Guidelines ................................................................. 21
Sample Rate Options .................................................................. 11
Getting Started ............................................................................ 21
Windowing Options................................................................... 11
Interface Board ........................................................................... 21
Range ............................................................................................ 12
Outline Dimensions ....................................................................... 22
Offset Correction........................................................................ 12
Ordering Guide .......................................................................... 22
FFT Averaging ............................................................................ 12
O
FFT Record Flash Endurance ................................................... 12
REVISION HISTORY
5/12—Rev. A to Rev. B
Changes to Table 10 ........................................................................ 10
2/12—Rev. 0 to Rev. A
Changes to Dual Memory Structure Section ................................ 7
Change to Table 14 ......................................................................... 11
Changes to Alarm Trigger Settings Section, Enable Alarm
Settings Section, Table 27, Table 28, Table 30, and
Table 31 ............................................................................................ 14
Change to Alarm Indicator Section ............................................. 19
10/10—Revision 0: Initial Version
Rev. B | Page 2 of 24
Data Sheet
ADIS16227
SPECIFICATIONS
TA = −40°C to +125°C, VDD = 3.3 V, unless otherwise noted.
Table 1.
Min
TA = 25°C
TA = 25°C, 0 g to 70 g range setting
TA = 25°C
TA = 25°C
With respect to full scale
±70
O
Typ
1.192
2.384
±5
±0.2
2.6
1.5
TE
With respect to package
TA = 25°C
−19.1
TJ = 85°C, see Figure 18
±0.2
−40
−1
10
+19.1
0.8
±1
−60
2.4
0.4
10,000
20
RST pulse low or Register GLOB_CMD[7] = 1
REC_CTRL[11:8] = 0x1 (SR0 sample rate selection)
Operating voltage range, VDD
Record mode, TA = 25°C
Sleep mode, TA = 25°C
±2
2.0
VIH = 3.3 V
VIL = 0 V
ISOURCE = 1.6 mA
ISINK = 1.6 mA
Max
5
467
3.3
7.75
9.0
13
14.25
26
22
TA = 25°C, 100.2 kHz sample rate option
TA = 25°C, 10 Hz to 1 kHz
X/Y-axes, ±5% flatness
X/Y-axes, ±10% flatness
Z-axis, ±5% flatness
Z-axis, ±10% flatness
−3 dB from 10 Hz magnitude
B
SO
Sensor Resonant Frequency
LOGIC INPUTS 1
Input High Voltage, VINH
Input Low Voltage, VINL
Logic 1 Input Current, IINH
Logic 0 Input Current, IINL
All Except RST
RST
Input Capacitance, CIN
DIGITAL OUTPUTS1
Output High Voltage, VOH
Output Low Voltage, VOL
FLASH MEMORY
Endurance 2
Data Retention 3
START-UP TIME 4
Initial Startup
Reset Recovery 5
Sleep Mode Recovery
CONVERSION RATE
Clock Accuracy
POWER SUPPLY
Power Supply Current
Test Conditions/Comments
LE
Parameter
ACCELEROMETERS
Measurement Range
Sensitivity, FFT
Sensitivity, Time Domain
Sensitivity Error
Nonlinearity
Cross-Axis Sensitivity
Alignment Error
Offset Error
Offset Temperature Coefficient
Output Noise
Output Noise Density
Bandwidth
3.15
Unit
g
mg/LSB
mg/LSB
%
%
%
Degree
g
mg/°C
mg rms
mg/√Hz
kHz
kHz
kHz
kHz
kHz
kHz
V
V
µA
µA
mA
pF
V
V
Cycles
Years
190
54
2.5
100.2
3
3.3
43
230
3.6
52
ms
ms
ms
kSPS
%
V
mA
µA
The digital I/O signals are 5 V tolerant.
Endurance is qualified as per JEDEC Standard 22, Method A117, and measured at −40°C, +25°C, +85°C, and +125°C.
3
Retention lifetime equivalent at junction temperature (TJ) = 85°C as per JEDEC Standard 22, Method A117. Retention lifetime depends on junction temperature.
4
The start-up times presented reflect the time it takes for data collection to begin.
5
The RST pin must be held low for at least 15 ns.
1
2
Rev. B | Page 3 of 24
ADIS16227
Data Sheet
TIMING SPECIFICATIONS
TA = 25°C, VDD = 3.3 V, unless otherwise noted.
Table 2.
Guaranteed by design, not tested.
Unit
MHz
µs
ns
ns
ns
ns
ns
ns
ns
ns
100
24.4
48.8
12.5
12.5
12.5
5
5
tSF
tCS
2
3
4
SCLK
6
B
SO
tDAV
5
MSB
DB14
DB13
tDSU
R/W
A6
DB12
DB11
A4
A3
tSFS
15
DB10
DB2
16
DB1
LSB
tDHD
A5
A2
D2
D1
09425-002
1
DIN
Max
2.25
tSR
CS
DOUT
Typ
LE
Timing Diagrams
Min 1
0.01
15.4
48.8
LSB
Figure 2. SPI Timing and Sequence
tSTALL
O
CS
SCLK
Figure 3. DIN Bit Sequence
Rev. B | Page 4 of 24
09425-003
1
Description
SCLK frequency
Stall period between data, between 16th and 17th SCLK
Chip select to SCLK edge
DOUT valid after SCLK edge
DIN setup time before SCLK rising edge
DIN hold time after SCLK rising edge
SCLK rise time
SCLK fall time
DOUT rise/fall times
CS high after SCLK edge
TE
Parameter
fSCLK
tSTALL
tCS
tDAV
tDSU
tDHD
tSR
tSF
tDF, tDR
tSFS
Data Sheet
ADIS16227
ABSOLUTE MAXIMUM RATINGS
Table 4. Package Characteristics
Table 3.
Rating
Package Type
14-Lead Module
2000 g
2000 g
−0.3 V to +6.0 V
−0.3 V to +5.3 V
−0.3 V to +3.6 V
−0.3 V to +3.6 V
−40°C to +125°C
−65°C to +150°C
θJA
31°C/W
θJC
11°C/W
ESD CAUTION
O
B
SO
LE
Stresses above those listed under Absolute Maximum Ratings
may cause permanent damage to the device. This is a stress
rating only; functional operation of the device at these or any
other conditions above those indicated in the operational
section of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect
device reliability.
TE
Parameter
Acceleration
Any Axis, Unpowered
Any Axis, Powered
VDD to GND
Digital Input Voltage to GND
Digital Output Voltage to GND
Analog Inputs to GND
Operating Temperature Range
Storage Temperature Range
Rev. B | Page 5 of 24
Device Weight
6.5 grams
ADIS16227
Data Sheet
PIN CONFIGURATION AND FUNCTION DESCRIPTIONS
aY
aZ
TOP VIEW
LOOK THROUGH
PINS ARE NOT VISIBLE
FROM THIS VIEW
TE
aX
14 12 10 8 6 4 2
PIN 2
PIN 13
PIN 1
LE
1. THE ARROWS ASSOCIATED WITH aX, aY, AND aZ DEFINE THE DIRECTION OF
VELOCITY CHANGE THAT PRODUCES A POSITIVE OUTPUT IN ACCELERATION
OUTPUT REGISTERS.
2. MATING CONNECTOR EXAMPLE: SAMTEC P/N CLM-107-02-LM-D-A.
09425-004
13 11 9 7 5 3 1
Figure 4. Pin Configuration
Table 5. Pin Function Descriptions
2
Type 1
S
I
I/O
I/O
I
S
I
O2
I
I
S is supply, O is output, I is input, and I/O is input/output.
DOUT is an output when CS is low. When CS is high, DOUT is in a three-state, high impedance mode.
O
1
Mnemonic
GND
NC
DIO2
DIO1
RST
VDD
DIN
DOUT
SCLK
CS
B
SO
Pin No.
1, 4, 9, 10
2, 6
3
5
7
8
11
12
13
14
Rev. B | Page 6 of 24
Description
Ground
No Connect
Digital Input/Output Line 2
Digital Input/Output Line 1
Reset, Active Low
Power Supply, 3.3 V
SPI, Data Input
SPI, Data Output
SPI, Serial Clock
SPI, Chip Select
Data Sheet
ADIS16227
THEORY OF OPERATION
OUTPUT
REGISTERS
TEMP
SENSOR
ADC
CONTROLLER
MOVABLE
FRAME
FIXED
PLATES
B
SO
UNIT SENSING
CELL
UNIT
FORCING
CELL
MOVING
PLATE
ANCHOR
09425-005
ACCELERATION
PLATE
CAPACITORS
Figure 5. MEMS Sensor Diagram
SIGNAL PROCESSING
O
Figure 6. Simplified Sensor Signal Processing Diagram
USER INTERFACE
TE
SPI Interface
The user registers manage user access to both sensor data and
configuration inputs. Each 16-bit register has its own unique bit
assignment and two addresses: one for its upper byte and one for
its lower byte. Table 8 provides a memory map for each register,
along with its function and lower byte address. The data
collection and configuration command uses the SPI, which
consists of four wires. The chip select (CS) signal activates the
SPI interface, and the serial clock (SCLK) synchronizes the
serial data lines. Input commands clock into the DIN pin, one
bit at a time, on the SCLK rising edge. Output data clocks out of
the DOUT pin on the SCLK falling edge. When the SPI is used
as a slave device, the DOUT contents reflect the information
requested using a DIN command.
Figure 6 offers a simplified block diagram for the ADIS16227.
The signal processing stage includes time domain data capture,
digital decimation/filtering, windowing, FFT analysis, FFT
averaging, and record storage. See Figure 13 for more details on
the signal processing operation.
Dual Memory Structure
The user registers provide addressing for all input/output operations
in the SPI interface. The control registers use a dual memory
structure. The controller uses SRAM registers for normal
operation, including user-configuration commands. The flash
memory provides nonvolatile storage for control registers that
have flash backup (see Table 8). Storing configuration data in
the flash memory requires a manual flash update command
(GLOB_CMD[6] = 1, DIN = 0xBE40). When the device powers
on or resets, the flash memory contents load into the SRAM, and
the device starts producing data according to the configuration
in the control registers.
MANUAL
FLASH
BACKUP
NONVOLATILE
FLASH MEMORY
(NO SPI ACCESS)
VOLATILE
SRAM
SPI ACCESS
START-UP
RESET
Figure 7. SRAM and Flash Memory Diagram
Rev. B | Page 7 of 24
09425-007
ANCHOR
CLOCK
LE
Digital vibration sensing in the ADIS16227 starts with a wide
bandwidth MEMS accelerometer core on each axis, which provides
a linear motion-to-electrical transducer function. Figure 5 provides
a basic physical diagram of the sensing element and its response
to linear acceleration. It uses a fixed frame and a moving frame
to form a differential capacitance network that responds to linear
acceleration. Tiny springs tether the moving frame to the fixed
frame and govern the relationship between acceleration and
physical displacement. A modulation signal on the moving plate
feeds through each capacitive path into the fixed frame plates and
into a demodulation circuit, which produces the electrical signal
that is proportional to the acceleration acting on the device.
09425-006
SENSING ELEMENT
CONTROL
REGISTERS
SPI SIGNALS
CAPTURE
BUFFER
TRIAXIAL
MEMS
SENSOR
SPI PORT
The ADIS16227 is a triaxial, wide bandwidth, vibration-sensing
system. It combines a triaxial MEMS accelerometer with a
sampling and advanced signal processing system. The SPIcompatible port and user register structure provide convenient
access to frequency domain vibration data and many user
controls.
ADIS16227
Data Sheet
BASIC OPERATION
VDD
15
14
13
12
SCLK
13
SCLK
MOSI
11
DIN
MISO
12
DOUT
IRQ1
5
DIO1
IRQ2
3
DIO2
CS
6
5
4
3
2
1
LOWER BYTE
10
0
CS
LE
9
09425-008
4
7
TE
SPI SLAVE
1
8
User control registers govern many internal operations. The
DIN bit sequence in Figure 12 provides the ability to write to
these registers, one byte at a time. Some configuration changes
and functions require only one write cycle. For example, set
GLOB_CMD[11] = 1 (DIN = 0xBF08) to start a manual capture
sequence. The manual capture starts immediately after the last bit
clocks into DIN (16th SCLK rising edge). Other configurations may
require writing to both bytes.
ADIS16227
14
9
SPI WRITE COMMANDS
8
SS
10
Figure 9. Generic Register Bit Definitions
+3.3V
SYSTEM
PROCESSOR
SPI MASTER
11
UPPER BYTE
09425-009
Table 8 provides a list of user registers with their lower byte
addresses. Each register consists of two bytes that each have their
own, unique 7-bit addresses. Figure 9 relates each register’s bits
to their upper and lower addresses.
The ADIS16227 uses a SPI for communication, which enables
a simple connection with a compatible, embedded processor
platform, as shown in Figure 8. The factory default configuration
for DIO1 provides a busy indicator signal that transitions low
when an event completes and data is available for user access.
Use the DIO_CTRL register (see Table 59) to reconfigure DIO1
and DIO2, if necessary.
Figure 8. Electrical Hook-Up Diagram
DIN
Function
Slave select
Interrupt request inputs (optional)
Master output, slave input
Master input, slave output
Serial clock
Figure 10. SPI Sequence for Manual Capture Start (DIN = 0xBF08)
SPI READ COMMANDS
A single register read requires two 16-bit SPI cycles that also use
the bit assignments in Figure 12. The first sequence sets R/W = 0
and communicates the target address (Bits[A6:A0]). Bits[D7:D0]
are don’t care bits for a read DIN sequence. DOUT clocks out the
requested register contents during the second sequence. The
second sequence can also use DIN to set up the next read. Figure 11
provides a signal diagram for all four SPI signals while reading
the PROD_ID register (see Table 63) pattern. In this diagram,
DIN = 0x5600 and DOUT reflect the decimal equivalent of 16,227.
B
SO
Pin Name
SS
IRQ1, IRQ2
MOSI
MISO
SCLK
09425-010
SCLK
Table 6. Generic Master Processor Pin Names and Functions
The ADIS16227 SPI interface supports full duplex serial
communication (simultaneous transmit and receive) and uses
the bit sequence shown in Figure 12. Table 7 provides a list of
the most common settings that require attention to initialize a
processor serial port for the ADIS16227 SPI interface.
Table 7. Generic Master Processor SPI Settings
CS
Description
ADIS16227 operates as a slave.
Bit rate setting.
Clock polarity/phase
(CPOL = 1, CPHA = 1).
Bit sequence.
Shift register/data length.
SCLK
O
MSB-First
16-Bit
DIN
DOUT
DOUT = 0011 1111 0110 0011 = 0x3F63 = 16,227 = PROD_ID
Figure 11. Example SPI Read, PROD_ID, Second Sequence
CS
SCLK
DOUT
R/W
DB15
A6
A5
A4
A3
A2
A1
A0
DB14 DB13 DB12 DB11 DB10 DB9 DB8
D7
D6
D5
D4
D3
D2
D1
D0
DB7
DB6
DB5
DB4
DB3
DB2
DB1
DB0
NOTES
1. DOUT BITS ARE BASED ON THE PREVIOUS 16-BIT SEQUENCE (R/W = 0).
Figure 12. Example SPI Read Sequence
Rev. B | Page 8 of 24
R/W
DB15
A6
A5
DB14 DB13
09425-012
DIN
09425-011
Processor Setting
Master
SCLK Rate ≤ 2.25 MHz
SPI Mode 3
Data Sheet
ADIS16227
Table 8. User Register Memory Map
Address
0x00
0x02
0x04
0x06
0x08
0x0A
0x0C
0x0E
0x10
0x12
0x14
0x16
0x18
0x1A
0x1C
0x1E
0x20
0x22
0x24
0x26
0x28
0x2A
0x2C
0x2E
0x30
0x32
0x34
0x36
0x38
0x3A
0x3C
0x3E
0x40
0x42
0x44
0x46
0x48
0x4A
0x4C
0x4E
0x50 to 0x51
0x52
0x54
0x56
0x58
0x70
0x72
0x74
0x76
Default
N/A
0x0000
0x0000
0x0000
N/A
0x8000
0x8000
0x0008
0x0000
0x0000
0x8000
0x8000
0x8000
0x0000
0x1130
0x0000
0x0000
0x0000
0x0000
0x0000
0x0000
0x0000
0x0000
0x0000
0x0000
0x0000
0x0080
0x000F
0x0000
N/A
0x0000
N/A
0x0000
0x0000
0x0000
0x0000
0x0000
0x0000
0x0000
0x0000
N/A
N/A
N/A
0x3F63
N/A
0x0000
0x0000
0x0000
N/A
O
Function
Status, flash memory write count
X-axis accelerometer offset correction
Y-axis accelerometer offset correction
Z-axis accelerometer offset correction
Record flash write/erase counter
Output, power supply during capture
Output, temperature during capture
Control, number of FFT records to average
Control, buffer address pointer
Control, record address pointer
Output, buffer for x-axis acceleration data
Output, buffer for y-axis acceleration data
Output, buffer for z-axis acceleration data
Control, record counter
Control, record control register
Control, record period (automatic mode)
Alarm, spectral band lower frequency limit
Alarm, spectral band upper frequency limit
Alarm, x-axis, Alarm 1 level
Alarm, y-axis, Alarm 1 level
Alarm, z-axis, Alarm 1 level
Alarm, x-axis, Alarm 2 level
Alarm, y-axis, Alarm 2 level
Alarm, z-axis, Alarm 2 level
Alarm, spectral alarm band pointer
Alarm, system alarm level
Alarm, configuration
Control, functional I/O configuration
Control, general-purpose I/O
Reserved
Status, system error flags
Control, global command register
Alarm, x-axis, status for spectral alarm bands
Alarm, y-axis, status for spectral alarm bands
Alarm, z-axis, status for spectral alarm bands
Alarm, x-axis, peak value (most severe alarm)
Alarm, y-axis, peak value (most severe alarm)
Alarm, z-axis, peak value (most severe alarm)
Record time stamp, lower word
Record time stamp, upper word
Reserved
Lot identification code
Lot identification code
Product identifier; convert to decimal = 16,227
Serial number
Alarm, x-axis, frequency of most severe alarm
Alarm, y-axis, frequency of most severe alarm
Alarm, z-axis, frequency of most severe alarm
Record settings
TE
Flash
Backup
Yes
Yes
Yes
Yes
No
Yes
Yes
Yes
Yes
Yes
No
No
No
No
Yes
Yes
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
Yes
Yes
Yes
Yes
Yes
N/A
No
No
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
Yes
Yes
Yes
Yes
N/A
N/A
N/A
N/A
LE
Access
Read only
Read only
Read only
Read only
N/A
Read only
Read only
Read/write
Read/write
Read/write
Read only
Read only
Read only
Read/write
Read/write
Read/write
Read/write
Read/write
Read/write
Read/write
Read/write
Read/write
Read/write
Read/write
Read/write
Read/write
Read/write
Read/write
Read/write
N/A
Read only
Write only
Read only
Read only
Read only
Read only
Read only
Read only
Read only
Read only
N/A
Read only
Read only
Read only
Read only
Read only
Read only
Read only
Read only
B
SO
Register
Name
FLASH_CNT
X_NULL
Y_NULL
Z_NULL
REC_FLSH_CNT
SUPPLY_OUT
TEMP_OUT
FFT_AVG
BUF_PNTR
REC_PNTR
X_BUF
Y_BUF
Z_BUF
REC_CNTR
REC_CTRL
REC_PRD
ALM_F_LOW
ALM_F_HIGH
ALM_X_MAG1
ALM_Y_MAG1
ALM_Z_MAG1
ALM_X_MAG2
ALM_Y_MAG2
ALM_Z_MAG2
ALM_PNTR
ALM_S_MAG
ALM_CTRL
DIO_CTRL
GPIO_CTRL
Reserved
DIAG_STAT
GLOB_CMD
ALM_X_STAT
ALM_Y_STAT
ALM_Z_STAT
ALM_X_PEAK
ALM_Y_PEAK
ALM_Z_PEAK
TIME_STAMP_L
TIME_STAMP_H
Reserved
LOT_ID1
LOT_ID2
PROD_ID
SERIAL_NUM
ALM_X_FREQ
ALM_Y_FREQ
ALM_Z_FREQ
REC_INFO
Rev. B | Page 9 of 24
Reference
Table 61
Table 18
Table 18
Table 18
Table 20
Table 48
Table 50
Table 19
Table 43
Table 44
Table 45
Table 45
Table 45
Table 13
Table 10
Table 11
Table 24
Table 25
Table 26
Table 27
Table 28
Table 29
Table 30
Table 31
Table 23
Table 32
Table 22
Table 59
Table 60
N/A
Table 58
Table 57
Table 33
Table 34
Table 35
Table 36
Table 37
Table 38
Table 54
Table 55
N/A
Table 62
Table 62
Table 63
Table 64
Table 39
Table 40
Table 41
Table 53
ADIS16227
Data Sheet
DATA RECORDING AND SIGNAL PROCESSING
The ADIS16227 provides a number of registers for configuring
its data collection and signal processing operation (see Table 9).
Figure 13 provides a signal flow diagram, which describes many
of these settings.
Table 9. Sampling/Signal Processing Register Summary
Address
0x02
0x04
0x06
0x08
0x0E
0x1A
0x1C
0x1E
0x3E
Description
X-axis offset correction
Y-axis offset correction
Z-axis offset correction
Record, flash write cycle counter
Record, FFT averages
Record, counter
Record, data processing
Record, automatic mode period
Trigger, record commands
Table 11. REC_PRD Register Bit Descriptions
Bits
[15:10]
[9:8]
Table 10. REC_CTRL Bit Descriptions
[3:2]
[1:0]
Description (Default = 0x1130)
Not used
Window setting:
00 = rectangular, 01 = Hanning, 10 = flat top, 11 = N/A
SR3, fs ÷ 512 (1 = enabled for analysis)
SR2, fs ÷ 64 (1 = enabled for analysis)
SR1, fs ÷ 8 (1 = enabled for analysis)
SR0, fs (1 = enabled for analysis)
Power-down between each recording (1 = enabled)
Not used
Signal range:
00 = 0 g to 1 g, 01 = 0 g to 5 g, 10 = 0 g to 20 g, 11 = 0 g
to 70 g
Storage method:
00 = none, 01 = alarm trigger, 10 = all, 11 = N/A
Recording mode:
00 = manual, 01 = automatic, 10 = manual time, 11 = N/A
O
[11]
[10]
[9]
[8]
[7]
[6]
[5:4]
RECORDING TIMES
The automatic recording period (REC_PRD) must be greater
than the total recording time. Use the following equations to
calculate the recording time:
Manual time mode
TR = TS + TPT + TST + TAST
FFT modes
B
SO
Bits
[15:14]
[13:12]
[7:0]
LE
The record control register is REC_CTRL (see Table 10), which
provides external controls for sample rates, dynamic range,
record storage, recording mode, and power management.
Description (Default = 0x0000)
Not used
Scale for data bits
00 = 1 second/LSB
01 = 1 minute/LSB
10 = 1 hour/LSB
Data bits, binary format, range = 0 to 255
TE
Register
X_NULL
Y_NULL
Z_NULL
REC_FLSH_CNT
FFT_AVG
REC_CNTR
REC_CTRL
REC_PRD
GLOB_CMD
For example, set DIO_CTRL[7:0] = 0x2F (DIN = 0xB62F) to
configure DIO2 as a positive external trigger input and
maintain the DIO1 factory default configuration as a positive
busy indicator. In manual mode, the start command triggers a
recording for an averaged FFT and stops after the recording is
complete. In automatic mode, the start command executes a
recording, and a timer continues to trigger recordings based on
the record period setting in REC_PRD (see Table 11).
RECORDING MODES
REC_CTRL[1:0] provides three modes for triggering: (1) manual,
(2) automatic, and (3) manual time domain. The manual and
automatic modes produce FFT events, which include data
collection, filtering, windowing, FFT analysis, and record
storage (if selected). The manual time domain mode produces
time-domain data in the buffer. All three modes require an
external trigger, using either the SPI interface or one of the
auxiliary digital I/O lines, DIO1 or DIO2. For the SPI external
trigger option, set GLOB_CMD[11] = 1 (DIN = 0x3F08). For
the digital I/O option, use the DIO_CTRL register (see
Table 59) to configure either DIO1 or DIO2 as an external
trigger input.
TR = N F × (TS + TPT + TFFT ) + TST + TAST
The storage time (TST) applies only when a storage method is
selected in REC_CTRL[3:2]. See Table 10 for more details on
the record storage setting. The alarm scan time (TAST) applies
only when the alarms are enabled in ALM_CTRL[4:0]. See
Table 22 for more details on enabling the alarms.
Table 12. Available Records
Function
Sample Time, TS
Processing Time, TPT
FFT Time, TFFT
Number of FFT Averages, NF
Storage Time, TST
Alarm Scan Time, TAST
Rev. B | Page 10 of 24
Time (ms)
See Table 15
10.4
26.6
See Table 19
120.0
2.21
Data Sheet
ADIS16227
Table 14. Sample Rate Settings and Filter Performance
Set GLOB_CMD[1] = 1 (DIN = 0xBE02) to power down the
ADIS16227. To reduce power consumption, set REC_CTRL[7]
= 1 to automatically power down after a record has completed.
Toggle the CS line from high to low to wake the device up and
place it in an idle state, where it waits for the next command.
When configured as an external trigger option, toggling DIO1
or DIO2 can wake the device up as well. Using DIO1 or DIO2
for this purpose avoids the potential for multiple devices
contending for DOUT when waking up with the CS line
approach. After completing the record cycle, the device remains
awake. Use GLOB_CMD[1] to put it back to sleep after reading
the record data.
RECORD STORAGE MODE
Sample Rate
(SPS)
100,189
12,524
1566
196
Bin Width
(Hz)
196
25
3.1
0.38
Bandwidth
(Hz)
26,000
6,262
783
98
Noise
(mg)
467
260
100
38
Table 15 provides the data sampling time (TS) for each sample
rate setting. This represents the time it takes to record data for
all three axes of vibration data.
Table 15. Sample Times, TS
Sample Rate Setting
SR0, REC_CTRL[8] = 1
SR1, REC_CTRL[9] = 1
SR2, REC_CTRL[10] = 1
SR3, REC_CTRL[11] = 1
Sample Time (ms), TS
5.27
42.15
337.17
2697.39
If more than one sample rate setting is active in REC_CTRL[11:8],
the sample rate setting automatically updates after each FFT
event and waits for the next trigger input. The order of priority
starts with the highest sample rate enabled and works toward the
lowest after each REC_CTRL[11:8] write cycle. When used in
conjunction with automatic trigger mode and record storage,
FFT analysis for each sample rate option requires no further
user inputs, except for collecting the data. Depending on the
number of FFT averages, the time period between each sample
rate selection may be quite large. Note that selecting multiple
sample rates reduces the number of records available for each
sample rate setting, as shown in Table 16.
B
SO
LE
After the ADIS16227 finishes processing FFT data, it stores the
data into the FFT buffer, where it is available for external access
using the SPI and x_BUF registers. REC_CTRL[3:2] provides
programmable conditions for writing buffer data into the FFT
records, which are in nonvolatile flash memory locations. Set
REC_CTRL[3:2] = 01 to store FFT buffer data into the flash
memory records only when an alarm condition is met. Set
REC_CTRL[3:2] = 10 to store every set of FFT data into the
flash memory locations. The flash memory record provides
space for a total of 16 records. Each record stored in flash
memory contains a header and frequency domain (FFT) data
from all three axes (x, y, and z). When all 16 records are full,
new records do not load into the flash memory. The
REC_CNTR register (see Table 13) provides a running count
for the number of records that are stored. Set GLOB_CMD[8] =
1 (DIN = 0xBF01) to clear all of the records in flash memory.
Setting
SR0
SR1
SR2
SR3
TE
POWER-DOWN
Table 13. REC_CNTR Bit Descriptions
Bits
[15:5]
[4:0]
Description (Default = 0x0000)
Not used
Total number of records taken, range = 0 to 16, binary
Table 16. Available Records
Number of Sample Rates Selected
1
2
3
4
Available Records
16
8
5
4
WINDOWING OPTIONS
The analog-to-digital converter (ADC) samples each accelerometer sensor at a rate of 100.2 kSPS (fs). REC_CTRL[11:8] provide
four different sample rate options for FFT analysis: SR0 (fs),
SR1(fs ÷ 8), SR2 (fs ÷ 64), and SR3 (fs ÷ 512). The reduced rates
come from a decimation filter, which reduces the bandwidth
and bin widths. See Figure 13 for the filter location in the signal
processing diagram and Table 14 for the performance trade-offs
associated with each sample rate setting.
REC_CTRL[13:12] provide three options for pre-FFT
windowing of time data. For example, set REC_CTRL[13:12] =
01 to use the Hanning window, which offers the best amplitude
resolution of the peaks between frequency bins and minimal
broadening of peak amplitudes. The rectangular and flat top
windows are also available because they are common windowing
options for vibration monitoring. The flat top window provides
accurate amplitude resolution with a trade-off of broadening
the peak amplitudes.
O
SAMPLE RATE OPTIONS
Rev. B | Page 11 of 24
ADIS16227
Data Sheet
RANGE
FFT AVERAGING
REC_CTRL[5:4] provide four range options for scaling
acceleration data prior to the FFT analysis stage. For example,
set REC_CTRL[5:4] = 10 to set the peak acceleration (AMAX) to
5 g. See Table 17 for the resolution associated with each setting
and Figure 13 for the location of this operation in the signal
flow diagram.
The FFT averaging function records a programmable number
of FFTs and combines them into a single, averaged FFT record.
This function is useful in reducing the variation of the FFT
noise floor, which enables detection of lower vibration levels. To
enable this function, write the number of averages to FFT_AVG.
Setting FFT_AVG = 0x0000 has the same effect as setting
FFT_AVG = 0x0001: no averaging. Setting FFT_AVG ≥ 0x0100
results in a setting of 256. Therefore, set FFT_AVG[15:8] = 0x01
(DIN = 0x8F01) to establish the maximum average setting of
256. Another example configuration is to set FFT_AVG =
0x00F0 (DIN = 0x8F00, DIN = 0x8EF0) to establish an average
setting of 240.
Table 17. Range Setting and LSB Weights
Time Mode
(mg/LSB)
0.0305
0.1526
0.6104
2.3842
FFT Mode
(mg/LSB)
0.0153
0.0763
0.3052
1.1921
TE
Table 19. FFT_AVG Register Bit Descriptions
Bits
[15:9]
[8:0]
OFFSET CORRECTION
The x_NULL registers (see Table 18) contain the offset
correction factors generated when using the internal, autonull
command. They represent the KO factor in Figure 13 and follow
the digital format in Table 18. Set GLOB_CMD[0] =1 (DIN =
0xBE01) and wait for 681 ms to execute this function.
LE
FFT RECORD FLASH ENDURANCE
The REC_FLSH_CNT register (see Table 20) increments each
time that all 16 records have FFT data.
Table 18. X_NULL, Y_NULL, and Z_NULL Bit Descriptions
Table 20. REC_FLSH_CNT Bit Descriptions
Description (Default = 0x0000)
Offset correction factor, twos complement,
2.3842 mg/LSB
Bits
[15:0]
B
SO
Bits
[15:0]
Description (Default = 0x0008)
Not used
Number of FFT averages for a single record,
NF in Figure 13, range = 1 to 256, binary
RANGE-SCALE SETTING
Ks= AMAX ÷ 215
AMAX = PEAK FROM REC_CTRL[5:4]
OFFSET CORRECTION
KO = X_NULL, Y_NULL, Z_NULL
SAMPLE RATE SETTING
REC_CTRL[11:8]
100kSPS
1
NA
Ks
WINDOW SETTING
REC_CTRL[13:12]
FFT RECORDS—NONVOLATILE FLASH MEMORY
FFT
RECORD
0
xK
K=1
÷N A
+
WINDOW
FFT
RECORD
1
NF = # OF AVERAGES
NF = FFT_AVG[8:0]
Na
O
TRIAXIS
MEMS
ACCEL
Ko
Description
Flash write cycle count, record data only, binary
FFT
FFT
AVERAGE
(NF)
Figure 13. Signal Flow Diagram, REC_CTRL[1:0] = 00 or 01, FFT Analysis Modes
Rev. B | Page 12 of 24
FFT
RECORD
m
FFT
RECORD
15
m = REC_CNTR
REC_CTRL[3:2]
FFT
BUFFER
BUFFER
REGISTER
AND SPI
09425-016
Range Setting (g)
(REC_CTRL[5:4])
0 to 1
0 to 5
0 to 20
0 to 70
Data Sheet
ADIS16227
SPECTRAL ALARMS
The ALM_CTRL register (see Table 22) provides control bits
that enable each axis’ spectral alarms, configures the system
alarm, sets the record delay for the spectral alarms, and
configures the clearing function for the DIAG_STAT error flags.
Table 22. ALM_CTRL Bit Descriptions
Description (Default = 0x0080)
Not used
Response delay, range: 0 to 15; represents the number
of spectral records for each spectral alarm before a
spectral alarm flag is set high
Latch DIAG_STAT error flags, which requires a clear
status command (GLOB_CMD[4]) to reset the flags to 0
(1 = enabled, 0 = disabled)
Enable DIO1 as an Alarm 1 output indicator and enable
DIO2 as an Alarm2 output indicator (1 = enabled)
System alarm comparison polarity
1 = trigger when less than ALM_MAGS[11:0]
0 = trigger when greater than ALM_MAGS[11:0]
System alarm, 1 = temperature 0 = power supply
Alarm S enable (ALM_S_MAG), 1 = enabled, 0 = disabled
Alarm Z enable (ALM_Z_MAG), 1 = enabled, 0 = disabled
Alarm Y enable (ALM_Y_MAG), 1 = enabled, 0 = disabled
Alarm X enable (ALM_X_MAG), 1 = enabled, 0 = disabled
O
Bits
[15:12]
[11:8]
[7]
[6]
[5]
[4]
[3]
[2]
[1]
[0]
ALM_F_LOW
ALM_x_MAG2
ALM_F_HIGH
ALM_x_MAG1
1
2
3
4
5
FREQUENCY
6
09425-020
LE
Description
Alarm frequency, lower limit
Alarm frequency, upper limit
X-Alarm Trigger Level 1 (warning)
Y-Alarm Trigger Level 1 (warning)
Z-Alarm Trigger Level 1 (warning)
X-Alarm Trigger Level 2 (fault)
Y-Alarm Trigger Level 2 (fault)
Z-Alarm Trigger Level 2 (fault)
Alarm pointer
System alarm trigger level
Alarm configuration
Alarm status
X-alarm status
Y-alarm status
Z-alarm status
X-alarm peak
Y-alarm peak
Z-alarm peak
X-axis alarm frequency of peak alarm
Y-axis alarm frequency of peak alarm
Z-axis alarm frequency of peak alarm
B
SO
Address
0x20
0x22
0x24
0x26
0x28
0x2A
0x2C
0x2E
0x30
0x32
0x34
0x3C
0x40
0x42
0x44
0x46
0x48
0x4A
0x70
0x72
0x74
The alarm function provides six programmable spectral bands,
as shown in Figure 14. Each spectral alarm band has lower and
upper frequency definitions for all four sample rate options. It
also has two independent trigger level settings, which are useful
for systems that value warning and fault condition indicators.
TE
Table 21. Alarm Function Register Summary
Register
ALM_F_LOW
ALM_F_HIGH
ALM_X_MAG1
ALM_Y_MAG1
ALM_Z_MAG1
ALM_X_MAG2
ALM_Y_MAG2
ALM_Z_MAG2
ALM_PNTR
ALM_S_MAG
ALM_CTRL
DIAG_STAT
ALM_X_STAT
ALM_Y_STAT
ALM_Z_STAT
ALM_X_PEAK
ALM_Y_PEAK
ALM_Z_PEAK
ALM_X_FREQ
ALM_Y_FREQ
ALM_Z_FREQ
ALARM DEFINITION
MAGNITUDE
The alarm function offers six spectral bands for alarm
detection. Each spectral band has high and low frequency
definitions, along with two different trigger thresholds (Alarm 1
and Alarm 2) for each accelerometer axis. Table 21 provides a
summary of each register used to configure the alarm function.
Figure 14. Spectral Band Alarm Setting Example, ALM_PNTR = 0x03
Select the spectral band for configuration by writing its number
(1 to 6) to ALM_PNTR[2:0] (see Table 23). Then, select the
sample rate setting using ALM_PNTR[9:8]. This number
represents a binary number, which corresponds to the x in the
SRx sample rates settings associated with REC_CTRL[11:8] (see
Table 10). For example set ALM_PNTR[7:0] = 0x05 (DIN =
0xB005) to select Alarm Spectral Band 5 and set
ALM_PNTR[15:8] =
0x02 (DIN = 0xB102) to select the SR2 sample rate option
from Table 14, 1,566 SPS.
Table 23. ALM_PNTR Bit Assignments
Bits
[15:10]
[9:8]
[7:3]
[2:0]
Rev. B | Page 13 of 24
Description (Default = 0x0000)
Not used
Sample rate setting, range: 0 to 3
Not used
Spectral band number, range: 1 to 6
ADIS16227
Data Sheet
After the spectral band and sample rate settings are set,
program the lower and upper frequency boundaries by writing
their bin numbers to the ALM_F_LOW (see Table 24) and
ALM_F_HIGH (see Table 25) registers. Use the bin width
definitions in Table 14 to convert a frequency into a bin number
for this definition. Calculate the bin number by dividing the
frequency by the bin width associated with the sample rate
setting. For example, 3400 Hz, divided by 196 Hz/bin (SR0
setting), rounded to the nearest integer, is equal to 17, or 0x12.
Therefore, set ALM_F_LOW[7:0] = 0x11 (DIN = 0xA011) to
establish 3400 Hz as the lower frequency for the SR0 sample
rate setting.
Table 24. ALM_F_LOW Bit Assignments
Bits
[15:8]
[7:0]
Bits
[15:0]
Table 30. ALM_Y_MAG2 Bit Assignments
Bits
[15:0]
Description (Default = 0x0000)
Y-axis Alarm Trigger Level 2, 16-bit unsigned; see
REC_CTRL[5:4] and Table 17 for the scale factor
Description (Default = 0x0000)
Z-axis Alarm Trigger Level 1, 16-bit unsigned; see
REC_CTRL[5:4] and Table 17 for the scale factor
LE
Bits
[15:0]
Description (Default = 0x0000)
System alarm trigger level, data format matches target
from ALM_CTRL[4]
Enable Alarm Settings
Before configuring the spectral alarm registers, clear their
current contents by setting GLOB_CMD[9] = 1 (DIN = 0xBF02).
After completing the spectral alarm band definitions, enable the
settings by setting GLOB_CMD[12] = 1 (DIN = 0xBF10). The
device ignores the save command if any of these locations have
already been written to.
B
SO
O
ALM_X_MAG2 > ALM_X_MAG1
ALM_Y_MAG2 > ALM_Y_MAG1
ALM_Z_MAG2 > ALM_Z_MAG1
ALARM INDICATOR SIGNALS
DIO_CTRL[5:2] and ALM_CTRL[6] provide controls for
establishing DIO1 and DIO2 as dedicated alarm output indicator
signals. Use DIO_CTRL[5:2] to select Alarm function for DIO1
and/or DIO2; then set ALM_CTRL[6] = 1 to enable DIO1 to
serve as an Alarm 1 indicator and DIO2 as an Alarm 2 indicator.
This setting establishes DIO1 to indicate Alarm 1 (warning)
conditions and DIO2 to indicate Alarm 2 (critical) conditions.
Table 26. ALM_X_MAG1 Bit Assignments
Description (Default = 0x0000)
X-axis Alarm Trigger Level 1, 16-bit unsigned; see
REC_CTRL[5:4] and Table 17 for the scale factor
Table 27. ALM_Y_MAG1 Bit Assignments
Bits
[15:0]
Description (Default = 0x0000)
X-axis Alarm Trigger Level 2, 16-bit unsigned; see
REC_CTRL[5:4] and Table 17 for the scale factor
Table 32. ALM_S_MAG Bit Assignments
The ALM_x_MAG1 and ALM_x_MAG2 registers provide two
independent trigger settings for all three axes of acceleration
data. They use the data format established by the range setting
in REC_CTRL[5:4] and recording mode in REC_CTRL[1:0].
For example, when using the 0 g to 1 g mode for FFT analysis,
3277 LSB is equivalent to 500.07 mg. To set the critical alarm to
500.07 mg when using the 0 g to 1 g range option in REC_CTRL2
for FFT records, set ALM_X_MAG2 = 0x0CCD (DIN = 0xAD0C,
0xACCD). See Table 10 and Table 17 for more information on
formatting each trigger level. Note that trigger settings associated
with Alarm 2 should be greater than the trigger settings for
Alarm 1. In other words, the alarm magnitude settings should
meet the following criteria:
Bits
[15:0]
Description (Default = 0x0000)
Z-axis Alarm Trigger Level 1, 16-bit unsigned; see
REC_CTRL[5:4] and Table 17 for the scale factor
Table 29. ALM_X_MAG2 Bit Assignments
Bits
[15:0]
Description (Default = 0x0000)
Not used
Upper frequency, bin number, range = 0 to 255
Alarm Trigger Settings
Bits
[15:0]
Table 31. ALM_Z_MAG2 Bit Assignments
Description (Default = 0x0000)
Not used
Lower frequency, bin number, range = 0 to 255
Table 25. ALM_F_HIGH Bit Assignments
Bits
[15:8]
[7:0]
Table 28. ALM_Z_MAG1 Bit Assignments
TE
Alarm Band Frequency Definitions
Description (Default = 0x0000)
Y-axis Alarm Trigger Level 1, 16-bit unsigned; see
REC_CTRL[5:4] and Table 17 for the scale factor
Rev. B | Page 14 of 24
Data Sheet
ADIS16227
Table 35. ALM_Z_STAT Bit Assignments
The FFT header (see Table 52) contains both generic alarm flags
(DIAG_STAT[13:8] (see Table 58) and spectral band-specific
alarm flags (ALM_x_STAT, see Table 33, Table 34 and Table 35).
The FFT header also contains magnitude (ALM_x_PEAK, see
Table 36, Table 37 and Table 38) and frequency information
(ALM_x_FREQ, see Table 39, Table 40, and Table 41) associated
with the highest magnitude of vibration content in the record.
ALARM STATUS
The ALM_x_STAT registers, in Table 33, Table 34, and Table 35,
provide alarm bits for each spectral band on the current sample
rate option.
Table 33. ALM_X_STAT Bit Assignments
Table 34. ALM_Y_STAT Bit Assignments
Description (Default = 0x0000)
Alarm 2 on Band 6, 1 = alarm set, 0 = no alarm
Alarm 1 on Band 6, 1 = alarm set, 0 = no alarm
Alarm 2 on Band 5, 1 = alarm set, 0 = no alarm
Alarm 1 on Band 5, 1 = alarm set, 0 = no alarm
Alarm 2 on Band 4, 1 = alarm set, 0 = no alarm
Alarm 1 on Band 4, 1 = alarm set, 0 = no alarm
Alarm 2 on Band 3, 1 = alarm set, 0 = no alarm
Alarm 1 on Band 3, 1 = alarm set, 0 = no alarm
Alarm 2 on Band 2, 1 = alarm set, 0 = no alarm
Alarm 1 on Band 2, 1 = alarm set, 0 = no alarm
Alarm 2 on Band 1, 1 = alarm set, 0 = no alarm
Alarm 1 on Band 1, 1 = alarm set, 0 = no alarm
Not used
Most critical alarm condition, spectral band, range: 1 to 6
O
Bits
[15]
[14]
[13]
[12]
[11]
[10]
[9]
[8]
[7]
[6]
[5]
[4]
[3]
[2:0]
Description (Default = 0x0000)
Alarm 2 on Band 6, 1 = alarm set, 0 = no alarm
Alarm 1 on Band 6, 1 = alarm set, 0 = no alarm
Alarm 2 on Band 5, 1 = alarm set, 0 = no alarm
Alarm 1 on Band 5, 1 = alarm set, 0 = no alarm
Alarm 2 on Band 4, 1 = alarm set, 0 = no alarm
Alarm 1 on Band 4, 1 = alarm set, 0 = no alarm
Alarm 2 on Band 3, 1 = alarm set, 0 = no alarm
Alarm 1 on Band 3, 1 = alarm set, 0 = no alarm
Alarm 2 on Band 2, 1 = alarm set, 0 = no alarm
Alarm 1 on Band 2, 1 = alarm set, 0 = no alarm
Alarm 2 on Band 1, 1 = alarm set, 0 = no alarm
Alarm 1 on Band 1, 1 = alarm set, 0 = no alarm
Not used
Most critical alarm condition, spectral band, range: 1 to 6
WORST-CONDITION MONITORING
The ALM_x_PEAK registers (see Table 36, Table 37, and Table
38) contain the peak magnitude for the worst-case alarm
condition in each axis. The ALM_x_FREQ registers (see Table
39, Table 40, and Table 41) contain the frequency bin number
for the worst-case alarm condition.
LE
Description (Default = 0x0000)
Alarm 2 on Band 6, 1 = alarm set, 0 = no alarm
Alarm 1 on Band 6, 1 = alarm set, 0 = no alarm
Alarm 2 on Band 5, 1 = alarm set, 0 = no alarm
Alarm 1 on Band 5, 1 = alarm set, 0 = no alarm
Alarm 2 on Band 4, 1 = alarm set, 0 = no alarm
Alarm 1 on Band 4, 1 = alarm set, 0 = no alarm
Alarm 2 on Band 3, 1 = alarm set, 0 = no alarm
Alarm 1 on Band 3, 1 = alarm set, 0 = no alarm
Alarm 2 on Band 2, 1 = alarm set, 0 = no alarm
Alarm 1 on Band 2, 1 = alarm set, 0 = no alarm
Alarm 2 on Band 1, 1 = alarm set, 0 = no alarm
Alarm 1 on Band 1, 1 = alarm set, 0 = no alarm
Not used
Most critical alarm condition, spectral band, range: 1 to 6
B
SO
Bits
[15]
[14]
[13]
[12]
[11]
[10]
[9]
[8]
[7]
[6]
[5]
[4]
[3]
[2:0]
Bits
[15]
[14]
[13]
[12]
[11]
[10]
[9]
[8]
[7]
[6]
[5]
[4]
[3]
[2:0]
TE
ALARM FLAGS AND CONDITIONS
Table 36. ALM_X_PEAK Bit Assignments
Bits
[15:0]
Description (Default = 0x0000)
Alarm peak, x-axis, accelerometer data format
Table 37. ALM_Y_PEAK Bit Assignments
Bits
[15:0]
Description (Default = 0x0000)
Alarm peak, y-axis, accelerometer data format
Table 38. ALM_Z_PEAK Bit Assignments
Bits
[15:0]
Description (Default = 0x0000)
Alarm peak, z-axis, accelerometer data format
Table 39. ALM_X_FREQ Bit Assignments
Bits
[15:8]
[7:0]
Description (Default = 0x0000)
Not used
Alarm frequency for x-axis peak alarm level,
FFT bin number, range: 0 to 255
Table 40. ALM_Y_FREQ Bit Assignments
Bits
[15:8]
[7:0]
Description (Default = 0x0000)
Not used
Alarm frequency for y-axis peak alarm level,
FFT bin number, range: 0 to 255
Table 41. ALM_Z_FREQ Bit Assignments
Bits
[15:8]
[7:0]
Rev. B | Page 15 of 24
Description (Default = 0x0000)
Not used
Alarm frequency for z-axis peak alarm level,
FFT bin number, range: 0 to 255
ADIS16227
Data Sheet
READING OUTPUT DATA
The ADIS16227 samples, processes, and stores x, y, and z acceleration data into the FFT buffer and FFT records (if selected).
In manual time mode, each axis’ record contains 512 samples
for each axis. Otherwise, each record contains the 256-point
FFT result for each accelerometer axis. Table 42 provides a
summary of registers that provide access to processed sensor
data.
Table 42. Output Data Registers
Description
Internal power supply
Internal temperature
Data buffer index pointer
FFT record index pointer
X-axis accelerometer buffer
Y- axis accelerometer buffer
Z- axis accelerometer buffer
FFT record retrieve command
Time stamp, lower word
Time stamp, upper word
FFT record header information
ACCESSING FFT RECORD DATA
The FFT records provide flash memory storage for FFT data.
The REC_PNTR register (see Table 44) and record retrieve
command in GLOB_CMD[13] (see Table 57) provide access to
the FFT records, as shown in Figure 16. For example, set
REC_PNTR[7:0] = 0x0A (DIN = 0x920A) and GLOB_CMD[13]
= 1 (DIN = 0xBF20) to load FFT Record 10 in the FFT buffer
for SPI/register access.
Table 44. REC_PNTR Bit Descriptions
Bits
[15:4]
[3:0]
Description (Default = 0x0000)
Not used
Data bits
FFT
FFT
RECORD RECORD
0
1
FFT
RECORD
m
FFT
RECORD
15
X
X
Z X
O
DATA IN BUFFERS LOAD INTO
USER OUTPUT REGISTERS
X_BUF
Z
Y
Z
X
Y
Z
X
Y
Z
SPI
REGISTERS
FFT
BUFFER
Figure 16. FFT Record Access
DATA FORMAT
Table 45 provides the bit assignments for the x_BUF registers.
The acceleration data format depends on the range scale and
recording mode settings in REC_CTRL. See Table 10 for
configuration details and Table 17 for the scale factors
associated with each setting. Table 46 provides some data
formatting examples for FFT mode, and Table 47 offers some
data formatting examples for the16-bit twos complement
format used in manual time mode.
Table 45. X_BUF, Y_BUF, Z_BUF Bit Descriptions
Bits
[15:0]
Y_BUF
0
Y
m = REC_PNTR
GLOB_CMD[13] = 1
B
SO
After completing an FFT event and updating the data buffer, the
ADIS16227 loads the first data samples from the data buffer
into the x_BUF registers (see Table 45) and sets the buffer index
pointer (BUF_PNTR) to 0x0000. The index pointer determines
which data samples load into the x_BUF registers. For example,
writing 0x009F to the BUF_PNTR register (DIN = 0x9100, DIN
= 0x909F) causes the 160th sample in each data buffer location
to load into the x_BUF registers. The index pointer increments
with every x_BUF read command, which causes the next set
of capture data to load into each capture buffer register automatically. This enables a process-efficient method for reading all
256 samples in a record, using sequential reads commands,
without having to manipulate BUF_PNTR.
Y
09425-019
READING DATA FROM THE DATA BUFFER
Description (Default = 0x0000)
Not used
Data bits
TE
Address
0x0A
0x0C
0x10
0x12
0x14
0x16
0x18
0x3E
0x4C
0x4E
0x76
Bits
[15:9]
[8:0]
LE
Register
SUPPLY_OUT
TEMP_OUT
BUF_PNTR
REC_PNTR
X_BUF
Y_BUF
Z_BUF
GLOB_CMD
TIME_STAMP_L
TIME_STAMP_H
REC_INFO
Table 43. BUF_PNTR Bit Descriptions
Description (Default = 0x8000)
Acceleration buffer registers
Z_BUF
Table 46. FFT Mode, 0 g to 5 g Range, Data Format Examples
BUF_PNTR
X-AXIS
Y-AXIS
Z-AXIS
ACCELEROMETER ACCELEROMETER ACCELEROMETER
FFT
FFT
FFT
BUFFER
BUFFER
BUFFER
Acceleration (mg)
4999.9237
7.63
0.1526
0.0763
0
256/512
FFT ANALYSIS
INTERNAL SAMPLING SYSTEM SAMPLES, PROCESSES, AND
STORES DATA IN FFT BUFFERS.
TEMP_OUT
09425-013
SUPPLY_OUT
Figure 15. Data Buffer Structure and Operation
Rev. B | Page 16 of 24
LSB
65,535
100
2
1
0
Hex
0xFFFF
0x0064
0x0002
0x0001
0x0000
Binary
1111 1111 1111 1111
0000 0000 0110 0100
0000 0000 0000 0010
0000 0000 0000 0001
0000 0000 0000 0000
Data Sheet
ADIS16227
Acceleration (mg)
+70,000
+1001.358
+4.7684
+2.3842
0
−2.3842
−4.7684
−1001.358
−70,000
LSB
+29,360
+420
+2
+1
0
−1
−2
−420
−29,360
Hex
0x72B0
0x01A4
0x0002
0x0001
0x0000
0xFFFF
0xFFFE
0xFE5C
0x8D50
Binary
0111 0010 1011 0000
0000 0001 1010 0100
0000 0000 0000 0010
0000 0000 0000 0001
0000 0000 0000 0000
1111 1111 1111 1111
1111 1111 1111 1110
1111 1110 0101 1100
1000 1101 0101 0000
POWER SUPPLY/TEMPERATURE
Table 48. SUPPLY_OUT Bits Descriptions
Bits
[15:12]
[11:0]
Description (Default = 0x8000)
Not used
Power supply, binary, +3.3 V = 0xA8F, 1.22 mV/LSB
B
SO
Table 49. Power Supply Data Format Examples
Supply Level (V)
3.6
3.3 + 0.0012207
3.3
3.3 − 0.0012207
3.15
LSB
2949
2704
2703
2702
2580
Hex
0xB85
0xA90
0xA8F
0xA8E
0xA14
Binary
1011 1000 0101
1010 1001 0000
1010 1000 1111
1010 1000 1110
1010 0001 0100
Table 50. TEMP_OUT Bit Descriptions
Description (Default = 0x8000)
Not used
Temperature data, offset binary,
1278 LSB = +25°C, −0.47°C/LSB
O
Bits
[15:12]
[11:0]
Table 51. Internal Temperature Data Format Examples
Temperature (°C)
125
25 + 0.47
25
25 − 0.047
0
−40
LSB
1065
1277
1278
1279
1331
1416
Hex
0x429
0x4FD
0x4FE
0x4FF
0x533
0x588
Each FFT record has an FFT header, which contains
information that fills all of the registers listed in Table 52. The
information in these registers contains recording time, record
configuration settings, status/error flags, and several alarm
outputs. The registers listed in Table 52 update with every
record event and also update with record-specific information
when using GLOB_CMD[13] to retrieve a data set from the
FFT record.
Table 52. FFT Header Register Information
Register
DIAG_STAT
ALM_X_STAT
ALM_Y_STAT
ALM_Z_STAT
ALM_X_PEAK
ALM_Y_PEAK
ALM_Z_PEAK
TIME_STAMP_L
TIME_STAMP_H
ALM_X_FREQ
ALM_Y_FREQ
ALM_Z_FREQ
REC_INFO
Address
0x3C
0x40
0x42
0x44
0x46
0x48
0x4A
0x4C
0x4E
0x70
0x72
0x74
0x76
LE
During every acceleration recording process, the ADIS16227 also
measures power supply and internal temperature. It takes a
5.12 ms record of power supply measurements at a sample rate
of 50 kHz and takes 64 samples of internal temperature data over
a period of 1.7 ms. The average of the power supply and internal
temperature loads into the SUPPLY_OUT and TEMP_OUT
registers, respectively.
FFT EVENT HEADER
Binary
0100 0010 1001
0100 1111 1101
0100 1111 1110
0100 1111 1111
0101 0011 0011
0101 1000 1000
Description
Alarm status
X-alarm status
Y-alarm status
Z-alarm status
X-alarm peak
Y-alarm peak
Z-alarm peak
Time stamp, lower word
Time stamp, upper word
X-alarm frequency of peak alarm
Y-alarm frequency of peak alarm
Z-alarm frequency of peak alarm
FFT record header information
TE
Table 47. Acceleration Format, Time Domain, 0 g to 70 g Range
The REC_INFO register (see Table 53) captures the settings
associated with the current FFT record.
Table 53. REC_INFO Bit Descriptions
Bits
[15:14]
[13:12]
[11:10]
[9]
[8:0]
Description (Default = 0x0000)
Sample rate setting:
00 = SR0, 01 = SR1, 10 = SR2, 11 = SR3
Window setting:
00 = rectangular, 01 = Hanning, 10 = flat top, 11 = N/A
Signal range:
00 = 0 g to 1 g, 01 = 0 g to 5 g, 10 = 0 g to 20 g, 11 =
0 g to 70 g
Not used
FFT averages, range: 1 to 256
The TIME_STAMP_x registers (see Table 54 and Table 55)
provide a relative time stamp, which identifies the time for the
current FFT record.
Table 54. TIME_STMP_L Bit Descriptions
Bits
[15:0]
Description (Default = 0x0000)
Time stamp, low integer, binary, seconds
Table 55. TIME_STMP_H Bit Descriptions
Bits
[15:0]
Rev. B | Page 17 of 24
Description (Default = 0x0000)
Time stamp, high integer, binary, seconds
ADIS16227
Data Sheet
SYSTEM TOOLS
STATUS/ERROR FLAGS
Table 56. System Tool Register Addresses
Register Name
FLASH_CNT
DIO_CTRL
GPIO_CTRL
DIAG_STAT
GLOB_CMD
LOT_ID1
LOT_ID2
PROD_ID
SERIAL_NUM
Address
0x00
0x36
0x38
0x3C
0x3E
0x52
0x54
0x56
0x58
Description
Flash write cycle count
Digital I/O configuration
General-purpose I/O control
Status, error flags
Global commands
Lot Identification Code 1
Lot Identification Code 2
Product identification
Serial number
GLOBAL COMMANDS
Table 57. GLOB_CMD Bit Descriptions
[12]
[11]
[10]
[9]
[8]
[7]
[6]
[5]
[4]
[3]
[2]
[1]
[0]
Bits
[15]
[14]
[13]
[12]
[11]
[10]
[9]
[8]
[7]
[6]
[5]
[4]
Execution Time
35 µs
40 µs
B
SO
[13]
Description
Clear x_NULL registers
Retrieve spectral alarm band information from the ALM_PNTR setting
Restore record data from flash
memory
Save spectral alarm band registers
to flash memory
Record start/stop
Set BUF_PNTR = 0x0000
Clear spectral alarm band
registers from flash
Clear records
Software reset
Save registers to flash memory
Flash test, compare sum of flash
memory with factory value
Clear DIAG_STAT register
Restore factory register settings
and clear the capture buffers
Self-test, result in DIAG_STAT[5]
Power-down
Autonull
O
Bits
[15]
[14]
Table 58. DIAG_STAT Bit Descriptions
Description (Default = 0x0000)
Not used
System alarm flag
Z-axis, Spectral Alarm 2 flag
Y-axis, Spectral Alarm 2 flag
X-axis, Spectral Alarm 2 flag
Z-axis, Spectral Alarm 1 flag
Y-axis, Spectral Alarm 1 flag
X-axis, Spectral Alarm 1 flag
Data ready/busy indicator (0 = busy, 1 = data ready)
Flash test result, checksum flag
Self-test diagnostic error flag
Recording escape flag, indicates use of the SPI-driven
interruption command, 0xE8
SPI communication failure, (SCLKs ≠ even multiple of 16)
Flash update failure
Power supply above 3.625 V
Power supply below 3.125 V
LE
The GLOB_CMD register provides an array of single-write
commands for convenience. Setting the assigned bit (see Table
57) to 1 activates each function. When the function completes,
the bit restores itself to 0. For example, clear the capture buffers by
setting GLOB_CMD[8] = 1 (DIN = 0xBF01). All of the commands
in the GLOB_CMD register require the power supply be within
normal limits for the execution times listed in Table 57.
The DIAG_STAT register (see Table 58) provides a number
of status/error flags that reflect the conditions observed in a
recording during SPI communication and diagnostic tests. A
1 indicates an error condition, and all of the error flags are
sticky, which means that they remain until they are reset by
setting GLOB_CMD[4] = 1 (DIN = 0xBE10) or by starting a
new recording event. DIAG_STAT[14:8] indicates which
ALM_x_MAGx thresholds were exceeded during a recording
event. The flag in DIAG_STAT[3] indicates that the total
number of SCLK clocks is not a multiple of 16.
TE
Table 56 provides an overview of the control registers that
provide support for system level functions.
1.9 ms
[3]
[2]
[1]
[0]
461 µs
OPERATION MANAGMENT
N/A
36 µs
25.8 ms
The ADIS16227 SPI port supports two different communication commands while it is processing data or executing a
command associated with the GLOB_CMD register: reading
DIAG_STAT (DIN = 0x3C00) and the escape code (DIN =
0xE8E8). The SPI ignores all other commands when the
processor is busy.
25.9 ms
53.3 ms
29.3 ms
5.6 ms
36 µs
80.9 ms
Software Busy Indicator
Use the DIAG_STAT read command to poll DIAG_STAT[7],
which is equal to 0 when the processor is busy and equal to
1 when the processor is idle and data is ready for SPI communications.
32.9 ms
N/A
681 ms
Rev. B | Page 18 of 24
Data Sheet
ADIS16227
Software Escape Code
Table 59. DIO_CTRL Bit Descriptions
The only SPI command available when the processor is busy
is the escape code, which is 0xE8E8. Send this command in a
repeating pattern, with a small delay between each write cycle,
to the DIN pin, while monitoring DIAG_STAT[7]. The following code example illustrates this process:
Bits
[15:6]
[5:4]
DIAG_STAT = 0;
DIAG_STAT = read_reg(0x3C);
while ((DIAG_STAT & 0x0080) == 0)
{
write_reg(0xE8E8)
delay_us(50)
DIAG_STAT = read_reg(0x3C)
}
[3:2]
The DIO_CTRL register (see Table 59) provides configuration
control options for the two digital I/O lines, DIO1 and DIO2.
Busy Indicator
Trigger Input
Δt
Δt ≥ 2.6µs
CAPTURE TIME
09425-014
DIO1
B
SO
The trigger function provides an input pin for starting record
events with a signal pulse. Set DIO_CTRL[7:0] = 0x2F (DIN =
0xB62F) to configure DIO2 as a positive trigger input and keep
DIO1 as a busy indicator. To start a trigger, the trigger input signal
must transition from low to high and then from high to low. The
recording process starts on the high-to-low transition, as shown
in Figure 17, and the pulse duration must be at least 2.6 µs.
DIO2
[0]
General-Purpose I/O
If DIO_CTRL configures either DIO1 or DIO2 as a generalpurpose digital line, use the GPIO_CTRL register in Table 60 to
configure its input/output direction, set the output level when
configured as an output, and monitor the status of an input.
LE
The busy indicator is an output signal that indicates internal
processor activity. This signal is active during data recording events
or internal processing (GLOB_CMD functions, for example). The
factory default setting for DIO_CTRL sets DIO1 as a positive,
active high, busy indicator signal. When configured in this
manner, use this signal to alert the master processor to read
data from data buffers.
TE
[1]
INPUT/OUTPUT FUNCTIONS
Description (Default = 0x000F)
Not used
DIO2 function selection
00 = general-purpose I/O (use GPIO_CTRL)
01 = alarm indicator output (per ALM_CTRL)
10 = trigger input
11 = busy indicator output
DIO1 function selection
00 = general-purpose I/O (use GPIO_CTRL)
01 = alarm indicator output (per ALM_CTRL)
10 = trigger input
11 = busy indicator output
DIO2 line polarity
1 = active high
0 = active low
DIO1 line polarity
1 = active high
0 = active low
O
Figure 17. Manual Trigger/Busy Indicator Sequence Example
Table 60. GPIO_CTRL Bit Descriptions
Bits
[15:10]
[9]
[8]
[7:2]
[1]
[0]
Alarm Indicator
DIO_CTRL[5:2] provide controls for establishing DIO1 and/or
DIO2 as a general alarm output indicator, which goes active when
any of the flags in DIAG_STAT[13:8] are active. For example, set
DIO_CTRL[7:0] = 0x12 (DIN = 0xB612) to configure DIO2 as
a generic alarm indicator with an active high polarity.
ALM_CTRL[6] (see Table 22) provides an additional control,
which enables DIO2 to reflect Alarm 2 and DIO1 to reflect Alarm 1
when they are selected as alarm indicators in DIO_CTRL[5:2]. For
example, set DIO_CTRL[7:0] = 0x17 (DIN = 0xB617) and set
ALM_CTRL[6] = 1 (DIN = 0xB440) to establish DIO2 as an activehigh Alarm 2 indicator and DIO1 as an active-high Alarm 1
indicator. Set GLOB_CMD[4] = 1 (DIN = 0xBE10) to clear the
DIAG_STAT error flags and restore the alarm indicator signal to
its inactive state.
Description (Default = 0x0000)
Not used
DIO2 output level
1 = high
0 = low
DIO1 output level
1 = high
0 = low
Reserved
DIO2 direction control
1 = output
0 = input
DIO1 direction control
1 = output
0 = input
SELF-TEST
Set GLOB_CMD[2] = 1 (DIN = 0xBE02) to run an automatic
self-test routine, which reports a pass/fail result to DIAG_STAT[5].
Rev. B | Page 19 of 24
ADIS16227
Data Sheet
FLASH MEMORY MANAGEMENT
DEVICE IDENTIFICATION
Set GLOB_CMD[5] = 1 (DIN = 0xBE20) to run an internal
checksum test on the flash memory, which reports a pass/fail
result to DIAG_STAT[6]. The FLASH_CNT register (see Table 61)
provides a running count of flash memory write cycles. This is a
tool for managing the endurance of the flash memory. Figure 18
quantifies the relationship between data retention and junction
temperature.
Table 62. LOT_ID1 and LOT_ID2 Bit Descriptions
Table 61. FLASH_CNT Bit Descriptions
Table 64. SERIAL_NUM Bit Descriptions
Bits
[15:0]
Bits
[15:0]
Table 63. PROD_ID Bit Descriptions
Bits
[15:0]
Description
0x3F63 = 16,227
Description
Serial number, lot specific
150
30
40
55
70
85
100
125
135
150
B
SO
JUNCTION TEMPERATURE (°C)
09425-015
300
LE
450
Figure 18. Flash/EE Memory Data Retention
O
RETENTION (Years)
600
0
Description
Lot identification code
TE
Description
Binary counter for writing to flash memory
Bits
[15:0]
Rev. B | Page 20 of 24
Data Sheet
ADIS16227
APPLICATIONS INFORMATION
MOUNTING GUIDELINES
The ADIS16227 provides a threaded hole for a 10-32 UNF
machine screw. This hole is 9 mm deep, and the tapped depth
is 7 mm. Use a torque of 15 inch-pounds when tightening the
10-32 mounting fastener and make sure that the fastener doesn’t
bottom-out in the ADIS16227 when tightening.
DIO1 and DIO2 signals. The connector is a dual row, 2 mm
(pitch) connector that works with a number of ribbon cable
systems, including 3M Part Number 152212-0100-GB (ribboncrimp connector) and 3M Part Number 3625/12 (ribbon cable).
The LEDs (D1 and D2) provide visual indication of the DIO1
and DIO2 signals.
spi_write(BF08h);
delay 30ms;
Data(0) = spi_reg_read(14h);
For n = 0 to 255
Data(n) = spi_reg_read(14h);
end
B
SO
n = n + 1;
09425-017
Figure 19. Electrical Schematic
LE
When the power supply voltage of the ADIS16227 reaches 3.15 V, it
executes a start-up sequence that places the device in manual
FFT mode. The following code example initiates a manual data
recording by setting GLOB_CMD[11] = 1 (DIN = 0xBF08) and
reads all 256 samples in the x-axis acceleration buffer, using DIN =
0x1400. The data from the first spi_reg_read is not valid because
this command starts the process. The second spi_reg_read
command (the first read inside the embedded for loop) produces
the first valid data. This code sequence produces CS, SCLK, and
DIN signals similar to the ones shown in Figure 11.
TE
GETTING STARTED
O
The ADIS16227/PCBZ provides the ADIS16227 on a small
printed circuit board (PCB) that simplifies the connection to an
existing processor system. A single 10-32 machine screw (Fastener
Express, FHS1106-4I2) secures the ADIS16227CMLZ to the
interface board. The first set of mounting holes on the interface
boards is in the four corners of the PCB and provides clearance for 440 machine screws. The second set of mounting holes provides a
pattern that matches the ADISUSBZ evaluation system, using M2
× 0.4 mm machine screws. These boards are made of IS410
material and are 0.063 inches thick. The J1 connector uses Pin 1
through Pin 12 in this pattern. Pin 13 and Pin 14 are for future
expansion, but they also provide convenient probe points for the
Rev. B | Page 21 of 24
09425-018
INTERFACE BOARD
Figure 20. PCB Assembly View and Dimensions
ADIS16227
Data Sheet
OUTLINE DIMENSIONS
15.20
15.00 SQ
14.80
Ø 4.04 9
10-32 UNF 7
Ø 6.10 90°,
NEAR SIDE
6.00
BCS
1.00 BSC
PITCH
LE
17.50 NOM
TE
BOTTOM VIEW
TOP VIEW
DETAIL A
FRONT VIEW
B
SO
SIDE VIEW
15.20
15.00
14.80
0.50 BCS
3.88 NOM
0.45 NOM
DETAIL A
4.20
4.10
4.00
06-21-2010-A
0.54
NOM
9.20
9.00
8.80
O
Figure 21. 14-Lead Module with Connector Interface
(ML-14-2)
Dimensions shown in millimeters
ORDERING GUIDE
Model 1
ADIS16227CMLZ
ADIS16227/PCBZ
1
Temperature Range
−40°C to +125°C
Package Description
14-Lead Module with Connector Interface
Evaluation Board
Z = RoHS Compliant Part.
Rev. B | Page 22 of 24
Package Option
ML-14-2
Data Sheet
ADIS16227
O
B
SO
LE
TE
NOTES
Rev. B | Page 23 of 24
ADIS16227
Data Sheet
O
B
SO
LE
TE
NOTES
©2010–2012 Analog Devices, Inc. All rights reserved. Trademarks and
registered trademarks are the property of their respective owners.
D09425-0-5/12(B)
Rev. B | Page 24 of 24
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