ADIS16228CMLZ

Digital Triaxial Vibration Sensor with FFT Analysis and Storage Digital ADIS16228 Data Sheet FEATURES GENERAL DESCRIPTION Frequency domain triaxial vibration sensor Flat frequency response up to 5 kHz Digital acceleration data, ±18 g measurement range Digital range settings: 0 g to 1 g/5 g/10 g/20 g Real-time sample mode: 20.48 kSPS, single-axis Capture sample modes: 20.48 kSPS, three axes Trigger modes: SPI, timer, external Programmable decimation filter, 11 rate settings Multirecord capture for selected filter settings Manual capture mode for time domain data collection FFT, 512-point, real valued, all three axes (x, y, z) 3 windowing options: rectangular, Hanning, flat top Programmable FFT averaging: up to 255 averages Storage: 14 FFT records on all three axes (x, y, z) Programmable alarms, 6 spectral bands 2-level settings for warning and fault definition Adjustable response delay to reduce false alarms Internal self-test with status flags Digital temperature and power supply measurements 2 auxiliary digital inputs/outputs SPI-compatible serial interface Identification registers: serial number, device ID, user ID Single-supply operation: 3.0 V to 3.6 V Operating temperature range: −40°C to +125°C 15 mm × 24 mm × 15 mm aluminum package, flex connector The ADIS16228 iSensor® is a complete vibration sensing system that combines triaxial acceleration sensing with advanced time domain and frequency domain signal processing. Time domain signal processing includes a programmable decimation filter and selectable windowing function. Frequency domain processing includes a 512-point, real-valued FFT for each axis, along with FFT averaging, which reduces the noise floor variation for finer resolution. The 14-record FFT storage system offers users the ability to track changes over time and capture FFTs with multiple decimation filter settings. The 20.48 kSPS sample rate and 5 kHz flat frequency band provide a frequency response that is suitable for many machine health applications. The aluminum core provides excellent mechanical coupling to the MEMS acceleration sensors. An internal clock drives the data sampling and signal processing system during all operations, which eliminates the need for an external clock source. The data capture function has three modes that offer several options to meet the needs of many different applications. In addition, real-time mode provides direct access to streaming data on one axis. The SPI and data buffer structure provide convenient access to data output. The ADIS16228 also offers a digital temperature sensor and digital power supply measurements. The ADIS16228 is available in a 15 mm × 24 mm × 15 mm module with flanges, machine screw holes (M2 or 2-56), and a flexible connector that enables simple user interface and installation. It has an extended operating temperature range of −40°C to +125°C. APPLICATIONS Vibration analysis Condition monitoring Machine health Instrumentation, diagnostics Safety shutoff sensing FUNCTIONAL BLOCK DIAGRAM DIO1 DIO2 RST INPUT/ OUTPUT ADIS16228 VDD ALARMS POWER MANAGEMENT GND CS TRIAXIAL MEMS SENSOR CONTROL REGISTERS CONTROLLER SCLK SPI PORT TEMP SENSOR CAPTURE BUFFER RECORD STORAGE OUTPUT REGISTERS DIN DOUT 10069-001 ADC FILTER WINDOW FFT SUPPLY Figure 1. Rev. F Document Feedback Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective owners. One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. Tel: 781.329.4700 ©2011–2018 Analog Devices, Inc. All rights reserved. Technical Support www.analog.com ADIS16228 Data Sheet TABLE OF CONTENTS Features .............................................................................................. 1 Alarm Definition ........................................................................ 18 Applications ....................................................................................... 1 Alarm Indicator Signals ............................................................. 19 General Description ......................................................................... 1 Alarm Flags and Conditions ..................................................... 19 Functional Block Diagram .............................................................. 1 Alarm Status ................................................................................ 20 Revision History ............................................................................... 3 Worst-Case Condition Monitoring.......................................... 20 Specifications..................................................................................... 4 Reading Output Data ..................................................................... 21 Timing Specifications .................................................................. 5 Reading Data from the Data Buffer ......................................... 21 Absolute Maximum Ratings............................................................ 6 Accessing FFT Record Data ...................................................... 21 ESD Caution .................................................................................. 6 Data Format ................................................................................ 22 Pin Configuration and Function Descriptions ............................. 7 Real-Time Data Collection ....................................................... 22 Theory of Operation ........................................................................ 8 Power Supply/Temperature ....................................................... 22 Sensing Element ........................................................................... 8 FFT Event Header ...................................................................... 23 Signal Processing .......................................................................... 8 System Tools .................................................................................... 24 User Interface ................................................................................ 8 Global Commands ..................................................................... 24 Basic Operation................................................................................. 9 Status/Error Flags ....................................................................... 24 SPI Write Commands .................................................................. 9 Power-Down ............................................................................... 24 SPI Read Commands ................................................................... 9 Operation Managment .............................................................. 25 Data Recording and Signal Processing ........................................ 12 Input/Output Functions ............................................................ 25 Recording Mode ......................................................................... 12 Self-Test ....................................................................................... 26 Spectral Record Production ...................................................... 13 Flash Memory Management ..................................................... 26 Sample Rate/Filtering ................................................................. 13 Device Identification.................................................................. 26 Dynamic Range/Sensitivity ....................................................... 15 Applications Information .............................................................. 27 Pre-FFT Windowing .................................................................. 16 Mating Connector ...................................................................... 27 FFT ............................................................................................... 17 Breakout Board ........................................................................... 27 Recording Times......................................................................... 17 PC-Based Evaluation Tools ....................................................... 27 Data Records ............................................................................... 17 Outline Dimensions ....................................................................... 29 FFT Record Flash Endurance ................................................... 17 Ordering Guide .......................................................................... 29 Spectral Alarms ............................................................................... 18 Rev. F | Page 2 of 29 Data Sheet ADIS16228 REVISION HISTORY 4/2018—Rev. E to Rev. F Changes to Figure 4........................................................................... 7 Deleted Interface Board Section, Flex Connector Care Section, Figure 25, and Figure 27; Renumbered Sequentially ..................27 Added Breakout Board Section, PC-Based Evaluation Tools Section, and Figure 26; Renumbered Sequentially .....................27 Added Figure 27 ..............................................................................28 Changes to Ordering Guide ...........................................................29 8/2015—Rev. D to Rev. E Added Axial Definitions Section and Figure 19; Renumbered Sequentially ......................................................................................15 Change to Scale Adjustment Section ............................................16 Change to Self-Test Section ...........................................................26 2/2014—Rev. C to Rev. D Moved Revision History ................................................................... 3 Change to Offset Temperature Coefficient Parameter, Table 1 .. 4 Changes to Figure 14 ......................................................................13 Changes to FFT Section, Table 19, and Table 20 .........................17 Added Flex Connector Care Section ............................................27 8/2013—Rev. B to Rev. C Changes to FFT Averaging Section .............................................. 16 3/2012—Rev. A to Rev. B Changes to Recording Times Section and Table 21 ................... 16 Changes to Interface Board Section ............................................. 26 8/2011—Rev. 0 to Rev. A Changes to General Description ..................................................... 1 Changes to Output Noise and Bandwidth Parameters, Table 1 .. 3 Added CAL_ENABLE Register to Table 8 ................................... 10 Changes to Real-Time Mode Section; Changes to Table 11; Change to Figure 14 ........................................................................ 12 Changes to Figure 15 ...................................................................... 13 Change to Dynamic Range Settings Section ............................... 15 Added Dynamic Range/Sensitivity Section; Added Table 13, Renumbered Sequentially; Added Figure 16, Figure 17, and Figure 18, Renumbered Sequentially............................................ 14 Changes to Recording Times Section........................................... 16 Changes to Figure 20 and Figure 21 ............................................. 20 Changes to Table 49, Table 50, and Table 51; Change to Real-Time Data Collection Section .............................................. 21 Change to Power-Down Section ................................................... 23 7/2011—Revision 0: Initial Version Rev. F | Page 3 of 29 ADIS16228 Data Sheet SPECIFICATIONS TA = −40°C to +125°C, VDD = 3.3 V, unless otherwise noted. Table 1. Parameter ACCELEROMETERS Measurement Range 1 Sensitivity, FFT Sensitivity, Time Domain Sensitivity Error Nonlinearity Cross-Axis Sensitivity Alignment Error Offset Error Offset Temperature Coefficient Output Noise Output Noise Density Bandwidth Sensor Resonant Frequency LOGIC INPUTS 3 Input High Voltage, VINH Input Low Voltage, VINL Logic 1 Input Current, IINH Logic 0 Input Current, IINL All Except RST RST Input Capacitance, CIN DIGITAL OUTPUTS3 Output High Voltage, VOH Output Low Voltage, VOL FLASH MEMORY Endurance 4 Data Retention 5 START-UP TIME 6 Initial Startup Reset Recovery 7 Sleep Mode Recovery CONVERSION RATE Clock Accuracy POWER SUPPLY Power Supply Current Test Conditions/Comments Min TA = 25°C TA = 25°C, 0 g to 20 g range setting TA = 25°C TA = 25°C With respect to full scale ±18 Typ 0.3052 0.6104 ±6 ±0.2 2.6 1.5 ±1 2 12 0.248 840 5000 5.5 With respect to package TA = 25°C TA = 25°C, 20.48 kHz sample rate, time domain TA = 25°C, 10 Hz to 1 kHz ±5% flatness, 2 CAL_ENABLE[4] = 0, see Figure 17 ±5% flatness,2 CAL_ENABLE[4] = 1, see Figure 18 Max ±1.25 2.0 VIH = 3.3 V VIL = 0 V ±0.2 −40 −1 10 ISOURCE = 1.6 mA ISINK = 1.6 mA 0.8 ±1 −60 2.4 0.4 TJ = 85°C, see Figure 24 10,000 20 RST pulse low or GLOB_CMD[7] = 1 REC_CTRL1[11:8] = 0x1 (SR0 sample rate selection) Operating voltage range, VDD Record mode, TA = 25°C Sleep mode, TA = 25°C 3.0 Unit g mg/LSB mg/LSB % % % Degrees g mg/°C mg rms mg/√Hz Hz Hz kHz V V µA µA mA pF V V Cycles Years 202 54 2.3 20.48 3 3.3 40 230 3.6 48 ms ms ms kSPS % V mA µA The maximum range depends on the frequency of vibration. Assumes that frequency flatness calibration is enabled. 3 The digital input/output signals are 5 V tolerant. 4 Endurance is qualified as per JEDEC Standard 22, Method A117 and measured at −40°C, +25°C, +85°C, and +125°C. 5 Retention lifetime equivalent at junction temperature (TJ) = 85°C as per JEDEC Standard 22, Method A117. Retention lifetime depends on junction temperature. 6 The start-up times presented reflect the time it takes for data collection to begin. 7 The RST pin must be held low for at least 15 ns. 1 2 Rev. F | Page 4 of 29 Data Sheet ADIS16228 TIMING SPECIFICATIONS TA = 25°C, VDD = 3.3 V, unless otherwise noted. Table 2. Parameter fSCLK tSTALL tCS tDAV tDSU tDHD tSR tSF tDF, tDR tSFS 1 Description SCLK frequency Stall period between data, between 16th and 17th SCLK Chip select to SCLK edge DOUT valid after SCLK edge DIN setup time before SCLK rising edge DIN hold time after SCLK rising edge SCLK rise time SCLK fall time DOUT rise/fall times CS high after SCLK edge Min 1 0.01 16.5 48.8 Typ Max 2.5 Unit MHz µs ns ns ns ns ns ns ns ns 100 24.4 48.8 12.5 12.5 12.5 5 5 Guaranteed by design, not tested. Timing Diagrams tSR CS tSF tCS tSFS 1 2 3 4 5 6 15 16 SCLK tDAV MSB DB14 DB13 tDSU DIN R/W A6 DB12 DB11 A4 A3 DB10 DB2 DB1 LSB tDHD A5 A2 D2 D1 10069-002 DOUT LSB Figure 2. SPI Timing and Sequence tSTALL 10069-003 CS SCLK Figure 3. DIN Bit Sequence Rev. F | Page 5 of 29 ADIS16228 Data Sheet ABSOLUTE MAXIMUM RATINGS Table 4. Package Characteristics Table 3. Parameter Acceleration Any Axis, Unpowered Any Axis, Powered VDD to GND Digital Input Voltage to GND Digital Output Voltage to GND Analog Inputs to GND Temperature Operating Temperature Range Storage Temperature Range Rating Package Type 15-Lead Module 2000 g 2000 g −0.3 V to +6.0 V −0.3 V to +5.3 V −0.3 V to +3.6 V −0.3 V to +3.6 V ESD CAUTION −40°C to +125°C −65°C to +150°C Stresses at or above those listed under Absolute Maximum Ratings may cause permanent damage to the product. This is a stress rating only; functional operation of the product at these or any other conditions above those indicated in the operational section of this specification is not implied. Operation beyond the maximum operating conditions for extended periods may affect product reliability. Rev. F | Page 6 of 29 θJA 31°C/W θJC 11°C/W Device Weight 6.5 grams Data Sheet ADIS16228 PIN CONFIGURATION AND FUNCTION DESCRIPTIONS PIN 1 PIN 15 PIN 15 BOTTOM VIEW TOP VIEW NOTES 1. THE LEADS ARE LOCATED ON THE BOTTOM SIDE OF THE FLEXIBLE CABLE. 2. THE LEAD FINISH IS IMMERSION GOLD OVER THE ELECTROLESS NICKEL. 3. THE THICKNESS OF THE GOLD FINISH IS BETWEEN 0.035µm AND 0.150µm. 4. PACKAGE IS NOT SUITABLE FOR SOLDER REFLOW ASSEMBLY PROCESSES. 5. EXAMPLE MATING CONNECTOR: AVX CORPORATION FLAT FLEXIBLE CONNECTOR (FFC) P/N: 04-6288-015-000-846. 10069-004 PIN 1 Figure 4. Pin Configuration Table 5. Pin Function Descriptions Pin No. 1, 2 3, 4, 5, 8 6, 9 7 10 11 12 Mnemonic VDD GND DNC DIO2 RST DIN DOUT Type 1 S S N/A I/O I I O 13 14 15 SCLK CS DIO1 I I I/O 1 Description Power Supply, 3.3 V. Ground. No Connect. Do not connect to these pins. Digital Input/Output Line 2. Reset, Active Low. SPI, Data Input. SPI, Data Output. DOUT is an output when CS is low. When CS is high, DOUT is in a three-state, high impedance mode. SPI, Serial Clock. SPI, Chip Select. Digital Input/Output Line 1. S is supply, N/A is not applicable, I/O is input/output, I is input, and O is output. Rev. F | Page 7 of 29 ADIS16228 Data Sheet THEORY OF OPERATION CAPTURE BUFFER TRIAXIAL MEMS SENSOR TEMP SENSOR ADC SENSING ELEMENT ANCHOR MOVABLE FRAME FIXED PLATES UNIT FORCING CELL ANCHOR DIN DOUT CLOCK Figure 6. Simplified Sensor Signal Processing Block Diagram USER INTERFACE SPI Interface The user registers (which include both the output registers and the control registers, as shown in Figure 6) manage user access to both sensor data and configuration inputs. Each 16-bit register has its own unique bit assignment and two addresses: one for its upper byte and one for its lower byte. Table 8 provides a memory map for each register, along with its function and lower byte address. The data collection and configuration command uses the SPI, which consists of four wires. The chip select (CS) signal activates the SPI interface, and the serial clock (SCLK) synchronizes the serial data lines. Input commands clock into the DIN pin, one bit at a time, on the SCLK rising edge. Output data clocks out of the DOUT pin on the SCLK falling edge. When the SPI is used as a slave device, the DOUT contents reflect the information requested using a DIN command. Figure 5. MEMS Sensor Diagram SIGNAL PROCESSING The user registers provide addressing for all input/output operations in the SPI interface. The control registers use a dual-memory structure. The controller uses SRAM registers for normal operation, including user-configuration commands. The flash memory provides nonvolatile storage for control registers that have flash backup (see Table 8). Storing configuration data in the flash memory requires a manual flash update command (GLOB_CMD[6] = 1, DIN = 0xBE40). When the device powers on or resets, the flash memory contents load into the SRAM and the device starts producing data according to the configuration in the control registers. Figure 6 offers a simplified block diagram for the ADIS16228. The signal processing stage includes time domain data capture, digital decimation/filtering, windowing, FFT analysis, FFT averaging, and record storage. See Figure 14 for more details on the signal processing operation. MANUAL FLASH BACKUP NONVOLATILE FLASH MEMORY (NO SPI ACCESS) VOLATILE SRAM SPI ACCESS START-UP RESET Figure 7. SRAM and Flash Memory Diagram Rev. F | Page 8 of 29 10069-007 UNIT SENSING CELL MOVING PLATE SCLK Dual-Memory Structure 10069-005 ACCELERATION PLATE CAPACITORS CONTROL REGISTERS CS 10069-006 CONTROLLER Digital vibration sensing in the ADIS16228 starts with a MEMS accelerometer core on each axis. Accelerometers translate linear changes in velocity into a representative electrical signal, using a micromechanical system like the one shown in Figure 5. The mechanical part of this system includes two different frames (one fixed, one moving) that have a series of plates to form a variable, differential capacitive network. When experiencing the force associated with gravity or acceleration, the moving frame changes its physical position with respect to the fixed frame, which results in a change in capacitance. Tiny springs tether the moving frame to the fixed frame and govern the relationship between acceleration and physical displacement. A modulation signal on the moving plate feeds through each capacitive path into the fixed frame plates and into a demodulation circuit, which produces the electrical signal that is proportional to the acceleration acting on the device. SPI SIGNALS OUTPUT REGISTERS SPI PORT The ADIS16228 is a vibration sensing system that combines a triaxial MEMS accelerometer with advanced signal processing. The SPI-compatible port and user register structure provide convenient access to frequency domain vibration data and many user controls. Data Sheet ADIS16228 BASIC OPERATION 15 14 CS SCLK 13 SCLK MOSI 11 DIN MISO 12 DOUT IRQ2 7 DIO2 IRQ1 15 DIO1 4 5 8 6 5 4 3 2 1 DIN Figure 10. SPI Sequence for Manual Capture Start (DIN = 0xBF08) SPI READ COMMANDS A single register read requires two 16-bit SPI cycles that also use the bit assignments that are shown in Figure 12. The first sequence sets R/W = 0 and communicates the target address (Bits[A6:A0]). Bits[D7:D0] are don’t care bits for a read DIN sequence. DOUT clocks out the requested register contents during the second sequence. The second sequence can also use DIN to set up the next read. Figure 11 provides a signal diagram for all four SPI signals while reading the PROD_ID. In this diagram, DIN = 0x5600 and DOUT reflects the decimal equivalent of 16,228. The ADIS16228 SPI interface supports full duplex serial communication (simultaneous transmit and receive) and uses the bit sequence shown in Figure 12. Table 7 provides a list of the most common settings that require attention to initialize a processor serial port for the ADIS16228 SPI interface. Table 7. Generic Master Processor SPI Settings Description The ADIS16228 operates as a slave. Bit rate setting. Clock polarity/phase (CPOL = 1, CPHA = 1). Bit sequence. Shift register/data length. CS SCLK DIN DOUT DOUT = 0011 1111 0110 0100 = 0x3F64 = 16,228 = PROD_ID Figure 11. Example SPI Read, PROD_ID, Second Sequence CS SCLK R/W DB15 A6 A5 A4 A3 A2 A1 DB14 DB13 DB12 DB11 DB10 DB9 A0 D7 D6 D5 D4 D3 D2 D1 D0 DB8 DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 NOTES 1. DOUT BITS ARE BASED ON THE PREVIOUS 16-BIT SEQUENCE (R/W = 0). Figure 12. Example SPI Read Sequence Rev. F | Page 9 of 29 R/W DB15 A6 A5 DB14 DB13 10069-012 DIN DOUT 0 LOWER BYTE SCLK Function Slave select Serial clock Master output, slave input Master input, slave output Interrupt request inputs (optional) MSB First 16-Bit 7 CS Table 6. Generic Master Processor Pin Names and Functions Processor Setting Master SCLK Rate ≤ 2.5 MHz SPI Mode 3 8 User control registers govern many internal operations. The DIN bit sequence in Figure 12 provides the ability to write to these registers, one byte at a time. Some configuration changes and functions require only one write cycle. For example, set GLOB_CMD[11] = 1 (DIN = 0xBF08) to start a manual capture sequence. The manual capture starts immediately after the last bit clocks into DIN (16th SCLK rising edge). Other configurations may require writing to both bytes. ADIS16228 Figure 8. Electrical Hook-Up Diagram Pin Name SS SCLK MOSI MISO IRQ1, IRQ2 9 SPI WRITE COMMANDS 2 3 10 10069-010 SS 11 Figure 9. Generic Register Bit Definitions 10069-008 SYSTEM PROCESSOR SPI MASTER 12 10069-011 1 13 UPPER BYTE I/O LINES ARE COMPATIBLE WITH 3.3V 3.3V OR 5V LOGIC LEVELS VDD 14 10069-009 Table 8 provides a list of user registers with their lower byte addresses. Each register consists of two bytes that each has its own unique 7-bit address. Figure 9 relates the bits of each register to their upper and lower addresses. The ADIS16228 uses a SPI for communication, which enables a simple connection with a compatible, embedded processor platform, as shown in Figure 8. The factory default configuration for DIO1 provides a busy indicator signal that transitions low when an event completes and data is available for user access. Use the DIO_CTRL register (see Table 66) to reconfigure DIO1 and DIO2, if necessary. ADIS16228 Data Sheet Table 8. User Register Memory Map Register Name FLASH_CNT X_SENS Y_SENS Z_SENS TEMP_OUT SUPPLY_OUT FFT_AVG1 FFT_AVG2 BUF_PNTR REC_PNTR X_BUF Y_BUF Z_BUF REC_CTRL1 REC_CTRL2 REC_PRD ALM_F_LOW ALM_F_HIGH ALM_X_MAG1 ALM_Y_MAG1 ALM_Z_MAG1 ALM_X_MAG2 ALM_Y_MAG2 ALM_Z_MAG2 ALM_PNTR ALM_S_MAG ALM_CTRL DIO_CTRL GPIO_CTRL AVG_CNT DIAG_STAT GLOB_CMD ALM_X_STAT ALM_Y_STAT ALM_Z_STAT ALM_X_PEAK ALM_Y_PEAK ALM_Z_PEAK TIME_STAMP_L TIME_STAMP_H Reserved LOT_ID1 LOT_ID2 PROD_ID SERIAL_NUM USER_ID REC_FLSH_CNT Reserved Reserved Reserved Reserved Access Read only Read/write Read/write Read/write Read only Read only Read/write Read/write Read/write Read/write Read only Read only Read only Read/write Read/write Read/write Read/write Read/write Read/write Read/write Read/write Read/write Read/write Read/write Read/write Read/write Read/write Read/write Read/write Read/write Read only Write only Read only Read only Read only Read only Read only Read only Read only Read only N/A Read only Read only Read only Read only Read/write Read only N/A N/A N/A N/A Flash Backup Yes Yes Yes Yes No No Yes Yes No No No No No Yes Yes Yes N/A N/A N/A N/A N/A N/A N/A N/A Yes Yes Yes Yes Yes Yes No No N/A N/A N/A N/A N/A N/A N/A N/A N/A Yes Yes Yes Yes Yes No N/A N/A N/A N/A Address 0x00 0x02 0x04 0x06 0x08 0x0A 0x0C 0x0E 0x10 0x12 0x14 0x16 0x18 0x1A 0x1C 0x1E 0x20 0x22 0x24 0x26 0x28 0x2A 0x2C 0x2E 0x30 0x32 0x34 0x36 0x38 0x3A 0x3C 0x3E 0x40 0x42 0x44 0x46 0x48 0x4A 0x4C 0x4E 0x50 0x52 0x54 0x56 0x58 0x5C 0x5E 0x62 0x64 0x66 0x68 Default N/A N/A N/A N/A 0x8000 0x8000 0x0108 0x0101 0x0000 0x0000 0x8000 0x8000 0x8000 0x1100 0x00FF 0x0000 0x0000 0x0000 0x0000 0x0000 0x0000 0x0000 0x0000 0x0000 0x0000 0x0000 0x0080 0x000F 0x0000 0x9630 0x0000 N/A 0x0000 0x0000 0x0000 0x0000 0x0000 0x0000 0x0000 0x0000 N/A N/A N/A 0x3F64 N/A 0x0000 N/A N/A N/A N/A N/A Function Status, flash memory write count X-axis accelerometer scale correction Y-axis accelerometer scale correction Z-axis accelerometer scale correction Output, temperature during capture Output, power supply during capture Control, FFT average size of 1, SR0 and SR1 Control, FFT average size of 2, SR2 and SR3 Control, buffer address pointer Control, record address pointer Output, buffer for x-axis acceleration data Output, buffer for y-axis acceleration data Output, buffer for z-axis acceleration data Control, Record Control Register 1 Control, Record Control Register 2 Control, record period (automatic mode) Alarm, spectral band lower frequency limit Alarm, spectral band upper frequency limit Alarm, x-axis, Alarm Trigger Level 1 (warning) Alarm, y-axis, Alarm Trigger Level 1 (warning) Alarm, z-axis, Alarm Trigger Level 1 (warning) Alarm, x-axis, Alarm Trigger Level 2 (fault) Alarm, y-axis, Alarm Trigger Level 2 (fault) Alarm, z-axis, Alarm Trigger Level 2 (fault) Alarm, spectral alarm band pointer Alarm, system alarm level Alarm, configuration Control, functional input/output configuration Control, general-purpose input/output Control, average count for sample rate options Status, system error flags Control, global command register Alarm, x-axis, status for spectral alarm bands Alarm, y-axis, status for spectral alarm bands Alarm, z-axis, status for spectral alarm bands Alarm, x-axis, peak value (most severe alarm) Alarm, y-axis, peak value (most severe alarm) Alarm, z-axis, peak value (most severe alarm) Record time stamp, lower word Record time stamp, upper word N/A Lot identification code Lot identification code Product identifier; convert to decimal = 16,228 Serial number User identification register Record flash write/erase counter N/A N/A N/A N/A Rev. F | Page 10 of 29 Reference See Table 68 See Table 16 See Table 17 See Table 18 See Table 56 See Table 54 See Table 19 See Table 20 See Table 47 See Table 48 See Table 49 See Table 50 See Table 51 See Table 9 See Table 14 See Table 10 See Table 28 See Table 29 See Table 30 See Table 31 See Table 32 See Table 33 See Table 34 See Table 35 See Table 27 See Table 36 See Table 26 See Table 66 See Table 67 See Table 11 See Table 65 See Table 64 See Table 37 See Table 38 See Table 39 See Table 40 See Table 41 See Table 42 See Table 61 See Table 62 See Table 69 See Table 70 See Table 71 See Table 72 See Table 73 See Table 24 Data Sheet Register Name Reserved Reserved REC_INFO1 ALM_X_FREQ ALM_Y_FREQ ALM_Z_FREQ REC_INFO2 REC_CNTR CAL_ENABLE ADIS16228 Access N/A N/A Read only Read only Read only Read only Read only Read only Read/write Flash Backup N/A N/A N/A N/A N/A N/A N/A No Yes Address 0x6A 0x6C 0x6E 0x70 0x72 0x74 0x76 0x78 0x7A Default N/A N/A N/A 0x0000 0x0000 0x0000 N/A 0x0000 0x0010 Function N/A N/A Record settings Alarm, x-axis, frequency of most severe alarm Alarm, y-axis, frequency of most severe alarm Alarm, z-axis, frequency of most severe alarm Record settings Record counter Control, frequency calibration enable Rev. F | Page 11 of 29 Reference See Table 59 See Table 43 See Table 44 See Table 45 See Table 60 See Table 22 See Table 13 ADIS16228 Data Sheet DATA RECORDING AND SIGNAL PROCESSING RECORDING MODE The recording mode selection establishes the data type (time or frequency domain), trigger type (manual or automatic), and data collection (captured or real time). The REC_CTRL1[1:0] bits (See Table 9) provide four operating modes: manual FFT, automatic FFT, manual time capture, and real time. After setting REC_CTRL1, the manual FFT, automatic FFT, and manual time capture modes require a start command to start acquiring a spectral or time domain record. There are two start command options in this mode: SPI and input/output. The SPI trigger involves setting GLOB_CMD[11] = 1 (DIN = 0xBF08). The input/output trigger involves using DIO_CTRL (see Table 66) to configure DIO1 or DIO2 as an input trigger line. Table 9. REC_CTRL1 (Base Address = 0x1A), Read/Write Bits [15:14] [13:12] 11 10 9 8 7 [6:4] [3:2] [1:0] Description (Default = 0x1100) Not used (don’t care). Window setting. 00 = rectangular, 01 = Hanning, 10 = flat top, 11 = N/A. SR3, 1 = enabled for FFT, 0 = disable. Sample rate = 20,480 ÷ 2AVG_CNT[15:12] (see Table 11). SR2, 1 = enabled for FFT, 0 = disable. Sample rate = 20,480 ÷ 2AVG_CNT[11:8] (see Table 11). SR1, 1 = enabled for FFT, 0 = disable. Sample rate = 20,480 ÷ 2AVG_CNT[7:4] (see Table 11). SR0, 1 = enabled for FFT, 0 = disable. Sample rate = 20,480 ÷ 2AVG_CNT[3:0] (see Table 11). Power-down between each recording. 1 = enabled. Not used (don’t care). Storage method. 00 = none, 01 = alarm trigger, 10 = all, 11 = N/A. Recording mode. 00 = manual FFT, 01 = automatic FFT, 10 = manual time capture, 11 = real-time sampling/data access. MEMS ADC Manual FFT Mode Set REC_CTRL1[1:0] = 00 to place the device in manual FFT mode. Then use a start command to trigger the production of a spectral record. When the device is acquiring a spectral record, use the busy indicator (DIO1, per factory default) to drive an interrupt service line on an external processor, which can start data collection after the process completes. DIAG_STAT is the only register that the SPI can read while the device is processing a command. Reading this register returns a 0x00 while the device is busy and 0x80 when the data is ready for external access. When the spectral record is complete, the device waits for another start command. Automatic FFT Mode Set REC_CTRL1[1:0] = 01 to place the device in automatic FFT mode. Use the REC_PRD register (see Table 10) to program the period between production of each spectral record. Then use a start command to trigger periodic acquisition of a spectral record. For example, set REC_PRD = 0x020A (DIN = 0x9E0A, 0x9F02) to set the trigger period to 10 hours. Table 10. REC_PRD (Base Address = 0x1E), Read/Write Bits [15:10] [9:8] [7:0] Description (Default = 0x0000) Not used (don’t care) Scale for data bits 00 = 1 second/LSB, 01 = 1 minute/LSB, 10 = 1 hour/LSB Data bits, binary format; range = 0 to 255 Manual Time Capture Mode Set REC_CTRL1[1:0] = 10 to place the device into manual time capture mode; then use a manual trigger to start a data collection cycle. When the device is operating in this mode, 512 samples of time domain data are loaded into the buffer for each axis. This data goes through all time domain signal processing, except the pre-FFT windowing, prior to loading into the data buffer for user access. The manual trigger options are the same as in the manual FFT mode (SPI, input/output). PROCESSING DATA BUFFER RECORDS Figure 13. Simplified Block Diagram Rev. F | Page 12 of 29 SPI AND REGISTERS 10069-023 The ADIS16228 provides a complete sensing system for recording and monitoring vibration data. Figure 13 provides a simplified block diagram for the signal processing associated with spectral record acquisition on all three axes (x, y, z). User registers provide controls for data type (time or frequency), trigger mode (manual or automatic), collection mode (real time or capture), sample rates/filtering, windowing, FFT averaging, spectral alarms, and input/output management. Data Sheet ADIS16228 Real-Time Mode Set REC_CTRL1[1:0] = 11 to place the device into real-time mode. In this mode, the device samples only one axis, at a rate of 20.48 kSPS, and provides data on its output register at the SR0 sample rate setting in AVG_CNT[3:0] (see Table 11). Select the axis of measurement in this mode by reading its assigned register. For example, select the x-axis by reading X_BUF, using DIN = 0x1400. See Table 49, Table 50, or Table 51 for more information on the x_BUF registers. Use DIO1 (Pin 15) to help manage external access to real-time data. For example, this signal is suitable for driving an interrupt line to initiate a service routine in an external processor. SPECTRAL RECORD PRODUCTION The ADIS16228 produces a spectral record by taking a time record of data on all three axes, then scaling, windowing, and performing an FFT process on each time record. This process repeats for a programmable number of FFT averages, with the FFT result of each cycle accumulating in the data buffer. After completing the selected number of cycles, the FFT averaging process completes by scaling the data buffer contents. Then the data buffer contents are available to the SPI and output data registers. SAMPLE RATE/FILTERING more than one sample rate option is enabled while the device is in the automatic FFT mode, the device produces a spectral record for one SRx option, and then waits for the next automatic trigger, which occurs based on the time setting in the REC_PRD register (see Table 10). See Figure 15 for more details on how multiple SRx options influence data collection and spectral record production. When in real-time mode, the output data rate reflects the SR0 setting. Table 12 provides a list of SRx settings available in the AVG_CNT register (see Table 11), along with the resulting sample rates, FFT bin widths, bandwidth, and estimated total noise. Note that each SRx setting also has associated range settings in the REC_CTRL2 register (see Table 14) and the FFT averaging settings that are shown in the FFT_AVG1 and FFT_AVG2 registers (see Table 19 and Table 20, respectively). Table 11. AVG_CNT (Base Address = 0x3A), Read/Write Bits [15:12] [11:8] [7:4] [3:0] The sample rate for each axis is 20.48 kSPS. The internal ADC samples all three axes in a time-interleaving pattern (x1, y1, z1, x2, y2…) that provides even distribution of data across the data record. The averaging/decimating filter provides a control for the final sample rate in the time record. By averaging and decimating the time domain data, this filter provides the ability to focus the spectral record on lower bandwidths, which produces finer frequency resolution in each FFT frequency bin. AVG_CNT (see Table 11) provides the setting for the four different sample rate options in REC_CTRL1[11:8] (SRx, see Table 9). All four options are available when using the manual FFT, automatic FFT, and manual time capture modes. When more than one sample rate option is enabled while the device is in one of the manual modes, the device produces a spectral record for one SRx at a time, starting with the lowest number. After completing the spectral record for one SRx option, the device waits for another start command before producing a spectral record for the next SRx option that is enabled in REC_CTRL1[11:8]. When Description (Default = 0x9630) Sample Rate Option 3, binary (0 to 10), SR3 option sample rate = 20,480 ÷ 2AVG_CNT[15:12] Sample Rate Option 2, binary (0 to 10), SR2 option sample rate = 20,480 ÷ 2AVG_CNT[11:8] Sample Rate Option 1, binary (0 to 10), SR1 option sample rate = 20,480 ÷ 2AVG_CNT[7:4] Sample Rate Option 0, binary (0 to 10), SR0 option sample rate = 20,480 ÷ 2AVG_CNT[3:0] Table 12. Sample Rate Settings and Filter Performance SRx Option 0 1 2 3 4 5 6 7 8 9 10 Rev. F | Page 13 of 29 Sample Rate, fS (SPS) 20,480 10,240 5120 2560 1280 640 320 160 80 40 20 Bin Width (Hz) 40 20 10 5 2.5 1.250 0.625 0.313 0.156 0.078 0.039 Bandwidth (Hz) 10,240 5120 2560 1280 640 320 160 80 40 20 10 Peak Noise per Bin (mg) 5.18 3.66 2.59 1.83 1.29 0.91 0.65 0.46 0.32 0.23 0.16 ADIS16228 Data Sheet FFT RECORDS—NONVOLATILE FLASH MEMORY RANGE-SCALE SETTING Ks= AMAX ÷ 215 AMAX = PEAK FROM REC_CTRL2[7:0] FFT RECORD 0 SENSITIVITY ADJUSTMENT X_SENS, Y_SENS, Z_SENS 20.48kSPS 1 NA WINDOW SETTING REC_CTRL1[13:12] m = REC_CNTR REC_CTRL2[3:2] Na xK K=1 WINDOW ÷N A FFT FFT AVERAGE (NF) FREQUENCY RESPONSE CORRECTION FFT_AVG1, FFT_AVG2 CAL_ENABLE[4] DATA BUFFER Figure 14. Signal Flow Diagram, REC_CTRL1[1:0] = 00 or 01, FFT Analysis Modes X1 Y1 Z1 X2 Y2 Z2 512 SAMPLES FFT1 RECORD 1 SR0 TRIGGER SPI/DIO/TIMER X512 Y512 Z512 PWR2 TEMP2 512 SAMPLES FFT2 512 SAMPLES RECORD 1 SR1 TRIGGER SPI/DIO/TIMER DATA RDY DATA CAPTURE FFTN RECORD 1 SR2 TRIGGER SPI/DIO/TIMER DATA RDY FFT AVG PWR TEMP FFT RECORD AVG AVG RECORD 1 SR3 TRIGGER SPI/DIO/TIMER DATA RDY DATA RDY Figure 15. Spectral Record Production, with All SRx Settings Enabled Rev. F | Page 14 of 29 RECORDS 10069-021 TRIAXIS MEMS ACCEL Ks Ko FFT RECORD 13 SPI REGISTER ACCESS 10069-016 SAMPLE RATE SETTING REC_CTRL1[11:8] FFT RECORD m FFT RECORD 1 Data Sheet ADIS16228 DYNAMIC RANGE/SENSITIVITY 1.4 The range of the ADIS16228 accelerometers depends on the frequency of the vibration. The accelerometers have a selfresonant frequency of 5.5 kHz, and the signal conditioning circuit applies a single-pole, low-pass filter (2.5 kHz) to the response. The self-resonant behavior of the accelerometer influences the relationship between vibration frequency and dynamic range, as shown in Figure 16, which displays the response to peak input amplitudes, assuming a sinusoidal vibration signature at each frequency. The accelerometer resonance and low-pass filter also influence the magnitude response, as shown in Figure 17. 1.3 MAGNITUDE (g) 1.2 1.1 1.0 +3σ 0.9 0.8 MEAN 0.7 Frequency Response Correction 1000 5000 FREQUENCY (Hz) 10069-117 –3σ 0.6 100 Figure 17. Magnitude/Frequency Response (CAL_ENABLE[4] = 0) The CAL_ENABLE register provides an on/off control bit for a magnitude/frequency correction that extends the flatness (5%) of this response up to 5 kHz. Set CAL_ENABLE[4] = 1 (DIN = 0xFA10) to enable this function, which produces a magnitude/frequency response like the one that is shown in Figure 18. Set CAL_ENABLE[4] = 0 to remove this correction, and use a response that reflects the curve that is shown in Figure 17. Note that this operation does not expand the dynamic range of the sensor, but it can simplify the process of setting spectral alarm limits and any other postprocessing routines. 1.1 MAGNITUDE (g) +3σ 1.0 MEAN –3σ Description (Default = 0x00FF) Not used (don’t care) Frequency/flatness calibration enable 1 = enable (see Figure 18) 0 = disable (see Figure 17) Not used (don’t care) [3:0] 0.9 100 1000 Figure 18. Magnitude/Frequency Response (CAL_ENABLE[4] = 1) Axial Definitions Figure 19 describes the axial and polarity definitions for all three accelerometers in the ADIS16228. 20 18 14 aX 18g PEAK RESPONSE 16g PEAK RESPONSE aZ 14g PEAK RESPONSE aY 12 10 10069-100 8 6 Figure 19. Accelerometer Axial and Polarity Definitions 4 2 2g PEAK RESPONSE 0 1000 2000 4000 FREQUENCY (Hz) 5000 6000 10069-116 PEAK MAGNITUDE (g) 16 5000 FREQUENCY (Hz) Figure 16. Peak Magnitude vs. Frequency Rev. F | Page 15 of 29 10069-118 Table 13. CAL_ENABLE (Base Address = 0x7A), Read/Write Bits [15:5] 4 ADIS16228 Data Sheet Dynamic Range Settings Scale Adjustment REC_CTRL2 (see Table 14) provides four range settings that are associated with each sample rate option, SRx. The range options that are referenced in REC_CTRL2 reflect the maximum dynamic range, which occurs at the lower part of the frequency range and does not account for the decrease in range (see Figure 16). For example, set REC_CTRL2[5:4] = 10 (DIN = 0x9C20) to set the peak acceleration (AMAX) to 10 g on the SR2 sample rate option. These settings help optimize FFT precision and sensitivity when monitoring lower magnitude vibrations. For each range setting in Table 14, this stage scales the time domain data so that the maximum value equates to 215 LSBs for time domain data and 216 LSBs for frequency domain data. The x_SENS registers (see Table 16, Table 17, and Table 18) provide a fine-scale adjustment function for each axis. The following equation describes how to use measured and ideal values to calculate the scale factor for each register in LSBs: Note that the maximum range for each setting is 1 LSB smaller than the listed maximum. For example, the maximum number of codes in the frequency domain analysis is 216 − 1, or 65,535. For example, when using a range setting of 1 g in one of the FFT modes, the maximum measurement is equal to 1 g times 216 − 1, divided by 216. See Table 15 for the resolution associated with each setting and Figure 14 for the location of this operation in the signal flow diagram. The real-time mode automatically uses the 20 g range setting. Table 14. REC_CTRL2 (Base Address = 0x1C), Read/Write Bits [15:8] [7:6] [5:4] [3:2] [1:0] Description (Default = 0x00FF) Not used (don’t care) Measurement range, SR3 00 = 1 g, 01 = 5 g, 10 = 10 g, 11 = 20 g Measurement range, SR2 00 = 1 g, 01 = 5 g, 10 = 10 g, 11 = 20 g Measurement range, SR1 00 = 1 g, 01 = 5 g, 10 = 10 g, 11 = 20 g Measurement range, SR0 00 = 1 g, 01 = 5 g, 10 = 10 g, 11 = 20 g Table 15. Range Settings and LSB Weights Range Setting (g) (REC_CTRL2[5:4]) 0 to 1 0 to 5 0 to 10 0 to 20 Time Mode (mg/LSB) 0.0305 0.1526 0.3052 0.6104 FFT Mode (mg/LSB) 0.0153 0.0763 0.1526 0.3052 SCFx = a XI  a XM × 218 − 1  where: aXI is the ideal x-axis value. aXM is the actual x-axis measurement. These registers contain correction factors, which come from the factory calibration process. The calibration process records accelerometer output in four different orientations and computes the correction factors for each register. These registers also provide write access for in-system adjustment. Gravity provides a common stimulus for this type of correction process. Use both +1 g and −1 g orientations to reduce the effect of offset on this measurement. In this case, the ideal measurement is 2 g, and the measured value is the difference of the accelerometer measurements at +1 g and −1 g orientations. The factory-programmed values are stored in flash memory and are restored by setting GLOB_CMD[3] = 1 (DIN = 0xBE08) (see Table 64). Table 16. X_SENS (Base Address = 0x02), Read/Write Bits [15:0] Description (Default = N/A) X-axis scale correction factor (SCFx), twos complement Table 17. Y_SENS (Base Address = 0x04), Read/Write Bits [15:0] Description (Default = N/A) Y-axis scale correction factor (SCFy), twos complement Table 18. Z_SENS (Base Address = 0x06), Read/Write Bits [15:0] Description (Default = N/A) Z-axis scale correction factor (SCFz), twos complement PRE-FFT WINDOWING REC_CTRL1[13:12] provide three options for pre-FFT windowing of time data. For example, set REC_CTRL1[13:12] = 01 to use the Hanning window, which offers the best amplitude resolution of the peaks between frequency bins and minimal broadening of peak amplitudes. The rectangular and flat top windows are also available because they are common windowing options for vibration monitoring. The flat top window provides accurate amplitude resolution with a trade-off of broadening the peak amplitudes. Rev. F | Page 16 of 29 Data Sheet ADIS16228 FFT The FFT process converts each 512-sample time record into a 256-point spectral record that provides magnitude vs. frequency data. Each FFT result loads into an accumulator stage that averages multiple FFT results for the FFT record. FFT Averaging FFT_AVG1 (Table 19) and FFT_AVG2 (Table 20) contain userconfigurable settings for the total number of FFT results in each record. Each byte contains a binary number that sets the number of averages for a particular sample rate setting (SR0 to SR3, per AVG_ CNT register, Table 11). For example, set FFT_AVG1[15:8] = 0x0B (DIN = 0x8D0B) to set the total number of averages for the SR1 setting to 11. The default setting for the SR0 sample rate causes an average of 8 FFT results for one FFT record. The default settings for SR1, SR2, and SR3 cause each FFT to contain only one FFT result (no averaging). Table 19. FFT_AVG1 (Base Address = 0x0C), Read/Write Bits [15:8] [7:0] Description (Default = 0x0108) Number of FFT results (NF in Figure 14) in a FFT record, for sample rate SR1 range = 1 to 255, binary format Number of FFT results (NF in Figure 14) in a FFT record, for sample rate SR0 range = 1 to 255, binary format Table 20. FFT_AVG2 (Base Address = 0x0E), Read/Write Bits [15:8] [7:0] Description (Default = 0x0101) Number of FFT results (NF in Figure 14) in a FFT record, for sample rate SR3 range = 1 to 255, binary format Number of FFT results (NF in Figure 14) in a FFT record, for sample rate SR2. range = 1 to 255, binary format RECORDING TIMES When using automatic FFT mode, the automatic recording period (REC_PRD) must be greater than the total recording time. Use the following equations to calculate the recording time: Manual time mode tR = tS + tPT + tST + tAST tS = (512/20480) × 2AVG_CNT Note that the AVG_CNT variable in this relationship refers to the decimal equivalent of the applicable nibble in the AVG_CNT register (See Table 11). FFT modes tR = NF × (tS + tPT + tFFT) + tST + tAST Table 21 provides a list of the processing times and settings that are used in these equations. Table 21. Typical Processing Times Function Processing Time, tPT FFT Time, tFFT Number of FFT Averages, NF Storage Time, tST Alarm Scan Time, tAST Time (ms) 18.7 32.7 Per FFT_AVG1, FFT_AVG2 120.0 2.21 The storage time (tST) applies only when a storage method is selected in REC_CTRL1[3:2] (see Table 9 for more details about the record storage settings). The alarm scan time (tAST) applies only when the alarms are enabled in ALM_CTRL[4:0] (see Table 26 for more information). Understanding the recording time helps predict when data is available, for systems that cannot use DIO1 to monitor the status of these operations. Note that when using automatic FFT mode, the automatic recording period (REC_PRD) must be greater than the total recording time. DATA RECORDS After the ADIS16228 finishes processing FFT data, it stores the data into the data buffer, where it is available for external access using the SPI and x_BUF registers (see Table 49 to Table 51). REC_CTRL1[3:2] (see Table 9) provides programmable conditions for writing buffer data into the FFT records, which are in nonvolatile flash memory locations. Set REC_CTRL1[3:2] = 01 to store data buffer data into the flash memory records only when an alarm condition is met. Set REC_CTRL1[3:2] = 10 to store every set of FFT data into the flash memory locations. The flash memory record provides space for a total of 14 records. Each record stored in flash memory contains a header and frequency domain (FFT) data from all three axes (x, y, and z). When all 14 records are full, new records do not load into the flash memory. The REC_CNTR register (see Table 22) provides a running count for the number of records that are stored. Set GLOB_CMD[8] = 1 (DIN = 0xBF01) to clear all of the records in flash memory. Table 22. REC_CNTR (Base Address = 0x78), Read Only Bits [15:5] [4:0] Description (Default = 0x0000) Not used Total number of records taken; range = 0 to 14, binary When used in conjunction with automatic trigger mode and record storage, FFT analysis for each sample rate option requires no additional inputs. Depending on the number of FFT averages, the time between each sample rate selection may be quite large. Note that selecting multiple sample rates reduces the number of records available for each sample rate setting, as shown in Table 23. Table 23. Available Records per Sample Rate Selected Number of Sample Rates Selected 1 2 3 4 Available Records 14 7 4 3 FFT RECORD FLASH ENDURANCE The REC_FLSH_CNT register (see Table 24) increments when all 14 records contain FFT data. Table 24. REC_FLSH_CNT (Base Address = 0x5E), Read Only Bits [15:0] Rev. F | Page 17 of 29 Description Flash write cycle count; record data only, binary ADIS16228 Data Sheet SPECTRAL ALARMS Address 0x20 0x22 0x24 0x26 0x28 0x2A 0x2C 0x2E 0x30 0x32 0x34 0x3C 0x40 0x42 0x44 0x46 0x48 0x4A 0x70 0x72 0x74 Description Alarm frequency band, lower limit Alarm frequency band, upper limit X-Axis Alarm Trigger Level 1 (warning) Y-Axis Alarm Trigger Level 1 (warning) Z-Axis Alarm Trigger Level 1 (warning) X-Axis Alarm Trigger Level 2 (fault) Y-Axis Alarm Trigger Level 2 (fault) Z-Axis Alarm Trigger Level 2 (fault) Alarm pointer System alarm trigger level Alarm configuration Alarm status X-axis alarm status Y-axis alarm status Z-axis alarm status X-axis alarm peak Y-axis alarm peak Z-axis alarm peak X-axis alarm frequency of peak alarm Y-axis alarm frequency of peak alarm Z-axis alarm frequency of peak alarm The ALM_CTRL register (see Table 26) provides control bits that enable the spectral alarms of each axis, configures the system alarm, sets the record delay for the spectral alarms, and configures the clearing function for the DIAG_STAT error flags (see Table 65). Table 26. ALM_CTRL (Base Address = 0x34), Read/Write Bits [15:12] [11:8] 7 6 5 4 3 2 1 0 Description (Default = 0x0080) Not used. Response delay; range = 0 to 15. Represents the number of spectral records for each spectral alarm before a spectral alarm flag is set high. Latch DIAG_STAT error flags. Requires a clear status command (GLOB_CMD[4]) to reset the flags to 0. 1 = enabled, 0 = disabled. Enable DIO1 as an Alarm 1 output indicator and enable DIO2 as an Alarm 2 output indicator. 1 = enabled. System alarm comparison polarity. 1 = trigger when less than ALM_S_MAG[11:0]. 0 = trigger when greater than ALM_S_MAG[11:0]. System alarm. 1 = temperature, 0 = power supply. Alarm S enable (ALM_S_MAG). 1 = enabled, 0 = disabled. Alarm Z enable (ALM_Z_MAG). 1 = enabled, 0 = disabled. Alarm Y enable (ALM_Y_MAG). 1 = enabled, 0 = disabled. Alarm X enable (ALM_X_MAG). 1 = enabled, 0 = disabled. The alarm function provides six programmable spectral bands, as shown in Figure 20. Each spectral alarm band has lower and upper frequency definitions for all of the sample rate options (SRx). It also has two independent trigger level settings, which are useful for systems that value warning and fault condition indicators. ALM_F_LOW ALM_x_MAG2 ALM_F_HIGH ALM_x_MAG1 1 2 3 4 5 6 FREQUENCY 10069-020 Table 25. Alarm Function Register Summary Register ALM_F_LOW ALM_F_HIGH ALM_X_MAG1 ALM_Y_MAG1 ALM_Z_MAG1 ALM_X_MAG2 ALM_Y_MAG2 ALM_Z_MAG2 ALM_PNTR ALM_S_MAG ALM_CTRL DIAG_STAT ALM_X_STAT ALM_Y_STAT ALM_Z_STAT ALM_X_PEAK ALM_Y_PEAK ALM_Z_PEAK ALM_X_FREQ ALM_Y_FREQ ALM_Z_FREQ ALARM DEFINITION MAGNITUDE The alarm function offers six spectral bands for alarm detection. Each spectral band has high and low frequency definitions, along with two different trigger thresholds (Alarm 1 and Alarm 2) for each accelerometer axis. Table 25 provides a summary of each register used to configure the alarm function. Figure 20. Spectral Band Alarm Setting Example, ALM_PNTR = 0x03 Select the spectral band for configuration by writing its number (1 to 6) to ALM_PNTR[2:0] (see Table 27). Then select the sample rate option using ALM_PNTR[9:8]. This number represents a binary number, which corresponds to the x in the SRx sample rates option associated with REC_CTRL1[11:8] (see Table 9). For example, set ALM_PNTR[7:0] = 0x05 (DIN = 0xB005) to select Alarm Spectral Band 5, and set ALM_PNTR[15:8] = 0x02 (DIN = 0xB102) to select the SR2 sample rate option. Table 27. ALM_PNTR (Base Address = 0x30), Read/Write Bits [15:10] [9:8] [7:3] [2:0] Description (Default = 0x0000) Not used Sample rate option; range = 0 to 3 for SR0 to SR3 Not used Spectral band number; range = 1 to 6 Alarm Band Frequency Definitions After the spectral band and sample rate settings are set, program the lower and upper frequency boundaries by writing their bin numbers to the ALM_F_LOW register (see Table 28) and ALM_F_HIGH register (see Table 29). Use the bin width definitions listed in Table 12 to convert a frequency into a bin number for this definition. Calculate the bin number by dividing the frequency by the bin width that is associated with the sample rate setting. For example, if the sample rate is 5120 Hz and the lower band frequency is 400 Hz, divide that number by the bin width of 10 Hz to arrive at the 40th bin as the lower band setting. Then set ALM_F_LOW[7:0] = 0x28 (DIN = 0xA028) to establish 400 Hz as the lower frequency for the 5120 SPS sample rate setting. Rev. F | Page 18 of 29 Data Sheet ADIS16228 Table 28. ALM_F_LOW (Base Address = 0x20), Read/Write Bits [15:8] [7:0] Description (Default = 0x0000) Not used Lower frequency, bin number; range = 0 to 255 Bits [15:0] Table 29. ALM_F_HIGH (Base Address = 0x22), Read/Write Bits [15:8] [7:0] Description (Default = 0x0000) Not used Upper frequency, bin number; range = 0 to 255 The ALM_x_MAG1 and ALM_x_MAG2 registers (see Table 30 to Table 35) provide two independent trigger settings for all three axes of acceleration data. They use the data format established by the range settings in the REC_CTRL2 register (see Table 14) and recording mode in REC_CTRL1[1:0] (see Table 9). For example, when using the 0 g to 1 g mode for FFT analysis, 32,768 LSB is the closest setting to 500 mg. Therefore, set ALM_Y_MAG2 = 0x8000 (DIN = 0xAD80, 0xAC00) to set the critical alarm to 500 mg, when using the 0 g to 1 g range option in REC_CTRL2 for FFT records. See Table 14 and Table 15 for more information about formatting each trigger level. Note that trigger settings that are associated with Alarm 2 should be greater than the trigger settings for Alarm 1. In other words, the alarm magnitude settings should meet the following criteria: ALM_X_MAG2 > ALM_X_MAG1 ALM_Y_MAG2 > ALM_Y_MAG1 ALM_Z_MAG2 > ALM_Z_MAG1 Description (Default = 0x0000) X-axis Alarm Trigger Level 1, 16-bit unsigned (see Table 14 and Table 15 for the scale factor) Table 31. ALM_Y_MAG1 (Base Address = 0x26), Read/Write Description (Default = 0x0000) Y-axis Alarm Trigger Level 1, 16-bit unsigned (see Table 14 and Table 15 for the scale factor) Table 32. ALM_Z_MAG1 (Base Address = 0x28), Read/Write Bits [15:0] Description (Default = 0x0000) Y-axis Alarm Trigger Level 2, 16-bit unsigned (see Table 14 and Table 15 for the scale factor) Table 35. ALM_Z_MAG2 (Base Address = 0x2E), Read/Write Bits [15:0] Description (Default = 0x0000) Z-axis Alarm Trigger Level 2, 16-bit unsigned (see Table 14 and Table 15 for the scale factor) Table 36. ALM_S_MAG (Base Address = 0x32), Read/Write Bits [15:0] Description (Default = 0x0000) System alarm trigger level, data format matches target from ALM_CTRL[4] Enable Alarm Settings Before configuring the spectral alarm registers, clear their current contents by setting GLOB_CMD[9] = 1 (DIN = 0xBF02). After completing the spectral alarm band definitions, save the settings by setting GLOB_CMD[12] = 1 (DIN = 0xBF10). The device ignores the save command if any of these locations has already been written to. ALARM INDICATOR SIGNALS Table 30. ALM_X_MAG1 (Base Address = 0x24), Read/Write Bits [15:0] Description (Default = 0x0000) X-axis Alarm Trigger Level 2, 16-bit unsigned (see Table 14 and Table 15 for the scale factor) Table 34. ALM_Y_MAG2 (Base Address = 0x2C), Read/Write Bits [15:0] Alarm Trigger Settings Bits [15:0] Table 33. ALM_X_MAG2 (Base Address = 0x2A), Read/Write Description (Default = 0x0000) Z-axis Alarm Trigger Level 1, 16-bit unsigned (see Table 14 and Table 15 for the scale factor) DIO_CTRL[5:2] (see Table 66) and ALM_CTRL[6] (see Table 26) provide controls for establishing DIO1 and DIO2 as dedicated alarm output indicator signals. Use DIO_CTRL[5:2] to select the alarm function for DIO1 and/or DIO2; then set ALM_CTRL[6] = 1 to enable DIO1 to serve as an Alarm 1 indicator and DIO2 as an Alarm 2 indicator. This setting establishes DIO1 to indicate Alarm 1 (warning) conditions and DIO2 to indicate Alarm 2 (critical) conditions. ALARM FLAGS AND CONDITIONS The FFT header (see Table 58) contains both generic alarm flags (DIAG_STAT[13:8]; see Table 65) and spectral band-specific alarm flags (ALM_x_STAT; see Table 37, Table 38, and Table 39). The FFT header also contains magnitude (ALM_x_PEAK; see Table 40, Table 41, and Table 42) and frequency information (ALM_x_FREQ; see Table 43, Table 44, and Table 45) associated with the highest magnitude of vibration content in the record. Rev. F | Page 19 of 29 ADIS16228 Data Sheet ALARM STATUS Table 39. ALM_Z_STAT (Base Address = 0x44), Read Only The ALM_x_STAT registers (see Table 37, Table 38, and Table 39 provide alarm bits for each spectral band on the current sample rate option. Bits 15 14 13 12 11 10 9 8 7 6 5 4 3 [2:0] Table 37. ALM_X_STAT (Base Address = 0x40), Read Only Bits 15 14 13 12 11 10 9 8 7 6 5 4 3 [2:0] Description (Default = 0x0000) Alarm 2 on Band 6; 1 = alarm set, 0 = no alarm Alarm 1 on Band 6; 1 = alarm set, 0 = no alarm Alarm 2 on Band 5; 1 = alarm set, 0 = no alarm Alarm 1 on Band 5; 1 = alarm set, 0 = no alarm Alarm 2 on Band 4; 1 = alarm set, 0 = no alarm Alarm 1 on Band 4; 1 = alarm set, 0 = no alarm Alarm 2 on Band 3; 1 = alarm set, 0 = no alarm Alarm 1 on Band 3; 1 = alarm set, 0 = no alarm Alarm 2 on Band 2; 1 = alarm set, 0 = no alarm Alarm 1 on Band 2; 1 = alarm set, 0 = no alarm Alarm 2 on Band 1; 1 = alarm set, 0 = no alarm Alarm 1 on Band 1; 1 = alarm set, 0 = no alarm Not used Most critical alarm condition, spectral band; range = 1 to 6 Table 38. ALM_Y_STAT (Base Address = 0x42), Read Only Bits 15 14 13 12 11 10 9 8 7 6 5 4 3 [2:0] Description (Default = 0x0000) Alarm 2 on Band 6; 1 = alarm set, 0 = no alarm Alarm 1 on Band 6; 1 = alarm set, 0 = no alarm Alarm 2 on Band 5; 1 = alarm set, 0 = no alarm Alarm 1 on Band 5; 1 = alarm set, 0 = no alarm Alarm 2 on Band 4; 1 = alarm set, 0 = no alarm Alarm 1 on Band 4; 1 = alarm set, 0 = no alarm Alarm 2 on Band 3; 1 = alarm set, 0 = no alarm Alarm 1 on Band 3; 1 = alarm set, 0 = no alarm Alarm 2 on Band 2; 1 = alarm set, 0 = no alarm Alarm 1 on Band 2; 1 = alarm set, 0 = no alarm Alarm 2 on Band 1; 1 = alarm set, 0 = no alarm Alarm 1 on Band 1; 1 = alarm set, 0 = no alarm Not used Most critical alarm condition, spectral band; range = 1 to 6 Description (Default = 0x0000) Alarm 2 on Band 6; 1 = alarm set, 0 = no alarm Alarm 1 on Band 6; 1 = alarm set, 0 = no alarm Alarm 2 on Band 5; 1 = alarm set, 0 = no alarm Alarm 1 on Band 5; 1 = alarm set, 0 = no alarm Alarm 2 on Band 4; 1 = alarm set, 0 = no alarm Alarm 1 on Band 4; 1 = alarm set, 0 = no alarm Alarm 2 on Band 3; 1 = alarm set, 0 = no alarm Alarm 1 on Band 3; 1 = alarm set, 0 = no alarm Alarm 2 on Band 2; 1 = alarm set, 0 = no alarm Alarm 1 on Band 2; 1 = alarm set, 0 = no alarm Alarm 2 on Band 1; 1 = alarm set, 0 = no alarm Alarm 1 on Band 1; 1 = alarm set, 0 = no alarm Not used Most critical alarm condition, spectral band; range = 1 to 6 WORST-CASE CONDITION MONITORING The ALM_x_PEAK registers (see Table 40, Table 41, and Table 42) contain the peak magnitude for the worst-case alarm condition in each axis. The ALM_x_FREQ registers (see Table 43, Table 44, and Table 45) contain the frequency bin number for the worst-case alarm condition. Table 40. ALM_X_PEAK (Base Address = 0x46), Read Only Bits [15:0] Description (Default = 0x0000) Alarm peak, x-axis, accelerometer data format Table 41. ALM_Y_PEAK (Base Address = 0x48), Read Only Bits [15:0] Description (Default = 0x0000) Alarm peak, y-axis, accelerometer data format Table 42. ALM_Z_PEAK (Base Address = 0x4A), Read Only Bits [15:0] Description (Default = 0x0000) Alarm peak, z-axis, accelerometer data format Table 43. ALM_X_FREQ (Base Address = 0x70), Read Only Bits [15:8] [7:0] Description (Default = 0x0000) Not used Alarm frequency for x-axis peak alarm level, FFT bin number; range = 0 to 255 Table 44. ALM_Y_FREQ (Base Address = 0x72), Read Only Bits [15:8] [7:0] Description (Default = 0x0000) Not used Alarm frequency for y-axis peak alarm level, FFT bin number; range = 0 to 255 Table 45. ALM_Z_FREQ (Base Address = 0x74), Read Only Bits [15:8] [7:0] Rev. F | Page 20 of 29 Description (Default = 0x0000) Not used Alarm frequency for z-axis peak alarm level, FFT bin number; range = 0 to 255 Data Sheet ADIS16228 READING OUTPUT DATA The ADIS16228 samples, processes, and stores vibration data from three axes (x, y, and z) into the data buffer and FFT records (if selected). In manual time capture mode, the record for each axis contains 512 samples. In manual and automatic FFT mode, each record contains the 256-point FFT result for each accelerometer axis. Table 46 provides a summary of registers that provide access to processed sensor data. DATA IN BUFFERS LOAD INTO USER OUTPUT REGISTERS X_BUF Z_BUF BUF_PNTR X-AXIS Y-AXIS Z-AXIS ACCELEROMETER ACCELEROMETER ACCELEROMETER FFT FFT FFT BUFFER BUFFER BUFFER Table 46. Output Data Registers Description Internal temperature Internal power supply Data buffer index pointer FFT record index pointer X-axis accelerometer buffer Y- axis accelerometer buffer Z- axis accelerometer buffer FFT record retrieve command Time stamp, lower word Time stamp, upper word FFT record header information FFT record header information 256/512 FFT ANALYSIS SUPPLY_OUT INTERNAL SAMPLING SYSTEM SAMPLES, PROCESSES, AND STORES DATA IN FFT BUFFERS. TEMP_OUT 10069-013 Address 0x08 0x0A 0x10 0x12 0x14 0x16 0x18 0x3E 0x4C 0x4E 0x6E 0x76 Figure 21. Data Buffer Structure and Operation Table 47. BUF_PNTR (Base Address = 0x10), Read/Write Bits [15:9] [8:0] READING DATA FROM THE DATA BUFFER After completing a spectral record and updating each data buffer, the ADIS16228 loads the first data sample from each data buffer into the x_BUF registers (see Table 49, Table 50, and Table 51) and sets the buffer index pointer in the BUF_PNTR register (see Table 47) to 0x0000. The index pointer determines which data samples load into the x_BUF registers. For example, writing 0x009F to the BUF_PNTR register (DIN = 0x9100, DIN = 0x909F) causes the 160th sample in each data buffer location to load into the x_BUF registers. The index pointer increments with every x_BUF read command, which causes the next set of capture data to load into each capture buffer register automatically. This enables an efficient method for reading all 256 samples in a record, using sequential read commands, without having to manipulate the BUF_PNTR register. Description (Default = 0x0000) Not used Data bits; range = 0 to 255 (FFT), 0 to 511 (time) ACCESSING FFT RECORD DATA The FFT records can be stored in flash memory. The REC_PNTR register (see Table 48) and GLOB_CMD[13] (see Table 64) provide access to the FFT records, as shown in Figure 22. For example, set REC_PNTR[7:0] = 0x0A (DIN = 0x920A) and GLOB_CMD[13] = 1 (DIN = 0xBF20) to load FFT Record 10 in the FFT buffer for SPI/register access. Table 48. REC_PNTR (Base Address = 0x12), Read/Write Bits [15:4] [3:0] Description (Default = 0x0000) Not used Data bits FFT RECORD 0 FFT RECORD 1 FFT RECORD m FFT RECORD 15 X X X X Y Z FFT HEADER 0 Y Z FFT HEADER 1 m = REC_PNTR GLOB_CMD[13] = 1 Y Z FFT HEADER m DATA BUFFER X, Y, Z FFT HEADER REGISTERS Figure 22. FFT Record Access Rev. F | Page 21 of 29 Y Z FFT HEADER 15 SPI REGISTERS 10069-119 Register TEMP_OUT SUPPLY_OUT BUF_PNTR REC_PNTR X_BUF Y_BUF Z_BUF GLOB_CMD TIME_STAMP_L TIME_STAMP_H REC_INFO1 REC_INFO2 Y_BUF 0 ADIS16228 Data Sheet DATA FORMAT REAL-TIME DATA COLLECTION Table 49, Table 50, and Table 51 list the bit assignments for the x_BUF registers. The acceleration data format depends on the range scale setting in REC_CTRL2 (see Table 14) and the recording mode settings in REC_CTRL1 (see Table 9). Table 52 provides some data formatting examples for the FFT mode, and Table 53 offers some data formatting examples for the 16-bit, twos complement format used in manual time mode. When using real-time mode, select the output channel by reading the associated x_BUF register. For example, set DIN = 0x1600 to select the y-axis sensor for sampling. After selecting the channel, use the data-ready signal to trigger subsequent data reading of the Y_BUF register. In this mode, use the time domain data formatting for a range setting of 20 g, as shown in Table 15. Table 49. X_BUF (Base Address = 0x14), Read Only At the end of each spectral record, the ADIS16228 also measures power supply and internal temperature. It accumulates a 5.12 ms record of power supply measurements at a sample rate of 50 kHz and takes 64 samples of internal temperature data over a period of 1.7 ms. The average of the power supply and internal temperature loads into the SUPPLY_OUT register (see Table 54) and the TEMP_OUT register (see Table 56), respectively. When using real-time mode, these registers update only when this mode starts. Bits [15:0] Description (Default = 0x8000) X-acceleration data buffer register. See Table 15 for scale sensitivity. Format = twos complement (time), binary (FFT). Table 50. Y_BUF (Base Address = 0x16), Read Only Bits [15:0] Description (Default = 0x8000) Y-acceleration data buffer register. See Table 15 for scale sensitivity. Format = twos complement (time), binary (FFT). POWER SUPPLY/TEMPERATURE Table 54. SUPPLY_OUT (Base Address = 0x0A), Read Only Table 51. Z_BUF (Base Address = 0x18), Read Only Bits [15:12] [11:0] Bits [15:0] Table 55. Power Supply Data Format Examples Description (Default = 0x8000) Z-acceleration data buffer register. See Table 15 for scale sensitivity. Format = twos complement (time), binary (FFT). Table 52. FFT Mode, 5 g Range, Data Format Examples Acceleration (mg) 4,999.9237 100 × 5 ÷ 65,536 2 × 5 ÷ 65,536 1 × 5 ÷ 65,536 0 LSB 65,535 100 2 1 0 Hex 0xFFFF 0x0064 0x0002 0x0001 0x0000 Binary 1111 1111 1111 1111 0000 0000 0110 0100 0000 0000 0000 0010 0000 0000 0000 0001 0000 0000 0000 0000 Table 53. Manual Time Mode, 5 g Range, Data Format Examples Acceleration (mg) +4999.847 ~1000 +2 × 5 ÷ 32,768 +1 × 5 ÷ 32,768 0 −1 × 5 ÷ 32,768 −2 × 5 ÷ 32,768 ~−1000 −5000 LSB +32,767 +6,554 +2 +1 0 −1 −2 −6554 −32,768 Hex 0x7FFF 0x199A 0x0002 0x0001 0x0000 0xFFFF 0xFFFE 0xE666 0x8000 Binary 1111 1111 1111 1111 0001 0001 10011010 0000 0000 0000 0010 0000 0000 0000 0001 0000 0000 0000 0000 1111 1111 1111 1111 1111 1111 1111 1110 1110 0110 0110 0110 1000 0000 0000 0000 Description (Default = 0x8000) Not used Power supply, binary, 3.3 V = 0xA8F, 1.22 mV/LSB Supply Level (V) 3.6 3.3 + 0.0012207 3.3 3.3 − 0.0012207 3.15 LSB 2949 2704 2703 2702 2580 Hex 0xB85 0xA90 0xA8F 0xA8E 0xA14 Binary 1011 1000 0101 1010 1001 0000 1010 1000 1111 1010 1000 1110 1010 0001 0100 Table 56. TEMP_OUT (Base Address = 0x08), Read Only Bits [15:12] [11:0] Description (Default = 0x8000) Not used Temperature data, offset binary, 1278 LSB = +25°C, −0.47°C/LSB Table 57. Internal Temperature Data Format Examples Temperature (°C) 125 25 + 0.47 25 25 − 0.47 0 −40 Rev. F | Page 22 of 29 LSB 1065 1277 1278 1279 1331 1416 Hex 0x429 0x4FD 0x4FE 0x4FF 0x533 0x588 Binary 0100 0010 1001 0100 1111 1101 0100 1111 1110 0100 1111 1111 0101 0011 0011 0101 1000 1000 Data Sheet ADIS16228 FFT EVENT HEADER Each FFT record has an FFT header that contains information that fills all of the registers listed in Table 58. The information in these registers contains recording time, record configuration settings, status/error flags, and several alarm outputs. The registers listed in Table 58 update with every record event and also update with record-specific information when using GLOB_CMD[13] (see Table 64) to retrieve a data set from the FFT record in flash memory. Address 0x3C 0x40 0x42 0x44 0x46 0x48 0x4A 0x4C 0x4E 0x6E 0x70 0x72 0x74 0x76 Table 59. REC_INFO1 (Base Address = 0x6E), Read Only Bits [15:14] [13:12] [11:10] Table 58. FFT Header Register Information Register DIAG_STAT ALM_X_STAT ALM_Y_STAT ALM_Z_STAT ALM_X_PEAK ALM_Y_PEAK ALM_Z_PEAK TIME_STMP_L TIME_STMP_H REC_INFO1 ALM_X_FREQ ALM_Y_FREQ ALM_Z_FREQ REC_INFO2 The REC_INFO1 register (see Table 59) and the REC_INFO2 register (see Table 60) capture the settings associated with the current FFT record. Description Alarm status X-axis alarm status Y-axis alarm status Z-axis alarm status X-axis alarm peak Y-axis alarm peak Z-axis alarm peak Time stamp, lower word Time stamp, upper word FFT record header information X-axis alarm frequency of peak alarm Y-axis alarm frequency of peak alarm Z-axis alarm frequency of peak alarm FFT record header information [9:8] [7:0] Description Sample rate option 00 = SR0, 01 = SR1, 10 = SR2, 11 = SR3 Window setting 00 = rectangular, 01 = Hanning, 10 = flat top, 11 = N/A Signal range 00 = 1 g, 01 = 5 g, 10 = 10 g, 11 = 20 g Not used (don’t care) FFT averages; range = 1 to 255 Table 60. REC_INFO2 (Base Address = 0x76), Read Only Bits [15:4] [3:0] Description Not used (don’t care) AVG_CNT setting The TIME_STMP_x registers (see Table 61 and Table 62) provide a relative time stamp that identifies the time for the current FFT record. Table 61. TIME_STMP_L (Base Address = 4C), Read Only Bits [15:0] Description (Default = 0x0000) Record time stamp, low integer, binary, seconds Table 62. TIME_STMP_H (Base Address = 0x4E), Read Only Bits [15:0] Rev. F | Page 23 of 29 Description (Default = 0x0000) Record time stamp, high integer, binary, seconds ADIS16228 Data Sheet SYSTEM TOOLS STATUS/ERROR FLAGS Table 63 provides an overview of the control registers that provide support for system-level functions. Table 63. System Tool Register Addresses Register Name FLASH_CNT DIO_CTRL GPIO_CTRL Address 0x00 0x36 0x38 DIAG_STAT GLOB_CMD LOT_ID1 LOT_ID2 PROD_ID SERIAL_NUM USER_ID 0x3C 0x3E 0x52 0x54 0x56 0x58 0x5C Description Flash memory write cycle count Digital input/output configuration General-purpose input/output control Status/error flags Global commands Lot Identification Code 1 Lot Identification Code 2 Product identification Serial number User identification register GLOBAL COMMANDS The GLOB_CMD register (see Table 64) provides an array of single-write commands for convenience. Setting the assigned bit to 1 activates each function. When the function completes, the bit restores itself to 0. For example, clear the capture buffers by setting GLOB_CMD[8] = 1 (DIN = 0xBF01). All of the commands in the GLOB_CMD register require that the power supply be within normal limits for the execution times listed in Table 64. Table 64. GLOB_CMD (Base Address = 0x3E), Write Only Bits 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Description Clear autonull correction Retrieve spectral alarm band information from the ALM_PNTR setting Retrieve record data from flash memory Save spectral alarm band registers to flash memory Record start/stop Set BUF_PNTR = 0x0000 Clear spectral alarm band registers from flash memory Clear records Software reset Save registers to flash memory Flash test, compare sum of flash memory with factory value Clear DIAG_STAT register Restore factory register settings and clear the capture buffers Self-test, result in DIAG_STAT[5] Power-down Autonull Execution Time 35 µs 40 µs The DIAG_STAT register (see Table 65) provides a number of status/error flags that reflect the conditions observed in a recording during SPI communication and diagnostic tests. An error condition is indicated by a setting of 1; and all of the error flags are sticky, which means that they remain until they are reset by setting GLOB_CMD[4] = 1 (DIN = 0xBE10) or by starting a new recording event. DIAG_STAT[14:8] indicates which ALM_x_MAGx thresholds were exceeded during a recording event. The flag in DIAG_STAT[3] indicates that the total number of SCLK clocks is not a multiple of 16. Table 65. DIAG_STAT (Base Address = 0x3C), Read Only Bits 15 14 13 12 11 10 9 8 7 6 5 4 Description (Default = 0x0000) Not used (don’t care) System alarm flag Z-axis, Spectral Alarm 2 flag Y-axis, Spectral Alarm 2 flag X-axis, Spectral Alarm 2 flag Z-axis, Spectral Alarm 1 flag Y-axis, Spectral Alarm 1 flag X-axis, Spectral Alarm 1 flag Data ready/busy indicator (0 = busy, 1 = data ready) Flash test result, checksum flag Self-test diagnostic error flag Recording escape flag, indicates use of the SPI-driven interruption command, 0xE8 SPI communication failure (SCLKs ≠ even multiple of 16) Flash update failure Power supply > 3.625 V Power supply < 3.125 V 1.9 ms 3 2 1 0 461 µs POWER-DOWN N/A 36 µs 25.8 ms 25.9 ms 52 ms 29.3 ms 5 ms 36 µs 84 ms To power down the ADIS16228, set GLOB_CMD[1] = 1 (DIN = 0xBE02). To reduce power consumption, set REC_CTRL1[7] = 1, which automatically results in a power-down after a record is complete. Toggle the CS line from high to low to wake up the device and place it in an idle state, where it waits for the next command. When DOI1 is configured as an external trigger, toggling it can wake up the device, as well. Using DIO1 for this purpose avoids the potential for multiple devices contending for DOUT when waking up with the CS line approach. After completing the record cycle, the device remains awake. Use GLOB_CMD[1] to put it back to sleep after reading the record data. 32.9 ms N/A 822 ms Rev. F | Page 24 of 29 Data Sheet ADIS16228 OPERATION MANAGMENT Alarm Indicator The ADIS16228 SPI port supports two different communication commands while it is processing data or executing a command associated with the GLOB_CMD register (see Table 64): reading DIAG_STAT (DIN = 0x3C00) (see Table 65) and the escape code (DIN = 0xE8E8). The SPI ignores all other commands when the processor is busy. DIO_CTRL[5:2] provide controls for establishing DIO1 and/or DIO2 as a general alarm output indicator that goes active when any of the flags in DIAG_STAT[13:8] is active. For example, set DIO_CTRL[7:0] = 0x12 (DIN = 0xB612) to configure DIO2 as a generic alarm indicator with an active high polarity. ALM_ CTRL[6] (see Table 26) provides an additional control, which enables DIO2 to reflect Alarm 2 and DIO1 to reflect Alarm 1 when they are selected as alarm indicators in DIO_CTRL[5:2]. For example, set DIO_CTRL[7:0] = 0x17 (DIN = 0xB617) and set ALM_CTRL[6] = 1 (DIN = 0xB440) to establish DIO2 as an active high Alarm 2 indicator and DIO1 as an active high Alarm 1 indicator. Set GLOB_CMD[4] = 1 (DIN = 0xBE10) to clear the DIAG_STAT error flags and restore the alarm indicator signal to its inactive state. Software Busy Indicator Use the DIAG_STAT read command to poll DIAG_STAT[7], which is equal to 0 when the processor is busy and equal to 1 when the processor is idle and data is ready for SPI communications. Software Escape Code The only SPI command that is available when the processor is busy capturing data is the escape code, which is 0xE8E8. This command is not available for interrupting any other processing tasks. Send this command in a repeating pattern, with a small delay between each write cycle, to the DIN pin while monitoring DIAG_STAT[7]. The following code example illustrates this process: DIAG_STAT = 0; DIAG_STAT = read_reg(0x3C); while ((DIAG_STAT & 0x0080) == 0) { write_reg(0xE8E8) delay_us(50) DIAG_STAT = read_reg(0x3C) } Table 66. DIO_CTRL (Base Address = 0x36), Read/Write Bits [15:6] [5:4] [3:2] INPUT/OUTPUT FUNCTIONS The DIO_CTRL register (see Table 66) provides configuration control options for the two digital input/output lines, DIO1 and DIO2. 1 Busy Indicator 0 The busy indicator is an output signal that indicates internal processor activity. This signal is active during data recording events or internal processing (GLOB_CMD functions, for example). The factory default setting for DIO_CTRL sets DIO1 as a positive, active high, busy indicator signal. When configured in this manner, use this signal to alert the master processor to read data from data buffers. Trigger Input The trigger function provides an input pin for starting record events with a signal pulse. Set DIO_CTRL[7:0] = 0x2F (DIN = 0xB62F) to configure DIO2 as a positive trigger input and keep DIO1 as a busy indicator. To start a trigger, the trigger input signal must transition from low to high and then from high to low. The recording process starts on the high-to-low transition, as shown in Figure 23, and the pulse duration must be at least 2.6 µs. DIO2 Δt 10069-014 DIO1 CAPTURE TIME General-Purpose Input/Output If the DIO_CTRL register configures either DIO1 or DIO2 as a general-purpose digital line, use the GPIO_CTRL register (see Table 67) to configure its input/output direction, set the output level when configured as an output, and monitor the status of an input. Table 67. GPIO_CTRL (Base Address = 0x38), Read/Write Bits [15:10] 9 8 [7:2] 1 Δt ≥ 2.6µs Description (Default = 0x000F) Not used DIO2 function selection 00 = general-purpose input/output (use GPIO_CTRL) 01 = alarm indicator output (per ALM_CTRL) 10 = trigger input 11 = busy/data-ready indicator output DIO1 function selection 00 = general-purpose input/output (use GPIO_CTRL) 01 = alarm indicator output (per ALM_CTRL) 10 = trigger input 11 = busy/data-ready indicator output DIO2 line polarity 1 = active high 0 = active low DIO1 line polarity 1 = active high 0 = active low 0 Figure 23. Manual Trigger/Busy Indicator Sequence Example Rev. F | Page 25 of 29 Description (Default = 0x0000) Not used DIO2 output level 1 = high; 0 = low DIO1 output level 1 = high; 0 = low Reserved DIO2 direction control 1 = output; 0 = input DIO1 direction control 1 = output; 0 = input ADIS16228 Data Sheet SELF-TEST DEVICE IDENTIFICATION Set GLOB_CMD[2] = 1 (DIN = 0xBE04) (see Table 64) to run an automatic self-test routine, which reports a pass/fail result to DIAG_STAT[5] (see Table 65). Table 69. LOT_ID1 (Base Address = 0x52), Read Only FLASH MEMORY MANAGEMENT Set GLOB_CMD[5] = 1 (DIN = 0xBE20) to run an internal checksum test on the flash memory, which reports a pass/fail result to DIAG_STAT[6]. The FLASH_CNT register (see Table 68) provides a running count of flash memory write cycles. This is a tool for managing the endurance of the flash memory. Figure 24 quantifies the relationship between data retention and junction temperature. Table 68. FLASH_CNT (Base Address = 0x00), Read Only Bits [15:0] Bits [15:0] Description Lot identification code Table 71. PROD_ID (Base Address = 0x56), Read Only Bits [15:0] Description (Default = 0x3F64) 0x3F64 = 16,228 Table 72. SERIAL_NUM (Base Address = 0x58), Read Only Description Serial number, lot specific Table 73 shows a blank register that is available for writing userspecific identification. Table 73. USER_ID (Base Address = 0x5C), Read/Write Bits [15:0] 450 300 30 40 55 70 85 100 125 135 JUNCTION TEMPERATURE (°C) 150 10069-015 150 0 Description Lot identification code Table 70. LOT_ID2 (Base Address = 0x54), Read Only Bits [15:0] Description Binary counter for writing to flash memory 600 RETENTION (Years) Bits [15:0] Figure 24. Flash®/EE Memory Data Retention Rev. F | Page 26 of 29 Description (Default = 0x000) User-written identification Data Sheet ADIS16228 APPLICATIONS INFORMATION MATING CONNECTOR BREAKOUT BOARD The mating connector for the ADIS16228, J2, is the AVX® 046288-015-000-846. Figure 25 provides a close-up view of this connector, which clamps down on the flex cable to press its metal pads onto the metal pads inside of the mating connector. The ADIS16ACL1/PCBZ breakout board provides a convenient means for connecting the ADIS16228 to an embedded processor, using a standard ribbon cable. This printed circuit board (PCB) provides four mounting holes (one in each corner), which provide clearance for 4-40 machine screws. J1 is a 16-pin connector, which mates with 2 mm pitch, IDC ribbon cables, such as the TCSD series from Samtec®. The LEDs (D1 and D2) are not populated; however, the pads are available to install to provide a visual representation of the DIO1 and DIO2 signals. The pads accommodate VCC™ CMD28-21VRC/TR8, which works well when R1 and R2 are approximately 400 Ω (0603 pad sizes). SLIDER LOCKING DIRECTION SLIDER MATING CONNECTOR PC-BASED EVALUATION TOOLS 10069-022 ADIS16228CMLZ FLEX CABLE The ADIS16ACL1/PCBZ provides a simple way to connect the ADIS16228 to the EVAL-ADIS2 evaluation system, which provides a PC-based method for evaluation of basic function and performance. For more information, visit the EVAL-ADIS2 Evaluation System page on the Analog Devices, Inc., website. Figure 25. Mating Connector Detail 1.250" J1 1 ADIS16ACL1/PCBZ J2 2 15 1.500" 1 15 16 10069-026 0.157" 0.157" Figure 26. ADIS16ACL1/PCBZ Top Level View/Dimensions Rev. F | Page 27 of 29 ADIS16228 Data Sheet VDD VDD J2 J1 J1 RST 1 2 SCLK 1 CS 3 4 DOUT 2 5 6 DIN 3 7 8 9 10 11 12 13 14 15 16 DIO1 SPARE PIN 4 5 SPARE PIN DIO2 DIO2 SPARE PIN 8 R2 400Ω D2 DGND C A CMD28-21VRC/TR8 (RED) A C 10 DIN 11 12 SCLK 13 CS 14 DIO1 CMD28-21VRC/TR8 (RED) 15 04-6288-015-000-846 DGND C1 10µF 9 RST DOUT R1 400Ω D1 VDD 7 SPARE PIN A3-16PA-2SV (71) DGND 6 DGND C2 0603 DNI ADIS16210/ADIS16228 PACKAGE PIN OUT DGND Figure 27. Electrical Schematic Rev. F | Page 28 of 29 10069-027 SPARE PIN Data Sheet ADIS16228 OUTLINE DIMENSIONS 24.20 24.00 23.80 15.20 15.00 SQ 14.80 TOP VIEW Ø 1.65 Hole and Slot Size for 1.5 mm Pin 20.20 20.00 19.80 BOTTOM VIEW 2.65 (4 PLCS) 3.50 (4 PLCS) R 2.65 R 0.83 (4 PLCS) (Centers of 2 R 0.83 Circles Separated by 0.89) 20.00 BSC 3.75 (4 PLCS) 0.254 NOM 8.20 8.00 7.80 0.50 NOM PITCH DETAIL A 3.50 NOM FRONT VIEW 15.20 15.00 14.80 04-27-2011-A DETAIL A Figure 28. 15-Lead Module with Connector Interface (ML-15-1) Dimensions shown in millimeters ORDERING GUIDE Model 1 ADIS16228CMLZ 1 Temperature Range −40°C to +125°C Package Description 15-Lead Module with Connector Interface Z = RoHS Compliant Part. ©2011–2018 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. D10069-0-4/18(F) Rev. F | Page 29 of 29 Package Option ML-15-1