ADIS16240/PCBZ

Low Power, Programmable Impact Sensor and Recorder ADIS16240 Data Sheet FEATURES FUNCTIONAL BLOCK DIAGRAM AN ADIS16240 XA YA TRIPLE-AXIS MEMS ACCELEROMETER ZA ANALOGTO-DIGITAL CONVERSION AND PROCESSING VDD POWER MANAGEMENT DIGITAL CONTROL AND SPI INTERFACE TEMPERATURE SENSOR CMP1 CMP2 ALARM DETECTION EVENT TRIGGER EVENT CAPTURE BUFFER CS SCLK DIN DOUT RST DIO1 DIO2 08133-001 Digital triple-axis accelerometer, ±19 g Programmable event recorder Internal and external trigger inputs Automatic event data storage in nonvolatile flash Low power operation Sleep mode current: 100 µA Continuous sampling current: 1 mA, 1 kSPS Wake-up and record function External trigger input and SPI trigger command Peak acceleration sample-and-hold Peak XYZ sum-of-squares output 1600 Hz (X, Y) and 550 Hz (Z) sensor bandwidth Digitally controlled sample rate, up to 4096 SPS Programmable alarms for condition monitoring Programmable digital input/output lines Data-ready output and alarm indicator output Real-time clock Digitally activated self-test Embedded temperature sensor Programmable power management SPI-compatible serial interface Auxiliary 10-bit ADC input Two analog trigger inputs with programmable threshold Single-supply operation: 2.4 V to 3.6 V >4000 g powered shock survivability Figure 1. APPLICATIONS Crash or impact detection Condition monitoring of valuable goods Safety, shut-off sensing Impact event recording Security sensing and tamper detection GENERAL DESCRIPTION The ADIS16240 is a fully integrated digital shock detection and recorder system. It combines industry-leading iMEMS® technology with a signal processing solution that optimizes dynamic performance for low power applications. The triple-axis sensing element enables shock measurement in all directions, eliminating the need for additional sensors and complex mechanical structures for many applications. The digital serial peripheral interface (SPI) uses four wires and is compatible with most processor platforms. The SPI interface provides access to sensor data and a set of configuration registers that control such operational parameters as offset bias correction, sample rate, sleep mode, peak detection, and event capture. Rev. C The programmable event recorder offers two trigger modes. The internal mode monitors continuous sampled data and triggers the capture, based on the user-defined threshold. The external mode uses the two comparator inputs and a user-defined threshold to trigger the event captures. This function also provides user configuration controls for capture length, pretrigger data, and data storage. Each event is stored with a header that captures temperature, power supply, and time. Several power management features, including sleep mode and a wake-up function, enable power optimization with respect to specific mechanical system requirements. The ADIS16240 is available in a 12 mm × 12 mm laminate-based ball grid array (BGA) that meets IPC/JEDEC standards for Pb-free solder reflow processing (J-STD-020C and J-STD-033). Document Feedback Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective owners. One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. Tel: 781.329.4700 ©2009–2012 Analog Devices, Inc. All rights reserved. Technical Support www.analog.com ADIS16240 Data Sheet TABLE OF CONTENTS Features .............................................................................................. 1 User Interface .................................................................................8 Applications ....................................................................................... 1 Capture ...........................................................................................8 Functional Block Diagram .............................................................. 1 Basic Operation .................................................................................9 General Description ......................................................................... 1 Memory Map .............................................................................. 10 Revision History ............................................................................... 2 Output Data Registers................................................................ 11 Specifications..................................................................................... 3 Event Recorder............................................................................ 12 Timing Specifications .................................................................. 4 Operational Control................................................................... 14 Absolute Maximum Ratings ............................................................ 5 Applications Information .............................................................. 17 ESD Caution .................................................................................. 5 Assembly...................................................................................... 17 Pin Configuration and Function Descriptions ............................. 6 Interface Printed Circuit Board (PCB) .................................... 17 Typical Performance Characteristics ............................................. 7 Outline Dimensions ....................................................................... 18 Theory of Operation ........................................................................ 8 Ordering Guide .......................................................................... 18 Sensing Element ........................................................................... 8 Data Sampling and Processing ................................................... 8 REVISION HISTORY 12/12—Rev. B to Rev. C Changes to Features Section............................................................ 1 Removed Bias Voltage Sensitivity from Table 1............................ 3 Changes to Table 7 .......................................................................... 10 Changes to Event Recorder Section ............................................. 12 Added Flash Memory Endurance Management Section .......... 16 Updated Outline Dimensions ....................................................... 18 Changes to Ordering Guide .......................................................... 18 8/12—Rev. A to Rev. B Updated Outline Dimensions ........................................................17 10/11—Rev. 0 to Rev. A Added Applications Information Section, Figure 23, Figure 24, Figure 25, Renumbered Sequentially ........................................... 16 Updated Outline Dimensions ....................................................... 18 Changes to Ordering Guide .......................................................... 18 4/09—Revision 0: Initial Version Rev. C | Page 2 of 20 Data Sheet ADIS16240 SPECIFICATIONS TA = 25°C, VDD = 2.4 V to 3.6 V unless otherwise noted. Table 1. Parameter ACCELEROMETER Dynamic Range Initial Sensitivity Sensitivity Temperature Coefficient Sensitivity Change with Supply Voltage Nonlinearity Sensor-to-Sensor Alignment Error Cross-Axis Sensitivity Initial Bias Error Bias Temperature Coefficient Output Noise Noise Density Bandwidth Conditions Axis −40°C to +85°C 2.4 V < VDD < 3.6 V Compare with best fit line 1 2 3 4 Typ ±16 ±19 51.4 ±0.01 6 ±2 ±0.1 ±1 X, Y −2.7 No external capacitance No external capacitance Sensor Resonant Frequency Self-Test Change in Output Response TEMPERATURE SENSOR SCALE FACTOR ADC INPUT Input Range Resolution Integral Nonlinearity, INL Differential Nonlinearity, DNL Offset Error Gain Error Input Capacitance LOGIC INPUTS 1 Input High Voltage, VINH Input Low Voltage, VINL Logic 1 Input Current, IINH Logic 0 Input Current, IINL Input Capacitance, CIN DIGITAL OUTPUTS Output High Voltage, VOH Output Low Voltage, VOL START-UP TIME Initial, Reset Recovery FLASH MEMORY Endurance 2 Data Retention 3 CONVERSION RATE SETTING POWER SUPPLY Average Supply Current 4 Sleep Mode Current Min X, Y Z X Y Z −10 +10 +10 TEMP_OUT = 0x0133 (307) at 25°C Max +2.7 ±1 24 480 1600 550 5.5 −21 +21 +36 0.244 0 −39 +39 +65 VDD 10 ±1 ±1 ±1 ±1 11 ±2 ±1.25 ±2 ±3 2.0 VIH = VDD VIL = 0 V ±0.2 −40 10 ISOURCE = 1.6 mA ISINK = 1.6 mA 0.8 ±1 −60 2.4 2.4 SMPL_PRD = 0x1F, VDD = 2.5 V 1 100 g mg/LSB % % % FS Degrees % g mg/°C mg rms µg/√Hz Hz Hz kHz LSB LSB LSB °C/LSB V Bits LSB LSB LSB LSB pF V V µA μA pF 0.4 V V 32 ms 4096 3.6 Cycles Years SPS V mA µA 10,000 20 TJ = 85°C Unit Note that the inputs are 5 V tolerant. Endurance is qualified as per JEDEC Standard 22, Method A117 and measured at −40°C, +25°C, +85°C, and +105°C. Retention lifetime equivalent at junction temperature (TJ) of 55°C as per JEDEC Standard 22, Method A117. Retention lifetime decreases with junction temperature. Instantaneous current has periodic peaks at the sample rate that can reach 30 mA. Rev. C | Page 3 of 20 ADIS16240 Data Sheet TIMING SPECIFICATIONS TA = 25°C, VDD = 3.3 V, unless otherwise noted. Table 2. Parameter fSCLK tDATARATE tCS tDAV tDSU tDHD tDF tDR tSFS 1 2 Min1 0.01 60 120 Description Serial clock rate2 Chip select period2 Chip select to clock edge Data output valid after SCLK edge Data input setup time before SCLK rising edge Data input hold time after SCLK rising edge Data output fall time Data output rise time CS high after SCLK edge Max1 2.5 Typ 30 20 20 10 10 25 25 430 Unit MHz μs ns ns ns ns ns ns ns Guaranteed by design; typical specifications are not tested or guaranteed. Based on sample rate selection. Timing Diagrams tDATARATE 08133-002 CS SCLK Figure 2. SPI Chip Select Timing CS tCS tSFS 1 2 3 4 5 6 15 16 SCLK tDAV MSB DB14 DB13 tDSU DIN W/R A6 DB12 DB11 A4 A3 DB10 DB2 DB1 LSB tDHD A5 A2 D2 D1 Figure 3. SPI Timing (Utilizing SPI Settings Typically Identified as Phase = 1, Polarity = 1) Rev. C | Page 4 of 20 LSB 08133-003 DOUT Data Sheet ADIS16240 ABSOLUTE MAXIMUM RATINGS Table 3. Parameter Acceleration Any Axis, Unpowered Any Axis, Powered VDD to GND Digital Input Voltage to GND Analog Inputs to GND Operating Temperature Range Storage Temperature Range Rating 2000 g 2000 g −0.3 V to +3.6 V −0.3 V to VDD + 0.3 V −0.3 V to VDD + 0.3 V −40°C to +85°C −65°C to +150°C Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. ESD CAUTION Rev. C | Page 5 of 20 ADIS16240 Data Sheet PIN CONFIGURATION AND FUNCTION DESCRIPTIONS TOP VIEW 1 2 3 4 5 6 7 8 9 10 11 A H J K L 08133-004 B C D E F G NOTES 1. THE ACTUAL PINS ARE NOT VISIBLE FROM THE TOP VIEW. Figure 4. Pin Configuration (Top View) A1 AZ X AY AY AX AX 08133-005 AZ Figure 5. Axis Orientation of Device (Top View) Table 4. Pin Function Descriptions Pin No. E10, E11 F10, F11 G10, G11 H10, H11 J10, J11 K9, L9 K8, L8 K7, L7 K6, L6 K3, L3 J1, J2 H1, H2 G1, G2 A5, B5 D4 to D8, E4, E8, F4, F8, G4, G8, H4 to H8 A1, A2, A10, A11, B1, B2, B10, B11, C3 to C9, D3, D9, E3, E9, F3, F9, G3, G9, H3, H9, J3 to J9, K1, K2, K10, K11, L1, L2, L10, L11 A3, A4, A6 to A9, B3, B4, B6 to B9, C1, C2, C10, C11, D1, D2, D10, D11, E1, E2, F1, F2, K4, K5, L4, L5 1 Mnemonic SCLK CS DIN DOUT DIO2 DIO1 AN CMP2 CMP1 RST XA YA ZA ST VDD GND NC I = input, O = output, I/O = input/output, S = supply. Rev. C | Page 6 of 20 Type 1 I I I O I/O I/O I I I I O O O I S S Description SPI Serial Clock SPI Chip Select, Active Low SPI Data Input SPI Data Output Multifunction Digital Input/Output 2 Multifunction Digital Input/Output 1 Analog Input Channel Analog Comparator Input 2 Analog Comparator Input 1 Reset, Active Low, No Pull-Up Resistor X-Axis Accelerometer Filter Pin Y-Axis Accelerometer Filter Pin Z-Axis Accelerometer Filter Pin Self-Test Input Control Line Power Supply, 3.3 V Ground No Connect Data Sheet ADIS16240 TYPICAL PERFORMANCE CHARACTERISTICS 2.8 30mA PEAK 2.3 1.8 CURRENT 1 1.3 08133-106 0.8 0.3 0 500 1000 1500 2000 2500 3000 SAMPLE RATE (SPS) 3500 4000 08133-108 SUPPLY CURRENT (mA) 3.3 4500 CH1 20.0V M40.0µs A CH1 T 40.5304µs 17.2mV Figure 9. Instantaneous Supply Current Figure 6. Supply Current vs. Sample Rate 1.6 1.4 1.0 0.8 CURRENT 0.6 1 0.4 08133-107 0.2 08133-109 SUPPLY CURRENT (mA) 30mA PEAK 1.2 0 2.4 2.6 2.8 3.0 3.2 CH1 50.0V 3.6 3.4 M40.0µs A CH1 T 40.5304µs SUPPLY VOLTAGE (V) Figure 7. Supply Current vs. Supply Voltage Figure 10. Instantaneous Supply Current 1.5 3.6V 3.0V 1.3 1.2 1.1 2.4V 1.0 08133-110 SUPPLY CURRENT (mA) 1.4 0.9 –40 –30 –20 –10 0 10 20 30 40 TEMPERATURE (°C) 50 60 70 80 90 Figure 8. Supply Current vs. Temperature Rev. C | Page 7 of 20 73.0mV ADIS16240 Data Sheet THEORY OF OPERATION The ADIS16240 is a triple-axis accelerometer system for shock detection and recording applications. This sensing system collects data autonomously and makes it available to any processor system that supports a 4-wire serial peripheral interface (SPI). SENSING ELEMENT Digital shock sensing starts with the triple-axis MEMS sensing element in the ADIS16240. This element provides a linear motionto-electrical transducer function. Figure 11 provides a basic physical diagram of the sensing element and its response to linear acceleration. It uses a fixed frame and a moving frame to form a differential capacitance network that responds to linear acceleration. Tiny springs tether the moving frame to the fixed frame and govern the relationship between acceleration and physical displacement. A modulation signal on the moving plate feeds through each capacitive path into the fixed frame plates and into a demodulation circuit, which produces the electrical signal that is proportional to the acceleration acting on the device. ANCHOR MOVABLE FRAME FIXED PLATES UNIT SENSING CELL UNIT FORCING CELL Data collection and configuration commands both use the SPI, which consists of four wires. The chip select (CS) signal activates the SPI interface, and the serial clock (SCLK) synchronizes the serial data lines. The serial input data clocks into DIN on the rising edge of SCLK, and the serial output data clocks out of DOUT on the falling edge of SCLK. Many digital processor platforms support this interface with dedicated serial ports and simple instruction sets. User Registers The user registers provide addressing for all input/output operations on the SPI interface. Each 16-bit register has its own unique bit assignment and has two 7-bit addresses: one for its upper byte and one for its lower byte. Table 7 provides a memory map for each register and identifies output registers as read only (R) and configuration registers as either read/write (R/W) or write only (W). The control registers use a dual-memory structure. The SRAM controls operation while the part is on and facilitates all user configuration inputs. The flash memory provides nonvolatile storage for the control registers that are identified with a “yes” in the flash backup column in Table 7. Storing configuration data in the flash memory requires a manual command (see GLOB_CMD[3] in Table 24). When the device starts up from an initial power-up or reset, the flash memory contents load into the SRAM. Then the device starts producing data according to the configuration in the control registers. ANCHOR MANUAL FLASH BACKUP Figure 11. MEMS Sensor Diagram NONVOLATILE FLASH MEMORY DATA SAMPLING AND PROCESSING (NO SPI ACCESS) The analog acceleration signals feed into an analog-to-digital converter stage that passes digitized data into the controller for data processing and capture. The ADIS16240 runs autonomously, based on the configuration in the user control registers. (SPI ACCESS) START-UP RESET Figure 13. Control Registers—SRAM and Flash Memory Diagram CAPTURE CAPTURE BUFFER CONTROL REGISTERS The ADIS16240 offers a recorder function that captures acceleration information based on either internal or external triggers. The buffer memory is 3 × 8192 samples and is capable of storing multiple trigger events. SPI SIGNALS MEMS SENSOR SPI PORT OUTPUT REGISTERS CONTROLLER VOLATILE SRAM 08133-009 MOVING PLATE SPI Interface 08133-007 ACCELERATION PLATE CAPACITORS USER INTERFACE INPUT/OUTPUT FUNCTIONS 08133-008 CLOCK Figure 12. Simplified Sensor Signal Processing Diagram Rev. C | Page 8 of 20 Data Sheet ADIS16240 BASIC OPERATION VDD User registers govern all data collection and configuration. Table 7 provides a memory map that includes all user registers, along with references to bit assignment tables that follow the generic assignments in Figure 15. 15 14 13 12 11 10 9 8 7 6 UPPER BYTE VDD 5 4 3 2 1 0 08133-011 The ADIS16240 starts up automatically when it has a valid power supply and begins producing digital acceleration data in the output registers. When using the factory-default configuration, DIO1 serves as a data-ready indicator signal that can drive a processor interrupt function. Figure 14 shows a schematic for connecting to a SPI-compatible processor platform, referred to as the SPI master. LOWER BYTE Figure 15. Generic Register Bit Assignments SPI Write Commands ADIS16240 SYSTEM PROCESSOR SPI MASTER Master processors write to the control registers, one byte at a time, using the bit assignments shown in Figure 18. The programmable registers in Table 7 provide controls for optimizing sensor operation and for starting various automated functions. For example, set GLOB_CMD[8] = 1 (DIN = 0xCB01) to wake up the device. SPI SLAVE SS CS SCLK SCLK MOSI DIN MISO DOUT IRQ1 DIO1 IRQ2 DIO2 08133-010 CS Figure 14. Electrical Hook-Up Diagram DIN Figure 16. SPI Sequence for a Wake-Up Command (DIN = 0xCB01) Table 5. Generic Master Processor Pin Names and Functions Some configurations require writing both bytes to a register, which takes two separate 16-bit sequences. See GLOB_CMD[3] in Table 24 for backing up configuration data in nonvolatile flash memory. Function Slave select. Interrupt request inputs. Master output, slave input. Master input, slave output. Serial clock. SPI Read Commands The ADIS16240 SPI interface supports full duplex serial communication (simultaneous transmit and receive) and uses the bit sequence shown in Figure 18. Processor platforms typically support SPI communication with general-purpose serial ports that require some configuration in their control registers. Table 6 lists the most common settings that require attention when initializing a pro-cessor serial port for communication with the ADIS16240. Table 6. Generic Master Processor SPI Settings Processor Setting Master SCLK Rate ≤ 2.5 MHz SPI Mode 3 (1,1) MSB First 16-Bit Description The ADIS16240 operates as a slave. Bit rate setting. Clock polarity/phase (CPOL = 1, CPHA = 1). Bit sequence. Shift register/data length. Reading data on the SPI requires two consecutive 16-bit sequences. The first sequence transmits the read command on DIN, and the second sequence receives the resulting data from DOUT. The 7-bit register address can represent either the upper or lower byte address for the target register. For example, DIN can be either 0x0200 or 0x0300 when reading the SUPPLY_OUT register. The SPI operates in full duplex mode, which means that the master processor can read the output data from DOUT while using the same SCLK pulses to transmit a new command on DIN. In Figure 17, the second SPI segment sets up the device to read YACCL_OUT on the following SPI segment (not shown). SPI SEGMENT 1 SPI SEGMENT 2 CS SCLK DIN = 0x0600 TO READ YACCL_OUT DIN DOUT DIN = 0x0400 PRODUCES XACCL_OUT CONTENTS ON DOUT DURING THE NEXT SPI SEGMENT Figure 17. Example SPI Read Sequence Rev. C | Page 9 of 20 DOUT = 0x802B = 2.21g, NEW DATA 08133-013 Pin Name SS IRQ1, IRQ2 MOSI MISO SCLK 08133-012 SCLK ADIS16240 Data Sheet MEMORY MAP Note that all registers are two bytes. All unused memory locations are reserved for future use. Table 7. User Register Memory Map Register Name FLASH_CNT SUPPLY_OUT XACCL_OUT YACCL_OUT ZACCL_OUT AUX_ADC TEMP_OUT XPEAK_OUT YPEAK_OUT ZPEAK_OUT XYZPEAK_OUT CAPT_BUF1 CAPT_BUF2 DIAG_STAT EVNT_CNTR CHK_SUM XACCL_OFF YACCL_OFF ZACCL_OFF CLK_TIME CLK_DATE CLK_YEAR WAKE_TIME WAKE_DATE ALM_MAG1 ALM_MAG2 ALM_CTRL XTRIG_CTRL CAPT_PNTR CAPT_CTRL GPIO_CTRL MSC_CTRL SMPL_PRD GLOB_CMD 2 Flash Backup Yes No No No No No No No No No No No 2 No2 No Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes No No Yes Yes Register Address 1 0x00 0x02 0x04 0x06 0x08 0x0A 0x0C 0x0E 0x10 0x12 0x14 0x16 0x18 0x1A 0x1C 0x1E 0x20 0x22 0x24 0x2E 0x30 0x32 0x34 0x36 0x38 0x3A 0x3C 0x3E 0x40 0x42 0x44 0x46 0x48 0x4A Default N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A 0x0000 0x0000 N/A 0x0000 0x0000 0x0000 0x0000 0x0000 0x0000 0x0000 0x0000 0x9000 0x9000 0x0000 0x0000 0x0000 0x0022 0x0000 0x0006 0x001F N/A Bit Assignments See Table 35 See Table 10 See Table 9 See Table 9 See Table 9 See Table 8 See Table 11 See Table 9 See Table 9 See Table 9 See Table 8 See Table 18 See Table 19 See Table 28 See Table 21 See Table 34 See Table 27 See Table 27 See Table 27 See Table 29 See Table 30 See Table 31 See Table 32 See Table 33 See Table 13 See Table 13 See Table 12 See Table 15 See Table 20 See Table 17 See Table 26 See Table 25 See Table 23 See Table 24 Function Flash memory write count Output, power supply Output, x-axis accelerometer Output, y-axis accelerometer Output, z-axis accelerometer Output, auxiliary ADC input Output, temperature Output, x-axis acceleration peak Output, y-axis acceleration peak Output, z-axis acceleration peak Output, sum-of-squares acceleration peak Output, Capture Buffer 1, X and Y acceleration Output, Capture Buffer 2, Z acceleration Diagnostic, error flags Diagnostic, event counter Diagnostic, check sum value from firmware test Calibration, x-axis acceleration offset adjustment Calibration, y-axis acceleration offset adjustment Calibration, z-axis acceleration offset adjustment Clock, hour and minute Clock, month and day Clock, year Wake-up setting, hour and minute Wake-up setting, month and day Alarm 1 amplitude threshold Alarm 2 amplitude threshold Alarm control Capture, external trigger control Capture, address pointer Capture, configuration and control General-purpose digital input/output control Miscellaneous control Internal sample period (rate) control System command Each register contains two bytes. The address of the lower byte is displayed. The address of the upper byte is equal to the address of the lower byte plus 1. The event capture buffer is also stored in flash, but the CAPT_BUFx registers, which only contain a single sample, are not stored in nonvolatile flash. CS SCLK DIN DOUT R/W D15 A6 A5 A4 A3 A2 A1 A0 DC7 DC6 DC5 DC4 DC3 DC2 DC1 DC0 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 NOTES 1. DOUT BITS ARE BASED ON THE PREVIOUS 16-BIT SEQUENCE, WHEN R/W = 0. Figure 18. SPI Communication Bit Sequence Rev. C | Page 10 of 20 R/W D15 A6 A5 D14 D13 08133-014 1 Read/ Write R R R R R R R R R R R R R R R R R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W W Data Sheet ADIS16240 OUTPUT DATA REGISTERS Table 9. Accelerometer Data Output Format1 Each output data register uses the bit assignments shown in Figure 19. The ND flag indicates that unread data resides in the register. This flag clears and returns to 0 after reading the register. It returns to 1 after the next internal sample updates the register with new data. When the data-ready function (the DIO1 and DIO2 pins and the MSC_CTRL register; see Table 25) drives data collection, the ND bit is always high and does not require validation. The EA flag indicates that one of the error flags in the DIAG_STAT register (see Table 28) is active (true). Binary 01 0011 0111 … 00 0000 0010 00 0000 0001 00 0000 0000 11 1111 1111 11 1111 1110 … 10 1100 1001 ND EA x x x x D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 08133-015 MSB FOR 10-BIT OUTPUT 1 Figure 19. Output Register Bit Assignments Table 8. Output Data Register Formats Register SUPPLY_OUT XACCL_OUT YACCL_OUT ZACCL_OUT AUX_ADC TEMP_OUT XPEAK_OUT1 YPEAK_OUT1 ZPEAK_OUT1 XYZPEAK_OUT2 Bits 10 10 10 10 10 10 10 10 10 12 Format Binary, 0 V = 0x0000 Twos complement Twos complement Twos complement Binary, 0 V = 0x0000 Binary, 25°C = 0x0133 Twos complement Twos complement Twos complement Binary, 0 g2 = 0x0000 Scale 4.88 mV 51.4 mg 51.4 mg 51.4 mg VDD/1024 0.244°C 51.4 mg 51.4 mg 51.4 mg 0.676 g2 Function requires MSC_CTRL[14] = 1. 2 Function requires MSC_CTRL[15] = 1. 1 Processing Sensor Data Processing sensor data starts with reading the appropriate output data register using the SPI. For example, use DIN = 0x0E00 to read the XPEAK_OUT register. Use the ND and EA bits to validate new data and normal operating status, if necessary. Then mask off all of the nondata bits and calculate the data, using the format and scale information shown in Table 8. For example, XACCL_OUT[9:0] and XYZPEAK_OUT[11:0] contain all relevant data for their function. Table 9, Table 10, and Table 11 provide output code examples for each output register. Hex 0x137 … 0x002 0x001 0x000 0x3FF 0x3FE … 0x2C9 Codes +311 … +2 +1 0 −1 −2 … −311 Acceleration +16 g … +102.8 mg +51.4 mg 0 −51.4 mg −102.8 mg … −16 g The XACCL_OUT register is located at Address 0x05[15:8] and Address 0x04[7:0]. The YACCL_OUT register is located at Address 0x07[15:8] and Address 0x06[7:0]. The ZACCL_OUT register is located at Address 0x09[15:8] and Address 0x08[7:0]. The XPEAK_OUT register is located at Address 0x0F[15:8] and Address 0x0E[7:0]. The YPEAK_OUT register is located at Address 0x11[15:8] and Address 0x10[7:0]. The ZPEAK_OUT register is located at Address 0x13[15:8] and Address 0x12[7:0]. When MSC_CTRL[14] = 1, the XPEAK_OUT, YPEAK_OUT, and ZPEAK_OUT registers track the peak acceleration in each acceleration output register. When MSC_CTRL[15] = 1, use the following equation to calculate the root mean square (rms) of all three peak registers, where 1 LSB = 0.822 g: XYZrms = XYZPEAK _ OUT Set GLOB_CMD[5] = 1 to reset these registers to 0x0000. Table 10. Power Supply Data Output Format1 Binary 10 1110 0010 … 10 1010 0101 10 1010 0100 10 1010 0011 … 01 1110 1100 1 Hex 0x2E2 … 0x2A5 0x2A4 0x2A3 … 0x1EC Codes 738 … 677 676 675 … 492 Power Supply (V) 3.6 … 3.30488 3.3 3.29502 … 2.4 The SUPPLY_OUT register is located at Address 0x03[15:8] and Address 0x02[7:0]. Table 11. Temperature Data Output Format1 Binary 10 0010 1001 … 01 0011 0100 01 0011 0011 01 0011 0010 … 00 0010 1001 1 Hex 0x229 … 0x134 0x133 0x132 … 0x029 Codes 553 … 308 307 306 … 41 Temperature (°C) +85°C … +25.244°C +25°C +24.756°C … −40°C The TEMP_OUT register is located at Address 0x0D[15:8] and Address 0x0C[7:0]. Rev. C | Page 11 of 20 ADIS16240 Data Sheet EVENT RECORDER The ADIS16240 provides a 3 × 8192 (8-bit) buffer memory for capturing and storing (in flash) transient acceleration data on all three axes (x, y, and z). There are a number of user controls for tailoring the event recorder for optimal system-level operation. Alarm 1 and Alarm 2 provide internal and external trigger options for starting a data capture sequence. Internal Trigger Setup Select the trigger data source for Alarm 1 and Alarm 2 using ALM_CTRL[15:8] (see Table 12). The ALM_MAG1 and ALM_ MAG2 registers contain threshold magnitude and direction settings for Alarm 1 and Alarm 2, respectively. The format for the data bits in these registers matches the trigger data source, which is set using ALM_CTRL[15:8]. For example, if ALM_ CTRL[15:12] equals 0010, then the format matches that of XACCL_OUT: 10-bit, twos complement, with 1 LSB = 51.4 mg of acceleration. Table 12. ALM_CTRL Register Bit Descriptions1 Bit [15:12] [11:8] [7:6] 5 4 3 2 1 0 1 Description (Default = 0x0000) Alarm 2 source selection 0000 = disabled 0001 = power supply voltage (SUPPLY_OUT) 0010 = x acceleration (XACCL_OUT) 0011 = y acceleration (YACCL_OUT) 0100 = z acceleration (ZACCL_OUT) 0101 = auxiliary ADC voltage (AUX_ADC) 0110 = temperature (TEMP_OUT) 0111 = XYZ peak acceleration (XYZPEAK_OUT) 1000 = external trigger Alarm 1 source selection (same as Alarm 2) Unused Alarm 2 capture trigger: 1 = enabled, 0 = disabled Alarm 1 capture trigger: 1 = enabled, 0 = disabled Unused Alarm indicator enable: 1 = enabled, 0 = disabled Alarm indicator polarity: 1 = positive, 0 = negative Alarm indicator pin: 1 = DIO2, 0 = DIO1 1 Description Set Alarm 1 and Alarm 2 to ZACCL_OUT Set Alarm 1 to trigger on a measured acceleration that has a magnitude of >2.57 g Set Alarm 2 to trigger on a measured acceleration that has a magnitude of