Programmable Digital Gyroscope Sensor
ADIS16260/ADIS16265
Data Sheet
FEATURES
GENERAL DESCRIPTION
Yaw rate gyroscope with range scaling
±80°/sec, ±160°/sec, and ±320°/sec settings
No external configuration required to start data collection
Start-up time: 165 ms
Sleep mode recovery time: 2.5 ms
Factory-calibrated sensitivity and bias
ADIS16265 calibration temperature range: −40°C to +85°C
ADIS16260 calibration temperature: +25°C
SPI-compatible serial interface
Relative angle displacement output
Embedded temperature sensor
Programmable operation and control
Automatic and manual bias correction controls
Sensor bandwidth selection: 50 Hz/330 Hz
Sample rate: 256 SPS/2048 SPS settings
Bartlett window FIR filter length, number of taps
Digital I/O: data ready, alarm indicator, general-purpose
Alarms for condition monitoring
Sleep mode for power management
DAC output voltage
Single-command self-test
Single-supply operation: 4.75 V to 5.25 V
3.3 V compatible digital lines
2000 g shock survivability
Operating temperature range: −40°C to +105°C
The ADIS16260 and the ADIS16265 are programmable digital
gyroscopes that combine industry-leading MEMS and signal
processing technology in a single compact package. They provide
accuracy performance that would require full motion calibration
with any other MEMS gyroscope in their class. When power is
applied, the ADIS16260 and the ADIS16265 automatically start up
and begin sampling sensor data, without requiring configuration
commands from a system processor. An addressable register
structure and a common serial peripheral interface (SPI) provide
simple access to sensor data and configuration settings. Many
digital processor platforms support the SPI with simple firmwarelevel instructions.
The ADIS16260 and the ADIS16265 provide several programmable
features for in-system optimization. The sensor bandwidth switch
(50 Hz and 330 Hz), Bartlett window FIR filter length, and sample
rate settings provide users with controls that enable noise vs.
bandwidth optimization. The digital input/output lines offer
options for a data ready signal that helps the master processor
efficiently manage data coherency, an alarm indicator signal for
triggering master processor interrupts, and a general-purpose
function for setting and monitoring system-level digital controls/
conditions.
The ADIS16260 and the ADIS16265 come in a LGA package
(11.2 mm × 11.2mm × 5.5 mm), which supports Pb-free solder
reflow assembly, in accordance with JEDEC J-STD-020. They
have an extended operating temperature range of −40°C to +105°C.
APPLICATIONS
Platform control and stabilization
Navigation
Medical instrumentation
Robotics
FUNCTIONAL BLOCK DIAGRAM
DIO1 DIO2 RST
SELF-TEST
RATE
MEMS
GYROSCOPE
SENSOR
INPUT/
OUTPUT
VCC
ALARMS
POWER
MANAGEMENT
GND
FILT
POWER
SUPPLY
AUX
ADC
VREF
AUX
DAC
CLOCK
USER
CONTROL
REGISTERS
SPI
PORT
FILTER
CALIBRATION
ADIS16260/ADIS16265
CS
OUTPUT
DATA
REGISTERS
SCLK
DIN
DOUT
08246-001
CONTROLLER
TEMPERATURE
SENSOR
Figure 1.
Rev. F
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ADIS16260/ADIS16265
Data Sheet
TABLE OF CONTENTS
Features .............................................................................................. 1
SPI Write Commands ................................................................ 11
Applications ....................................................................................... 1
SPI Read Commands ................................................................. 11
General Description ......................................................................... 1
Memory Map .............................................................................. 12
Functional Block Diagram .............................................................. 1
Processing Sensor Data ............................................................. 13
Revision History ............................................................................... 2
Operational Controls ................................................................. 13
Specifications..................................................................................... 3
Input/Output Functions ............................................................ 15
Timing Specifications .................................................................. 5
Diagnostics .................................................................................. 16
Absolute Maximum Ratings............................................................ 6
Product Identification................................................................ 17
ESD Caution .................................................................................. 6
Applications Information .............................................................. 18
Pin Configuration and Function Descriptions ............................. 7
Assembly...................................................................................... 18
Typical Performance Characteristics ............................................. 8
Bias Optimization....................................................................... 18
Theory of Operation ........................................................................ 9
Interface Printed Circuit Board ................................................ 18
Sensing Element ........................................................................... 9
Outline Dimensions ....................................................................... 20
Data Sampling and Processing ................................................... 9
Ordering Guide .......................................................................... 20
User Interface ................................................................................ 9
Basic Operation .......................................................................... 10
REVISION HISTORY
9/2018—Rev. E to Rev. F
Changes to General Description Section ...................................... 1
Changes to Assembly Section, Interface Printed Circuit Board
Section, and Figure 19 .................................................................... 18
Changes to Ordering Guide .......................................................... 20
1/2014—Rev. D to Rev. E
Change to Table 3 ............................................................................. 6
Change to Bias Optimization Section .......................................... 18
10/2011—Rev. C to Rev. D
Change to Step 9, Bias Optimization Section ............................. 18
5/2011—Rev. B to Rev. C
Changes to Bias Optimization Section ........................................ 18
12/2010—Rev. A to Rev. B
Changes to Equation in Internal Sample Rate Section .............. 13
Changes to Figure 15...................................................................... 14
Changes to Bias Optimization Section ........................................ 18
10/2009—Rev. 0 to Rev. A
Added ADIS16260.............................................................. Universal
Changes to Features List and General Description Section ........1
Changes to Table 1.............................................................................4
Change to Absolute Maximum Ratings Table Section .................6
Changes to Interface Printed Circuit Board Section ................. 18
Changes to Ordering Guide .......................................................... 20
9/2009—Revision 0: Initial Version
Rev. F | Page 2 of 20
Data Sheet
ADIS16260/ADIS16265
SPECIFICATIONS
TA = −40°C to +105°C, VCC = 5.0 V, angular rate = 0°/sec, ±1 g, ±320°/sec range setting, unless otherwise noted.
Table 1.
Parameter
SENSITIVITY 1
Initial Tolerance
Temperature Coefficient
Nonlinearity
BIAS
In-Run Bias Stability
Turn-On-to-Turn-On Bias Stability
Angular Random Walk
Temperature Coefficient
Linear Acceleration Effect
Voltage Sensitivity
NOISE PERFORMANCE
Output Noise
Rate Noise Density
FREQUENCY RESPONSE
3 dB Bandwidth
Sensor Resonant Frequency
SELF-TEST STATE
Change for Positive Stimulus
Change for Negative Stimulus
Internal Self-Test Cycle Time
ADC INPUT
Resolution
Integral Nonlinearity
Differential Nonlinearity
Offset Error
Gain Error
Input Range
Input Capacitance
ON-CHIP VOLTAGE REFERENCE
Accuracy
Temperature Coefficient
Output Impedance
Test Conditions/Comments
Clockwise rotation is positive output
25°C, dynamic range = ±320°/sec 2
25°C, dynamic range = ±160°/sec
25°C, dynamic range = ±80°/sec
25°C, dynamic range = ±320°/sec
ADIS16260
ADIS16265
Best fit straight line
Min
Typ
0.07326
0.03663
0.01832
±0.2
125
25
0.1
Max
Unit
±1
°/sec/LSB
°/sec/LSB
°/sec/LSB
%
ppm/°C
ppm/°C
% of FS
25°C, 1σ
25°C, 1σ
25°C, 1σ
ADIS16260
ADIS16265
Any axis
VCC = 4.75 V to 5.25 V
0.007
0.025
2
0.03
0.005
0.2
0.5
°/sec
°/sec
°/√hour
°/sec/°C
°/sec/°C
°/sec/g
°/sec/V
25°C, ±320°/sec range, no filtering, 50 Hz, 256 SPS
25°C, ±320°/sec range, no filtering, 330 Hz, 2048 SPS
25°C, ±160°/sec range, 4-tap filter setting, 50 Hz
25°C, ±80°/sec range, 16-tap filter setting, 50 Hz
25°C, f = 25 Hz, ±320°/sec range, no filtering
0.4
0.9
0.2
0.1
0.044
°/sec rms
°/sec rms
°/sec rms
°/sec rms
°/sec/√Hz rms
SENS_AVG[7] = 0
SENS_AVG[7] = 1
50
330
14
Hz
Hz
kHz
320°/sec dynamic range setting
320°/sec dynamic range setting
+575
−575
+1100
−1100
25
+1500
−1500
12
±2
±1
±4
±2
0
During acquisition
2.5
20
2.5
25°C
−10
+10
±40
70
Rev. F | Page 3 of 20
LSB
LSB
ms
Bits
LSB
LSB
LSB
LSB
V
pF
V
mV
ppm/°C
Ω
ADIS16260/ADIS16265
Parameter
DAC OUTPUT
Resolution
Relative Accuracy
Differential Nonlinearity
Offset Error
Gain Error
Output Range
Output Impedance
Output Settling Time
LOGIC INPUTS
Input High Voltage, VINH
Input Low Voltage, VINL
Logic 1 Input Current, IINH
Logic 0 Input Current, IINL
All Except RST
RST
Input Capacitance, CIN
DIGITAL OUTPUTS
Output High Voltage, VOH
Output Low Voltage, VOL
SLEEP TIMER
Timeout Period 3
START-UP TIME
Initial Start-Up Time
Sleep Mode Recovery
Flash Update Time
Flash Test Process Time
FLASH MEMORY
Endurance 4
Data Retention 5
CONVERSION RATE
Minimum Conversion Time
Maximum Conversion Time
Maximum Throughput Rate
Minimum Throughput Rate
POWER SUPPLY
Operating Voltage Range, VCC
Power Supply Current
Data Sheet
Test Conditions/Comments
5 kΩ/100 pF to GND
Min
Typ
Max
12
4
1
±5
±0.5
For Code 101 to Code 4095
0
2.5
2
10
Unit
Bits
LSB
LSB
mV
%
V
Ω
µs
Internal 3.3 V interface
2.0
VIH = 3.3 V
VIL = 0 V
±0.2
−40
−1
10
The RST pin has an internal pull-up.
Internal 3.3 V interface
ISOURCE = 1.6 mA
ISINK = 1.6 mA
0.8
±10
−60
2.4
0.5
V
V
128
sec
ms
ms
ms
ms
ms
20,000
10
TJ = 55°C
SMPL_PRD[7:0] = 0x00
SMPL_PRD[7:0] = 0xFF
SMPL_PRD[7:0] = 0x00
SMPL_PRD[7:0] = 0xFF
Cycles
Years
0.488
7.75
2048
0.129
4.75
Low power mode, SMPL_PRD[7:0] ≥ 0x08
Normal mode, SMPL_PRD[7:0] ≤ 0x07
Sleep mode
µA
mA
pF
0.4
165
2.5
50
18
70
Normal mode, SMPL_PRD[7:0] ≤ 0x07
Low power mode, SMPL_PRD[7:0] ≥ 0x08
V
V
µA
5.0
17
41
350
ms
sec
SPS
SPS
5.25
V
mA
mA
µA
ADIS16260/ADIS16265 characterization data represents ±4σ to fall within the ±1% limit.
The maximum guaranteed measurement range is ±320°/sec. The sensor outputs will measure beyond this range, but performance is not assured.
Guaranteed by design.
4
Endurance is qualified as per JEDEC Standard 22, Method A117, and measured at −40°C, +25°C, +85°C, and +125°C.
5
Retention lifetime equivalent at a junction temperature (TJ) of 55°C, as per JEDEC Standard 22, Method A117. Retention lifetime decreases with junction temperature.
1
2
3
Rev. F | Page 4 of 20
Data Sheet
ADIS16260/ADIS16265
TIMING SPECIFICATIONS
TA = −40°C to +85°C, VCC = 5.0 V, unless otherwise noted.
Table 2.
Normal Mode
(SMPL_PRD[7:0] ≤ 0x07, fS ≥ 64 Hz)
Min1
Typ
Max1
0.01
2.5
32
9
48.8
Parameter
fSCLK
tDATARATE
tSTALL
tCS
Description
Serial clock
Data rate period
Stall period between data
Chip select to clock edge
tDAV
Data output valid after SCLK falling
edge2
Data input setup time before SCLK
rising edge
Data input hold time after SCLK
rising edge
Data output fall time
Data output rise time
CS high after SCLK edge3
tDSU
tDHD
tDF
tDR
tSFS
Low Power Mode
(SMPL_PRD[7:0] ≥ 0x08, fS ≤ 56.9 Hz)
Min1
Typ
Max1
0.01
1.0
42
12
48.8
100
100
Unit
MHz
μs
μs
ns
ns
24.4
24.4
ns
48.8
48.8
ns
5
5
12.5
12.5
5
5
5
12.5
12.5
ns
ns
ns
5
1
Guaranteed by design; not production tested.
The MSB presents an exception to this parameter. The MSB clocks out on the falling edge of CS. The rest of the DOUT bits are clocked after the falling edge of SCLK and
are governed by this specification.
3
This parameter may need to be expanded to allow for proper capture of the LSB. After CS goes high, the DOUT line goes into a high impedance state.
2
Timing Diagrams
tDATARATE
CS
08246-002
SCLK
tSTALL
Figure 2. SPI Chip Select Timing
CS
tCS
tSFS
1
SCLK
2
3
4
5
6
15
16
tDAV
*
MSB
DB14
DB13
tDSU
DIN
R/W
DB12
DB11
A4
A3
DB10
DB2
DB1
LSB
tDHD
A5
A2
D2
D1
*NOT DEFINED
Figure 3. SPI Timing (Using SPI Settings Typically Identified as CPOL = 1, CPHA = 1)
Rev. F | Page 5 of 20
LSB
08246-003
DOUT
ADIS16260/ADIS16265
Data Sheet
ABSOLUTE MAXIMUM RATINGS
Stresses at or above those listed under Absolute Maximum
Ratings may cause permanent damage to the product. This is a
stress rating only; functional operation of the product at these
or any other conditions above those indicated in the operational
section of this specification is not implied. Operation beyond
the maximum operating conditions for extended periods may
affect product reliability.
Table 3.
Parameter
Acceleration
Any Axis, Unpowered, 0.5 ms
Any Axis, Powered, 0.5 ms
VCC to GND
Digital Input/Output Voltage to GND
Analog Inputs to GND
Operating Temperature Range1
Storage Temperature Range1
1
Rating
2000 g
2000 g
−0.3 V to +6.0 V
−0.3 V to +5.3 V
−0.3 V to +3.5 V
−40°C to +125°C
−65°C to +150°C
ESD CAUTION
Extended exposure to temperatures outside the temperature range of −40°C
to +85°C can adversely affect the accuracy of the factory calibration. For best
accuracy, store the part within the temperature range of −40°C to +85°C.
Rev. F | Page 6 of 20
Data Sheet
ADIS16260/ADIS16265
PIN CONFIGURATION AND FUNCTION DESCRIPTIONS
VREF GND GND VCC VCC
1
DOUT
2
DIN
3
CS
4
DIO1
5
19
18
17
16
ADIS16260/
ADIS16265
TOP VIEW
(Not to Scale)
POSITIVE OUTPUT
ROTATIONAL
DIRECTION
6
7
8
9
15
FILT
14
RATE
13
AUX
ADC
12
AUX
DAC
11
DNC
10
DIO2 RST DNC DNC DNC
NOTES
1. DNC = DO NOT CONNECT.
2. THE PINS CANNOT BE SEEN FROM THE TOP.
THIS LOOK-THOUGH VIEW OF THEIR LOCATION
IS OFFERED FOR REFERENCE IN DEVELOPING
PCB PATTERNS.
08246-005
20
SCLK
Figure 4. Pin Configuration
AXIS OF ROTATION
PIN 10
PIN 1
PIN 6
NOTES
1. ARROW INDICATES THE DIRECTION OF ROTATION
THAT PRODUCES A POSITIVE RESPONSE IN
THE GYRO_OUT REGISTER.
08246-022
PIN 5
Figure 5. Axial Orientation
Table 4. Pin Function Descriptions
Pin No.
1
2
3
4
5, 6
7
8, 9, 10, 11
12
13
14
15
16, 17
18, 19
20
1
Mnemonic
SCLK
DOUT
DIN
CS
DIO1, DIO2
RST
DNC
AUX DAC
AUX ADC
RATE
FILT
VCC
GND
VREF
Type 1
I
O
I
I
I/O
I
O
I
O
I
S
S
O
Description
SPI Serial Clock.
SPI Data Output. Clocks output on SCLK falling edge.
SPI Data Input. Clocks input on SCLK rising edge.
SPI Chip Select. Active low.
Configurable Digital Input/Output.
Reset. Active low.
Do Not Connect.
Auxiliary DAC Output.
Auxiliary ADC Input.
Rate Output. For bandwidth reduction only; output is not specified.
Filter Terminal.
5.0 V Power Supply.
Ground.
Precision Reference Output.
I = input, I/O = input/output, O = output, S = supply.
Rev. F | Page 7 of 20
ADIS16260/ADIS16265
Data Sheet
TYPICAL PERFORMANCE CHARACTERISTICS
0.1
MEAN
+1σ
0.01
–1σ
0.001
0.1
1
10
100
Tau (Seconds)
1k
08246-020
ROOT ALLAN VARIANCE (°/sec)
1
Figure 6. Gyroscope Allan Variance
Rev. F | Page 8 of 20
Data Sheet
ADIS16260/ADIS16265
THEORY OF OPERATION
SENSING ELEMENT
The sensing element operates on the principle of a resonator
gyro. Two polysilicon sensing structures each contain a dither
frame that is electrostatically driven to resonance, producing
the necessary velocity element to produce a Coriolis force during
angular rate. At two of the outer extremes of each frame,
orthogonal to the dither motion, movable fingers are placed
between fixed pickoff fingers to form a capacitive pickoff
structure that senses Coriolis motion. The resulting signal is fed
into a series of gain and demodulation stages that produce the
electrical rate signal output. The differential structure minimizes
the response to linear acceleration (gravity, vibration, and so
on) and to EMI.
DATA SAMPLING AND PROCESSING
The ADIS16260 and the ADIS16265 run autonomously, based
on the configuration in the user control registers. The analog
gyroscope signal feeds into an analog-to-digital converter
(ADC) stage, which passes digitized data into the controller for
data processing and register loading. Data processing in the
embedded controller includes correction formulas, filtering,
and checking for preset alarm conditions. The correction formulas
are unique for each individual ADIS16260/ADIS16265 and come
from the factory characterization of each device over a
temperature range of −40°C to +85°C.
SPI Interface
Data collection and configuration commands both use the SPI,
which consists of four wires. The chip select (CS) signal activates
the SPI interface, and the serial clock (SCLK) signal synchronizes
the serial data lines. The serial input data clocks into DIN on
the SCLK rising edge, and the serial output data clocks out of
DOUT on the SCLK falling edge. Many digital processor platforms support this interface with dedicated serial ports and
simple instruction sets.
User Registers
The user registers provide addressing for all input/output
operations on the SPI interface. Each 16-bit register has its
own unique bit assignment and has two 7-bit addresses: one
for its upper byte and one for its lower byte. Table 7 provides a
memory map of the user registers, along with the function of
each register.
The control registers use a dual memory structure. The SRAM
controls operation while the part is on and facilitates all user
configuration inputs. The flash memory provides nonvolatile
storage for control registers that have flash backup (see Table 7).
Storing configuration data in the flash memory requires a separate
command (GLOB_CMD[3] = 1, DIN = 0xBE08). When the
device powers on or resets, the flash memory contents are
loaded into the SRAM, and the device then starts producing
data according to the configuration in the control registers.
MANUAL
FLASH
BACKUP
NONVOLATILE
FLASH MEMORY
CONTROLLER
CONTROL
REGISTERS
AIN
SIGNALS
CLOCK
VOLATILE
SRAM
(NO SPI ACCESS)
SPI SIGNALS
ADC
SPI PORT
SPI PORT
OUTPUT
REGISTERS
SPI ACCESS
STARTUP
OR RESET
Figure 8. SRAM and Flash Memory Diagram
08246-007
MEMS
SENSOR
TEMP
SENSOR
USER INTERFACE
Figure 7. Simplified Sensor Signal Processing Diagram
Rev. F | Page 9 of 20
08246-008
The ADIS16260 and the ADIS16265 integrate a MEMS gyroscope
with data sampling, signal processing, and calibration functions,
along with a simple user interface. This sensing system collects
data autonomously and makes it available to any processor system
that supports a 4-wire serial peripheral interface (SPI).
ADIS16260/ADIS16265
Data Sheet
BASIC OPERATION
The ADIS16260 and the ADIS16265 SPI interface supports fullduplex serial communication (simultaneous transmit and
receive) and uses the bit sequence shown in Figure 11. Processor
platforms typically support SPI communication with generalpurpose serial ports that require some configuration in their
control registers. Table 6 provides a list of the most common
settings that require attention to initialize the serial port of a
processor for communication with the ADIS16260 and the
ADIS16265.
The ADIS16260 and the ADIS16265 require only power, ground,
and the four SPI signals to produce data and make it available
to an embedded processor. Figure 9 provides a schematic for
connecting the ADIS16260 and the ADIS16265 to a SPIcompatible processor and includes one of the configurable
digital I/O lines. The MSC_CTRL[2:0] bits are used to configure
this line as a data ready indicator (see the Data Ready I/O
Indicator section).
INPUT/OUTPUT LINES ARE COMPATIBLE
WITH 3.3V OR 5V LOGIC LEVELS
Table 6. Generic Master Processor SPI Settings
5V
Processor Setting
Master
VDD
4 CS
SS
SCLK
16
17
VCC
VCC
SCLK Rate ≤ 2.5 MHz
SPI Mode 3
MSB First Mode
16-Bit Mode
1 SCLK
SYSTEM
PROCESSOR MOSI
SPI MASTER
3 DIN
ADIS16260/
ADIS16265
SPI SLAVE
2 DOUT
5 DIO1
IRQ
GND
GND
18
19
User registers govern all data collection and configuration.
Table 7 provides a memory map that includes all user registers,
along with references to the bit assignment tables that follow the
generic bit assignments in Figure 10.
08246-009
MISO
Description
The ADIS16260 and the ADIS16265
operate as slaves
Bit rate setting (SMPL_PRD[7:0] ≤ 0x07)
Clock polarity, phase (CPOL = 1, CPHA = 1)
Bit sequence
Shift register/data length
15
Table 5. Generic Master Processor Pin Names and Functions
Pin Name
SS
IRQ
MOSI
MISO
SCLK
14
13
12
11
10
9
8
7
6
5
UPPER BYTE
Function
Slave select
Interrupt request input
Master output, slave input
Master input, slave output
Serial clock
4
3
LOWER BYTE
Figure 10. Generic Register Bit Definitions
CS
SCLK
DOUT
R/W
DB15
A6
A5
A4
A3
A2
A1
DB14 DB13 DB12 DB11 DB10 DB9
A0
D7
D6
D5
D4
D3
D2
D1
D0
DB8
DB7
DB6
DB5
DB4
DB3
DB2
DB1
DB0
NOTES
1. DOUT BITS ARE BASED ON THE PREVIOUS 16-BIT SEQUENCE (R/W = 0).
Figure 11. SPI Communication Bit Sequence
Rev. F | Page 10 of 20
R/W
DB15
A6
A5
DB14 DB13
08246-013
DIN
2
1
0
08246-010
Figure 9. Electrical Connection Diagram
Data Sheet
ADIS16260/ADIS16265
SPI WRITE COMMANDS
SPI READ COMMANDS
Master processors write to the control registers, one byte
at a time, using the bit sequence shown in Figure 11. Some
configurations require writing both bytes to a register, which
takes two separate 16-bit sequences, whereas others require
only one byte. The programmable registers in Table 7 provide
controls for optimizing sensor operation and for starting various
automated functions. For example, to start an automatic bias
null sequence, set GLOB_CMD[0] = 1 by writing 0xBE01 to the
SPI transmit register of the master processor, which feeds the
DIN line. The process starts immediately after the last bit clocks
into DIN (16th SCLK rising edge).
Reading data through the SPI requires two consecutive 16-bit
sequences, separated by an appropriate stall time (see Figure 2).
The first sequence transmits the read command and address on
DIN, and the second receives the resulting data from DOUT. The
7-bit register address can represent either the upper or lower byte
address for the target register. For example, when reading the
GYRO_OUT register, the address can be either 0x04 or 0x05.
Figure 13 provides a full-duplex mode example of reading the
GYRO_OUT register. In addition, the second SPI segment sets
the device up to read TEMP_OUT on the following SPI segment
(not shown in Figure 13).
CS
08246-011
SCLK
DIN
Figure 12. SPI Sequence for Autonull (DIN = 0xBE01)
CS
SPI SEGMENT 1
SPI SEGMENT 2
SCLK
DOUT
DIN = 0x0400 PRODUCES GYRO_OUT CONTENTS ON
DOUT DURING THE NEXT SPI SEGMENT
DOUT = 0x822B = 21.9047°/sec, NEW DATA, NO ALARM
Figure 13. Example SPI Read Sequence (±320°/sec Range Setting)
Rev. F | Page 11 of 20
08246-012
DIN
ADIS16260/ADIS16265
Data Sheet
MEMORY MAP
All unused memory locations are reserved for future use.
Table 7. User Register Memory Map
Name
FLASH_CNT
SUPPLY_OUT
GYRO_OUT
Access
Read only
Read only
Read only
Flash
Backup
Yes
No
No
AUX_ADC
TEMP_OUT
ANGL_OUT
Read only
Read only
Read/write
No
No
No
GYRO_OFF
GYRO_SCALE
Read/write
Read/write
Yes
Yes
ALM_MAG1
ALM_MAG2
ALM_SMPL1
ALM_SMPL2
ALM_CTRL
Read/write
Read/write
Read/write
Read/write
Read/write
Yes
Yes
Yes
Yes
Yes
AUX_DAC
GPIO_CTRL
MSC_CTRL
SMPL_PRD
SENS_AVG
SLP_CNT
DIAG_STAT
GLOB_CMD
Read/write
Read/write
Read/write
Read/write
Read/write
Read/write
Read only
Write only
No
No
Yes
Yes
Yes
Yes
No
No
LOT_ID1
LOT_ID2
PROD_ID
Read only
Read only
Read only
SERIAL_NUM
Read only
1
Default
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
0x0000
0x0800
N/A
0x0000
0x0000
0x0000
0x0000
0x0000
N/A
Register Description
Flash memory write count
Output, power supply measurement
Output, rate of rotation measurement
Reserved
Output, analog input channel measurement
Output, internal temperature measurement
Output, angle displacement
Reserved
Calibration, offset/bias adjustment
Calibration, scale adjustment
Reserved
Alarm 1 magnitude/polarity setting
Alarm 2 magnitude/polarity setting
Alarm 1 dynamic rate of change setting
Alarm 2 dynamic rate of change setting
Alarm control register
Reserved
Yes
Yes
Yes
Address 1
0x00
0x02
0x04
0x06 to 0x09
0x0A
0x0C
0x0E
0x10 to 0x13
0x14
0x16
0x18 to 0x1F
0x20
0x22
0x24
0x26
0x28
0x2A to
0x2F
0x30
0x32
0x34
0x36
0x38
0x3A
0x3C
0x3E
0x40 to 0x51
0x52
0x54
0x56
0x0000
N/A
0x0000
0x0001
0x0402
0x0000
N/A
N/A
N/A
N/A
N/A
0x3F89/0x3F84
Yes
0x58
N/A
Control, DAC output voltage setting
Control, digital I/O line
Control, data ready, self-test settings
Control, internal sample rate
Control, dynamic range, filtering
Control, sleep mode initiation
Diagnostic, error flags
Control, global commands
Reserved
Lot Identification Code 1
Lot Identification Code 2
Product identifier; convert to decimal =
16,265/16,260
Serial number
Bit
Assignments
See Table 9
See Table 10
See Table 13
See Table 12
See Table 11
See Table 16
See Table 17
See Table 26
See Table 26
See Table 27
See Table 27
See Table 28
See Table 22
See Table 20
See Table 21
See Table 14
See Table 15
See Table 19
See Table 25
See Table 18
See Table 31
See Table 31
See Table 31
See Table 31
Each register contains two bytes. The address of the lower byte is displayed. The address of the upper byte is equal to the address of the lower byte plus 1.
Rev. F | Page 12 of 20
Data Sheet
ADIS16260/ADIS16265
PROCESSING SENSOR DATA
Table 11. ANGL_OUT Data Format Examples
Table 8 provides a summary of the output data registers, which
use the bit pattern shown in Figure 14. The ND bit is equal to 1
when the register contains unread data. The EA bit is high when
any error/alarm flag in the DIAG_STAT register is equal to 1.
Angle1
359.9630°
359.9264°
0.36630°
0.03663°
0°
MSB FOR 12-BIT OUTPUT
08246-021
MSB FOR 14-BIT OUTPUT
ND EA
1
Decimal
9827 LSB
9826 LSB
10 LSB
1 LSB
0 LSB
Hex
0x2663
0x2662
0x000A
0x0001
0x0000
Binary Output
10 0110 0110 0011
10 0110 0110 0010
00 0000 0000 1010
00 0000 0000 0001
00 0000 0000 0000
359.963° + 1 LSB is equal to 0x0000.
Figure 14. Output Register Bit Assignments
Table 12. TEMP_OUT Data Format Examples
Table 8. Output Data Register Formats
Register
SUPPLY_OUT
GYRO_OUT1
ANGL_OUT
TEMP_OUT2
AUX_ADC
1
2
Bits
12
14
14
12
12
Scale
1.8315 mV
0.07326°/sec
0.03663°
0.1453°C
610.5 μV
Temperature
+105°C
+25.1453°C
+25°C
+24.8547°C
−40°C
Reference
See Table 9
See Table 10
See Table 11
See Table 12
See Table 13
Assumes that the scaling is set to ±320°/sec. This factor scales with the range.
0x0000 = 25°C (±5°C).
Table 9. SUPPLY_OUT Data Format Examples
Supply Voltage (V)
5.25
5.0 + 0.00183
5.0
5.0 − 0.00183
4.75
Decimal
2867 LSB
2731 LSB
2730 LSB
2729 LSB
2594 LSB
Hex
0xB33
0xAAB
0xAAA
0xAA9
0xA22
Binary Output
1011 0011 0011
1010 1010 1011
1010 1010 1010
1010 1010 1001
1010 0010 0010
Table 10. GYRO_OUT Data Format Examples
Rotation Rate
(°/sec)1
+320
+0.07326
0
−0.07326
−320
1
Decimal
+4368 LSB
+1 LSB
0 LSB
−1 LSB
−4368 LSB
Hex
0x1110
0x0001
0x0000
0x3FFF
0x2EF0
Binary Output
01 0001 0001 0000
00 0000 0000 0001
00 0000 0000 0000
11 1111 1111 1111
10 1110 1111 0000
For the ±320°/sec setting, rate values scale with the range setting.
Decimal
+551 LSB
+1 LSB
0 LSB
−1 LSB
−447 LSB
Hex
0x227
0x001
0x000
0xFFF
0xE41
Binary Output
0010 0010 0111
0000 0000 0001
0000 0000 0000
1111 1111 1111
1110 0100 0001
Table 13. AUX_ADC Data Format Examples
Input (mV)
2500
1200
0.6105
0
Decimal
4095 LSB
1966 LSB
1 LSB
0 LSB
Hex
0xFFF
0x7AE
0x001
0x000
Binary Output
1111 1111 1111
0111 1010 1110
0000 0000 0001
0000 0000 0000
OPERATIONAL CONTROLS
Internal Sample Rate
The SMPL_PRD register controls the internal sample rate using the
bit assignments in Table 14. When SMPL_PRD[7:0] = 0x00, the
internal sample rate is 2048 SPS. When SMPL_PRD[7:0] ≥ 0x01,
use the bit definitions in Table 14 and the following equation to
calculate the sample rate.
fS
1
1
t S t B (N S 1)
Table 14. SMPL_PRD Bit Descriptions
Bits
[15:8]
7
[6:0]
Rev. F | Page 13 of 20
Description (Default = 0x0001)
Not used
Time base (tB): 0 = 1.953 ms, 1 = 60.54 ms
Increment setting (NS)
ADIS16260/ADIS16265
Data Sheet
Sensor Bandwidth
Dynamic Range
The gyroscope signal chain has several filter stages that shape
its frequency response. Figure 15 provides a block diagram of
each filter stage and Table 15 lists the SENS_AVG register
controls for bandwidth.
The SENS_AVG[10:8] bits provide three dynamic range settings
for this gyroscope. The lower dynamic range settings (±80°/sec
and ±160°/sec) limit the minimum filter tap sizes to maintain
resolution. For example, set SENS_AVG[10:8] = 010 (DIN =
0xB902) for a measurement range of ±160°/sec. Because this
setting can influence the filter settings, program SENS_AVG[10:8]
and then SENS_AVG[2:0] if more filtering is required.
Ce
FILT
N
740Hz
N = 2m
m = SENS_AVG[2:0]
1
× R × CT
fC =
Calibration
N
2
R = 90kΩ
CT = CINT + Ce
The GYRO_OFF and GYRO_SCALE registers provide user
controls for making in-system adjustments to offset and scale
factor.
FROM INTERNAL
PROCESSING
Figure 15. Signal Processing Diagram
Table 15. SENS_AVG Bit Descriptions
Bits
[15:11]
[10:8]
Description (Default = 0x0402)
Not used.
Measurement range (sensitivity) selection.
100 = ±320°/sec (default condition).
010 = ±160°/sec, filter taps ≥ 4 (Bits[2:0] ≥ 0x02).
001 = ±80°/sec, filter taps ≥ 16 (Bits[2:0] ≥ 0x04).
Primary pole setting (k).
1: CINT = 0.0047 μF (bandwidth = 330 Hz).
0: CINT = 0.0377 μF (bandwidth = 50 Hz).
Not used.
Number of taps in each stage; value of m in N = 2m.
7
[6:3]
[2:0]
GYRO_OFF
Table 16. GYRO_OFF Bit Descriptions
Bits
[15:12]
[11:0]
Bits
[15:12]
[11:0]
–20
–60
–80
–100
N=2
N=4
N = 16
N = 64
0.01
0.1
FREQUENCY (f/fS)
1
08246-015
MAGNITUDE (dB)
–40
–140
0.001
Description (Default = 0x0000)
Not used.
Offset adjustment factor, twos complement format,
0.018315°/sec per LSB.
Examples follow:
0x000: Add 0°/sec to gyroscope data.
0x001: Add 0.018315°/sec to gyroscope data.
0x0AA: Add 3.11355°/sec to gyroscope data.
0xF0F: Subtract 4.41392°/sec from gyroscope data.
0xFFF: Subtract 0.018315°/sec from gyroscope data.
Table 17. GYRO_SCALE Bit Descriptions
0
–120
GYRO_SCALE
Figure 17. User Calibration Registers
Digital Filtering
A programmable low-pass filter provides additional opportunity
for noise reduction on the inertial sensor outputs. This filter
contains two cascaded averaging filters that provide a Bartlett
window, FIR filter response (see Figure 16). For example, set
SENS_AVG[2:0] = 100 (DIN = 0xB804) to set each stage to 16
taps. When used with the default sample rate of 256 SPS, this
reduces the bandwidth of the digital filter to approximately 5.2 Hz.
TO OUTPUT
REGISTERS
08246-016
fC
08246-014
RATE
FROM
GYRO
SENSOR
Figure 16. Digital Filter Frequency, Bartlett Window FIR Filter
(Phase = N Samples)
Rev. F | Page 14 of 20
Description (Default = 0x0800)
Not used.
Scale adjustment factor, offset binary format,
0.00048828/LSB.
Examples follow:
0x000: Multiply output by 0.
0x7F0: Multiply gyroscope data by 0.99218.
0x800: Multiply output by 1.
0x8A0: Multiply output by 1.077812.
0xFFF: Multiply output by 1.9995.
Data Sheet
ADIS16260/ADIS16265
Global Commands
Data Ready I/O Indicator
The GLOB_CMD register provides trigger bits for several
functions. Setting the assigned bit to 1 starts each operation,
which returns the bit to 0 after completion. For example, set
GLOB_CMD[7] = 1 (DIN = 0xBE80) to execute a software
reset, which stops the sensor operation and runs the device
through its start-up sequence. This sequence includes loading
the control registers with the contents of their respective flash
memory locations prior to producing new data.
The MSC_CTRL[2:0] bits configure one of the digital I/O lines
as a data ready signal for driving an interrupt. For example, set
MSC_CTRL[2:0] = 100 (DIN = 0xB404) to configure DIO1 as
a negative-pulse data ready signal. The pulse width is between
100 µs and 200 µs over all conditions.
Table 18. GLOB_CMD Bit Descriptions
Bits
[15:8]
7
[6:4]
3
2
1
0
Description
Not used.
Software reset command.
Not used.
Flash update command.
Auxiliary DAC data latch.
Factory calibration restore command.
Autonull command.
9
8
[7:3]
2
Setting SMPL_PRD[7:0] ≥ 0x08 also sets the sensor to low
power mode. For systems that require lower power dissipation,
in-system characterization helps users to quantify the associated
performance trade-offs. In addition to sensor performance, low
power mode affects SPI data rates (see Table 2). Use SLP_CNT[7:0]
to put the device into sleep mode for a specified period. For
example, SLP_CNT[7:0] = 0x64 (DIN = 0xBA64) puts the
ADIS16260 and ADIS16265 to sleep for 50 seconds.
Table 19. SLP_CNT Bit Descriptions
Description (Default = 0x0000)
Not used.
Programmable sleep time bits, 0.5 sec/LSB.
INPUT/OUTPUT FUNCTIONS
DIO1 and DIO2 are configurable, general-purpose I/O lines
that serve multiple purposes according to the following control
register priority: MSC_CTRL, ALM_CTRL, and GPIO_CTRL.
For example, set GPIO_CTRL = 0x0202 (DIN = 0xB302, and
then 0xB202) to configure DIO1 as an input and DIO2 as an
output set high.
Table 20. GPIO_CTRL Bit Descriptions
0
1
0
Description (Default = 0x0000)
Not used.
Memory test (cleared upon completion).
1 = enabled, 0 = disabled.
Internal self-test enable (cleared upon completion).
1 = enabled, 0 = disabled.
Manual self-test, negative stimulus.
1 = enabled, 0 = disabled.
Manual self-test, positive stimulus.
1 = enabled, 0 = disabled.
Not used.
Data ready enable.
1 = enabled, 0 = disabled.
Data ready polarity.
1 = active high, 0 = active low.
Data ready line select.
1 = DIO2, 0 = DIO1.
Auxiliary DAC
The 12-bit AUX_DAC line can drive its output to within 5 mV
of the ground reference when it is not sinking current. As the
output approaches 0 V, the linearity begins to degrade (~100 LSB
starting point). As the sink current increases, the nonlinear
range increases. The DAC latch command moves the values of
the AUX_DAC register into the DAC input register, enabling
both bytes to take effect at the same time.
Table 22. AUX_DAC Bit Descriptions
General-Purpose I/O
Bits
[15:10]
9
8
[7:2]
1
Bits
[15:12]
11
10
Power Management
Bits
[15:8]
[7:0]
Table 21. MSC_CTRL Bit Descriptions
Description
Not used.
General-Purpose I/O Line 2 (DIO2) data level.
General-Purpose I/O Line 1 (DIO1) data level.
Not used.
General-Purpose I/O Line 2 (DIO2) direction control.
1 = output, 0 = input.
General-Purpose I/O Line 1 (DIO1) direction control.
1 = output, 0 = input.
Bits
[15:12]
[11:0]
Description (Default = 0x0000)
Not used.
Data bits, scale factor = 0.6105 mV/code.
Offset binary format, 0 V = 0 codes.
Table 23. Setting AUX_DAC = 2 V
DIN
0xB0CC
0xB10C
0xBE04
Rev. F | Page 15 of 20
Description
AUX_DAC[7:0] = 0xCC (204 LSB).
AUX_DAC[15:8] = 0x0C (3072 LSB).
GLOB_CMD[2] = 1.
Move values into the DAC input register, resulting in
a 2 V output level.
ADIS16260/ADIS16265
Data Sheet
Status
DIAGNOSTICS
Self-Test
The self-test function allows the user to verify the mechanical
integrity of each MEMS sensor. It applies an electrostatic force to
each sensor element, which results in mechanical displacement
that simulates a response to actual motion. Table 1 lists the
expected response for each sensor, which provides pass/fail
criteria.
Set MSC_CTRL[10] = 1 (DIN = 0xB504) to run the internal
self-test routine, which exercises the inertial sensor, measures
the response, makes a pass/fail decision, reports the decision to
error flags in the DIAG_STAT register, and then restores normal
operation. MSC_CTRL[10] resets itself to 0 after completing the
routine. The MSC_CTRL[9:8] bits provide manual control of the
self-test function for investigation of potential failures. Table 24
outlines an example test flow for using this option to verify the
gyroscope function.
Table 24. Manual Self-Test Example Sequence
DIN
0xB601
0xB904
0xB802
0x0400
0xB502
0x0400
0xB501
0x0400
0xB500
Description
SMPL_PRD[7:0] = 0x01, sample rate = 256 SPS.
SENS_AVG[15:8] = 0x04, gyroscope range =
±320°/sec.
SENS_AVG[7:0] = 0x02, four-tap averaging filter.
Delay = 50 ms.
Read GYRO_OUT.
MSC_CTRL[9:8] = 10, gyroscope negative self-test.
Delay = 50 ms.
Read GYRO_OUT.
Determine whether the bias in the gyroscope
output changed according to the self-test
response specified in Table 1.
MSC_CTRL[9:8] = 01, gyroscope/accelerometer
positive self-test.
Delay = 50 ms.
Read GYRO_OUT.
Determine whether the bias in the gyroscope
output changed according to the self-test
response specified in Table 1.
MSC_CTRL[15:8] = 0x00.
The error flags provide indicator functions for common
system level issues. All of the flags are cleared (set to 0) after
each DIAG_STAT register read cycle. If an error condition
remains, the error flag returns to 1 during the next sample
cycle. DIAG_STAT[1:0] does not require a read of this register
to return to 0. If the power supply voltage goes back into range,
these two flags are cleared automatically.
Table 25. DIAG_STAT Bit Descriptions
Bits
[15:10]
9
8
7
6
5
4
3
2
1
0
Description
Not used.
Alarm 2 status (1 = active, 0 = inactive).
Alarm 1 status (1 = active, 0 = inactive).
Not used.
Flash test, checksum flag (1 = fail, 0 = pass).
Self-test diagnostic error flag (1 = fail, 0 = pass).
Sensor overrange (1 = fail, 0 = pass).
SPI communication failure (1 = fail, 0 = pass).
Flash update failure (1 = fail, 0 = pass).
Power supply > 5.25 V.
1 = power supply > 5.25 V, 0 = power supply ≤ 5.25 V.
Power supply < 4.75 V.
1 = power supply < 4.75 V, 0 = power supply ≥ 4.75 V.
Alarm Registers
The alarm function provides monitoring for two independent
conditions. The ALM_CTRL register provides control inputs
for data source, data filtering (prior to comparison), static
comparison, dynamic rate-of-change comparison, and output
indicator configurations. The ALM_MAGx registers establish
the trigger threshold and polarity configurations. Table 29 gives
an example of how to configure a static alarm. The ALM_SMPLx
registers provide the numbers of samples to use in the dynamic
rate-of-change configuration. The period equals the number in
the ALM_SMPLx register multiplied by the sample period time,
which is established by the SMPL_PRD register. See Table 30 for
an example of how to configure the sensor for this type of function.
Table 26. ALM_MAG1, ALM_MAG2 Bit Descriptions
Zero motion provides results that are more reliable. The settings
in Table 24 are flexible and allow for optimization around speed
and noise influence. For example, using fewer filtering taps
decreases delay times but increases the potential for noise
influence.
Bits
15
14
[13:0]
Memory Test
Table 27. ALM_SMPL1, ALM_SMPL2 Bit Descriptions
Setting MSC_CTRL[11] = 1 (DIN = 0xB508) performs a checksum
comparison between the flash memory and SRAM to help
verify memory integrity. The pass/fail result is loaded into the
DIAG_STAT[6] register.
Bits
[15:8]
[7:0]
Rev. F | Page 16 of 20
Description (Default = 0x0000)
Comparison polarity (1 = greater than, 0 = less than).
Not used.
Data bits that match the format of the trigger source
selection.
Description (Default = 0x0000)
Not used.
Data bits: number of samples (both 0x00 and 0x01 = 1).
Data Sheet
ADIS16260/ADIS16265
Table 28. ALM_CTRL Bit Descriptions
Table 30. Alarm Configuration Example 2
Bits
15
DIN
0xA9AA, 0xA804
3
2
Description (Default = 0x0000)
Rate-of-change enable for Alarm 2 (1 = rate of change,
0 = static level).
Alarm 2 source selection.
000 = disable.
001 = power supply output.
010 = gyroscope output.
011 = not used.
100 = not used.
101 = auxiliary ADC input.
110 = temperature output.
111 = not used.
Rate-of-change enable for Alarm 1 (1 = rate of change,
0 = static level).
Alarm 1 source selection (same as for Alarm 2).
Not used.
Comparison data filter setting (1 = filtered data, 0 =
unfiltered data).
Not used.
Alarm output enable (1 = enabled, 0 = disabled).
1
0
Alarm output polarity (1 = active high, 0 = active low).
Alarm output line select (1 = DIO2, 0 = DIO1).
[14:12]
11
[10:8]
[7:5]
4
Table 29. Alarm Configuration Example 1
DIN
0xA922, 0xA817
0xA181, 0xA000
0xA33F, 0xA200
Description
ALM_CTRL = 0x2217.
Alarm 1 input = GYRO_OUT.
Alarm 2 input = GYRO_OUT.
Static level comparison, filtered data.
DIO2 output indicator, positive polarity.
ALM_MAG1 = 0x8100.
Alarm 1 is true if GYRO_OUT > +18.755°/sec.
ALM_MAG2 = 0x3F00.
Alarm 2 is true if GYRO_OUT < −18.755°/sec.
0xB601
0xA40A
0xA60A
0xA181, 0xA000
0xA30F, 0xA200
Description
ALM_CTRL = 0xAA04.
Alarm 1 input = GYRO_OUT.
Alarm 2 input = GYRO_OUT.
Rate-of-change comparison, unfiltered data.
DIO1 output indicator, negative polarity.
SMPL_PRD = 0x0001.
Sample rate = 256 SPS.
ALM_SMPL1[7:0] = 0x000A.
Alarm 1 rate of change period = 3.906 ms.
ALM_SMPL2[7:0] = 0x000A.
Alarm 2 rate of change period = 3.906 ms.
ALM_MAG1 = 0x8100.
Alarm 1 is true if GYRO_OUT changes more
than 18.755°/sec over a period of 3.906 ms.
ALM_MAG2 = 0x0F00.
Alarm 2 is true if GYRO_OUT changes less
than 18.755°/sec over a period of 3.906 ms.
PRODUCT IDENTIFICATION
Table 31 provides a summary of the registers that identify
the product: PROD_ID, which identifies the product type;
LOT_ID1 and LOT_ID2, the 32-bit lot identification code;
and SERIAL_NUM, which displays the 16-bit serial number.
All four registers are two bytes in length.
Table 31. Identification Registers
Register Name
LOT_ID1
LOT_ID2
PROD_ID
Address
0x52
0x54
0x56
SERIAL_NUM
0x58
Rev. F | Page 17 of 20
Description
Lot Identification Code 1
Lot Identification Code 2
Product identification = 0x3F89 or
0x3F84
(0x3F89 = 16,265 decimal; 0x3F84 =
16,260 decimal)
Serial number
ADIS16260/ADIS16265
Data Sheet
APPLICATIONS INFORMATION
ASSEMBLY
When developing a process flow for installing ADIS16260/
ADIS16265 devices on printed circuit boards (PCBs), see
the JEDEC J-STD-020C standard document for the reflow
temperature profile and processing information. The ADIS16260/
ADIS16265 can use the Sn-Pb eutectic process and the Pb-free
eutectic process from this standard, with one exception, the
peak temperature exposure is 240°C. For a more complete list
of assembly process suggestions, see the ADIS162xx LGA
Assembly Guidelines page on Engineer Zone. Figure 18
provides an example pattern for the location of the
ADIS16260/ADIS16265 on a printed circuit board.
5.0865
8×
0.773
16×
10.173
2×
The Allan Variance curve in Figure 6 provides a trade-off
relationship between accuracy and averaging time. For example,
an average time of 1 second produce an accuracy of ~0.035 °/sec
(1 σ).
INTERFACE PRINTED CIRCUIT BOARD
The ADIS16265/PCBZ includes one ADIS16265BCCZ IC on a
1.2 inch × 1.3 inch PCB. The interface PCB simplifies the IC
connection of these devices to an existing processor system. The
four mounting holes accommodate either M2 (2 mm) or 2-56
machine screws. These boards are made of IS410 material and
are 0.063 inches thick. The second-level assembly uses a
SAC305-compatible solder composition, which has a presolder
reflow thickness of approximately 0.005 inches.
The pad pattern on these PCBs matches that shown in Figure 20.
J1 and J2 are dual-row, 2 mm (pitch) connectors that work with
a number of ribbon cable systems, including 3M Part Number
152212-0100-GB (ribbon crimp connector) and 3M Part Number
3625/12 (ribbon cable). The schematic and connector pin
assignments for the ADIS16265/PCBZ are shown in Figure 19.
7.600
4×
08246-006
0.500
20×
1.127
20×
Multiply by −1.
Write to GYRO_OFF.
Update flash, set GLOB_CMD[3] = 1 (DIN = 0xBE08), and
wait for >50 ms and resume operation.
1
2
11mm × 11mm STACKED LGA PACKAGE
3
Figure 18. Recommended Pad Layout (Units in Millimeters)
4
5
BIAS OPTIMIZATION
6
Use the following steps to fine-tune the bias to an accuracy that
approaches the in-run bias stability, 0.007°/sec (1 σ).
1.
2.
3.
4.
5.
6.
Apply 5 V and wait 10 sec.
Set SENS_AVG[10:8] = 001 (DIN = 0xB901).
Set GYRO_OFF = 0x0000
(DIN = 0x9400, DIN = 0x9500).
Collect GYRO_OUT data for 150 sec at a sample rate of
256 SPS.
Average data record.
Round to the nearest integer.
Rev. F | Page 18 of 20
7
8
9
10
11
C1
7
1
4
2
3
18
19
16
17
RST
AUX ADC
SCLK
CS
AUX DAC
DOUT
DIN
VREF
13
12
20
1
2
3
4
5
ADIS16265
6
GND
7
GND
8
VCC
10
9
VCC
DIO2
12
RATE
14
FILT
15
DIO1
6
5
C2
Figure 19. Electrical Schematic
11
12
08246-017
3.800
8×
7.
8.
9.
ADIS16260/ADIS16265
1.100
Data Sheet
1.050
2 × 0.925
*
2 × 0.673
J1
U1
*
*
J2
iSensor
C1
4 × Ø0.087
M2 × 0.4
2 × 0.000
Figure 20. PCB Assembly View and Dimensions
Rev. F | Page 19 of 20
08246-018
0.865
*PIN 1 IDENTIFIER
2 × 0.900
0.035
2 × 0.000
0.200
0.150
ADIS16260/ADIS16265
Data Sheet
OUTLINE DIMENSIONS
7.600
BSC
(4×)
3.800
BSC
(8×)
11.15
MAX
16
15
11.00
TYP
20
0.200
MIN
(ALL SIDES)
7.00
TYP
1.000 BSC
(20×)
1
10.173
BSC
(2×)
0.900 BSC
(16×)
11
10
TOP VIEW
PIN 1
INDICATOR
6
5
BOTTOM VIEW
0.373 BSC
(20×)
022007-B
5.50
MAX
SIDE VIEW
Figure 21. 20-Terminal Stacked Land Grid Array [LGA]
(CC-20-1)
Dimensions shown in millimeters
ORDERING GUIDE
Model1
ADIS16260BCCZ
ADIS16265BCCZ
ADIS16265/PCBZ
1
Temperature Range
−40°C to +105°C
−40°C to +105°C
Package Description
20-Terminal Stacked Land Grid Array [LGA]
20-Terminal Stacked Land Grid Array [LGA]
Evaluation Board
Z = RoHS Compliant Part.
©2009–2018 Analog Devices, Inc. All rights reserved. Trademarks and
registered trademarks are the property of their respective owners.
D08246-0-9/18(F)
Rev. F | Page 20 of 20
Package Option
CC-20-1
CC-20-1
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