Data Sheet
Six Degrees of Freedom Inertial Sensor
ADIS16385
FUNCTIONAL BLOCK DIAGRAM
AUX_ADC AUX_DAC
B
SO
APPLICATIONS
O
Platform stabilization and control
Navigation
Robotics
CALIBRATION AND
DIGITAL PROCESSING
OUTPUT REGISTERS
AND SPI INTERFACE
POWER
MANAGEMENT
SIGNAL CONDITIONING
AND CONVERSION
TRI-AXIS MEMS
ACCELERATION
SENSOR
CS
SCLK
DIN
DOUT
VCC
GND
DIGITAL
CONTROL
SELF-TEST
RST
DIO1
DIO2
DIO3
DIO4/CLKIN
08562-001
TRI-AXIS MEMS
ANGULAR RATE
SENSOR
ALARMS
ADIS16385
TEMPERATURE
SENSORS
LE
Tri-axis digital gyroscope with digital range scaling
±75°/sec, ±150°/sec, ±300°/sec settings
Orthogonal alignment: –19.675°/sec
Figure 12. Example SPI Read, Second 16-Bit Sequence
Burst Read Function
The burst read function enables the user to read all output registers
using one command on the DIN line and shortens the stall time
between each 16-bit segment to one SCLK cycle (see Table 2).
Figure 13 provides the burst read sequence of data on each SPI
signal. The sequence starts with writing 0x3E00 to DIN, followed
by each output register clocking out on DOUT, in the order in
which they appear in Table 8.
O
CS
1
2
3
11
SCLK
DIN
0x3E00
DON’T CARE
DOUT
DIAG_STAT
For burst read, SCLK rate ≤ 1 MHz.
XGYRO_OUT
AUX_ADC
Figure 13. Burst Read Sequence
CS
SCLK
DIN
DOUT
R/W
D15
A6
A5
A4
A3
A2
A1
A0
DC7
DC6
DC5
DC4
DC3
DC2
DC1
DC0
D14
D13
D12
D11
D10
D9
D8
D7
D6
D5
D4
D3
D2
D1
D0
NOTES
1. THE DOUT BIT PATTERN REFLECTS THE ENTIRE CONTENTS OF THE REGISTER IDENTIFIED BY [A6:A0]
IN THE PREVIOUS 16-BIT DIN SEQUENCE WHEN R/W = 0.
2. IF R/W = 1 DURING THE PREVIOUS SEQUENCE, DOUT IS NOT DEFINED.
Figure 14. SPI Communication Bit Sequence
Rev. B | Page 9 of 20
R/W
D15
A6
A5
D14
D13
08562-014
1
XGYRO_OUT
CS
The ADIS16385 SPI interface supports full-duplex serial
communication (simultaneous transmit and receive) and uses
the bit sequence shown in Figure 14. Table 7 provides a list of
the most common settings that require attention to initialize a
processor’s serial port for the ADIS16385 SPI interface.
Processor Setting
Master
SCLK Rate ≤ 2 MHz1
SPI Mode 3
MSB First Mode
16-Bit Mode
0x0800
Figure 11. SPI Read Example
Table 6. Generic Master Processor Pin Names and Functions
Pin Name
SS
SCLK
MOSI
MISO
IRQ
0x0600
LE
Figure 10. Electrical Connection Diagram
0x0400
DOUT
08562-010
13
08562-012
10
SYS TEM
PROCESS OR
SPI MASTER
08562-011
5V
08562-013
I/O LINES ARE COMPATIBLE WITH
3.3V OR 5V LOGIC LEVELS
The ADIS16385 provides two different options for acquiring
sensor data: single register and burst register. A single register
read requires two 16-bit SPI cycles. The first cycle requests the
contents of a register using the bit assignments in Figure 14.
Bit DC7 to Bit DC0 are don’t care for a read, and then the output
register contents follow on DOUT during the second sequence.
Figure 11 includes three single register reads in succession. In
this example, the process starts with DIN = 0x0400 to request
the contents of XGYRO_OUT, then follows with 0x0600 to
request YGYRO_OUT and 0x0800 to request ZGYRO_OUT.
Full-duplex operation enables processors to use the same 16-bit
SPI cycle to read data from DOUT while requesting the next set
of data on DIN. Figure 12 provides an example of the four SPI
signals when reading XGYRO_OUT in a repeating pattern.
TE
VDD
READING SENSOR DATA
ADIS16385
Data Sheet
OUTPUT DATA REGISTERS
Table 12. Analog Input, Offset Binary Format
The output registers in Table 8 provide the most recent sensor
data produced by the ADIS16385. All of the inertial sensor
outputs use a 16-bit twos complement, data format. Figure 6
provides arrows to describe the direction of motion that produces
a positive output in each inertial sensor’s output data register.
Input Voltage
3.3 V
1V
1.6118 mV
805.9 μV
0V
Register
XGYRO_OUT1
YGYRO_OUT1
ZGYRO_OUT1
XACCL_OUT
YACCL_OUT
ZACCL_OUT
TEMP_OUT2
AUX_ADC
1
2
Address
0x04
0x06
0x08
0x0A
0x0C
0x0E
0x10
0x12
Measurement
Gyroscope, x-axis
Gyroscope, y-axis
Gyroscope, z-axis
Accelerometer, x-axis
Accelerometer, y-axis
Accelerometer, z-axis
Internal temperature
Auxiliary ADC
Format
Table 9
Table 9
Table 9
Table 10
Table 10
Table 10
Table 11
Table 12
Assumes that the scaling is set to ±300°/sec. This factor scales with the range.
This is most useful for monitoring relative changes in the temperature.
Hex
0xFFF
0x4D9
0x002
0x001
0x000
Binary
XXXX 1111 1111 1111
XXXX 0100 1101 1001
XXXX 0000 0000 0010
XXXX 0000 0000 0001
XXXX 0000 0000 0000
DEVICE CONFIGURATION
The control registers in Table 13 provide users with a variety of
configuration options. The SPI provides access to these registers,
one byte at a time, using the bit assignments in Figure 14. Each
register has 16 bits, where Bits[7:0] represent the lower address,
and Bits[15:8] represent the upper address. Figure 15 provides
an example of writing 0x03 to Address 0x37 (SMPL_PRD[15:8]),
using DIN = 0xB703. This example reduces the sample rate by a
factor of eight (see Table 28).
TE
Table 8. Output Data Register Formats
Decimal
4095
1241
2
1
0
CS
Hex
0x5DC0
0x0002
0x0001
0x0000
0xFFFF
0xFFFE
0xA240
Binary
0101 1101 1100 0000
0000 0000 0000 0010
0000 0000 0000 0001
0000 0000 0000 0000
1111 1111 1111 1111
1111 1111 1111 1110
1010 0010 0100 0000
Table 10. Acceleration, Twos Complement Format
Figure 15. Example SPI Write Sequence
Dual Memory Structure
Writing configuration data to a control register updates its SRAM
contents, which are volatile. After optimizing each relevant control
register setting in a system, set GLOB_CMD[3] = 1 (DIN =
0xBE08) to back these settings up in nonvolatile flash memory.
The flash backup process requires a valid power supply level for
the entire 75 ms process time. Table 13 provides a user register
memory map that includes a flash backup column. A yes in this
column indicates that a register has a mirror location in flash and,
when backed up properly, it automatically restores itself during
startup or after a reset. Figure 16 provides a diagram of the dualmemory structure used to manage operation and store critical user
settings.
Hex
0x4E20
0x0002
0x0001
0x0000
0xFFFF
0xFFFE
0xB1E0
Binary
0100 1110 0010 0000
0000 0000 0000 0010
0000 0000 0000 0001
0000 0000 0000 0000
1111 1111 1111 1111
1111 1111 1111 1110
1011 0001 1110 0000
MANUAL
FLASH
BACKUP
Table 11. Temperature, Twos Complement Format
Temperature
+105°C
+25.1356°C
+25.0678°C
+25°C
+24.9322°C
+24.8644°C
−40°C
Decimal
+1180
+2
+1
0
−1
−2
−959
Hex
0x49C
0x002
0x001
0x000
0xFFF
0xFFE
0xC41
Binary
XXXX 0100 1001 1100
XXXX 0000 0000 0010
XXXX 0000 0000 0001
XXXX 0000 0000 0000
XXXX 1111 1111 1111
XXXX 1111 1111 1110
XXXX 1100 0100 0001
Rev. B | Page 10 of 20
NONVOLATILE
FLASH MEMORY
VOLATILE
SRAM
(NO SPI ACCESS)
SPI ACCESS
START-UP
RESET
Figure 16. SRAM and Flash Memory Diagram
08562-016
Decimal
+20000
+2
+1
0
−1
−2
− 20000
O
Acceleration
+5 g
+0.5 mg
+0.25 mg
0g
−0.25 mg
−0.5 mg
−5 g
DIN
DIN = 1011 0111 0000 0011 = 0xB703, WRITES “0x03” TO ADDRESS “0x37.”
08562-015
Decimal
+24000
+2
+1
0
−1
−2
−24000
B
SO
Rotation Rate
+300°/sec
+0.025°/sec
+0.0125°/sec
0°/sec
−0.0125°/sec
−0.025°/sec
−300°/sec
LE
SCLK
Table 9. Rotation Rate, Twos Complement Format
Data Sheet
ADIS16385
USER REGISTERS
Table 13. User Register Memory Map 1
1
2
Default
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
0x0000
0x0000
0x0000
0x0000
0x0000
0x0000
0x0000
0x0000
0x0000
0x0000
0x0000
0x0000
0x0000
0x0006
0x0001
0x0402
0x0000
0x0000
0x0000
N/A
N/A
N/A
0x4001
N/A
Register Description
Flash memory write count
Reserved
X-axis gyroscope output
Y-axis gyroscope output
Z-axis gyroscope output
X-axis accelerometer output
Y-axis accelerometer output
Z-axis accelerometer output
Internal temperature output
Auxiliary ADC output
Reserved
X-axis gyroscope bias correction factor
Y-axis gyroscope bias correction factor
Z-axis gyroscope bias correction factor
X-axis acceleration bias correction factor
Y-axis acceleration bias correction factor
Z-axis acceleration bias correction factor
Alarm 1 amplitude threshold
Alarm 2 amplitude threshold
Alarm 1 dynamic time change
Alarm 2 dynamic time change
Alarm control
Auxiliary DAC output level setting
Auxiliary digital input/output control
Miscellaneous control: data-ready, self-test
Sample clock source, decimation rate
Dynamic range and digital filter control
Sleep mode control
System status (error flags)
System command (global)
Reserved
Lot Identification Code 1
Lot Identification Code 2
Product identification, ADIS16385
Serial number
TE
Address 2
0x00
0x02
0x04
0x06
0x08
0x0A
0x0C
0x0E
0x10
0x12
0x14 to 0x19
0x1A
0x1C
0x1E
0x20
0x22
0x24
0x26
0x28
0x2A
0x2C
0x2E
0x30
0x32
0x34
0x36
0x38
0x3A
0x3C
0x3E
0x40 to 0x51
0x52
0x54
0x56
0x58
LE
Flash Backup
Yes
N/A
No
No
No
No
No
No
No
No
N/A
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
No
No
Yes
Yes
Yes
No
No
No
N/A
Yes
Yes
Yes
Yes
B
SO
R/W
R
N/A
R
R
R
R
R
R
R
R
N/A
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
W
R
R/W
N/A
R
R
R
R
O
Name
FLASH_CNT
Reserved
XGYRO_OUT
YGYRO_OUT
ZGYRO_OUT
XACCL_OUT
YACCL_OUT
ZACCL_OUT
TEMP_OUT
AUX_ADC
Reserved
XGYRO_OFF
YGYRO_OFF
ZGYRO_OFF
XACCL_OFF
YACCL_OFF
ZACCL_OFF
ALM_MAG1
ALM_MAG2
ALM_SMPL1
ALM_SMPL2
ALM_CTRL
AUX_DAC
GPIO_CTRL
MSC_CTRL
SMPL_PRD
SENS_AVG
SLP_CTRL
DIAG_STAT
GLOB_CMD
Reserved
LOT_ID1
LOT_ID2
PROD_ID
SERIAL_NUM
Reference
Table 20
N/A
Table 9
Table 9
Table 9
Table 10
Table 10
Table 10
Table 11
Table 12
N/A
Table 31
Table 31
Table 31
Table 32
Table 32
Table 32
Table 34
Table 35
Table 36
Table 36
Table 37
Table 25
Table 24
Table 21
Table 28
Table 29
Table 16
Table 22
Table 15
N/A
Table 17
Table 17
Table 19
Table 18
N/A = not applicable.
Each register contains two bytes. The address of the lower byte is displayed. The address of the upper byte is equal to the address of the lower byte plus 1.
Rev. B | Page 11 of 20
ADIS16385
Data Sheet
SYSTEM FUNCTIONS
Table 14. System Tool Registers
Register Name
MSC_CTRL
SLP_CTRL
DIAG_STAT
GLOB_CMD
LOT_ID1
LOT_ID2
PROD_ID
SERIAL_NUM
Address
0x34
0x3A
0x3C
0x3E
0x52
0x54
0x56
0x58
Description
Self-test, calibration, data-ready
Sleep mode control
Error flags
Single-command functions
Lot Identification Code 1
Lot Identification Code 2
Product identification
Serial number
GLOBAL COMMANDS
Bits
[15:9]
[8]
[7:0]
Description (Default = 0x0000)
Not used.
Normal sleep mode (1 = start sleep mode).
Timed sleep mode (write 0x01 to 0xFF to start).
Sleep mode duration, binary, 0.5 sec/LSB.
PRODUCT IDENTIFICATION
The PROD_ID register in Table 19 contains the binary equivalent
of 16,385. It provides a product-specific variable for systems that
need to track this in their system software. The LOT_ID1 and
LOT_ID2 registers in Table 17 combine to provide a unique, 32-bit
lot identification code. The SERIAL_NUM register in Table 18
contains a binary number that represents the serial number on
the device label. The assigned serial numbers in SERIAL_NUM
are lot specific.
Table 17. LOT_ID1, LOT_ID2 Bit Descriptions
LE
The GLOB_CMD register in Table 15 provides trigger bits for
device reset, flash memory management, DAC control, and
calibration control. Start each of these functions by writing a 1 to
the assigned bit in GLOB_CMD. After completing the task, the bit
automatically returns to 0. For example, set GLOB_CMD[7] = 1
(DIN = 0xBE80) to initiate a software reset, which stops the
sensor operation and runs the device through its start-up
sequence. Set GLOB_CMD[3] = 1 (DIN = 0xBE08) to back up
the user register contents in nonvolatile flash. This sequence
includes loading the control registers with the data in their
respective flash memory locations prior to producing new data.
Table 16. SLP_CTRL Bit Descriptions
TE
The ADIS16385 provides a number of system-level controls for
managing its operation, using the registers in Table 14.
Table 18. SERIAL_NUM Bit Descriptions
B
SO
Bits
[15:14]
[13:0]
Bits
[15:0]
Description (Default = 0x0000)
Not used
Software reset
Not used
Flash update
Auxiliary DAC data latch
Factory calibration restore
Automatic bias correction
O
Description
Lot identification, binary code
Description
Reserved
Serial number, 1 to 9999 (0x270F)
Table 19. PROD_ID Bit Descriptions
Table 15. GLOB_CMD Bit Descriptions
Bits
[15:8]
[7]
[6:4]
[3]
[2]
[1]
[0]
Bits
[15:0]
Description (Default = 0x4001)
Product identification = 0x4001
MEMORY MANAGEMENT
The FLASH_CNT register in Table 20 provides a 16-bit counter
that helps track the number of write cycles to the nonvolatile flash
memory. The flash is updated every time a manual flash update
occurs. A manual flash update is initiated by the GLOB_CMD[3]
bit and is also performed at the completion of the GLOB_CMD[1:0]
functions (see Table 15).
POWER MANAGEMENT
The SLP_CTRL register, in Table 16, provides two different sleep
modes for system-level management: normal and timed. Set
SLP_CTRL[8] = 1 (DIN = 0xBB01) to start normal sleep mode.
When the device is in sleep mode, the following events can
cause it to wake up: assert CS from high to low, assert RST
from high to low, or cycle the power. Use SLP_CTRL[7:0] to put
the device into sleep mode for a specified period. For example,
SLP_CNT[7:0] = 0x64 (DIN = 0xBA64) puts the ADIS16385 to
sleep for 50 seconds.
Table 20. FLASH_CNT Bit Descriptions
Bits
[15:0]
Rev. B | Page 12 of 20
Description
Binary counter
Data Sheet
ADIS16385
Set MSC_CTRL[11] = 1 (DIN = 0xB508) to perform a checksum test of the internal program memory. This takes a summation
of the internal program memory and compares it with the original
summation value for the same locations (from factory configuration).
Check the results in the DIAG_STAT register, which is in Table 22.
DIAG_STAT[6] equals 0 if the sum matches the correct value
and 1 if it does not. Make sure that the power supply is within
specification for the entire 20 ms that this function takes to
complete.
SELF-TEST FUNCTION
Table 21. MSC_CTRL Bit Descriptions
[10]
[9]
[8]
[7]
[6]
O
[5:3]
[2]
Description (Default = 0x0006)
Not used
Checksum memory test (cleared upon completion)1
(1 = enabled, 0 = disabled)
Internal self-test (cleared upon completion)1
(1 = enabled, 0 = disabled)
Not used
Manual self-test
(1 = enabled, 0 = disabled)
Linear acceleration bias compensation for gyroscopes
(1 = enabled, 0 = disabled)
Point of percussion, per Figure 6
(1 = enabled, 0 = disabled)
Not used
Data-ready enable
(1 = enabled, 0 = disabled)
Data-ready polarity
(1 = active high, 0 = active low)
Data-ready line select
(1 = DIO2, 0 = DIO1)
B
SO
Bits
[15:12]
[11]
[1]
[0]
1
The bit is automatically reset to 0 after finishing the test.
Set MSC_CTRL[8] = 1 (DIN = 0xB501) to manually activate
the self-test function on all six sensors. Set MSC_CTRL[8] = 0
(DIN = 0xB500) to manually deactivate the self-test function on
all six sensors. Measure the output bias for each MSC_CTRL[8]
setting (0 and 1), take the difference between them, and compare
this difference with the expected self-test response in Table 1.
STATUS
The DIAG_STAT register in Table 22 provides error flags for
a number of functions. Each flag uses 1 to indicate an error
condition and 0 to indicate a normal condition. Reading this
register provides access to each flag’s status and resets all of the
bits to 0 for monitoring future operation. If the error condition
remains, the error flag will return to 1 at the conclusion of the
next sample cycle. DIAG_STAT[0] does not require a read of
this register to return to 0. If the power supply voltage goes back
into range, this flag clears automatically. The SPI communication
error flag in DIAG_STAT[3] indicates that the number of SCLKs
in a SPI sequence did not equal a multiple of 16 SCLKs.
LE
The MSC_CTRL register in Table 21 provides a self-test function
for all six MEMS inertial sensors. This function allows the user
to verify the mechanical integrity of each MEMS sensor. When
enabled, the self-test applies an electrostatic force to each internal
sensor element, which causes them to move. The movement in
each element simulates its response to actual rotation/acceleration
and generates a predictable electrical response in the sensor outputs.
Table 1 provides the expected response for both gyroscopes and
accelerometers that can help establish pass/fail limits during
system-level diagnostic testing.
There are two self-test options in the MSC-CTRL register:
internal and manual. Set MSC_CTRL[10] = 1 (DIN = 0xB504)
to run the internal self-test routine, which exercises all inertial
sensors, measures each response, computes the response to the
self-test stimulus, makes pass/fail decisions, and reports them
to the error flags in DIAG_STAT[5] and DIAG_STAT[15:10].
DIAG_STAT[15:10] provide individual error flags for each inertial
sensor; DIAG_STAT[5] provides a single bit for indicating a
failure in any of the inertial sensors. MSC_CTRL[10] resets
itself to 0 after completing the routine.
TE
Checksum Test
Table 22. DIAG_STAT Bit Descriptions
Bits
[15]
[14]
[13]
[12]
[11]
[10]
[9]
[8]
[7]
[6]
[5]
[4]
[3]
[2]
[1]
[0]
Rev. B | Page 13 of 20
Description (Default = 0x0000)
Z-axis accelerometer self-test failure (1 = fail, 0 = pass)
Y-axis accelerometer self-test failure (1 = fail, 0 = pass)
X-axis accelerometer self-test failure (1 = fail, 0 = pass)
Z-axis gyroscope self-test failure (1 = fail, 0 = pass)
Y-axis gyroscope self-test failure (1 = fail, 0 = pass)
X-axis gyroscope self-test failure (1 = fail, 0 = pass)
Alarm 2 status (1 = active, 0 = inactive)
Alarm 1 status (1 = active, 0 = inactive)
Not used
Flash test, checksum flag (1 = fail, 0 = pass)
Self-test diagnostic error flag (1 = fail, 0 = pass)
Sensor overrange (1 = overrange, 0 = normal)
SPI communication failure (1 = fail, 0 = pass)
Flash update failure (1 = fail, 0 = pass)
Not used
Power supply low (1 = VDD < 4.85 V, 0 = VDD ≥ 4.85 V)
ADIS16385
Data Sheet
INPUT/OUTPUT CONFIGURATION
Table 23 provides a summary of registers that provide input/output
configuration and control.
Table 23. Input/Output Registers
Register Name
AUX_DAC
GPIO_CTRL
MSC_CTRL
Address
0x30
0x32
0x34
Description
Output voltage control, AUX_DAC
General-purpose I/O control
Self-test, calibration, data-ready
Example I/O Configuration
For example, set GPIO_CTRL[3:0] = 0100 (DIN = 0xB204)
to set DIO3 as an output signal pin and DIO1, DIO2, and
DIO4 as input signal pins. Set the output on DIO3 to 1 by
setting GPIO_CTRL[10] = 1 (DIN = 0xB304). Then, read
GPIO_CTRL[7:0] (DIN = 0x3200) and mask off GPIO_CTRL[9:8]
and GPIO_CTRL[11] to monitor the digital signal levels on
DIO4, DIO2, and DIO1.
AUXILIARY DAC
The factory-default setting of MSC_CTRL[2:0] (110) establishes
DIO1 as a positive polarity data-ready signal. See Table 21 for
additional data-ready configuration options. For example, set
MSC_CTRL[2:0] = 100 (DIN = 0xB404) to change the polarity of
the data-ready signal on DIO1 for interrupt inputs that require
negative logic inputs for activation. The pulse width is typically
between 40 μs and 80 μs.
The AUX_DAC register in Table 25 provides user controls for
setting the output voltage on the AUX_DAC pin. The 12-bit
AUX_DAC line can drive its output to within 5 mV of the ground
reference when it is not sinking current. As the output approaches
0 V, the linearity begins to degrade (~100 LSB starting point). As
the sink current increases, the nonlinear range increases. The
DAC latch command in GLOB_CMD[2] (see Table 15) moves
the values of the AUX_DAC register into the DAC input register,
enabling both bytes to take effect at the same time. This prevents
undesirable output levels, which reflect single-byte changes of
the AUX_DAC register.
LE
GENERAL-PURPOSE I/O
[1]
[0]
Bits
[15:12]
[11:0]
Description (Default = 0x0000)
Not used
Data bits, scale factor = 0.8059 mV/LSB
Offset binary format, 0 V = 0 LSB
Table 26. Setting AUX_DAC = 1 V
Table 24. GPIO_CTRL Bit Descriptions
Description (Default = 0x0000)
Not used
General-Purpose I/O Line 4 (DIO4) data level
General-Purpose I/O Line 3 (DIO3) data level
General-Purpose I/O Line 2 (DIO2) data level
General-Purpose I/O Line 1 (DIO1) data level
Not used
General-Purpose I/O Line 4 (DIO4) direction control
(1 = output, 0 = input)
General-Purpose I/O Line 3 (DIO3) direction control
(1 = output, 0 = input)
General-Purpose I/O Line 2 (DIO2) direction control
(1 = output, 0 = input)
General-Purpose I/O Line 1 (DIO1) direction control
(1 = output, 0 = input)
DIN
0xB0D9
0xB104
0xBE04
O
[2]
Table 25. AUX_DAC Bit Descriptions
B
SO
DIO1, DIO2, DIO3, and DIO4 are configurable, general-purpose
I/O lines that serve multiple purposes. The data-ready controls
in MSC_CTRL[2:0] have the highest priority for configuring
DIO1 and DIO2. The alarm indicator controls in ALM_CTRL[2:0]
have the second-highest priority for configuring DIO1 and DIO2.
The external clock control associated with SMPL_PRD[7:0] has
the highest priority for DIO4 configuration (see Table 28).
GPIO_CTRL in Table 24 has the lowest priority for configuring
DIO1, DIO2, and DIO4 and has absolute control over DIO3.
Bits
[15:12]
[11]
[10]
[9]
[8]
[7:4]
[3]
TE
DATA-READY I/O INDICATOR
Rev. B | Page 14 of 20
Description
AUX_DAC[7:0] = 0xD9 (217 LSB)
AUX_DAC[15:8] = 0x04 (1024 LSB)
GLOB_CMD[2] = 1; move values into the DAC input
register, resulting in a 1 V output level
Data Sheet
ADIS16385
DIGITAL PROCESSING CONFIGURATION
0
Table 27. Digital Processing Registers
Description
Sample rate control
Digital filtering and range control
–20
–40
SAMPLE RATE
The internal sampling system produces new data in the output
data registers at a rate of 1024 SPS. The SMPL_PRD register in
Table 28 provides two functional controls that affect sampling
and register update rates. SMPL_PRD[12:8] provides a control
for reducing the update rate, using an averaging filter with a
decimated output. These bits provide a binomial control that
divides the data rate by a factor of 2 every time this number
increases by 1. For example, set SMPL_PRD[12:8] = 00100
(DIN = 0xB704) to set the decimation factor to 16. This reduces
the update rate to 64 SPS and the bandwidth to 31 Hz.
–60
–80
–100
N=2
N=4
N = 16
N = 64
TE
–120
–140
0.001
0.01
0.1
1
FREQUENCY (f/fS)
08562-017
Address
0x36
0x38
MAGNITUDE (dB)
Register Name
SMPL_PRD
SENS_AVG
Figure 17. Bartlett Window, FIR Filter Frequency Response
(Phase Delay = N Samples)
DYNAMIC RANGE
Table 28. SMPL_PRD Bit Descriptions
Description (Default = 0x0001)
Not used
Average/decimation rate setting, binomial
Not used
Clock: 1 = internal (1024 SPS), 0 = external
INPUT CLOCK CONFIGURATION
B
SO
SMPL_PRD[0] provides a control for synchronizing the internal
sampling to an external clock source. Set SMPL_PRD[0] = 0
(DIN = 0xB600) to enable the external clock. See Table 2 and
Figure 4 for timing information.
DIGITAL FILTERING
O
The SENS_AVG register in Table 29 provides user controls for
the low-pass filter. This filter contains two cascaded averaging
filters that provide a Bartlett window, FIR filter response (see
Figure 18). For example, set SENS_AVG[2:0] = 100 (DIN = 0xB804)
to set each stage to 16 taps. When used with the default sample
rate of 1024 SPS and zero decimation (SMPL_PRD[12:8] = 00000),
this value reduces the sensor bandwidth to approximately 20 Hz.
MEMS
SENSOR
The SENS_AVG[10:8] bits provide three dynamic range settings
for this gyroscope. The lower dynamic range settings (±75°/sec
and ±150°/sec) limit the minimum filter tap sizes to maintain
resolution. For example, set SENS_AVG[10:8] = 010 (DIN =
0xB902) for a measurement range of ±150°/sec. Because this
setting can influence the filter settings, program SENS_AVG[10:8]
before programming SENS_AVG[2:0] if more filtering is
required.
LE
Table 29. SENS_AVG Bit Descriptions
Bits
[15:11]
[10:8]
Description (Default = 0x0402)
Not used
Measurement range (sensitivity) selection
100 = ±300°/sec (default condition)
010 = ±150°/sec, filter taps ≥ 4 (Bits[2:0] ≥ 0x02)
001 = ±75°/sec, filter taps ≥ 16 (Bits[2:0] ≥ 0x04)
Not used
Number of taps in each stage; value of B in NB = 2B
[7:3]
[2:0]
BARTLETT WINDOW
FIR FILTER
LOW-PASS
FILTER
330Hz
1
NB
ADC
GYROSCOPES
LOW-PASS, TWO-POLE (404Hz, 757Hz)
ACCELEROMETERS
CLOCK
1024SPS
NB
x(n)
n=1
1
NB
NB
x(n)
n=1
B = SENS_AVG[2:0]
NB = 2B
NB = NUMBER OF TAPS
(PER STAGE)
AVERAGE/
DECIMATION
FILTER
1
ND
ND
÷ND
x(n)
n=1
D = SMPL_PRD[12:8]
ND = 2D
ND = NUMBER OF TAPS
LOW-PASS, SINGLE-POLE (330Hz)
EXTERNAL CLOCK ENABLED
BY SMPL_PRD[0] = 0
Figure 18. Sampling and Frequency Response Block Diagram
Rev. B | Page 15 of 20
08562-018
Bits
[15:13]
[12:8]
[7:1]
[0]
ADIS16385
Data Sheet
CALIBRATION
The mechanical structure and assembly process of the ADIS16385
provide excellent position and alignment stability for each sensor,
even after subjected to temperature cycles, shock, vibration, and
other environmental conditions. The factory calibration includes a
dynamic characterization of each sensor’s behavior over temperature
and generates sensor-specific correction formulas. The bias
correction registers in Table 30 provide users with the ability to
address bias shifts that can result from mechanical stress. Figure 19
illustrates the summing function of each sensor’s offset correction
register.
ADC
Description
Gyroscope bias, x-axis
Gyroscope bias, y-axis
Gyroscope bias, z-axis
Accelerometer bias, x-axis
Accelerometer bias, y-axis
Accelerometer bias, z-axis
Automatic calibration
FACTORY
CALIBRATION
AND
FILTERING
Table 31. XGYRO_OFF, YGYRO_OFF, and ZGYRO_OFF
Bit Descriptions
Bits
[15:0]
XGYRO_OUT
08562-019
XGYRO_OFF
Figure 19. User Calibration, XGYRO_OFF Example
There are two options for optimizing gyroscope bias accuracy
prior to system deployment: automatic bias correction (ABC)
and manual bias correction (MBC).
AUTOMATIC BIAS CORRECTION (ABC)
1.
2.
3.
4.
5.
O
The ABC function provides a simple measure-and-adjust function
for the three gyroscope sensors. Set GLOB_CMD[0] = 1 (DIN =
0xBE01) to start the ABC function, which automatically performs
the following steps to correct the bias on each gyroscope:
Waits for the next output register update.
Reads the output register of the gyroscope.
Multiplies the measurement by −1 to change its polarity.
Writes the final value into the offset register.
Performs a manual flash backup function to store the
correction factor in nonvolatile flash memory.
Description (Default = 0x0000)
Twos complement, 0.003125°/sec per LSB. Typical
adjustment range = ±102°/sec.
Table 32. XACCL_OFF, YACCL_OFF, and ZACCL_OFF
Bit Descriptions
B
SO
X-AXIS
MEMS
GYRO
Address
0x1A
0x1C
0x1E
0x20
0x22
0x24
0x3E
The manual bias correction (MBC) function requires the user to
collect the desired number of samples, calculate the averages to
develop bias estimates for each gyroscope channel, and then write
them into the bias offset registers, located in Table 31 for the gyroscopes. For example, set XGYRO_OFF = 0x1FF6 (DIN = 0x9B1F,
0x9AF6) to adjust the XGYRO_OUT offset by −0.03125°/sec
(−10 LSBs). Table 32 provides a manual adjustment function for
the accelerometer channels as well.
LE
Register
XGYRO_OFF
YGYRO_OFF
ZGYRO_OFF
XACCL_OFF
YACCL_OFF
ZACCL_OFF
GLOB_CMD
MANUAL BIAS CORRECTION
TE
Table 30. Registers for User Calibration
The accuracy of the bias correction depends on the internal
averaging time used for the data sample, which depends on the
decimation setting. For example, set SMPL_PRD[15:8] = 0x10
(DIN = 0xB710) to establish a decimation rate of 216, or 65536.
This establishes an averaging time of 80 seconds at a sample
rate of 819.2 SPS, which results in an Allan Variance of 0.006°/sec
on the x-axis and y-axis gyroscopes and 0.0016°/sec on the z-axis
gyroscope.
Bits
[15:0]
Description (Default = 0x0000)
Data bits. Twos complement, 0.25 mg/LSB. Typical
adjustment range = ±8 g.
RESTORING FACTORY CALIBRATION
Set GLOB_CMD[1] = 1 (DIN = 0xBE02) to execute the factory
calibration restore function. This is a single-command function,
which resets each user calibration register to 0x0000 and all sensor
data to 0. Then, it automatically updates the flash memory within
50 ms. See Table 15 for more information on GLOB_CMD.
POINT-OF-PERCUSSION/LINEAR-g COMPENSATION
Set MSC_CTRL[6] = 1 (DIN = 0xB446) to enable this feature
and maintain the factory-default settings for DIO1. This feature
performs a point-of-percussion translation to the point identified
in Figure 6. See Table 21 for more information on MSC_CTRL.
Set MSC_CTRL[7] = 1 to enable internal compensation for
linear-g on the gyroscope bias.
Rev. B | Page 16 of 20
Data Sheet
ADIS16385
ALARMS
The ADIS16385 provides two independent alarms, Alarm 1 and
Alarm 2, which have a number of programmable settings. Table 33
provides a list of registers for these user settings.
Table 33. Registers for Alarm Configuration
Address
0x26
0X28
0x2A
0x2C
0x2E
Description
Alarm 1 trigger setting
Alarm 2 trigger setting
Alarm 1 sample period
Alarm 2 sample period
Alarm configuration
Table 37. ALM_CTRL Bit Descriptions
Bits
[15:12]
The ALM_CTRL register in Table 37 provides data source
selection (Bits[15:8]), static/dynamic setting for each alarm
(Bits[7:6]), trigger polarity (Bits[5:4]), data source filtering
(Bit[3]), and alarm indicator signal (Bits[2:0]).
STATIC ALARM USE
Description (Default = 0x0000)
Threshold setting; matches for format of
ALM_CTRL[11:8] output register selection
B
SO
Bits
[15:0]
Table 35. ALM_MAG2 Bit Descriptions
Bits
[15:0]
Description (Default = 0x0000)
Threshold setting; matches for format of
ALM_CTRL[15:12] output register selection
DYNAMIC ALARM USE
O
The dynamic alarm setting monitors the data selection for a
rate-of-change comparison. The rate-of-change comparison is
represented by the magnitude in the ALM_MAGx registers over
the time represented by the number-of-samples setting in the
ALM_SMPLx registers, located in Table 36. See Table 38, Alarm 2,
for a dynamic alarm configuration example.
Table 36. ALM_SMPL1 and ALM_SMPL2 Bit Descriptions
Bits
[15:8]
[7:0]
Description (Default = 0x0000)
Alarm 2 data source selection
0000 = disable
0001 = x-axis gyroscope output
0010 = y-axis gyroscope output
0011 = z-axis gyroscope output
0100 = x-axis accelerometer output
0101 = y-axis accelerometer output
0110 = z-axis accelerometer output
0111 = internal temperature output
1000 = auxiliary ADC input
1001 = DIAG_STAT > 0x0000
Alarm 1 data source selection (same as Alarm 2)
Alarm 2, dynamic/static (1 = dynamic, 0 = static)
Alarm 1, dynamic/static (1 = dynamic, 0 = static)
Alarm 2 polarity (1 = greater than, 0 = less than)
Alarm 1 polarity (1 = greater than, 0 = less than)
Data source filtering (1 = filtered, 0 = unfiltered)
Alarm indicator (1 = enabled, 0 = disabled)
Alarm indicator active polarity (1 = high, 0 = low)
Alarm output line select (1 = DIO2, 0 = DIO1)
[11:8]
[7]
[6]
[5]
[4]
[3]
[2]
[1]
[0]
LE
The static alarms setting compares the data source selection
(ALM_CTRL[15:8]) with the values in the ALM_MAGx registers
in Table 34 and Table 35. The data format in these registers
matches the format of the data selection in ALM_CTRL[15:8].
The ALM_CTRL[5:4] bits provide polarity settings. See Table 38,
Alarm 1, for a static alarm configuration example.
Table 34. ALM_MAG1 Bit Descriptions
The DIAG_STAT[9:8] bits provide error flags that indicate an
alarm condition. The ALM_CTRL[2:0] bits provide controls for
a hardware indicator using DIO1 or DIO2.
TE
Register
ALM_MAG1
ALM_MAG2
ALM_SMPL1
ALM_SMPL2
ALM_CTRL
ALARM REPORTING
Description (Default = 0x0000)
Not used
Binary, number of samples (both 0x00 and 0x01 = 1)
Alarm Example
Table 38 offers an example that configures Alarm 1 to trigger when
filtered ZACCL_OUT data drops below 0.7 g, and Alarm 2 to
trigger when filtered ZGYRO_OUT data changes by more than
50°/sec over a 100 ms period, or 500°/sec2. The filter setting
helps reduce false triggers from noise and refine the accuracy
of the trigger points. The ALM_SMPL2 setting of 102 samples
provides a comparison period that is 99.6 ms for an internal
sample rate of 1024 SPS. Because Alarm 1 is a static alarm in
this example, there is no need to program ALM_SMPL1.
Table 38. Alarm Configuration Example 1
DIN
0xAF36,
0xAEAF
0xA90F,
0xA8A0
0xA70A,
0xA6F0
0xAC66
Rev. B | Page 17 of 20
Description
ALM_CTRL = 0x36AF.
Alarm 2: dynamic, Δ-ZGYRO_OUT
(Δ-time, ALM_SMPL2) > ALM_MAG2.
Alarm 1: static, ZACCL_OUT < ALM_MAG1. Use filtered
data source for comparison. DIO2 output indicator,
positive polarity.
ALM_MAG2 = 0x0FA0 (+50°/sec).
ALM_MAG1 = 0x0AF0 (0.7 g).
ALM_SMPL2[7:0] = 0x66 (102 samples).
ADIS16385
Data Sheet
APPLICATIONS INFORMATION
PROTOTYPE INTERFACE BOARD
INSTALLATION TIPS
The ADIS16385/PCBZ includes one ADIS16385BMLZ, one
interface printed circuit board (PCB), and four M2×18 machine
screws. The interface PCB provides larger connectors than the
ADIS16385BMLZ for simpler prototyping, four tapped M2
holes for attachment of the ADIS16385BMLZ, and four holes
(machine screw size M2.5 or #4) for mounting the interface
PCB to a solid structure. J1 and J2 are dual-row, 2 mm (pitch)
connectors that work with a number of ribbon cable systems,
including 3M Part Number 152212-0100-GB (ribbon crimp
connector) and 3M Part Number 3625/12 (ribbon cable).
Figure 22 and Figure 23 provide the mechanical design information
used for the ADIS16385/PCBZ. Use Figure 22 and Figure 23 when
implementing a connector-down approach, where the mating
connector and the ADIS16385BMLZ are on the same surface.
When designing a connector-up system, use the mounting
holes shown in Figure 22 as a guide in designing the bulkhead
mounting system and use Figure 23 as a guide in developing
the mating connector interface on a flexible circuit or other
connector system.
TE
15.600 BSC
C
L
C
L
2x Ø 0.560 BSC
ALIGNMENT HOLES
FOR MATING SOCKET
39.60 BSC
19.800 BSC
17.520
LE
Figure 20 provides the top-level view of the interface board. Install
the ADIS16385BMLZ onto this board using the silk pattern as
an orientation guide. Align the pins on the ADIS16385BMLZ to
the mating connector on the interface PCB with care. Misalignment or wrong orientation can cause permanent damage.
Figure 21 provides the pin assignments for J1 and J2. The pin
descriptions match those listed in Table 5. The ADIS16385 does
not require external capacitors for normal operation; therefore,
the interface PCB does not use the C1/C2 pads.
31.200 BSC
4x Ø 2.500 BSC
08562-022
2.280
5.00 BSC
B
SO
5.00 BSC
Figure 22. Suggested Mounting Hole Locations, Connector Down
0.4334 [11.0]
0.019685
[0.5000]
(TYP)
0.0240 [0.610]
0.054 [1.37]
O
08562-020
0.022 MIN/
0.025 MAX DIA 2x
NONPLATED
THRU HOLE 2×
2
SCLK
DNC
1
2
GND
CS
3
4
DOUT
DNC
3
4
DNC
DNC
5
6
DIN
GND
5
6
CLKIN
GND
7
8
GND
DNC
7
8
DNC
GND
9
10
VCC
DNC
9
10
DNC
VCC
11
12
VCC
DIO2
11
12
DIO1
08562-021
J2
J1
1
0.0394 [1.00]
0.022 DIA THRU HOLE (TYP)
NONPLATED THRU HOLE
Figure 23. Suggested Layout and Mechanical Design for the Mating Connector
Figure 20. Physical Diagram for the ADIS16385/PCBZ
RST
0.0394 [1.00] 0.1800
[4.57]
08562-023
C
L
Figure 21. J1/J2 Pin Assignments
Rev. B | Page 18 of 20
Data Sheet
ADIS16385
OUTLINE DIMENSIONS
35.90
35.60
35.30
15.80
15.60
15.40
31.40
31.20
31.00
5.50
20.00
19.80
19.60
44.30
44.00
43.70
TE
17.70
17.50
17.30
47.50
47.20
46.90
2.40 THRU HOLE
(4×)
BOTTOM VIEW
B
SO
FRONT VIEW
LE
2.200
(4×)
39.30
39.00
38.70
39.30
38.90
38.50
20.70
3.10
2.80
2.50
O
0.30 SQ
BSC (24×)
1.00 BSC
LEAD PITCH
SIDE VIEW
07-23-2010-B
15.50
Figure 24. 24-Lead Module with Connector Interface
(ML-24-5)
Dimensions shown in millimeters
ORDERING GUIDE
Model 1
ADIS16385BMLZ
ADIS16385/PCBZ
1
Temperature Range
−40°C to +105°C
Package Description
24-Lead Module with Connector Interface
Interface PCB
Z = RoHS Compliant Part.
Rev. B | Page 19 of 20
Package Option
ML-24-5
ADIS16385
Data Sheet
O
B
SO
LE
TE
NOTES
©2010–2011 Analog Devices, Inc. All rights reserved. Trademarks and
registered trademarks are the property of their respective owners.
D08562-0-12/11(B)
Rev. B | Page 20 of 20
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