100 MHz to 4000 MHz RF/IF Digitally Controlled VGA ADL5240
FEATURES
Operating frequency from 100 MHz to 4000 MHz Digitally controlled VGA with serial and parallel interfaces 6-bit, 0.5 dB digital step attenuator 31.5 dB gain control range with ±0.25 dB step accuracy Gain block amplifier specifications Gain: 19.7 dB at 2.14 GHz OIP3: 41.0 dBm at 2.14 GHz P1dB: 19.5 dBm at 2.14 GHz Noise figure: 2.9 dB at 2.14 GHz Gain block or digital step attenuator can be first Single supply operation from 4.75 V to 5.25 V Low quiescent current of 93 mA Thermally efficient, 5 mm × 5 mm, 32-lead LFCSP The companion ADL5243 integrates a ¼ W driver amplifier to the output of the gain block and DSA
GENERAL DESCRIPTION
The ADL5240 is a high performance, digitally controlled variable gain amplifier (VGA) operating from 100 MHz to 4000 MHz. The VGA integrates a high performance, 20 dB gain, internally matched amplifier (AMP) with a 6-bit digital step attenuator (DSA) that has a gain control range of 31.5 dB in 0.5 dB steps with ±0.25 dB step accuracy. The attenuation of the DSA can be controlled using a serial or parallel interface. Both the gain block and DSA are internally matched to 50 Ω at their inputs and outputs and are separately biased. The separate bias allows all or part of the ADL5240 to be used, which facilitates easy reuse throughout a design. The pinout of the ADL5240 also enables either the gain block or DSA to be first, giving the VGA maximum flexibility in a signal chain. The ADL5240 consumes just 93 mA and operates from a single supply ranging from 4.75 V to 5.25 V. The VGA is packaged in a thermally efficient, 5 mm × 5 mm, 32-lead LFCSP and is fully specified for operation from −40°C to +85°C. A fully populated evaluation board is available.
APPLICATIONS
Wireless infrastructure Automated test equipment RF/IF gain control
FUNCTIONAL BLOCK DIAGRAM
D1/DATA D0/CLK D2/LE SEL D3 D4 D5 D6
25
32
31
30
29
28
27
26
VDD 1 SERIAL/PARALLEL INTERFACE NC 2
24 VDD
23 NC
NC 3
22 NC
DSAIN 4 0.5dB NC 5 1dB 2dB 4dB 8dB 16dB
21 DSAOUT
20 NC
NC 6
ADL5240
AMP
19 NC
NC 7
18 NC
NC 8
9 10 11 12 13 14 15 16
17 NC
AMPOUT/VCC
AMPIN
NC
NC
NC
NC
NC
NC
Figure 1.
Rev. 0
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09430-001
ADL5240 TABLE OF CONTENTS
Features .............................................................................................. 1 Applications....................................................................................... 1 General Description ......................................................................... 1 Functional Block Diagram .............................................................. 1 Revision History ............................................................................... 2 Specifications..................................................................................... 3 Absolute Maximum Ratings............................................................ 8 ESD Caution.................................................................................. 8 Pin Configuration and Function Descriptions............................. 9 Typical Performance Characteristics ........................................... 10 Applications Information .............................................................. 15 Basic Layout Connections......................................................... 15 SPI Timing................................................................................... 17 Loop Performance...................................................................... 19 Thermal Considerations............................................................ 20 Evaluation Board ............................................................................ 21 Outline Dimensions ....................................................................... 24 Ordering Guide .......................................................................... 24
REVISION HISTORY
7/11—Revision 0: Initial Version
Rev. 0 | Page 2 of 24
ADL5240 SPECIFICATIONS
VDD = 5 V, VCC = 5 V, TA = 25oC Table 1.
Parameter OVERALL FUNCTION Frequency Range AMPLIFIER FREQUENCY = 150 MHz Gain vs. Frequency vs. Temperature vs. Supply Input Return Loss Output Return Loss Output 1 dB Compression Point Output Third-Order Intercept Noise Figure AMPLIFIER FREQUENCY = 450 MHz Gain vs. Frequency vs. Temperature vs. Supply Input Return Loss Output Return Loss Output 1 dB Compression Point Output Third-Order Intercept Noise Figure AMPLIFIER FREQUENCY = 748 MHz Gain vs. Frequency vs. Temperature vs. Supply Input Return Loss Output Return Loss Output 1 dB Compression Point Output Third-Order Intercept Noise Figure AMPLIFIER FREQUENCY = 943 MHz Gain vs. Frequency vs. Temperature vs. Supply Input Return Loss Output Return Loss Output 1 dB Compression Point Output Third-Order Intercept Noise Figure Test Conditions/Comments Min 100 Using the AMPIN and AMPOUT pins ±50 MHz −40°C ≤ TA ≤ +85°C 4.75 V to 5.25 V S11 S22 ∆f = 1 MHz, POUT = 4 dBm/tone Using the AMPIN and AMPOUT pins ±50 MHz −40°C ≤ TA ≤ +85°C 4.75 V to 5.25 V S11 S22 ∆f = 1 MHz, POUT = 4 dBm/tone Using the AMPIN and AMPOUT pins ±50 MHz −40°C ≤ TA ≤ +85°C 4.75 V to 5.25 V S11 S22 ∆f = 1 MHz, POUT = 4 dBm/tone Using the AMPIN and AMPOUT pins 19.0 ±18 MHz −40°C ≤ TA ≤ +85°C 4.75 V to 5.25 V S11 S22 18.5 ∆f = 1 MHz, POUT = 4 dBm/tone 20.5 ±0.01 ±0.27 ±0.01 −30.3 −24.8 20.1 40.0 2.7 22.0 dB dB dB dB dB dB dBm dBm dB 20.6 ±0.01 ±0.31 ±0.01 −25.7 −23.7 20.2 40.0 2.7 dB dB dB dB dB dB dBm dBm dB 20.3 ±0.11 ±0.36 ±0.01 −18.3 −15.7 20.2 39.0 2.9 dB dB dB dB dB dB dBm dBm dB 17.6 ±1.0 ±0.04 ±0.04 −10.4 −7.7 18.3 30.0 2.8 dB dB dB dB dB dB dBm dBm dB Typ Max 4000 Unit MHz
Rev. 0 | Page 3 of 24
ADL5240
Parameter AMPLIFIER FREQUENCY = 1960 MHz Gain vs. Frequency vs. Temperature vs. Supply Input Return Loss Output Return Loss Output 1 dB Compression Point Output Third-Order Intercept Noise Figure AMPLIFIER FREQUENCY = 2140 MHz Gain vs. Frequency vs. Temperature vs. Supply Input Return Loss Output Return Loss Output 1 dB Compression Point Output Third-Order Intercept Noise Figure AMPLIFIER FREQUENCY = 2630 MHz Gain vs. Frequency vs. Temperature vs. Supply Input Return Loss Output Return Loss Output 1 dB Compression Point Output Third-Order Intercept Noise Figure AMPLIFIER FREQUENCY = 3600 MHz Gain vs. Frequency vs. Temperature vs. Supply Input Return Loss Output Return Loss Output 1 dB Compression Point Output Third-Order Intercept Noise Figure DSA FREQUENCY = 150 MHz Insertion Loss vs. Frequency vs. Temperature Attenuation Range Attenuation Step Error Attenuation Absolute Error Input Return Loss Output Return Loss Input Third-Order Intercept Test Conditions/Comments Using the AMPIN and AMPOUT pins ±30 MHz −40°C ≤ TA ≤ +85°C 4.75 V to 5.25 V S11 S22 ∆f = 1 MHz, POUT = 4 dBm/tone Using the AMPIN and AMPOUT pins 18.0 ±30 MHz −40°C ≤ TA ≤ +85°C 4.75 V to 5.25 V S11 S22 17.5 ∆f = 1 MHz, POUT = 4 dBm/tone Using the AMPIN and AMPOUT pins 18.0 ±60 MHz −40°C ≤ TA ≤ +85°C 4.75 V to 5.25 V S11 S22 18.0 ∆f = 1 MHz, POUT = 4 dBm/tone Using the AMPIN and AMPOUT pins ±100 MHz −40°C ≤ TA ≤ +85°C 4.75 V to 5.25 V S11 S22 ∆f = 1 MHz, POUT = 4 dBm/tone Using the DSAIN and DSAOUT pins Minimum attenuation ±50 MHz −40°C ≤ TA ≤ +85°C All attenuation states All attenuation states Minimum attenuation Minimum attenuation ∆f = 1 MHz, POUT = 4 dBm/tone, minimum attenuation 19.6 ±0.03 ±0.05 ±0.10 −15.1 −12.2 18.8 37.0 3.1 −1.5 ±0.12 ±0.09 28.8 ±0.18 ±1.35 −13.3 −13.4 45.5 dB dB dB dB dB dB dBm dBm dB dB dB dB dB dB dB dB dB dBm 19.6 ±0.01 ±0.22 ±0.04 −11.0 −13.3 19.9 41.0 2.9 22.0 dB dB dB dB dB dB dBm dBm dB 19.7 ±0.02 ±0.25 ±0.04 −11.0 −12.0 19.5 41.0 2.9 22.0 dB dB dB dB dB dB dBm dBm dB Min Typ 19.8 ±0.03 ±0.26 ±0.03 −11.9 −12.6 19.8 40.0 2.9 Max Unit dB dB dB dB dB dB dBm dBm dB
Rev. 0 | Page 4 of 24
ADL5240
Parameter DSA FREQUENCY = 450 MHz Insertion Loss vs. Frequency vs. Temperature Attenuation Range Attenuation Step Error Attenuation Absolute Error Input Return Loss Output Return Loss Input Third-Order Intercept DSA FREQUENCY = 748 MHz Insertion Loss vs. Frequency vs. Temperature Attenuation Range Attenuation Step Error Attenuation Absolute Error Input Return Loss Output Return Loss Input Third-Order Intercept DSA FREQUENCY = 943 MHz Insertion Loss vs. Frequency vs. Temperature Attenuation Range Attenuation Step Error Attenuation Absolute Error Input Return Loss Output Return Loss Input 1 dB Compression Point Input Third-Order Intercept DSA FREQUENCY = 1960 MHz Insertion Loss vs. Frequency vs. Temperature Attenuation Range Attenuation Step Error Attenuation Absolute Error Input Return Loss Output Return Loss Input 1 dB Compression Point Input Third-Order Intercept DSA FREQUENCY = 2140 MHz Insertion Loss vs. Frequency vs. Temperature Attenuation Range Attenuation Step Error Attenuation Absolute Error Input Return Loss Output Return Loss Input 1 dB Compression Point Input Third-Order Intercept Test Conditions/Comments Using the DSAIN and DSAOUT pins Minimum attenuation ±50 MHz −40°C ≤ TA ≤ +85°C All attenuation states All attenuation states Minimum attenuation Minimum attenuation ∆f = 1 MHz, POUT = 4 dBm/tone, minimum attenuation Using the DSAIN and DSAOUT pins Minimum attenuation ±50 MHz −40°C ≤ TA ≤ +85°C All attenuation states All attenuation states Minimum attenuation Minimum attenuation ∆f = 1 MHz, POUT = 4 dBm/tone, minimum attenuation Using the DSAIN and DSAOUT pins Minimum attenuation ±18 MHz −40°C ≤ TA ≤ +85°C All attenuation states All attenuation states Minimum attenuation Minimum attenuation Minimum attenuation ∆f = 1 MHz, POUT = 4 dBm/tone, minimum attenuation Using the DSAIN and DSAOUT pins Minimum attenuation ±30 MHz −40°C ≤ TA ≤ +85°C All attenuation states All attenuation states Minimum attenuation Minimum attenuation Minimum attenuation ∆f = 1 MHz, POUT = 4 dBm/tone, minimum attenuation Using the DSAIN and DSAOUT pins Minimum attenuation ±30 MHz −40°C ≤ TA ≤ +85°C All attenuation states All attenuation states Minimum attenuation Minimum attenuation Minimum attenuation ∆f = 1 MHz, POUT = 4 dBm/tone, minimum attenuation
Rev. 0 | Page 5 of 24
Min
Typ −1.5 ±0.02 ±0.10 30.7 ±0.14 ±0.42 −17.6 −17.6 41.0 −1.6 ±0.02 ±0.11 30.9 ±0.15 ±0.32 −17.4 −17.4 40 −1.6 ±0.01 ±0.12 30.9 ±0.13 ±0.30 −16.6 −16.5 30.5 48.5 −2.4 ±0.02 ±0.16 31.0 ±0.15 ±0.29 −12.0 −11.5 31.5 45.0 −2.5 ±0.02 ±0.17 31.0 ±0.12 ±0.26 −11.9 −11.2 31.5 44.5
Max
Unit dB dB dB dB dB dB dB dB dBm dB dB dB dB dB dB dB dB dBm dB dB dB dB dB dB dB dB dBm dBm dB dB dB dB dB dB dB dB dBm dBm dB dB dB dB dB dB dB dB dBm dBm
ADL5240
Parameter DSA FREQUENCY = 2630 MHz Insertion Loss vs. Frequency vs. Temperature Attenuation Range Attenuation Step Error Attenuation Absolute Error Input Return Loss Output Return Loss Input 1 dB Compression Point Input Third-Order Intercept DSA FREQUENCY = 3600 MHz Insertion Loss vs. Frequency vs. Temperature Attenuation Range Attenuation Step Error Attenuation Absolute Error Input Return Loss Output Return Loss Input 1 dB Compression Point Input Third-Order Intercept DIGITAL STEP ATTENUATOR GAIN SETTLING Minimum Attenuation to Maximum Attenuation Maximum Attenuation to Minimum Attenuation AMP-DSA LOOP FREQUENCY = 943 MHz Gain vs. Frequency Gain Range Input Return Loss Output Return Loss Output 1 dB Compression Point Output Third-Order Intercept Noise Figure AMP-DSA LOOP FREQUENCY = 2140 MHz Gain vs. Frequency Gain Range Input Return Loss Output Return Loss Output 1 dB Compression Point Output Third-Order Intercept Noise Figure Test Conditions/Comments Using the DSAIN and DSAOUT pins Minimum attenuation ±60 MHz −40°C ≤ TA ≤ +85°C All attenuation states All attenuation states Minimum attenuation Minimum attenuation Minimum attenuation ∆f = 1 MHz, POUT = 4 dBm/tone, minimum attenuation Using the DSAIN and DSAOUT pins Minimum attenuation ±100 MHz −40°C ≤ TA ≤ +85°C All attenuation states All attenuation states Minimum attenuation Minimum attenuation Minimum attenuation ∆f = 1 MHz, POUT = 4 dBm/tone, minimum attenuation Min Typ −2.6 ±0.04 ±0.19 31.2 ±0.16 ±0.19 −13.1 −12.0 31.5 43.0 −2.8 ±0.03 ±0.21 32.1 ±0.37 ±0.31 −20.2 −18.2 31.0 43.0 36 36 Using the AMPIN and DSAOUT pins, DSA at minimum attenuation ±18 MHz Between maximum and minimum attenuation states S11 S22 ∆f = 1 MHz, POUT = 1 dBm/tone Using the AMPIN and DSAOUT pins, DSA at minimum attenuation ±30 MHz Between maximum and minimum attenuation states S11 S22 ∆f = 1 MHz, POUT = 1 dBm/tone 18.2 ±0.01 31.3 −14.9 −16.4 17.9 37.5 3.0 dB dB dB dB dB dBm dBm dB 18.9 ±0.01 30.8 −20.5 −19.7 18.6 36.0 2.7 dB dB dB dB dB dBm dBm dB Max Unit dB dB dB dB dB dB dB dB dBm dBm dB dB dB dB dB dB dB dB dBm dBm ns ns
Rev. 0 | Page 6 of 24
ADL5240
Parameter AMP-DSA LOOP FREQUENCY = 2630 MHz Gain vs. Frequency Gain Range Input Return Loss Output Return Loss Output 1 dB Compression Point Output Third-Order Intercept Noise Figure DSA-AMP LOOP FREQUENCY = 943 MHz Gain vs. Frequency Gain Range Input Return Loss Output Return Loss Output 1 dB Compression Point Output Third-Order Intercept Noise Figure DSA-AMP LOOP Frequency = 2140 MHz Gain vs. Frequency Gain Range Input Return Loss Output Return Loss Output 1 dB Compression Point Output Third-Order Intercept Noise Figure DSA-AMP LOOP Frequency = 2630 MHz Gain vs. Frequency Gain Range Input Return Loss Output Return Loss Output 1 dB Compression Point Output Third-Order Intercept Noise Figure POWER SUPPLIES Voltage Supply Current Amplifier Digital Step Attenuator Test Conditions/Comments Using the AMPIN and DSAOUT pins, DSA at minimum attenuation ±60 MHz S11 S22 ∆f = 1 MHz, POUT = 1 dBm/tone Using the DSAIN and AMPOUT pins, DSA at minimum attenuation ±18 MHz Between maximum and minimum attenuation states S11 S22 ∆f = 1 MHz, POUT = 4 dBm/tone Using the DSAIN and AMPOUT pins, DSA at minimum attenuation ±30 MHz Between maximum and minimum attenuation states S11 S22 ∆f = 1 MHz, POUT = 4 dBm/tone Using the DSAIN and AMPOUT pins, DSA at minimum attenuation ±60 MHz Between maximum and minimum attenuation states S11 S22 ∆f = 1 MHz, POUT = 4 dBm/tone Using the VDD and VCC pins 4.75 5.0 93 0.5 5.25 120 V mA mA 18.2 ±0.01 31.7 −15.7 −16.9 19.8 40.8 5.2 dB dB dB dB dB dBm dBm dB 18.0 ±0.01 31.1 −13.7 −10.0 19.7 37.5 4.9 dB dB dB dB dB dBm dBm dB 18.9 ±0.01 30.8 −17.2 −23.7 20.2 40.0 4.4 dB dB dB dB dB dBm dBm dB Min Typ Max Unit
17.7 ±0.11 31.5 −15.2 −9.6 16.9 33.7 3.0
dB dB dB dB dB dBm dBm dB
Rev. 0 | Page 7 of 24
ADL5240 ABSOLUTE MAXIMUM RATINGS
Table 2.
Parameter Supply Voltage (VDD, VCC) Input Power AMPIN DSAIN Internal Power Dissipation θJA (Exposed Pad Soldered Down) θJC (Exposed Pad is the Contact) Maximum Junction Temperature Lead Temperature (Soldering, 60 sec) Operating Temperature Range Storage Temperature Range Rating 6.5 V 16 dBm 30 dBm 0.5 W 36.8°C/W 6.9°C/W 150°C 240°C −40°C to +85°C −65°C to +150°C
ESD CAUTION
Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.
Rev. 0 | Page 8 of 24
ADL5240 PIN CONFIGURATION AND FUNCTION DESCRIPTIONS
32 31 30 29 28 27 26 25
VDD NC NC DSAIN NC NC NC NC 1 2 3 4 5 6 7 8 24 23 22 21 20 19 18 17
SEL D0/CLK D1/DATA D2/LE D3 D4 D5 D6
PIN 1 INDICATOR
ADL5240
TOP VIEW (Not to Scale)
VDD NC NC DSAOUT NC NC NC NC
NC AMPOUT/VCC NC NC NC NC AMPIN NC
9 10 11 12 13 14 15 16
NOTES 1. NC = NO CONNECT. DO NOT CONNECT TO THIS PIN. 2. THE EXPOSED PAD MUST BE CONNECTED TO GROUND.
Figure 2. Pin Configuration
Table 3. Pin Function Descriptions
Pin No. 1, 24 2, 3, 5, 6, 7, 8, 9, 11, 12, 13, 14, 16, 17, 18, 19, 20, 22, 23 4 10 15 21 25 26 27 28 29 30 31 32 Mnemonic VDD NC Description Supply Voltage for DSA. Connect this pin to a 5 V supply. No Connect. Do not connect to this pin.
DSAIN AMPOUT/VCC AMPIN DSAOUT D6 D5 D4 D3 D2/LE D1/DATA D0/CLK SEL EPAD
RF Input to DSA. RF Output from Amplifier/Supply Voltage for Amplifier. A bias to the amplifier is provided through a choke inductor connected to this pin. RF Input to Amplifier. RF Output from DSA. Data Bit in Parallel Mode (LSB). Connect this pin to the supply in serial mode. Data Bit in Parallel Mode. Connect this pin to ground in serial mode. Data Bit in Parallel Mode. Connect this pin to ground in serial mode. Data Bit in Parallel Mode. Connect this pin to ground in serial mode. Data Bit in Parallel Mode/Latch Enable in Serial Mode. Data Bit in Parallel Mode (MSB)/Data in Serial Mode. Connect this pin to ground in parallel mode. This pin functions as a clock in serial mode. Select Pin. Connect this pin to the supply to select parallel mode operation; connect this pin to ground to select serial mode operation. Exposed Pad. The exposed pad must be connected to ground.
Rev. 0 | Page 9 of 24
09430-002
ADL5240 TYPICAL PERFORMANCE CHARACTERISTICS
45
30 28
45 40 35 30 25 20 15 10 3.6
NOISE FIGURE, GAIN, P1dB, OIP3 (dB, dBm)
40 35 30 OIP3
26
P1dB (dBm)
25 20 15 GAIN 10 5 0 0 0.4 0.8 1.2 1.6 2.0 2.4 2.8 3.2 3.6 FREQUENCY (GHz) NF
09430-003
24 22 20 18 16
+85°C +25°C –40°C 0 0.4 0.8 1.2 1.6 2.0 2.4 2.8 3.2
OIP3 (dBm)
09430-008 09430-007
09430-006
P1dB
FREQUENCY (GHz)
Figure 3. AMP: Gain, P1dB, OIP3 at POUT = 4 dBm/Tone and Noise Figure vs. Frequency
Figure 6. AMP: OIP3 at POUT = 4 dBm/Tone and P1dB vs. Frequency and Temperature
21.0 20.5 –40°C 20.0
46
1960MHz
44 42 40 38
2140MHz 943MHz
748MHz
OIP3 (dBm)
GAIN (dB)
19.5 19.0 18.5
+25°C +85°C
36 34 32 30 28
450MHz
2630MHz
18.0 17.5 0 0.4 0.8 1.2 1.6 2.0 2.4 2.8 3.2 3.6 FREQUENCY (GHz)
26 24
09430-004
150MHz
3600MHz
22 –5
–3
–1
1
3
5
7
9
11
13
15
17
POUT PER TONE (dBm)
Figure 4. AMP: Gain vs. Frequency and Temperature
Figure 7. AMP: OIP3 vs. POUT and Frequency
0 –5
4.5
4.0
–10
S-PARAMETERS (dB)
+85°C
NOISE FIGURE (dB)
S22
–15 –20
3.5 +25°C
3.0
S12
–25 –30
2.5
–40°C
2.0
–35
S11
0.5 0.9 1.3 1.7 2.1 2.5 2.9 3.3 3.7 4.1
09430-005
–40 0.1
1.5 0 0.4 0.8 1.2 1.6 2.0 2.4 2.8 3.2 3.6 4.0 FREQUENCY (GHz)
FREQUENCY (GHz)
Figure 5. AMP: Input Return Loss (S11), Output Return Loss (S22), and Reverse Isolation (S12) vs. Frequency
Figure 8. AMP: Noise Figure vs. Frequency and Temperature
Rev. 0 | Page 10 of 24
ADL5240
0 –5 –10 0dB
1.0 0.8 0.6
31.5dB 16dB 30.5dB
ATTENUATION (dB)
–15 –20 –25 –30
STEP ERROR (dB)
0.4 0.2 0 –0.2 –0.4 –0.6
31dB
–35 31.5dB 0.5 0.9 1.3 1.7 2.1 2.5 2.9 3.3 3.7 4.1
09430-009
–0.8 0.5 0.9 1.3 1.7 2.1 2.5 2.9 3.3 3.7 4.1
09430-016
09430-013 09430-012
–40 0.1
–1.0 0.1
FREQUENCY (GHz)
FREQUENCY (GHz)
Figure 9. DSA: Attenuation vs. Frequency
Figure 12. DSA: Step Error vs. Frequency, All Attenuation States
–1 –6 –11 –16 16dB –21 –26 –31 8dB
0dB
1.0
748MHz
0.8
450MHz
4dB
1960MHz
0.6
ABSOLUTE ERROR (dB)
ATTENUATION (dB)
0.4 0.2
2140MHz
0 –0.2 –0.4 –0.6 –0.8
2630MHz
943MHz
+85°C +25°C –40°C
3600MHz
31.5dB
09430-010
–36 0.1
–1.0 0 4 8 12 16 20 24 28 32
0.5
0.9
1.3
1.7
2.1
2.5
2.9
3.3
3.7
4.1
FREQUENCY (GHz)
ATTENUATION (dB)
Figure 10. DSA: Attenuation vs. Frequency and Temperature
Figure 13. DSA: Absolute Error vs. Attenuation
0.5 0.4 0.3
450MHz 748MHz 943MHz
1960MHz 2140MHz 2630MHz 3600MHz
0 –5
INPUT RETURN LOSS (dB)
–10 –15 –20
STEP ERROR (dB)
0.2 0.1 0 –0.1 –0.2 –0.3 –0.4 0 4 8 12 16 20 24 28 32
09430-011
0dB
31.5dB –25 –30 –35 –40 0.1
–0.5
0.5
0.9
1.3
1.7
2.1
2.5
2.9
3.3
3.7
4.1
ATTENUATION (dB)
FREQUENCY (GHz)
Figure 11. DSA: Step Error vs. Attenuation
Figure 14. DSA: Input Return Loss vs. Frequency, All States
Rev. 0 | Page 11 of 24
ADL5240
0 –5
OUTPUT RETURN LOSS (dB)
–10 –15
0dB
3
–20 31.5dB –25 –30 –35
09430-014
4
–40 0.1
0.5
0.9
1.3
1.7
2.1
2.5
2.9
3.3
3.7
4.1
CH3 2.00V
CH4 200mV
FREQUENCY (GHz)
M10ns 10GS/s A CH3 IT 1.0ps/pt
1.24V
Figure 15. DSA: Output Return Loss vs. Frequency, All States
Figure 18. DSA: Gain Settling Time, 0 dB to 31.5 dB
36
50
35 IIP3 34
45
40
IP1dB (dBm)
IIP3 (dBm)
3
33
35
32 IP1dB 31
30
4
25
09430-015
30 0.9
1.2
1.5
1.8
2.1
2.4
2.7
3.0
3.3
20 3.6
CH3 2.00V
CH4 200mV
FREQUENCY (GHz)
M10ns 10GS/s A CH3 IT 1.0ps/pt
1.24V
Figure 16. DSA: Input P1dB and Input IP3 vs. Frequency, Minimum Attenuation State
Figure 19. DSA: Gain Settling Time, 31.5 dB to 0 dB
200 150 100
22
1960MHz
20
GAIN AND NOISE FIGURE (dB)
18 GAIN 16 14 12 10 8 6 4 2 NOISE FIGURE
2140MHz
PHASE (Degrees)
50 0 –50 –100
2630MHz
943MHz
09430-017
0
4
8
12
16
20
24
28
32
0.5
0.9
1.3
1.7
2.1
2.5
2.9
3.3
3.7
4.1
ATTENUATION (dB)
FREQUENCY (GHz)
Figure 17. DSA: Phase vs. Attenuation
Figure 20. AMP-DSA Loop: Gain and Noise Figure vs. Frequency, Minimum Attenuation State
Rev. 0 | Page 12 of 24
09430-020
–150
0 0.1
09430-019
09430-018
ADL5240
0 –5 –10 S11 22 20 S22
GAIN AND NOISE FIGURE (dB)
18 GAIN 16 14 12 10 8 6 4 2 NOISE FIGURE
S-PARAMETERS (dB)
–15 –20 –25 S12 –30 –35
09430-021
0.5
0.9
1.3
1.7
2.1
2.5
2.9
3.3
3.7
4.1
0.5
0.9
1.3
1.7
2.1
2.5
2.9
3.3
3.7
4.1
FREQUENCY (GHz)
FREQUENCY (GHz)
Figure 21. AMP-DSA Loop: Input Return Loss (S11), Output Return Loss (S22), and Reverse Isolation (S12) vs. Frequency, Minimum Attenuation State
40 38 36 943MHz 34
OIP3 (dBm)
Figure 24. DSA-AMP Loop: Gain and Noise Figure vs. Frequency, Minimum Attenuation State
0 –5 S22 –10 S11 –15 –20 –25 S12 –30 –35 0.1
32 30 28 26 24 22 –4 –2 0 2 4 6 8 10 12 14 16
09430-022
2140MHz 2630MHz
S-PARAMETERS (dB)
20 –6
0.5
0.9
1.3
1.7
2.1
2.5
2.9
3.3
3.7
4.1
POUT (dBm)
FREQUENCY (GHz)
Figure 22. AMP-DSA Loop: OIP3 vs. POUT and Frequency, Minimum Attenuation State
Figure 25. DSA-AMP Loop: Input Return Loss (S11), Output Return Loss (S22), and Reverse Isolation (S12) vs. Frequency, Minimum Attenuation State
20.0 19.5 19.0 18.5
GAIN (dB)
44 42 943MHz 40 38 2140MHz
OIP3 (dBm)
943MHz
36 34 32 30 2140MHz
18.0 2630MHz 17.5 17.0
28 16.5 16.0 –4 26
09430-023
2630MHz
–2
0
2
4
6
8
10
12
14
16
18
20
–4
–2
0
2
4
6
8
10
12
14
16
POUT (dBm)
POUT (dBm)
Figure 23. AMP-DSA Loop: Gain vs. POUT and Frequency, Minimum Attenuation State
Figure 26. DSA-AMP Loop: OIP3 vs. POUT and Frequency, Minimum Attenuation State
Rev. 0 | Page 13 of 24
09430-026
24 –6
09430-025
09430-024
–40 0.1
0 0.1
ADL5240
20.0 19.5 19.0 18.5
30
943MHz
25
PERCENTAGE (%)
09430-027
20
GAIN (dB)
2140MHz
18.0
15
2630MHz
17.5 17.0 16.5 16.0 –4
10
5
18.8
18.9
19.0
19.1
19.2
19.3
19.4
19.5
19.6
19.7
19.8
19.9
20.0
20.1
20.2
20.3
20.4
20.5
4.0
POUT (dBm)
P1dB (dBm)
Figure 27. DSA-AMP Loop: Gain vs. POUT and Frequency, Minimum Attenuation State
110
30
Figure 30. AMP: P1dB Distribution at 2140 MHz
105
25
SUPPLY CURRENT (mA)
5.25V
PERCENTAGE (%)
100 5.00V 95 4.75V 90
20
15
10
85
5
09430-028
0
10
20
30
40
50
60
70
80
90
33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 OIP3 (dBm)
TEMPERATURE (°C)
Figure 28. AMP: Supply Current vs. Voltage and Temperature
Figure 31. AMP: OIP3 Distribution at 2140 MHz
35 30 25
70 60 50
PERCENTAGE (%)
PERCENTAGE (%)
20 15 10 5 0
40 30 20 10 0
09430-029
2.0
2.2
2.4
2.6
2.8
3.0
3.2
3.4
3.6
3.8
GAIN (dB)
NOISE FIGURE (dB)
Figure 29. AMP: Gain Distribution at 2140 MHz
Figure 32. AMP: Noise Figure Distribution at 2140 MHz
Rev. 0 | Page 14 of 24
09430-032
18.8
18.9
19.0
19.1
19.2
19.3
19.4
19.5
19.6
19.7
19.8
19.9
20.0
20.1
20.2
20.3
20.4
20.5
09430-031
80 –40 –30 –20 –10
0
09430-030
–2
0
2
4
6
8
10
12
14
16
18
20
0
ADL5240 APPLICATIONS INFORMATION
BASIC LAYOUT CONNECTIONS
The basic connections for operating the ADL5240 are shown in Figure 33.
VDD SERIAL PARALLEL INTERFACE
VDD
0.1µF
C8
32 31 30 29 28 27 26 25
SEL D0/CLK D1/DATA D2/LE D3 D4 D5 D6
1 2
VDD NC NC DSAIN NC NC NC NC
VDD NC NC
24 23 22 21 20 19 18 17
DSAIN
100pF
3 4 5
100pF
DSAOUT
ADL5240
DSAOUT NC NC NC NC
C6
C7
6 7 8
9 10 11 12 13 14 15 16
NC AMPOUT/VCC NC NC NC NC AMPIN NC
AMPOUT
0.1µF
0.1µF
AMPIN
C2 L1 470nH
C1
C3 68pF C4 1.2nF C5
09430-033
VCC
1µF
Figure 33. Basic Connections
Rev. 0 | Page 15 of 24
ADL5240
Amplifier Bias
The dc bias for the amplifier in ADL5240 is supplied through Inductor L1 and is connected to the AMPOUT pin. Three decoupling capacitors (C3, C4, and C5) are used to prevent RF signals from propagating onto the dc lines. The dc supply ranges from 4.75 V to 5.25 V and should be connected to the VCC test point on the evaluation board.
DSA RF Input Interface
Pin 4 is the RF input for the DSA of ADL5240. The input impedance of the DSA is close to 50 Ω over the entire frequency range; therefore, no external components are required. Only a dc blocking capacitor (C6) is required.
DSA RF Output Interface
Pin 21 is the RF output for the DSA of ADL5240. The output impedance of the DSA is close to 50 Ω over the entire frequency range; therefore, no external components are required. Only a dc blocking capacitor (C7) is required.
Digital Step Attenuator Bias
The bias for the DSA is provided through the VDD pin. At least one decoupling capacitor (C8) is recommended on the VDD trace. The voltage ranges from 4.75 V to 5.25 V and should be connected to the VDD test point on the evaluation board. The DSA is shown to work for dc voltages as low as 2.5 V.
DSA SPI Interface
The DSA of the ADL5240 can operate in either serial or parallel mode. Pin 32 (SEL) controls the mode of operation. To select serial mode, connect SEL to ground; to select parallel mode, connect SEL to VDD. In parallel mode, Pin 25 to Pin 30 (D6 to D1) are the data bits, with D6 being the LSB. Connect Pin 31 (D0) to ground during the parallel mode of operation. In serial mode, Pin 29 is the latch enable (LE), Pin 30 is the data (DATA), and Pin 31 is the clock (CLK). Pin 26, Pin 27, and Pin 28 are not used in serial mode and should be connected to ground. Pin 25 (D6) should be connected to VDD during the serial mode of operation. To prevent noise from coupling onto the digital signals, an RC filter can be used on each data line.
Amplifier RF Input Interface
Pin 15 is the RF input for the amplifier of ADL5240. The amplifier is internally matched to 50 Ω at the input; therefore, no external components are required. Only a dc blocking capacitor (C1) is required.
Amplifier RF Output Interface
Pin 10 is the RF output for the amplifier of ADL5240. The amplifier is internally matched to 50 Ω at the output; therefore, no external components are required. Only a dc blocking capacitor (C2) is required. The bias is provided through this pin via a choke inductor.
Rev. 0 | Page 16 of 24
ADL5240
SPI TIMING
Table 5 provides details about the timing characteristics for the SPI signals—namely, the clock (CLK), latch enable (LE), and data (DATA) signals—and Figure 34 shows the corresponding SPI timing diagram. Table 4. Mode Selection Table
Pin 32 (SEL) Connect to Ground Connect to Supply Functionality Serial mode Parallel mode
SPI Timing Sequence
Figure 35 is the timing sequence for the SPI function using a 6-bit operation. The clock can be as fast as 20 MHz. In serial mode, Register B5 (MSB) is first and Register B0 (LSB) is last.
Table 5. SPI Timing Setup
Parameter fCLK t1 t2 t3 t4 t5 t6 Limit 10 30 30 10 10 10 30 Unit MHz ns min ns min ns min ns min ns min ns min Test Conditions/Comments Data clock frequency Clock high time Clock low time Data to clock setup time Clock to data hold time Clock low to LE setup time LE pulse width
t1
CLK
t5 t2
t3
DATA MSB B5
t4
B4 B3 B2 B1 LSB B0
t6
LE
09430-034
Figure 34. SPI Timing Diagram (Data Is Loaded MSB First), Serial Mode
D0/CLK
D1/DATA
MSB B5
B4
B3
B2
B1
LSB B0
D2/LE
D6
Figure 35. SPI Timing Sequence, Serial Mode
Rev. 0 | Page 17 of 24
09430-035
ADL5240
Table 6. DSA Attenuation Truth Table—Serial Mode
Attenuation State (dB) 0 (Reference) 0.5 1.0 2.0 4.0 8.0 16.0 31.5 B5 (MSB) 1 1 1 1 1 1 0 0 B4 1 1 1 1 1 0 1 0 B3 1 1 1 1 0 1 1 0 B2 1 1 1 0 1 1 1 0 B1 1 1 0 1 1 1 1 0 B0 (LSB) 1 0 1 1 1 1 1 0
Table 7. DSA Attenuation Truth Table—Parallel Mode
Attenuation State (dB) 0 (Reference) 0.5 1.0 2.0 4.0 8.0 16.0 31.5 D1 (MSB) 1 1 1 1 1 1 0 0 D2 1 1 1 1 1 0 1 0 D3 1 1 1 1 0 1 1 0 D4 1 1 1 0 1 1 1 0 D5 1 1 0 1 1 1 1 0 D6 (LSB) 1 0 1 1 1 1 1 0
Rev. 0 | Page 18 of 24
ADL5240
LOOP PERFORMANCE
The ADL5240 can be configured so that either the DSA precedes the amplifier (see Figure 36) or the amplifier precedes the DSA (see Figure 37). The performance of the loop configurations is presented in Figure 20 to Figure 27. To improve the overall return loss, a shunt capacitor can be placed between the amplifier and DSA. This helps to align the phases of the two blocks.
SERIAL PARALLEL INTERFACE
VDD
VDD
0.1µF
C7
32 31 30 29 28 27 26 25
SEL D0/CLK D1/DATA D2/LE D3 D4 D5 D6
1 2
VDD NC NC DSAIN NC NC NC NC
VDD NC NC
24 23 22 21 20 19 18 17
RFIN
100pF
3 4 5
ADL5240
DSAOUT NC NC NC NC
C6
6 7 8
9 10 11 12 13 14 15 16
NC AMPOUT/VCC NC NC NC NC AMPIN NC
RFOUT
0.1µF
100pF
C2 L1 470nH
C1
C3 68pF C4 1.2nF C5
09430-036
VCC
1µF
Figure 36. DSA-AMP Loop Configuration
Rev. 0 | Page 19 of 24
ADL5240
VDD SERIAL PARALLEL INTERFACE
VDD
0.1µF
C7
32 31 30 29 28 27 26 25
SEL D0/CLK D1/DATA D2/LE D3 D4 D5 D6
1 2 3 4 5 6 7
VDD NC NC DSAIN NC NC NC NC
VDD NC NC
24 23 22 21 20 19 18 17
100pF
RFOUT
ADL5240
DSAOUT NC NC NC NC
C6
C2 100pF
8
9 10 11 12 13 14 15 16
NC AMPOUT/VCC NC NC NC NC AMPIN NC
0.1µF
RFIN
C1 L1 470nH
C3 68pF C4 1.2nF C5
09430-037
VCC
1µF
Figure 37. AMP-DSA Loop Configuration
THERMAL CONSIDERATIONS
The ADL5240 is packaged in a thermally efficient, 5 mm × 5 mm, 32-lead LFCSP. The thermal resistance from junction to air (θJA) is 36.8oC/W. The thermal resistance for the product was extracted assuming a standard 4-layer JEDEC board with 25 conductive, epoxy filled thermal vias. The thermal resistance from junction to case (θJC) is 6.9oC/W, where case is the exposed pad of the lead frame package. The ADL5240 consumes approximately 93 mA with a 5 V supply voltage. Even though the part dissipates less than 0.5 W, for the best thermal performance, it is recommended to add as many thermal vias as possible under the exposed pad of the LFCSP. The thermal resistance values given in this section assume a minimum of 25 thermal vias arranged in a 5 × 5 array with a diameter of 13 mils and a pitch of 25 mils. Figure 38 shows a close-up of the thermal via distribution under the exposed pad.
Figure 38. Exposed Pad with Thermal Via Distribution
Rev. 0 | Page 20 of 24
09430-038
ADL5240 EVALUATION BOARD
The schematic of the ADL5240 evaluation board is shown in Figure 39, the evaluation board configuration options are detailed in Table 8, and the layout of the ADL5240 evaluation board is shown in Figure 40 and Figure 41. Each RF trace on the evaluation board has a characteristic impedance of 50 Ω and is fabricated on Rogers3003 material. In addition, each trace is a coplanar waveguide (CPWG) with a width of 25 mils, a spacing of 20 mils, and a dielectric thickness of 10 mils. The input to and output from the DSA and amplifier should be ac-coupled with capacitors of appropriate values to ensure the broadband performance. The bias to the amplifier is provided by connecting a choke to the AMPOUT pin. Bypassing capacitors are recommended on all supply lines to minimize the RF coupling. The DSA and the amplifier can be individually biased or connected to the VDD plane using Resistors R2 and R1. The ADL5240 can be operated in two ways: the amplifier can precede the DSA (AMP-DSA loop configuration) or the DSA can precede the amplifier (DSA-AMP loop configuration). The evaluation board can be configured to handle either option. In normal operation, R12 and R13 are open, and R10 and R11 are 0 Ω and are used to terminate any RF coupling onto the bypass trace. To configure the ADL5240 in AMP-DSA loop configuration, R12 should be replaced with a capacitor, R13 should be replaced with a 0 Ω resistor, and R10 and R11 should be left open. Similarly, to configure the ADL5240 in the DSA-AMP loop configuration, R16 should be replaced with a capacitor, R17 should be replaced with a 0 Ω resistor, and R14 and R15 should be left open. The digital signal traces incorporate a footprint for an RC filter to prevent potential noise from coupling onto the signal. In normal operation, Resistors R3 to R9 are 0 Ω and Capacitors C9 to C15 are open.
Rev. 0 | Page 21 of 24
ADL5240
DATA R3 0 R4 0 R5 0 R6 0 R7 0 S1 AGND 3 2 R8 0 1 C9 DNI AGND VDD VDD R2 DNI PAD AGND C8 0.1µF AGND 32 31 30 29 28 27 26 25 C10 DNI AGND C11 DNI AGND C12 DNI AGND C13 DNI AGND C14 DNI AGND C15 AGND DNI AGND R9 0 1 2 3 4 5 6 7 8 9 LE CLK
SEL D0 D1 D2 D3 D4 D5 D6
DSAIN
C1 100pF R12 R10 0 R11 AGND 0 R13 DNI AGND DNI
NC AMPOUT/VCC NC NC NC NC AMPIN NC
1 2 3 4 5 6 7 8
VDD NC NC DSAIN NC NC NC NC
ADL5240
VDD NC NC DSAOUT NC NC NC NC
24 23 22 21 20 19 18 17
C2 100pF R16 R14 0 R15 AGND AGND 0 R17 DNI C3 DNI
DSAOUT
AMPOUT
C4 0.1µF VCC L1 470nH C7 68pF C6 1.2nF C5 1µF R1 DNI VDD AGND
9 10 11 12 13 14 15 16
AMPIN
0.1µF
AGND
Figure 39. ADL5240 Evaluation Board
Table 8. Evaluation Board Configuration Options
Component C1, C2 C3, C4 C5, C6, C7 Function/Notes Input/output dc blocking capacitors for DSA. Input/output dc blocking capacitors for AMP. Power supply decoupling for amplifier. The bias associated with the AMPOUT pin is the most sensitive to noise because the bias is connected directly to the output. The smallest capacitor (C7) should be the closest to the AMPOUT pin. Power supply decoupling for the DSA. Capacitors of the RC filter on the digital signals leading to the SPI chip. The bias for the amplifier comes through L1 when VCC is connected to a 5 V supply. L1 should be high impedance for the frequency of operation while providing low resistance for the dc current. Resistors to connect the supply for the amplifier and the DSA to the same VDD plane. Resistors of the RC filter on the digital signals leading to the SPI chip. These resistors are used to terminate RF coupling onto the traces and to close the loop. R12 and R16 are replaced with capacitors, and R13 and R17 are replaced with 0 Ω to close the loop. Switch to change between the serial mode and parallel mode of operation. Connect to supply for parallel mode and to ground for serial mode operation. Default Value C1, C2 = 100 pF C3, C4 = 0.1 μF C5 = 1 μF C6 = 1.2 nF C7 = 68 pF C8 = 0.1 μF C9, C10, C11, C12, C13, C14, C15 = open L1 = 470 nH
C8 C9, C10, C11, C12, C13, C14, C15 L1
R1, R2 R3, R4, R5, R6, R7, R8, R9 R10, R11, R14, R15 R12, R13, R16, R17 S1
R1, R2 = open R3, R4, R5, R6, R7, R8, R9 = 0 Ω R10, R11, R14, R15 = 0Ω R12, R13, R16, R17 = open S1 connected to ground
Rev. 0 | Page 22 of 24
09430-039
ADL5240
09430-040
Figure 40. Evaluation Board Layout—Top
Figure 41. Evaluation Board Layout—Bottom
Rev. 0 | Page 23 of 24
09430-041
ADL5240 OUTLINE DIMENSIONS
5.00 BSC SQ 0.60 MAX
25 24 PIN 1 INDICATOR 32 1
0.60 MAX PIN 1 INDICATOR 3.45 3.30 SQ 3.15
8 16 BOTTOM VIEW 9
4.75 BSC SQ
0.50 BSC
EXPOSED PAD
17 TOP VIEW
1.00 0.85 0.80 SEATING PLANE
12° MAX
0.80 MAX 0.65 TYP
0.50 0.40 0.30 0.05 MAX 0.02 NOM COPLANARITY 0.08 0.20 REF
0.25 MIN
3.50 REF FOR PROPER CONNECTION OF THE EXPOSED PAD, REFER TO THE PIN CONFIGURATION AND FUNCTION DESCRIPTIONS SECTION OF THIS DATA SHEET.
COMPLIANT TO JEDEC STANDARDS MO-220-VHHD-2
Figure 42. 32-Lead Lead Frame Chip Scale Package [LFCSP_VQ] 5 mm × 5 mm Body, Very Thin Quad (CP-32-3) Dimensions shown in millimeters
ORDERING GUIDE
Model 1 ADL5240ACPZ-R7 ADL5240-EVALZ
1
Temperature Range −40°C to +85°C
Package Description 32 Lead LFCSP_VQ, 7" Tape and Reel Evaluation Board
Package Option CP-32-3
Z = RoHS Compliant Part.
©2011 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. D09430-0-7/11(0)
Rev. 0 | Page 24 of 24
05-25-2011-A
0.30 0.25 0.18
