Data Sheet
FEATURES
Operating frequency from 100 MHz to 4000 MHz Digitally controlled VGA with serial and parallel interfaces 6-bit, 0.5 dB digital step attenuator 31.5 dB gain control range with ±0.25 dB step accuracy Gain Block Amplifier 1 Gain: 19.2 dB at 2140 MHz OIP3: 40.2 dBm at 2140 MHz P1dB: 19.8 dBm at 2140 MHz Noise figure: 2.9 dB at 2140 MHz ¼ W Driver Amplifier 2 Gain: 14.2 dB at 2140 MHz OIP3: 41.1 dBm at 2140 MHz P1dB: 26.0 dBm at 2140 MHz Noise figure: 3.7 dB at 2140 MHz Gain block, DSA, or ¼ W driver amplifier can be first Low quiescent current of 175 mA The companion ADL5240 integrates a gain block with DSA
100 MHz to 4000 MHz RF/IF Digitally Controlled VGA ADL5243
GENERAL DESCRIPTION
The ADL5243 is a high performance, digitally controlled variable gain amplifier operating from 100 MHz to 4000 MHz. The VGA integrates two high performance amplifiers and a digital step attenuator (DSA). Amplifier 1 (AMP1) is an internally matched gain block amplifier with 20 dB gain, and Amplifier 2 (AMP2) is a broadband ¼ W driver amplifier. The DSA is 6-bit with a 31.5 dB gain control range, 0.5 dB steps, and ±0.25 dB step accuracy. The attenuation of the DSA can be controlled using a serial or parallel interface. The gain block and DSA are internally matched to 50 Ω at their inputs and outputs, and all three internal devices are separately biased. The separate bias allows all or part of the ADL5243 to be used, which allows for easy reuse throughout a design. The pinout of the ADL5243 also enables the gain block, DSA, or ¼ W driver amplifier to be first, giving the VGA maximum flexibility in a signal chain. The ADL5243 consumes 175 mA and operates off a single supply ranging from 4.75 V to 5.25 V. The VGA is packaged in a thermally efficient, 5 mm × 5 mm, 32-lead LFCSP and is fully specified for operation from −40°C to +85°C. A fully populated evaluation board is available.
APPLICATIONS
Wireless infrastructure Automated test equipment RF/IF gain control
FUNCTIONAL BLOCK DIAGRAM
D1/DATA D0/CLK D2/LE SEL D3 D4 D5 D6
25
32
31
30
29
28
27
26
VDD 1 SERIAL/PARALLEL INTERFACE NC 2
24 VDD
23 NC
NC 3
22 NC
DSAIN 4 0.5dB NC 5 1dB 2dB 4dB 8dB 16dB
21 DSAOUT
20 NC
ADL5243
AMP1OUT/VCC 6
19 AMP2IN
NC 7
AMP1
AMP2
18 NC
NC 8
9 10 11 12 13 14 15 16
17 NC
AMP2OUT/VCC2
AMP1IN
NC
NC
NC
NC
NC
VBIAS
Figure 1.
Rev. A
Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective owners.
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09431-001
ADL5243 TABLE OF CONTENTS
Features .............................................................................................. 1 General Description ......................................................................... 1 Functional Block Diagram .............................................................. 1 Revision History ............................................................................... 2 Specifications..................................................................................... 3 Absolute Maximum Ratings............................................................ 9 ESD Caution.................................................................................. 9 Pin Configuration and Function Descriptions........................... 10 Typical Performance Characteristics ........................................... 11 Applications Information .............................................................. 20
Data Sheet
Basic Layout Connections......................................................... 20 SPI Timing................................................................................... 21 ADL5243 Amplifier 2 Matching .............................................. 23 ADL5243 Loop Performance.................................................... 26 Thermal Considerations............................................................ 26 Soldering Information and Recommended PCB Land Pattern................................................................................ 26 Evaluation Board ............................................................................ 27 Outline Dimensions ....................................................................... 30 Ordering Guide .......................................................................... 30
REVISION HISTORY
8/11—Rev. 0 to Rev. A Changes to Features Section............................................................ 1 7/11—Revision 0: Initial Version
Rev. A | Page 2 of 32
Data Sheet SPECIFICATIONS
VDD = 5V, VCC = 5V, VCC2 = 5V, TA = 25oC. Table 1.
Parameter OVERALL FUNCTION Frequency Range AMPLIFIER 1 FREQUENCY = 150 MHz Gain vs. Frequency vs. Temperature vs. Supply Input Return Loss Output Return Loss Output 1 dB Compression Point Output Third-Order Intercept Noise Figure AMPLIFIER 1 FREQUENCY = 450 MHz Gain vs. Frequency vs. Temperature vs. Supply Input Return Loss Output Return Loss Output 1 dB Compression Point Output Third-Order Intercept Noise Figure AMPLIFIER 1 FREQUENCY = 748 MHz Gain vs. Frequency vs. Temperature vs. Supply Input Return Loss Output Return Loss Output 1 dB Compression Point Output Third-Order Intercept Noise Figure AMPLIFIER 1 FREQUENCY = 943 MHz Gain vs. Frequency vs. Temperature vs. Supply Input Return Loss Output Return Loss Output 1 dB Compression Point Output Third-Order Intercept Noise Figure Conditions Min 100 Using the AMP1IN and AMP1OUT pins ±50 MHz −40°C ≤ TA ≤ +85°C 4.75 V to 5.25 V S11 S22 ∆f = 1 MHz, POUT = 3 dBm/tone Using the AMP1IN and AMP1OUT pins ±50 MHz −40°C ≤ TA ≤ +85°C 4.75 V to 5.25 V S11 S22 ∆f = 1 MHz, POUT = 3 dBm/tone Using the AMP1IN and AMP1OUT pins ±50 MHz −40°C ≤ TA ≤ +85°C 4.75 V to 5.25 V S11 S22 ∆f = 1 MHz, POUT = 3 dBm/tone Using the AMP1IN and AMP1OUT pins 19.0 ±18 MHz −40°C ≤ TA ≤ +85°C 4.75 V to 5.25 V S11 S22 18.5 ∆f = 1 MHz, POUT = 3 dBm/tone 20.3 ±0.01 ±0.28 ±0.02 −24.0 −21.5 19.9 40.4 2.7 20.8 ±0.02 ±0.32 ±0.01 −22.0 −21.6 19.6 39.6 2.7 20.6 ±0.10 ±0.36 ±0.01 −17.8 −16.5 19.5 38.4 2.8 18.2 ±0.97 ±0.07 ±0.03 −10.4 −8.2 18.4 29.5 2.8 Typ
ADL5243
Max 4000
Unit MHz dB dB dB dB dB dB dBm dBm dB dB dB dB dB dB dB dBm dBm dB dB dB dB dB dB dB dBm dBm dB
22.0
dB dB dB dB dB dB dBm dBm dB
Rev. A | Page 3 of 32
ADL5243
Parameter AMPLIFIER 1 FREQUENCY = 1960 MHz Gain vs. Frequency vs. Temperature vs. Supply Input Return Loss Output Return Loss Output 1 dB Compression Point Output Third-Order Intercept Noise Figure AMPLIFIER 1 FREQUENCY = 2140 MHz Gain vs. Frequency vs. Temperature vs. Supply Input Return Loss Output Return Loss Output 1 dB Compression Point Output Third-Order Intercept Noise Figure AMPLIFIER 1 FREQUENCY = 2630 MHz Gain vs. Frequency vs. Temperature vs. Supply Input Return Loss Output Return Loss Output 1 dB Compression Point Output Third-Order Intercept Noise Figure AMPLIFIER 1 FREQUENCY = 3600 MHz Gain vs. Frequency vs. Temperature vs. Supply Input Return Loss Output Return Loss Output 1 dB Compression Point Output Third-Order Intercept Noise Figure AMPLIFIER 2 FREQUENCY = 748 MHz Gain vs. Frequency Input Return Loss Output Return Loss Output 1 dB Compression Point Output Third-Order Intercept Noise Figure Conditions Using the AMP1IN and AMP1OUT pins ±30 MHz −40°C ≤ TA ≤ +85°C 4.75 V to 5.25 V S11 S22 ∆f = 1 MHz, POUT = 3 dBm/tone Using the AMP1IN and AMP1OUT pins 17.5 ±30 MHz −40°C ≤ TA ≤ +85°C 4.75 V to 5.25 V S11 S22 17.5 ∆f = 1 MHz, POUT = 3 dBm/tone Using the AMP1IN and AMP1OUT pins 17.5 ±60 MHz −40°C ≤ TA ≤ +85°C 4.75 V to 5.25 V S11 S22 17.5 ∆f = 1 MHz, POUT = 3 dBm/tone Using the AMP1IN and AMP1OUT pins ±100 MHz −40°C ≤ TA ≤ +85°C 4.75 V to 5.25 V S11 S22 ∆f = 1 MHz, POUT = 3 dBm/tone Using the AMP2IN and AMP2OUT pins ±50 MHz S11 S22 ∆f = 1 MHz, POUT = 5 dBm/tone Min Typ
Data Sheet
Max Unit dB dB dB dB dB dB dBm dBm dB 21.5 dB dB dB dB dB dB dBm dBm dB dB dB dB dB dB dB dBm dBm dB dB dB dB dB dB dB dBm dBm dB dB dB dB dB dBm dBm dB
19.5 ±0.02 ±0.26 ±0.04 −13.5 −12.4 19.6 40.4 2.9 19.2 ±0.02 ±0.26 ±0.05 −13.3 −12.2 19.8 40.2 2.9 19.0 ±0.03 ±0.22 ±0.05 −17.3 −12.3 19.5 39.5 2.9 18.0 ±0.10 ±0.05 ±0.12 −30.7 −9.0 18.0 34.6 3.3 17.5 ±0.14 −12.7 −8.6 24.7 41.5 5.6
21.5
Rev. A | Page 4 of 32
Data Sheet
Parameter AMPLIFIER 2 FREQUENCY = 943 MHz Gain vs. Frequency vs. Temperature vs. Supply Input Return Loss Output Return Loss Output 1 dB Compression Point Output Third-Order Intercept Noise Figure AMPLIFIER 2 FREQUENCY = 2140 MHz Gain vs. Frequency vs. Temperature vs. Supply Input Return Loss Output Return Loss Output 1 dB Compression Point Output Third-Order Intercept Noise Figure AMPLIFIER 2 FREQUENCY = 2630 MHz Gain vs. Frequency vs. Temperature vs. Supply Input Return Loss Output Return Loss Output 1 dB Compression Point Output Third-Order Intercept Noise Figure DSA FREQUENCY = 150 MHz Insertion Loss vs. Frequency vs. Temperature Attenuation Range Attenuation Step Error Attenuation Absolute Error Input Return Loss Output Return Loss Input Third-Order Intercept Conditions Using the AMP2IN and AMP2OUT pins ±18 MHz −40°C ≤ TA ≤ +85°C 4.75 V to 5.25 V S11 S22 ∆f = 1 MHz, POUT = 5 dBm/tone Using the AMP2IN and AMP2OUT pins 13.0 ±30 MHz −40°C ≤ TA ≤ +85°C 4.75 V to 5.25 V S11 S22 ∆f = 1 MHz, POUT = 5 dBm/tone Using the AMP2IN and AMP2OUT pins ±60 MHz −40°C ≤ TA ≤ +85°C 4.75 V to 5.25 V S11 S22 ∆f = 1 MHz, POUT = 5 dBm/tone Using the DSAIN and DSAOUT pins, minimum attenuation ±50 MHz −40°C ≤ TA ≤ +85°C Between maximum and minimum attenuation states All attenuation states All attenuation states −1.5 ±0.12 ±0.10 28.8 ±0.18 ±1.35 −13.5 −13.3 45.2 13.0 ±0.13 ±0.56 ±0.09 −9.4 −8.3 24.5 40.4 4.1 14.2 ±0.03 ±0.50 ±0.09 −10.7 −8.1 26.0 41.1 3.7 Min Typ 16.5 ±0.05 ±0.39 ±0.10 −11.2 −8.1 25.0 43.3 5.3
ADL5243
Max Unit dB dB dB dB dB dB dBm dBm dB 15.5 dB dB dB dB dB dB dBm dBm dB dB dB dB dB dB dB dBm dBm dB
∆f = 1 MHz, POUT = 5 dBm/tone
dB dB dB dB dB dB dB dB dBm
Rev. A | Page 5 of 32
ADL5243
Parameter DSA FREQUENCY = 450 MHz Insertion Loss vs. Frequency vs. Temperature Attenuation Range Attenuation Step Error Attenuation Absolute Error Input Return Loss Output Return Loss Input Third-Order Intercept DSA FREQUENCY = 748 MHz Insertion Loss vs. Frequency vs. Temperature Attenuation Range Attenuation Step Error Attenuation Absolute Error Input Return Loss Output Return Loss Input Third-Order Intercept DSA FREQUENCY = 943 MHz Insertion Loss vs. Frequency vs. Temperature Attenuation Range Attenuation Step Error Attenuation Absolute Error Input Return Loss Output Return Loss Input 1 dB Compression Point Input Third-Order Intercept DSA FREQUENCY = 1960 MHz Insertion Loss vs. Frequency vs. Temperature Attenuation Range Attenuation Step Error Attenuation Absolute Error Input Return Loss Output Return Loss Input 1 dB Compression Point Input Third-Order Intercept Conditions Using the DSAIN and DSAOUT pins, minimum attenuation ±50 MHz −40°C ≤ TA ≤ +85°C Between maximum and minimum attenuation states All attenuation states All attenuation states Min Typ
Data Sheet
Max Unit
∆f = 1 MHz, POUT = 5 dBm/tone Using the DSAIN and DSAOUT pins, minimum attenuation ±50 MHz −40°C ≤ TA ≤ +85°C Between maximum and minimum attenuation states All attenuation states All attenuation states
−1.4 ±0.02 ±0.12 30.7 ±0.14 ±0.39 −17.7 −17.4 41.2
dB dB dB dB dB dB dB dB dBm
∆f = 1 MHz, POUT = 5 dBm/tone Using the DSAIN and DSAOUT pins, minimum attenuation ±18 MHz −40°C ≤ TA ≤ +85°C Between maximum and minimum attenuation states All attenuation states All attenuation states
−1.5 ±0.02 ±0.12 30.9 ±0.15 ±0.30 −17.1 −17.1 40.4
dB dB dB dB dB dB dB dB dBm
∆f = 1 MHz, POUT = 5 dBm/tone Using the DSAIN and DSAOUT pins, minimum attenuation ±30 MHz −40°C ≤ TA ≤ +85°C Between maximum and minimum attenuation states All attenuation states All attenuation states
−1.6 ±0.01 ±0.13 30.9 ±0.15 ±0.28 −16.0 −15.9 30.5 48.3
dB dB dB dB dB dB dB dB dBm dBm
∆f = 1 MHz, POUT = 5 dBm/tone
−2.5 ±0.04 ±0.18 30.8 ±0.15 ±0.35 −10.3 −9.6 31.5 44.7
dB dB dB dB dB dB dB dB dBm dBm
Rev. A | Page 6 of 32
Data Sheet
Parameter DSA FREQUENCY = 2140 MHz Insertion Loss vs. Frequency vs. Temperature Attenuation Range Attenuation Step Error Attenuation Absolute Error Input Return Loss Output Return Loss Input 1 dB Compression Point Input Third-Order Intercept DSA FREQUENCY = 2630 MHz Insertion Loss vs. Frequency vs. Temperature Attenuation Range Attenuation Step Error Attenuation Absolute Error Input Return Loss Output Return Loss Input 1 dB Compression Point Input Third-Order Intercept DSA FREQUENCY = 3600 MHz Insertion Loss vs. Frequency vs. Temperature Attenuation Range Attenuation Step Error Attenuation Absolute Error Input Return Loss Output Return Loss Input 1 dB Compression Point Input Third-Order Intercept DSA Gain Settling Minimum Attenuation to Maximum Attenuation Maximum Attenuation to Minimum Attenuation LOOP FREQUENCY = 943 MHz Gain vs. Frequency Gain Range Input Return Loss Output Return Loss Output 1 dB Compression Point Output Third-Order Intercept Noise Figure Conditions Using the DSAIN and DSAOUT pins, minimum attenuation ±30 MHz −40°C ≤ TA ≤ +85°C Between maximum and minimum attenuation states All attenuation states All attenuation states Min Typ
ADL5243
Max Unit
∆f = 1 MHz, POUT = 5 dBm/tone Using the DSAIN and DSAOUT pins, minimum attenuation ±60 MHz −40°C ≤ TA ≤ +85°C Between maximum and minimum attenuation states All attenuation states All attenuation states
−2.6 ±0.02 ±0.19 30.9 ±0.13 ±0.32 −9.8 −9.3 31.5 44.6
dB dB dB dB dB dB dB dB dBm dBm
∆f = 1 MHz, POUT = 5 dBm/tone Using the DSAIN and DSAOUT pins, minimum attenuation ±100 MHz −40°C ≤ TA ≤ +85°C Between maximum and minimum attenuation states All attenuation states All attenuation states
−2.8 ±0.02 ±0.21 31.2 ±0.18 ±0.24 −10.0 −9.6 31.5 43.8
dB dB dB dB dB dB dB dB dBm dBm
∆f = 1 MHz, POUT = 5 dBm/tone Using the DSAIN and DSAOUT pins
−3.0 ±0.02 ±0.23 31.7 ±0.38 ±0.18 −12.3 −11.7 31.0 42.2 36 36
dB dB dB dB dB dB dB dB dBm dBm ns ns
AMP1–DSA–AMP2, DSA at minimum attenuation ±18 MHz Between maximum and minimum attenuation states S11 S22 ∆f = 1 MHz, POUT = 5 dBm/tone 34.0 ±0.10 29.3 −14.2 −10.1 25.1 42.8 2.9 dB dB dB dB dB dBm dBm dB
Rev. A | Page 7 of 32
ADL5243
Parameter LOOP FREQUENCY = 2140 MHz Gain vs. Frequency Gain Range Input Return Loss Output Return Loss Output 1 dB Compression Point Output Third-Order Intercept Noise Figure LOOP FREQUENCY = 2630 MHz Gain vs. Frequency Gain Range Input Return Loss Output Return Loss Output 1 dB Compression Point Output Third-Order Intercept Noise Figure POWER SUPPLIES Voltage Supply Current Conditions AMP1 – DSA – AMP2, DSA at minimum attenuation ±30 MHz Between maximum and minimum attenuation states S11 S22 ∆f = 1 MHz, POUT = 5 dBm/tone AMP1 – DSA – AMP2, DSA at minimum attenuation ±60 MHz Between maximum and minimum attenuation states S11 S22 ∆f = 1 MHz, POUT = 5 dBm/tone Min Typ
Data Sheet
Max Unit dB dB dB dB dB dBm dBm dB dB dB dB dB dB dBm dBm dB 5.25 120 120 V mA mA mA
31.3 ±0.03 32.5 −9.3 −5.4 25.3 40.0 3.1 29.5 ±0.56 30.0 −12.6 −5.8 24.6 39.3 3.1 4.75 5.0 89 86 0.5
AMP1 AMP2 DSA
Rev. A | Page 8 of 32
Data Sheet ABSOLUTE MAXIMUM RATINGS
Table 2.
Parameter Supply Voltage (VDD, VCC, VCC2) Input Power AMP1IN AMP2IN (50 Ω Impedance) DSAIN Internal Power Dissipation θJA (Exposed Paddle Soldered Down) θJC (Exposed Paddle) Maximum Junction Temperature Lead Temperature (Soldering, 60 sec) Operating Temperature Range Storage Temperature Range Rating 6.5 V 16 dBm 20 dBm 30 dBm 1.0 W 34.8°C/W 6.2°C/W 150°C 240°C −40°C to +85°C −65°C to +150°C
ADL5243
ESD CAUTION
Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.
Rev. A | Page 9 of 32
ADL5243 PIN CONFIGURATION AND FUNCTION DESCRIPTIONS
32 31 30 29 28 27 26 25 SEL D0/CLK D1/DATA D2/LE D3 D4 D5 D6
Data Sheet
VDD NC NC DSAIN NC AMP1OUT/VCC NC NC
1 2 3 4 5 6 7 8
PIN 1 INDICATOR
ADL5243
TOP VIEW (Not to Scale)
24 23 22 21 20 19 18 17
VDD NC NC DSAOUT NC AMP2IN NC NC
NC AMP1IN NC NC NC NC AMP2OUT/VCC2 VBIAS
9 10 11 12 13 14 15 16
NOTES 1. NC = NO CONNECT. DO NOT CONNECT TO THIS PIN. 2. THE EXPOSED PAD MUST BE CONNECTED TO GROUND.
Figure 2. Pin Configuration
Table 3. Pin Function Descriptions
Pin No. 1, 24 2, 3, 5, 7, 8, 9, 11, 12, 13, 14, 17, 18, 20, 22, 23 4 6 10 15 16 19 21 25 26 27 28 29 30 31 32 Mnemonic VDD NC DSAIN AMP1OUT/VCC AMP1IN AMP2OUT/VCC2 VBIAS AMP2IN DSAOUT D6 D5 D4 D3 D2/LE D1/DATA D0/CLK SEL EPAD Description Supply Voltage for DSA. Connect this pin to a 5 V supply. No Connect. Do not connect to this pin. RF Input to DSA. RF Output from Amplifier 1/Supply Voltage for Amplifier 1. Bias to Gain Block Amplifier 1 is provided through a choke to this pin when connected to VCC. RF Input to Gain Block Amplifier 1. RF Output from Amplifier 2/Supply Voltage for Amplifier 2. Bias to Driver Amplifier 2 is provided through a choke to this pin when connected to VCC2. Bias for Driver Amplifier 2. RF Input to Amplifier 2. RF Output from DSA. Data Bit in Parallel Mode (LSB). Connect to supply in serial mode. Data Bit in Parallel Mode. Connect to ground in serial mode. Data Bit in Parallel Mode. Connect to ground in serial mode. Data Bit in Parallel Mode. Connect to ground in serial mode. Data Bit in Parallel Mode/Latch Enable in Serial Mode. Data Bit in Parallel Mode (MSB)/Data in Serial Mode. Connect this pin to ground in parallel mode. This pin functions as a clock in serial mode. Select Pin. Connect this pin to the supply for parallel mode operation; connect this pin to ground for serial mode operation. Exposed Paddle. The exposed paddle must be connected to ground.
Rev. A | Page 10 of 32
09431-002
Data Sheet TYPICAL PERFORMANCE CHARACTERISTICS
45
NOISE FIGURE, GAIN, P1dB, OIP3 (dB, dBm)
ADL5243
28
OIP3
45 40 35 30 25 20 OIP3 (dBm)
09431-008 09431-007
40 35 30
26 24 P1dB (dBm)
P1dB
25 20 15 10 5 0 0 0.4 0.8 1.2 1.6 2.0 2.4
22 20 18 16 14
GAIN
NF
09431-003
+85°C +25°C –40°C
0 0.4 0.8 1.2 1.6 2.0 2.4 2.8 3.2
15 10 3.6
2.8
3.2
3.6
FREQUENCY (GHz)
FREQUENCY (GHz)
Figure 3. AMP1: Gain, P1dB, OIP3 at POUT = 3 dBm/Tone and Noise Figure vs. Frequency
22.0 21.5 21.0 20.5
Figure 6. AMP1: OIP3 at Pout = 3 dBm/Tone and P1dB vs. Frequency and Temperature
42 40 38 36 1960MHz 2140MHz 2630MHz 943MHz 450MHz 748MHz
OIP3 (dBm)
GAIN (dB)
20.0 19.5 19.0 18.5 18.0 17.5 0 0.4 0.8 1.2 1.6 +25°C
–40°C
34 32 30 28 26 24 22 3600MHz 150MHz
+85°C
2.0
2.4
2.8
3.2
3.6
09431-004
17.0
20 –4
–2
0
2
4
6
8
10
12
14
16
FREQUENCY (GHz)
POUT PER TONE (dBm)
Figure 4. AMP1: Gain vs. Frequency and Temperature
0 –5 –10 S22 S11 S12 NOISE FIGURE (dB)
4.0 3.5 3.0 2.5 2.0 1.5 5.0 4.5
Figure 7. AMP1: OIP3 vs. POUT and Frequency
S-PARAMETERS (dB)
–15 –20 –25 –30 –35 –40 –45 0.5 0.9 1.3 1.7 2.1 2.5 2.9
+85°C
+25°C
–40°C
3.3
3.7
4.1
09431-005
–50 0.1
0
0.4
0.8
1.2
1.6
2.0
2.4
2.8
3.2
3.6
4.0
FREQUENCY (GHz)
FREQUENCY (GHz)
Figure 5. AMP1: Input Return Loss (S11), Output Return Loss (S22), and Reverse Isolation (S12) vs. Frequency
Figure 8. AMP1: Noise Figure vs. Frequency and Temperature
Rev. A | Page 11 of 32
09431-006
ADL5243
50 NOISE FIGURE, GAIN, P1dB, OIP3 (dB, dBm) 45 40 35 P1dB (dBm) 30 25 20 15 10 5 0 0.925 0.930 0.935 0.940 0.945 0.950 NF P1dB OIP3 26.5 27.0
Data Sheet
45
43
26.0
41 OIP3 (dBm)
09431-014
25.5
39
GAIN
25.0
37
24.5
+85°C +25°C –40°C
35
09431-009
0.955
0.960
0.965
0.930
0.935
0.940
0.945
0.950
0.955
0.960
FREQUENCY (GHz)
FREQUENCY (GHz)
Figure 9. AMP2–943 MHz: Gain, P1dB, OIP3 at POUT = 5 dBm/Tone and Noise Figure vs. Frequency
18.0
Figure 12. AMP2–943 MHz: OIP3 at POUT = 5 dBm/Tone and P1dB vs. Frequency and Temperature
45 44 961MHz 43 42 41 40 39 943MHz
17.5 –40°C +25°C 16.5 +85°C 16.0
17.0
925MHz
15.5 38
09431-010
0.930
0.935
0.940
0.945
0.950
0.955
0.960
0.965
–2
0
2
4
6
8
10
12
14
16
18
FREQUENCY FREQUENCY (GHz)
POUT PER TONE (dBm)
Figure 10. AMP2–943 MHz: Gain vs. Frequency and Temperature
0 –5 S22 –10 –15 –20 –25 –30 –35 0.80 S11 7.5 7.0 6.5
Figure 13. AMP2–943 MHz: OIP3 vs. POUT and Frequency
S-PARAMETERS (dB)
NOISE FIGURE (dB)
6.0 5.5 5.0 4.5 4.0 3.5 0.80
+85°C
+25°C
S12
–40°C –40°C
09431-011
0.85
0.90
0.95
1.00
1.05
1.10
0.83
0.86
0.89
0.92
0.95
0.98
1.01
1.04
1.07
1.10
FREQUENCY (GHz)
FREQUENCY (GHz)
Figure 11. AMP2–943 MHz: Input Return Loss (S11), Output Return Loss (S22,) and Reverse Isolation (S12) vs. Frequency
Figure 14. AMP2–943 MHz: Noise Figure vs. Frequency and Temperature
Rev. A | Page 12 of 32
09431-013
15.0 0.925
OIP3 (dBm)
GAIN (dB)
37 –4
09431-012
24.0 0.925
33 0.965
Data Sheet
45
ADL5243
28.0
43
NOISE FIGURE, GAIN, P1dB, OIP3 (dB, dBm)
OIP3
40
27.5
35 30
41
27.0
P1dB (dBm)
39
25 20 15 10
26.5
37
GAIN
26.0
35
25.5
5 0 2.11
NF
09431-015
+85°C +25°C –40°C
33
2.12
2.13
2.14
2.15
2.16
2.17
2.12
2.13
2.14
2.15
2.16
FREQUENCY (GHz)
FREQUENCY (GHz)
Figure 15. AMP2–2140 MHz: Gain, P1dB, OIP3 at POUT = 5 dBm/Tone and Noise Figure vs. Frequency
16.0 15.5 15.0 14.5 14.0 13.5 13.0 12.5
09431-016
Figure 18. AMP2–2140 MHz: OIP3 at POUT = 5 dBm/Tone and P1dB vs. Frequency and Temperature
42
2.17GHz
41
–40°C +25°C +85°C
2.11GHz
40
OIP3 (dBm)
39 38 37 36 35 34 –6
2.14GHz
GAIN (dB)
2.12
2.13
2.14
2.15
2.16
2.17
–4
–2
0
2
4
6
8
10
12
14
16
18
20
22
FREQUENCY (GHz)
POUT PER TONE (dBm)
Figure 16. AMP2–2140 MHz: Gain vs. Frequency and Temperature
0
5.5 5.0
Figure 19. AMP2–2140 MHz: OIP3 vs. POUT and Frequency
–5 S11
S-PARAMETERS (dB)
–10
S22
NOISE FIGURE (dB)
4.5 4.0
+85°C
–15
+25°C 3.5 3.0 2.5 2.0 2.00 –40°C
–20 S12 –25
09431-017
2.05
2.10
2.15
2.20
2.25
2.30
2.03
2.06
2.09
2.12
2.15
2.18
2.21
2.24
2.27
2.30
FREQUENCY (GHz)
FREQUENCY (GHz)
Figure 17. AMP2–2140 MHz: Input Return Loss (S11), Output Return Loss (S22), and Reverse Isolation (S12) vs. Frequency
Figure 20. AMP2–2140 MHz: Noise Figure vs. Frequency and Temperature
Rev. A | Page 13 of 32
09431-020
–30 2.00
09431-019
12.0 2.11
09431-018
25.0 2.11
31 2.17
OIP3 (dBm)
P1dB
ADL5243
45
NOISE FIGURE, GAIN, P1dB, OIP3 (dB, dBm)
Data Sheet
28.0 42.0 41.5 41.0 40.5
OIP3 (dBm)
09431-026 09431-024
40 35 30 25 20 15 10 5 0 2.57
OIP3
27.5 27.0 26.5
P1dB
P1dB (dBm)
26.0 25.5 25.0 24.5 24.0
+85°C +25°C –40°C
40.0 39.5 39.0 38.5 38.0 37.5 2.61 2.63 2.65 2.67 37.0 2.69
GAIN
NF
23.5
09431-021
2.59
2.61
2.63
2.65
2.67
2.69
23.0 2.57
2.59
FREQUENCY (GHz)
FREQUENCY (GHz)
Figure 21. AMP2–2630 MHz: Gain, P1dB, OIP3 at POUT = 5 dBm/Tone and Noise Figure vs. Frequency
15.0 14.5 14.0 13.5
GAIN (dB)
Figure 24. AMP2–2630 MHz: OIP3 at POUT = 5 dBm/Tone and P1dB vs. Frequency and Temperature
42 41 40
2.69GHz 2.63GHz
–40°C
OIP3 (dBm)
39 38
2.57GHz
+25°C +85°C
37 36 35 34 33 32
13.0 12.5 12.0 11.5
09431-022
31 2.59 2.61 2.63 2.65 2.67 2.69
–4 –2 0 2 4 6 8 10 12 14 16 18 20 22
09431-025
11.0 2.57
30 –6
FREQUENCY (GHz)
POUT PER TONE (dBm)
Figure 22. AMP2–2630 MHz: Gain vs. Frequency and Temperature
0
6.0 5.5
Figure 25. AMP2–2630 MHz: OIP3 vs. POUT and Frequency
–5 S11
S-PARAMETERS (dB)
5.0 NOISE FIGURE (dB) 4.5 4.0 3.5 3.0 2.5 2.0 2.50
+85°C
–10
S22
–15
+25°C
–20 S12 –25
–40°C
2.55
2.60
2.65
2.70
2.75
2.80
09431-023
–30 2.50
2.53
2.56
2.59
2.62
2.65
2.68
2.71
2.74
2.77
2.80
FREQUENCY (GHz)
FREQUENCY (GHz)
Figure 23. AMP2–2630 MHz: Input Return Loss (S11), Output Return Loss (S22), and Reverse Isolation (S12) vs. Frequency
Figure 26. AMP2–2630 MHz: Noise Figure vs. Frequency and Temperature
Rev. A | Page 14 of 32
Data Sheet
0 –5 –10
ATTENUATION (dB)
ADL5243
0dB
1.0 0.8 0.6 450MHz 748MHz 943MHz 1960MHz 2140MHz 2630MHz 3600MHz
ABSOLUTE ERROR (dB)
31.5dB
09431-027
0.4 0.2 0 –0.2 –0.4 –0.6
–15 –20 –25 –30 –35 –40 0.1
–0.8
0.5
0.9
1.3
1.7
2.1
2.5
2.9
3.3
3.7
4.1
0
4
8
12
16
20
24
28
32
FREQUENCY (GHz)
ATTENUATION (dB)
Figure 27. DSA: Attenuation vs. Frequency
–1 –6 –11 –16 16dB –21 –26 –31 31.5dB
09431-028
Figure 30. DSA: Absolute Error vs. Attenuation
0dB
0
4dB 8dB
INPUT RETURN LOSS (dB)
–5 0dB –10
ATTENUATION (dB)
–15 31.5dB –20
+85°C +25°C –40°C
–25
0.5
0.9
1.3
1.7
2.1
2.5
2.9
3.3
3.7
4.1
0.5
0.9
1.3
1.7
2.1
2.5
2.9
3.3
3.7
4.1
FREQUENCY (GHz)
FREQUENCY (GHz)
Figure 28. DSA: Attenuation vs. Frequency and Temperature
0.5 0.4 0.3 450MHz 748MHz 943MHz 1960MHz 2140MHz 2630MHz 3600MHz
Figure 31. DSA: Input Return Loss vs. Frequency, All States
0
–5
OUTPUT RETURN LOSS (dB)
STEP ERROR (dB)
0.2 0.1 0 –0.1 –0.2 –0.3 –0.4
09431-029
–10
0dB
–15 31.5dB
–20
–25
0
4
8
12
16
20
24
28
32
0.5
0.9
1.3
1.7
2.1
2.5
2.9
3.3
3.7
4.1
ATTENUATION (dB)
FREQUENCY (GHz)
Figure 29. DSA: Step Error vs. Attenuation
Figure 32. DSA: Output Return Loss vs. Frequency, All States
Rev. A | Page 15 of 32
09431-032
–0.5
–30 0.1
09431-031
–36 0.1
–30 0.1
09431-030
–1.0
ADL5243
36
IIP3
50
Data Sheet
150
1960MHz
35
45
100
2140MHz
PHASE (Degrees)
34
IP1dB (dBm)
40
50
2630MHz
33
35
IIP3 (dBm)
0
32
IP1dB
30
–50
31
25
–100
943MHz
09431-033
1.2
1.5
1.8
2.1
2.4
2.7
3.0
3.3
0
4
8
12
16
20
24
28
32
FREQUENCY (GHz)
ATTENUATION (dB)
Figure 33. DSA: Input P1dB and Input IP3 vs. Frequency, Minimum Attenuation State
50
NOISE FIGURE, GAIN, P1dB, OIP3 (dB, dBm)
Figure 36. DSA: Phase vs. Attenuation
45 40 35 30 25 20 15 10 5 0 925
930
OIP3
GAIN
3
P1dB
4
NF
935 940 945 950 955 960 965
09431-037
CH3 CH3 2.00V
CH4 200mV
M10ns 10GS/s A CH3 IT 1.0ps/pt
1.24V
09431-034
FREQUENCY (MHz)
Figure 34. DSA: Gain Settling Time, 0 dB to 31.5 dB
Figure 37. Loop–943 MHz: Gain, P1dB, OIP3 at POUT = 5 dBm/Tone and Noise Figure vs. Frequency, Minimum Attenuation State
0 –10 –20
S-PARAMETERS (dB)
S22
–30 –40 –50 –60 –70 –80
S11
3
4
S12
09431-035
0.75
0.80
0.85
0.90
0.95
1.00
1.05
1.10
FREQUENCY (GHz)
Figure 35. DSA: Gain Settling Time, 31.5 dB to 0 dB
Figure 38. Loop–943 MHz: Input Return Loss (S11), Output Return Loss (S22), and Reverse Isolation (S12) vs. Frequency, Minimum Attenuation State
Rev. A | Page 16 of 32
09431-038
CH3 CH3 2.00V
CH4 200mV
M10ns 10GS/s A CH3 IT 1.0ps/pt
1.24V
–90 0.70
09431-036
30 0.9
20 3.6
–150
Data Sheet
46
925MHz
ADL5243
42
2.14GHz
44 42
OIP3 (dBm)
961MHz 943MHz
41 40 39 38 37 36 35
2.17GHz
2.11GHz
40 38 36 34 32
4 6 8 10 12 14 16 18 20 22
OIP3 (dBm)
1
3
5
7
9
11
13
15
17
19
21
POUT PER TONE (dBm)
POUT PER TONE (dBm)
Figure 39. Loop–943 MHz: OIP3 vs. POUT and Frequency, Minimum Attenuation State
45
NOISE FIGURE, GAIN, P1dB, OIP3 (dB, dBm)
Figure 42. Loop–2140 MHz: OIP3 vs. POUT and Frequency, Minimum Attenuation State
45
NOISE FIGURE, GAIN, P1dB, OIP3 (dB, dBm)
OIP3
40 35
40 35 30 25 20 15 10 5 0 2.57
OIP3
GAIN
30 25 20 15 10 5 0 2.11
GAIN P1dB
P1dB
NF
09431-040
NF
09431-043
09431-044
2.12
2.13
2.14
2.15
2.16
2.17
2.59
2.61
2.63
2.65
2.67
2.69
FREQUENCY (GHz)
FREQUENCY (GHz)
Figure 40. Loop–2140 MHz: Gain, P1dB, OIP3 at POUT = 5 dBm/Tone and Noise Figure vs. Frequency, Minimum Attenuation State
5 0 –5
S-PARAMETERS (dB)
Figure 43. Loop–2630 MHz: Gain, P1dB, OIP3 at POUT = 5 dBm/Tone and Noise Figure vs. Frequency, Minimum Attenuation State
5 0
S22
S-PARAMETERS (dB)
–5 –10 –15 –20 –25 –30 –35 –40 –45
S22 S11
–10 –15 –20 –25 –30 –35 –40 2.05 2.10 2.15 2.20
S11
S12
S12
2.25
2.30
09431-041
–45 2.00
–50 2.50
2.55
2.60
2.65
2.70
2.75
2.80
2.85
2.90
FREQUENCY (GHz)
FREQUENCY (GHz)
Figure 41. Loop–2140 MHz: Input Return Loss (S11), Output Return Loss (S22), and Reverse Isolation (S12) vs. Frequency, Minimum Attenuation State
Figure 44. Loop–2630 MHz: Input Return Loss (S11), Output Return Loss (S22), and Reverse Isolation (S12) vs. Frequency, Minimum Attenuation State
Rev. A | Page 17 of 32
09431-042
09431-039
34
ADL5243
42 41 40 39
OIP3 (dBm)
Data Sheet
45
2.69GHz 2.63GHz
PERCENTAGE (%)
09431-045
40 35 30 25 20 15 10 5 0
18.3 18.4 18.5 18.6 18.7 18.8 18.9 19.0 19.1 19.2 19.3 19.4 19.5 19.6 19.7 19.8 19.9 20.0
09431-048 09431-050 09431-049
38 37 36 35 34 33
0 2 4 6 8 10 12 POUT PER TONE (dBm) 14 16 18 2.57GHz
GAIN (dB)
Figure 45. Loop–2630 MHz: OIP3 vs. POUT and Frequency, Minimum Attenuation State
110 105 100 95 90 85 80
5
PERCENTAGE (%)
Figure 48. AMP1: Gain Distribution at 2140 MHz
25
20
SUPPLY CURRENT (mA)
5.25V 5.00V 4.75V
15
10
75 70 –40 –30 –20 –10
0
18.8
18.9
19.0
19.1
19.2
19.3
19.4
19.5
19.6
19.7
19.8
19.9
20.0
20.1
20.2
20.3
20.4
TEMPERATURE (°C)
P1dB (dBm)
Figure 46. AMP1: Supply Current vs. Voltage and Temperature
110 105 100 SUPPLY CURRENT (mA) 95 90 85 80 75 70 65 0 10 20 30 40 50 60 70 80 90
09431-047
Figure 49. AMP1: P1dB Distribution at 2140 MHz
35 30
5.25V
PERCENTAGE (%)
25 20 15 10 5 0
5.00V 5.00V
4.75V
60 –40 –30 –20 –10
33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50
TEMPERATURE (°C)
OIP3 (dBm)
Figure 47. AMP2: Supply Current vs. Voltage and Temperature
Figure 50. AMP1: OIP3 Distribution at 2140 MHz
Rev. A | Page 18 of 32
20.5
0
10
20
30
40
50
60
70
80
90
09431-046
Data Sheet
100 90 80
PERCENTAGE (%)
ADL5243
70 60 50
PERCENTAGE (%)
70 60 50 40 30 20 10
09431-051
40 30 20 10 0
NOISE FIGURE (dB)
33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 OIP3 (dBm)
Figure 51. AMP1: Noise Figure Distribution at 2140 MHz
40 35 30
PERCENTAGE (%)
Figure 54. AMP2: OIP3 Distribution at 2140 MHz
60
50
25 20 15 10 5 0
PERCENTAGE (%)
40
30
20
10
09431-052
GAIN (dB)
NOISE FIGURE (dB)
Figure 52. AMP2: Gain Distribution at 2140 MHz
50 45 40
PERCENTAGE (%)
Figure 55. AMP2: Noise Figure Distribution at 2140 MHz
35 30 25 20 15 10 5 0
25.2
25.3
25.4
25.5
25.6
25.7
25.8
25.9
26.0
26.1
26.2
26.3
26.4
26.5
26.6
26.7
26.8
26.9
P1dB (dBm)
Figure 53. AMP2: P1dB Distribution at 2140 MHz
09431-053
Rev. A | Page 19 of 32
09431-055
0
4.2 4.3 4.4
13.3
13.4
13.5
13.6
13.7
13.8
13.9
14.0
14.1
14.2
14.3
14.4
14.5
14.6
14.7
14.8
14.9
15.0
4.5
3.0
3.1
3.2
3.3
3.4
3.5
3.6
3.7
3.8
3.9
4.0
4.1
09431-054
0
2.3 2.4 2.5 2.6 2.7 2.8 2.9 3.0 3.1 3.2 3.3 3.4 3.5 3.6 3.7 3.8
ADL5243 APPLICATIONS INFORMATION
BASIC LAYOUT CONNECTIONS
Data Sheet
The basic connections for operating the ADL5243 are shown in Figure 56. The schematic is configured for 2140 MHz operation.
SERIAL PARALLEL INTERFACE
VDD
VDD
0.01µF
C17
32 31 30 29 28 27 26 25
SEL D0/CLK D1/DATA D2/LE D3 D4 D5 D6
1 2
VDD NC NC DSAIN NC NC NC
VDD NC NC
24 23 22 21 20 19 18 17
C1 100pF DSAIN AMP1OUT C4 0.1µF 470nH
3 4 5 6 7 8
C5 100pF
DSAOUT
ADL5243
DSAOUT NC AMP2IN NC NC
NC AMP1IN NC NC NC NC AMP2OUT/VCC2 VBIAS
AMP1OUT/VCC
AMP2IN C27 2.2pF C28 1.8pF C8 10pF
C15 68pF C14 1.2nF
9 10 11 12 13 14 15 16
VCC2
C13 1µF
C21 0.1µF AMP1IN
L2 9.5nH C3 10pF C25 10nF C20 10µF
C22 1pF
VCC C23 10pF AMP2OUT
Figure 56. Basic Connections
Rev. A | Page 20 of 32
09431-056
Data Sheet
Amplifier 1 Power Supply
AMP1 in the ADL5243 is a broadband gain block. The dc bias is supplied through Inductor L1 and is connected to the AMP1OUT pin. Three decoupling capacitors (C13, C14, and C25) are used to prevent RF signals from propagating on the dc lines. The dc supply ranges from 4.75 V to 5.25 V and should be connected to the VCC test pin.
ADL5243
Additionally, bias is provided through this pin. Figure 56 shows the output matching components and is configured for 2140 MHz.
DSA RF Input Interface
Pin 4 is the RF input for the DSA of the ADL5243. The input impedance of the DSA is close to 50 Ω over the entire frequency range; therefore, no external components are required. Only a dc blocking capacitor (C1) is required.
Amplifier 1 RF Input Interface
Pin 10 is the RF input for AMP1 of the ADL5243. The amplifier is internally matched to 50 Ω at the input; therefore, no external components are required. Only a dc blocking capacitor (C21) is required.
DSA RF Output Interface
Pin 21 is the RF output for the DSA of the ADL5243. The output impedance of the DSA is close to 50 Ω over the entire frequency range; therefore, no external components are required. Only a dc blocking capacitor (C5) is required.
Amplifier 1 RF Output Interface
Pin 6 is the RF output for AMP1 of the ADL5243. The amplifier is internally matched to 50 Ω at the output as well; therefore, no external components are required. Only a dc blocking capacitor (C4) is required. The bias is provided through this pin via a choke inductor, L1.
DSA SPI Interface
The DSA of the ADL5243 can operate in either serial or parallel mode. Pin 32 (SEL) controls the mode of operation. For serial mode operation, connect SEL to ground, and for parallel mode operation, connect SEL to VDD. In parallel mode, Pin 25 to Pin 30 (D6 to D1) are the data bits, with D6 being the LSB. Connect Pin 31 (D0) to ground during parallel mode of operation. In serial mode, Pin 29 is the latch enable (LE), Pin 30 is the data (DATA), and Pin 31 is the clock (CLK). Pin 26, Pin 27, and Pin 28 are not used in the serial mode and should be connected to ground. Pin 25 (D6) should be connected to VDD during the serial mode of operation. To prevent noise from coupling onto the digital signals, an RC filter can be used on each data line.
Amplifier 2 Power Supply
The collector bias for AMP2 is supplied through Inductor L2 and is connected to the AMP2OUT pin, whereas the base bias is provided through Pin 16. The base bias is connected to the same supply pin as the collector bias. Three decoupling capacitors (C3, C20, and C25) are used to prevent RF signals from propagating on the dc lines. The dc supply ranges from 4.75 V to 5.25 V and should be connected to the VCC2 test pin.
SPI TIMING
SPI Timing Sequence
Figure 58 shows the timing sequence for the SPI function using a 6-bit operation. The clock can be as fast as 20 MHz. In serial mode operation, Register B5 (MSB) is first, and Register B0 (LSB) is last. Table 4. Mode Selection Table
Pin 32 (SEL) Connect to Ground Connect to Supply Functionality Serial mode Parallel mode
Amplifier 2 RF Input Interface
Pin 19 is the RF input for AMP2 of the ADL5243. The input of the amplifier is easily matched to 50 Ω with a combination of series and shunt capacitors and a microstrip line serving as an inductor. Figure 56 shows the input matching components and is configured for 2140 MHz.
Amplifier 2 RF Output Interface
Pin 15 is the RF input for AMP2 of the ADL5243. The output of the amplifier is easily matched to 50 Ω with a combination of series and shunt capacitors and a microstrip line serving as an inductor. Table 5. SPI Timing Specifications
Parameter FCLK t1 t2 t3 t4 t5 t6 Limit 10 30 30 10 10 10 30 Unit MHz ns min ns min ns min ns min ns min ns min
Test Conditions/Comments Data clock frequency Clock high time Clock low time Data to clock setup time Clock to data hold time Clock low to LE setup time LE pulse width
Rev. A | Page 21 of 32
ADL5243
t1
CLK
Data Sheet
t5 t2 t3
DATA MSB B5
t4
B4 B3 B2 B1 LSB B0
t6
LE
09431-057
Figure 57. SPI Timing Diagram (Data Loaded MSB First)
D0/CLK
D1/DATA
MSB B5
B4
B3
B2
B1
LSB B0
D2/LE
D6
Figure 58. SPI Timing Sequence
Table 6. DSA Attenuation Truth Table—Serial Mode
Attenuation State 0 dB (Reference) 0.5 dB 1.0 dB 2.0 dB 4.0 dB 8.0 dB 16.0 dB 31.5 dB B5 (MSB) 1 1 1 1 1 1 0 0 B4 1 1 1 1 1 0 1 0 B3 1 1 1 1 0 1 1 0 B2 1 1 1 0 1 1 1 0 B1 1 1 0 1 1 1 1 0 B0 (LSB) 1 0 1 1 1 1 1 0
Table 7. DSA Attenuation Truth Table—Parallel Mode
Attenuation State 0 dB (Reference) 0.5 dB 1.0 dB 2.0 dB 4.0 dB 8.0 dB 16.0 dB 31.5 dB D1 (MSB) 1 1 1 1 1 1 0 0 D2 1 1 1 1 1 0 1 0 D3 1 1 1 1 0 1 1 0 D4 1 1 1 0 1 1 1 0 D5 1 1 0 1 1 1 1 0 D6 (LSB) 1 0 1 1 1 1 1 0
Rev. A | Page 22 of 32
09431-058
Data Sheet
ADL5243 AMPLIFIER 2 MATCHING
The AMP2 input and output of the ADL5243 can be easily matched to 50 Ω with two or three external components and the microstrip line used as an inductor. Table 8 lists the required matching components values. All capacitors are Murata GRM155 series (0402 size), and Inductor L1 is a Coilcraft® 0603CS series (0603 size). For all frequency bands, the Table 8. Component Values
Frequency 748 MHz 943 MHz 2140 MHz 2630 MHz C27 0Ω 0Ω 2.2 pF 2.7 pF C26 Open 3.9 pF Open 1.1 pF C28 5.1 pF Open 1.8 pF Open C8 12 pF 6 pF 10 pF 10 pF C22 1.3 pF 1.3 pF 1 pF 1.3 pF C23 100 pF 100 pF 10 pF 20 pF L2 56 nH 56 nH 9.5 nH 9.5 nH R10 18 Ω 18 Ω 0Ω 0Ω
ADL5243
placement of Capacitors C22, C26, and C28 is critical. Table 9 lists the recommended component spacing of C22, C26, and C28 for the various frequencies. The component spacing is referenced from the center of the component to the edge of the package. Figure 59 to Figure 62 show the graphical representation of the matching network.
R12 3.9 nH 3.3 nH 0Ω 0Ω
Table 9. Component Spacing
Frequency 748 MHz 943 MHz 2140 MHz 2630 MHz C26: λ1 (mils) N/A 236 N/A 126 C28: λ2 (mils) 315 N/A 366 N/A C22: λ3 (mils) 201 394 244 240
Rev. A | Page 23 of 32
ADL5243
NC 20 λ2
Data Sheet
ADL5243
AMP2IN 19
λ1 C27 0Ω
R10 18Ω
AMP2IN C8 12pF
AMP2OUT/VCC2
C26 OPEN
C28 5.1pF
NC 18
VBIAS
16
NC
13
NC
NC 17
14
15
λ3
L2 56nH R12 3.9nH
C22 1.3pF C23 100pF
AMP2OUT
09431-061
Figure 59. AMP2: Matching Circuit at 748 MHz
NC 20 λ2
ADL5243
AMP2IN 19
AMP2OUT//VCC2
λ1 C27 0Ω NC 18
VBIAS
R10 18Ω
AMP2IN C8 6pF
C26 3.9pF
C28 OPEN
NC
13
NC
NC 17
14
15
16
λ3
L2 56nH R12 3.3nH
C22 1.3pF C23 100pF
AMP2OUT
09431-062
Figure 60. AMP2: Matching Circuit at 943 MHz
Rev. A | Page 24 of 32
Data Sheet
NC 20 λ2
ADL5243
ADL5243
AMP2IN 19
λ1 C27 2.2pF
R10 0Ω
AMP2IN C8 10pF
AMP2OUT/VCC2
C26 OPEN
C28 1.8pF
NC 18
VBIAS
16
NC
13
NC
NC 17
14
15
λ3
L2 9.5nH R12 0Ω
C22 1pF C23 10pF
AMP2OUT
09431-064
Figure 61. AMP2: Matching Circuit at 2140 MHz
NC 20 λ2
ADL5243
AMP2IN 19
AMP2OUT//VCC2
λ1 C27 2.7pF NC 18
VBIAS
R10 0Ω
AMP2IN C8 10pF
C26 1.1pF
C28 OPEN
NC
13
NC
NC 17
14
15
16
λ3
L2 9.5nH R12 0Ω
C22 1.3pF C23 20pF
AMP2OUT
09431-065
Figure 62. AMP2: Matching Circuit at 2630 MHz
Rev. A | Page 25 of 32
ADL5243
ADL5243 LOOP PERFORMANCE
The typical configuration of the ADL5243 is to connect in AMP1-DSA-AMP2 mode, as shown in Figure 63. Because AMP1and DSA are broadband in nature and internally matched, only an ac-coupling capacitor is required between them. The AMP2 is externally matched for each frequency band of operation, and these matching elements should be placed between the DSA and AMP2 and at the output of AMP2. Figure 37 to Figure 45 show the performance of the ADL5243 when connected in a loop for the three primary frequency bands of operation, namely 943 MHz, 2140 MHz, and 2630 MHz.
VCC VDD/SPI VCC2
Data Sheet
For the best thermal performance, it is recommended to add as many thermal vias as possible under the exposed pad of the LFCSP. The above thermal resistance numbers assume a minimum of 25 thermal vias arranged in a 5 × 5 array with a via diameter of 13 mils, via pad of 25 mils, and pitch of 25 mils. The vias are plated with copper, and the drill hole is filled with a conductive copper paste. For optimal performance, it is recommended to fill the thermal vias with a conductive paste of equivalent thermal conductivity, as mentioned above, or use an external heat sink to dissipate the heat quickly without affecting the die junction temperature. It is also recommended to extend the ground pattern as shown in Figure 64 to improve thermal efficiency.
SOLDERING INFORMATION AND RECOMMENDED PCB LAND PATTERN
Figure 64 shows the recommended land pattern for the ADL5243. To minimize thermal impedance, the exposed paddle on the 5 mm × 5 mm LFCSP package is soldered down to a ground plane. To improve thermal dissipation, 25 thermal vias are arranged in a 5 × 5 array under the exposed paddle. If multiple ground layers exist, they should be tied together using vias. For more information on land pattern design and layout, see the AN-772 Application Note, A Design and Manufacturing Guide for the Lead Frame Chip Scale Package (LFCSP).
1 DSAIN 25 MIL VIA PAD WITH 13 MIL VIA 24 DSAOUT
RFIN
AMP1
DSA
IMN
AMP2
OMN
RFOUT
ADL5243
Figure 63. ADL5243 Loop Block Diagram
THERMAL CONSIDERATIONS
The ADL5243 is packaged in a thermally efficient, 5 mm × 5 mm, 32-lead LFCSP. The thermal resistance from junction to air (θJA) is 34.8°C/W. The thermal resistance for the product was extracted assuming a standard 4-layer JEDEC board with 25 copper platter thermal vias. The thermal vias are filled with conductive copper paste, AE3030, with a thermal conductivity of 7.8 W/mk and thermal expansion as follows: α1 of 4 × 10−5/°C and α2 of 8.6 × 10−5/°C. The thermal resistance from junction to case (θJC) is 6.2°C/W, where case is the exposed pad of the lead frame package.
09431-067
8
17
Figure 64. Recommended Land Pattern
Rev. A | Page 26 of 32
09431-068
Data Sheet EVALUATION BOARD
The schematic of the ADL5243 evaluation board is shown in Figure 65. All RF traces on the evaluation board have a characteristic impedance of 50 Ω and are fabricated from Rogers3003 material. The traces are CPWG with a width of 25 mils, spacing of 20 mils, and dielectric thickness of 10 mils. The input and output to the DSA and amplifier should be accoupled with capacitors of appropriate value to ensure broadband performance. The bias to AMP1 is provided through a choke connected to the AMP1OUT pin and, similarly, bias to AMP2 is provided through a choke connected to the AMP2OUT pin. Bypassing capacitors are recommended on all supply lines to minimize RF coupling. The DSA and the amplifiers can be Table 10. Evaluation Board Configurations Options
Component C1, C5 C4, C21 C13, C14, C15 Function AC coupling caps for DSA. AC coupling capacitors for AMP1. Power supply bypassing capacitors for AMP1. Capacitor C15 should be closest to the device. The bias for AMP1 comes through L1 when connected to a 5 V supply. L1 should be high impedance for the frequency of operation, while providing low resistance for the dc current. AMP2 input ac-coupling capacitor. AMP2 output ac-coupling capacitor. AMP2 shunt output tuning capacitor. ANP2 shunt input tuning capacitor. AMP2 series input tuning capacitor. AMP2 shunt input tuning capacitor. Power supply bypassing capacitors for AMP2. Capacitor C3 should be closest to the device. The bias for AMP2 comes through L2 when connected to a 5 V supply. L1 should be high impedance for the frequency of operation, while providing low resistance for the dc current. Power supply bypassing capacitor. Placeholder for the series component for the other frequency band. Digital signal filter resistors. Digital signal filter capacitors. Replace with capacitors and resistors to connect the device in a loop. Resistors to connect the supply for the amplifier and the DSA to the same VDD plane. Switch to change between serial and parallel mode operation; connect to a supply for parallel mode and to ground for serial mode operation. Digital control. Default Value C1, C5 = 100 pF C4, C21 = 0.1 μF C13 = 1 μF C14 = 1.2 nF C15 = 68 pF L1 = 470 nH
ADL5243
individually biased or connected to the VDD plane through Resistors R1, R2, and R11. When configuring the ADL5243 evaluation board in the AMP1-DSA-AMP2 loop, remove Capacitors C1, C4, C5, and C8 and remove Resistor R10. Place 100 pF in place of C2, 10 pF in place of C6, and 0 Ω in place of C7 and C24. If needed, placing a shunt capacitor (1.3 pF) at the output of the DSA improves the output return loss of this loop. On the digital signal traces, provisions for an RC filter are made to clean any potential coupled noise. In normal operation, Resistors R3 to R9 are 0 Ω and Capacitors C9 to C15 are open.
L1
C8 C23 C22 C26 C27 C28 C3, C25, C20
L2
C8 = 10 pF C23 = 10 pF C22 = 1.0 pF at 244 mils from edge of package DNP C27 = 2.2 pF C28 = 1.8 pF at 366 mils from edge of package C3 = 10 pF C25 = 10 nF C20 = 10 μF L2 = 9.5 nH
C17 R10, R12 R3, R4, R5, R6, R7, R8, R9 C9, C10, C11, C12, C16, C18, C19 C2, C6, C7, C24 R1, R2, R11 S1 P1
C17 = 0.1 μF R10, R12 = 0 Ω R3, R4, R5, R6, R7, R8, R9 = 0 Ω C9, C10, C11, C12, C16, C18, C19 = open C2, C6, C7, C24 = open R1, R2 = open 3-pin rocker 9-pin connector
Rev. A | Page 27 of 32
ADL5243
DATA CLK R3 0Ω R4 0Ω R5 0Ω R6 0Ω 3 2 1 S1 C9 DNI VDD VDD R2 DNI C17 0.1µF DSAIN C1 100pF AGND 1 VDD 2 NC 3 NC 4 DSAIN 5 NC 6 AMP1OUT/VCC 7 NC AMP1IN 8 NC NC AGND C10 DNI AGND C11 DNI AGND C12 DNI AGND C16 DNI AGND C18 DNI AGND C19 DNI AGND R7 0Ω R8 0Ω R9 0Ω
Data Sheet
LE P1 1 2 3 4 5 6 7 8 9 AGND
AGND
SEL1 32 D0/CLK 31 D1/DATA 30
D2/LE 29 D3 28
D4 27 D5 26 D6 25
DSAOUT VDD 24 NC 23 C5 100pF
C2 DNI
ADL5243
AMP2OUT/VCC2
NC 22 DSAOUT 21 NC 20 AMP2IN 19 NC 18 NC 17 VBIAS
C6 DNI
C24 DNI C4 AMP1OUT 0.1µF
C27 2.2pF
C7 DNI R10 0Ω C26 DNI C28 1.8pF C8 10pF AMP2IN
NC
NC
NC
NC
AGND
10
11
12
13
14
15
VCC
L1 470nH
16
9
AGND
AGND VDD R1 DNI C13 1µF C14 1.2nF C15 68pF C21 0.1µF R12 0Ω C3 10pF C23 10pF C25 10nF AGND AGND L2 9.5nH
AGND
VCC2
R11 DNI C20 10µF
VDD
AGND AMP1IN C22 1pF
Figure 65. ADL5243 Evaluation Board
Rev. A | Page 28 of 32
09431-069
AMP2OUT
AGND
Data Sheet
ADL5243
09431-070
Figure 66. Evaluation Board Layout—Top
Figure 67. Evaluation Board Layout—Bottom
Rev. A | Page 29 of 32
09431-071
ADL5243 OUTLINE DIMENSIONS
5.00 BSC SQ 0.60 MAX
25 24 PIN 1 INDICATOR 32 1
Data Sheet
0.60 MAX PIN 1 INDICATOR 3.45 3.30 SQ 3.15
8 16 BOTTOM VIEW 9
4.75 BSC SQ
0.50 BSC
EXPOSED PAD
17 TOP VIEW
1.00 0.85 0.80 SEATING PLANE
12° MAX
0.80 MAX 0.65 TYP
0.50 0.40 0.30 0.05 MAX 0.02 NOM COPLANARITY 0.08 0.20 REF
0.25 MIN
3.50 REF FOR PROPER CONNECTION OF THE EXPOSED PAD, REFER TO THE PIN CONFIGURATION AND FUNCTION DESCRIPTIONS SECTION OF THIS DATA SHEET.
COMPLIANT TO JEDEC STANDARDS MO-220-VHHD-2
Figure 68. 32-Lead Lead Frame Chip Scale Package [LFCSP_VQ] 5 mm × 5 mm Body, Very Thin Quad (CP-32-3) Dimensions shown in millimeters
ORDERING GUIDE
Model 1 ADL5243ACPZ-R7 ADL5243-EVALZ
1
Temperature Range −40°C to +85°C
Package Description 32-Lead Lead Frame Chip Scale Package LFCSP_VQ Evaluation Board
Package Option CP-32-3
Z = RoHS Compliant Part.
Rev. A | Page 30 of 32
05-25-2011-A
0.30 0.25 0.18
Data Sheet NOTES
ADL5243
Rev. A | Page 31 of 32
ADL5243 NOTES
Data Sheet
©2011 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. D09431-0-8/11(A)
Rev. A | Page 32 of 32
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