ADL5306ACPZ-REEL7

60 dB Range (100 nA to 100 µA) Low Cost Logarithmic Converter ADL5306 FEATURES Optimized for fiber optic photodiode interfacing Measures current over 3 decades Law conformance 0.1 dB from 100 nA to 100 μA Single- or dual-supply operation (3 V to ±5.5 V total) Full log-ratio capabilities Temperature stable Nominal slope of 10 mV/dB (200 mV/decade) Nominal intercept of 1 nA (set by external resistor) Optional adjustment of slope and intercept Rapid response time for a given current level Miniature 16-lead chip scale package (LFCSP 3 mm × 3 mm) Low power: ~5 mA quiescent current APPLICATIONS Low cost optical power measurement Wide range baseband logarithmic compression Measurement of current and voltage ratios Optical absorbance measurement GENERAL DESCRIPTION The ADL5306∗ is a low cost microminiature logarithmic converter optimized for determining optical power in fiber optic systems. The ADL5306 is derived from the AD8304 and AD8305 translinear logarithmic converters. This family of devices provides wide measurement dynamic range in a versatile and easy-to-use form. A single-supply voltage between 3 V and 5.5 V is adequate; dual supplies may optionally be used. Low quiescent current (5 mA typical) permits use in battery-operated applications. IPD, the 100 nA to 100 µA input current applied to the INPT pin, is the collector current of an optimally scaled NPN transistor that converts this current to a voltage (VBE) with a precise logarithmic relationship. A second converter is used to handle the reference current, IREF, applied to IREF. These input nodes are biased slightly above ground (0.5 V). This is generally acceptable for photodiode applications where the anode does not need to be grounded. Similarly, this bias voltage is easily accounted for in generating IREF. The logarithmic front end’s output is available at VLOG. The basic logarithmic slope at this output is 200 mV/decade (10 mV/dB) nominal; a 60 dB range corresponds to a 600 mV output change. When this voltage (or the buffer output) is applied to an ADC that permits an external reference voltage to be employed, the ADL5306’s 2.5 V voltage reference output at VREF can be used to improve scaling accuracy. FUNCTIONAL BLOCK DIAGRAM VPOS +5V NC 0.2 log10 VREF 2.5V RREF 200kΩ 20kΩ 80kΩ IREF SCAL BFIN VBE2 Q2 I TEMPERATURE LOG COMPENSATION 451Ω 1nF Q1 VLOG VBE1 IPD INPT 1nF VOUT BIAS GENERATOR 14.2kΩ 1kΩ 1kΩ PD COMM 0.5V VBIAS I (1nA ) 6.69kΩ COMM VSUM 0.5V 1nF VNEG COMM 03727-0-001 Figure 1. Functional Block Diagram The logarithmic intercept (reference current) is nominally positioned at 1 nA by using the externally generated, 100 µA IREF current provided by a 200 kΩ resistor connected between VREF, at 2.5 V, and IREF, at 0.5 V. The intercept can be adjusted over a narrow range by varying this resistor. The part can also operate in a log-ratio mode, with limited accuracy, where the numerator and denominator currents are applied to INPT and IREF, respectively. A buffer amplifier is provided to drive substantial loads, raise the basic 10 mV/dB slope, serve as a precision comparator (threshold detector), or implement low-pass filters. Its rail-to-rail output stage can swing to within 100 mV of the positive and negative supply rails, and its peak current-sourcing capacity is 25 mA. A fundamental aspect of translinear logarithmic converters is that small-signal bandwidth falls as current level diminishes, and low frequency noise-spectral density increases. At the 100 nA level, the ADL5306’s bandwidth is about 100 kHz; it increases in proportion to IPD up to a maximum of about 10 MHz. The increase in noise level at low currents can be addressed by using a buffer amplifier to realize low-pass filters of up to three poles. The ADL5306 is available in a 16-lead LFCSP package and is specified for operation from–40°C to +85°C. ∗ Protected by US Patent 5,519,308. Rev. 0 Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective companies. One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. www.analog.com Tel: 781.329.4700 Fax: 781.326.8703 © 2003 Analog Devices, Inc. All rights reserved. ADL5306 TABLE OF CONTENTS Specifications..................................................................................... 3 Response Time and Noise Considerations ............................. 10 Absolute Maximum Ratings............................................................ 4 Applications..................................................................................... 11 Pin Configuration and Pin Function Descriptions...................... 5 Using a Negative Supply ............................................................ 11 Typical Performance Characteristics ............................................. 6 Characterization Methods ........................................................ 12 General Structure.............................................................................. 9 Evaluation Board ............................................................................ 14 Theory............................................................................................ 9 Outline Dimensions ....................................................................... 16 Managing Intercept and Slope .................................................. 10 Ordering Guide .......................................................................... 16 REVISION HISTORY Rev. 0: Initial Version Rev. 0 | Page 2 of 16 ADL5306 SPECIFICATIONS Table 1. VP = 5 V, VN = 0, TA = 25°C, RREF = 200 kΩ, unless otherwise noted Parameter INPUT INTERFACE Specified Current Range, IPD Input Current Min/Max Limits Reference Current, IREF, Range Summing Node Voltage Temperature Drift Input Offset Voltage LOGARITHMIC OUTPUT Logarithmic Slope Conditions INPT (Pin 4), IREF (Pin 3) Flows toward INPT pin Flows toward INPT pin Flows toward IREF pin Internally preset; may be altered by user –40°C < TA < +85°C VIN – VSUM , VIREF – VSUM VLOG (Pin 9) –40°C < TA < +85°C Logarithmic Intercept2 Law Conformance Error Wideband Noise3 Small-Signal Bandwidth3 Maximum Output Voltage Minimum Output Voltage Output Resistance REFERENCE OUTPUT Voltage wrt Ground Maximum Output Current Incremental Output Resistance OUTPUT BUFFER Input Offset Voltage Input Bias Current Incremental Input Resistance Output Range Incremental Output Resistance Peak Source/Sink Current Small-Signal Bandwidth Slew Rate POWER SUPPLY Positive Supply Voltage Quiescent Current Negative Supply Voltage (Optional) 1 2 3 –40°C < TA < +85°C 100 nA < IPD < 100 µA IPD > 1 µA IPD > 1 µA Min1 Typ 100n 100n 0.46 0.5 0.015 –20 190 185 0.3 0.1 Limited by VN = 0 V 4.375 Max1 Unit 100µ 1 100µ 0.54 A mA A V mV/°C mV +20 200 1 0.1 0.7 0.7 1.7 0.01 5 210 215 1.7 2.5 0.4 5.625 mV/dec mV/dec nA nA dB µV/√Hz MHz V V kΩ VREF (Pin 2) –40°C < TA < +85°C Sourcing (grounded load) Load current < 10 mA BFIN (Pin 10); SCAL (Pin 11); VOUT (Pin 12) 2.435 2.4 2.5 2.565 2.6 V V mA Ω +20 0.4 35 VP – 0.1 mV µA MΩ V 0.5 50 15 15 Ω mA MHz V/µs 20 2 –20 Flowing out of Pin 10 or Pin 11 RL = 1 kΩ to ground Load current < 10 mA GAIN = 1 0.2 V to 4.8 V output swing VPOS (Pin 8); VNEG (Pin 6) (VP – VN ) ≤ 11 V 3 (VP – VN ) ≤ 11 V –5.5 5 5.4 0 Minimum and maximum specified limits on parameters that are guaranteed but not tested are six sigma values. Other values of logarithmic intercept can be achieved by adjusting RREF. Output noise and incremental bandwidth are functions of input current measured using the output buffer connected for GAIN = 1. Rev. 0 | Page 3 of 16 5.5 6.6 V mA V ADL5306 ABSOLUTE MAXIMUM RATINGS Table 2. ADL5306 Absolute Maximum Ratings Parameter Supply Voltage VP – VN Input Current Internal Power Dissipation θJA Maximum Junction Temperature Operating Temperature Range Storage Temperature Range Lead Temperature Range (Soldering 60 sec) Rating 12 V 20 mA 500 mW 135°C/W 125°C –40°C to +85°C –65°C to +150°C 300°C Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. Rev. 0 | Page 4 of 16 ADL5306 PIN CONFIGURATION AND PIN FUNCTION DESCRIPTIONS COMM COMM COMM COMM 16 15 14 13 12 VOUT NC 1 11 SCAL VREF 2 ADL5306 IREF 3 10 BFIN INPT 4 9 5 6 7 VLOG 8 VSUM VNEG VNEG VPOS 03727-0-002 Figure 2. 16-Lead Leadframe Chip Scale Package (LFCSP) Table 3. Pin Function Descriptions Pin No. 1 2 3 4 Mnemonic NC VREF IREF INPT 5 6, 7 8 9 10 11 12 13–16 VSUM VNEG VPOS VLOG BFIN SCAL VOUT COMM Function N/A Reference Output Voltage of 2.5 V. Accepts (Sinks) Reference Current IREF. Accepts (Sinks) Photodiode Current IPD. Usually connected to photodiode anode such that photocurrent flows into INPT. Guard Pin. Used to shield the INPT current line and for optional adjustment of the INPT and IREF node potential. Optional Negative Supply, VN. This pin is usually grounded; for details of usage, see the Applications section. Positive Supply, ( VP – VN ) ≤ 11 V. Output of the Logarithmic Front End. Buffer Amplifier Noninverting Input. Buffer Amplifier Inverting Input. Buffer Output. Analog Ground. Rev. 0 | Page 5 of 16 ADL5306 TYPICAL PERFORMANCE CHARACTERISTICS (VP = 5 V, VN = 0 V, RREF = 200 kΩ, TA = 25°C, unless otherwise noted.) 1.2 1.5 TA = –40°C, 0°C, +25°C, +70°C, +85°C VN = 0V TA = –40°C, 0°C, +25°C, +70°C, +85°C VN = 0V 1.0 ERROR (dB (10mV/dB)) 1.0 VLOG (V) 0.8 0.6 0.4 0.2 0 10n 100n 1µ 10µ 100µ 100n 1µ 10µ 100µ 1m IPD (A) 03727-0-006 Figure 6. Law Conformance Error vs. IPD (IREF = 10 µA) for Multiple Temperatures, Normalized to 25°C 1.5 TA = –40°C, 0°C, +25°C, +70°C, +85°C VN = 0V 1.0 ERROR (dB (10mV/dB)) 1.0 VLOG (V) +25°C 0°C –40°C TA = –40°C, 0°C, +25°C, +70°C, +85°C VN = 0V 1.2 0.8 0.6 0.4 +85°C 0.5 +70°C 0 +25°C –0.5 –40°C 0°C –1.0 0.2 100n 1µ 10µ 100µ IREF (A) –1.5 10n 1m 100n 1µ 10µ 100µ IREF (A) 03727-0-004 Figure 4. VLOG vs. IREF for Multiple Temperatures 1m 03727-0-007 Figure 7. Law Conformance Error vs. IREF (IPD = 10 µA) for Multiple Temperatures, Normalized to 25°C 0.3 1.6 1.4 0.2 ERROR (dB (10mV/dB)) 1.2 VLOG (V) –0.5 03727-0-003 1.4 100nA 1µA 0.8 10µA 100µA 0.6 0.4 100µA 0.1 100nA 10µA 0 1µA –0.1 –0.2 0.2 0 10n 0 –1.5 10n 1m Figure 3. VLOG vs. IPD for Multiple Temperatures 1.0 +70°C –1.0 IPD (A) 0 10n +85°C 0.5 100n 1µ 10µ 100µ IPD (A) –0.3 10n 1m 03727-0-005 Figure 5. VLOG vs. IPD for Multiple Values of IREF (Decade Steps from 10 nA to 1 mA) 100n 1µ 10µ IPD (A) 100µ 1m 03727-0-008 Figure 8. Law Conformance Error vs. IPD for Multiple Values of IREF (Decade Steps from 10 nA to 1 mA) Rev. 0 | Page 6 of 16 ADL5306 0.3 1.6 1.4 0.2 1.2 100nA ERROR (dB) 1.0 VLOG (V) 0.1 100µA 10µA 0.8 0.6 1µA 100nA 100µA 0 1µA 10µA –0.1 0.4 –0.2 0.2 0 10n 100n 1µ 10µ 100µ IREF (A) –0.3 10n 1m 1.2 0.2 1.0 0 +3V, 0V +5V, –5V –0.1 100µ 1m 03727-0-012 10µA TO 100µA: tRISE < 1µs, tFALL < 1µs 0.8 +5V, 0V +3V, –0.5V VOUT (V) ERROR (dB (10mV/dB)) 0.3 0.1 10µ Figure 12. Law Conformance Error vs. IREF for Multiple Values of IPD (Decade Steps from 10 nA to 1 mA) 1µA TO 10µA: tRISE < 1µs, tFALL < 5µs 0.6 100nA TO 1µA: tRISE < 5µs, tFALL < 20µs 0.4 –0.2 0.2 100n 1µ 10µ 100µ IPD (A) 0 –20 1m 0 20 40 60 80 100 120 140 160 TIME (µs) 03727-0-010 180 03727-0-013 Figure 13. Pulse Response: IPD to VOUT (G = 1) Figure 10. Law Conformance Error vs. IPD for Various Supply Conditions 1.4 4 TA = –40°C, +85°C 3 1.2 MEAN + 3 @ –40°C 2 100nA TO 1µA: tRISE = 30µs, tFALL = 5µs 1.0 1µA TO 10µA: tRISE = 5µs, tFALL < 1µs 1 VOUT (V) ERROR (dB (10mV/dB)) 1µ IREF (A) Figure 9. VLOG vs. IREF for Multiple Values of IPD (Decade Steps from 10 nA to 1 mA) –0.3 10n 100n 03727-0-009 MEAN ±3 @ +85°C 0 0.8 10µA TO 100µA: tRISE = 1µs, tFALL < 1µs 0.6 –1 0.4 –2 MEAN – 3 @ –40°C –3 –4 10n 100n 1µ 10µ IPD (A) 0.2 100µ 0 –20 1m 03727-0-011 0 20 40 60 80 100 120 140 160 TIME (µs) Figure 14. Pulse Response: IREF to VOUT (G = 1) Figure 11. VINPT – VSUM vs. IPD Rev. 0 | Page 7 of 16 180 03727-0-014 ADL5306 5 10 100nA 0 0 NORMALIZED RESPONSE (dB) NORMALIZED RESPONSE (dB) 5 100µA –5 –10 –15 10µA –20 –25 1µA –30 –5 Av = 1 Av = 5 –10 Av = 2 –15 Av = 2.5 –20 –35 –40 100 1k 10k 100k 1M 10M –25 10k 100M FREQUENCY (Hz) 1M 10M 100M FREQUENCY (Hz) Figure 15. Small-Signal AC Response (5% Sine Modulation), from IPD to VOUT (G = 1) for IPD in Decade Steps from 10 nA to 1 mA 03727-0-018 Figure 18. Small-Signal AC Response of the Buffer for Various Closed-Loop Gains (RL = 1 kΩ, CL < 2 pF) 2.0 10 5 100nA 1.5 0 1.0 100µA –5 MEAN + 3σ VOS DRIFT (mV) NORMALIZED RESPONSE (dB) 100k 03727-0-015 –10 –15 10µA –20 0.5 0 –0.5 MEAN – 3σ –25 –1.0 1µA –30 –1.5 –35 –40 100 1k 10k 100k 1M 10M FREQUENCY (Hz) –2.0 –40 –30 –20 –10 100M 0 10 20 30 40 50 60 70 80 90 TEMPERATURE (°C) 03727-0-016 Figure 16. Small-Signal AC Response (5% Sine Modulation), from IREF to VOUT (G = 1) for IREF in Decade Steps from 10 nA to 1 mA 03727-0-019 Figure 19. Buffer Input Offset Drift vs. Temperature (3σ to Either Side of Mean) 6 100 5 10 100nA mVrms µVrms/ Hz 4 1µA 1 10µA 0.1 3 2 100µA 1 0.01 100 1k 10k 100k FREQUENCY (Hz) 1M 0 10n 10M 03727-0-017 Figure 17. Spot Noise Spectral Density at VOUT (G = 1) vs. Frequency for IPD in Decade Steps from 10 nA to 1 mA 100n 1µ 10µ IPD (A) 100µ 1m 03727-0-020 Figure 20. Total Wideband Noise Voltage at VOUT vs. IPD (G = 1) Rev. 0 | Page 8 of 16 ADL5306 GENERAL STRUCTURE The ADL5306 addresses a wide variety of interfacing conditions to meet the needs of fiber optic supervisory systems, and is useful in many nonoptical applications. This section explains the structure of this unique style of translinear log amp. The simplified schematic in Figure 21 shows the key elements. THEORY The base-emitter voltage of a BJT (bipolar junction transistor) can be expressed by the following equation, which immediately shows its basic logarithmic nature: VBE = kT/q ln(IC / IS) BIAS GENERATOR PHOTODIODE 2.5V INPUT CURRENT 80kΩ IPD 0.5V IREF IREF VBE2 44µA/dec 0.5V 2.5V 14.2kΩ 451Ω VLOG 0.5V Q1 where: IC is the collector current IS is a scaling current, typically only 10–17 A kT/q is the thermal voltage, proportional to absolute temperature (PTAT), and is 25.85 mV at 300 K. TEMPERATURE COMPENSATION (SUBTRACT AND DIVIDE BY T°K) 20kΩ COMM VSUM INPT VBE1 VREF VBE1 Q2 VBE2 VNEG (NORMALLY GROUNDED) (1) 6.69kΩ COMM 03727-0-021 Figure 21. Simplified Schematic The photodiode current IPD is received at Pin INPT. The voltage at this node is essentially equal to the voltage on the two adjacent guard pins, VSUM and IREF, due to the low offset voltage of the JFET op amp. Transistor Q1 converts IPD to a corresponding logarithmic voltage, as shown in Equation 1. A finite positive value of VSUM is needed to bias the collector of Q1 for the usual case of a single-supply voltage. This is internally set to 0.5 V, one fifth of the 2.5 V reference voltage appearing on Pin VREF. The resistance at the VSUM pin is nominally 16 kΩ; this voltage is not intended as a general bias source. The ADL5306 also supports the use of an optional negative supply voltage, VN , at Pin VNEG. When VN is –0.5 V or more negative, VSUM may be connected to ground; thus, INPT and IREF assume this potential. This allows operation as a voltageinput logarithmic converter by the inclusion of a series resistor at either or both inputs. Note that the resistor setting, IREF, will need to be adjusted to maintain the intercept value. It should also be noted that the collector-emitter voltages of Q1 and Q2 are now the full VN, and effects due to self-heating will cause errors at large input currents. The input-dependent VBE1 of Q1 is compared with the reference VBE2 of a second transistor, Q2, operating at IREF. This is generated externally to a recommended value of 10 µA. However, other values over a several-decade range can be used with a slight degradation in law conformance (see Figure 8). IS is never precisely defined and exhibits an even stronger temperature dependence, varying by a factor of roughly a billion between –35°C and +85°C. Thus, to make use of the BJT as an accurate logarithmic element, both of these temperaturedependencies must be eliminated. The difference between the base-emitter voltages of a matched pair of BJTs, one operating at the photodiode current IPD and the other operating at a reference current IREF, can be written as VBE1 – VBE2 = kT/q ln(IPD / IS) – kT/q ln(IREF / IS) = ln(10) kT/q log10(IPD / IREF) (2) = 59.5 mV log10(IPD / IREF) (T = 300 K) The uncertain, temperature-dependent saturation current, IS, that appears in Equation 1 has therefore been eliminated. To eliminate the temperature variation of kT/q, this difference voltage is processed by what is essentially an analog divider. Effectively, it puts a variable under Equation 2. The output of this process, which also involves a conversion from voltage mode to current mode, is an intermediate, temperaturecorrected current: ILOG = IY log10(IPD / IREF) (3) where IY is an accurate, temperature-stable scaling current that determines the slope of the function (change in current per decade). For the ADL5306, IY is 44 µA, resulting in a temperature-independent slope of 44 µA/decade for all values of IPD and IREF . This current is subsequently converted back to a voltage-mode output, VLOG, scaled 200 mV/decade. Rev. 0 | Page 9 of 16 ADL5306 It is apparent that this output should be zero for IPD = IREF, and would need to swing negative for smaller values of input current. To avoid this, IREF would need to be as small as the smallest value of IPD. In the ADL5306, an internal offset voltage is added to VLOG to shift it upward by 0.8 V. This moves the intercept to the left by four decades, from 10 µA to 1 nA: ILOG = IY log10(IPD / IINTC) As previously noted, the internally generated 2.5 V bias combines with the on-chip resistors to introduce an accurate offset voltage of 0.8 V at the VLOG pin, equivalent to four decades. This results in a logarithmic transfer function that can be written as (4) where IINTC is the operational / value of the intercept current. Since values of IPD < IINTC result in a negative VLOG, a negative supply of sufficient value is required to accommodate this situation (discussed later). The voltage VLOG is generated by applying ILOG to an internal resistance of 4.55 kΩ, formed by the parallel combination of a 6.69 kΩ resistor to ground and the 14.2 kΩ resistor to the internal 2.5 V reference. At the VLOG pin, the output current ILOG generates a voltage of VLOG = ILOG × 4.55 kΩ = 44 µA × 4.55 kΩ × log10 (IPD / IREF) MANAGING INTERCEPT AND SLOPE (5) = VY log10 (IPD / IREF) where VY = 200 mV/decade or 10 mV/dB. Note that any resistive loading on VLOG will lower this slope and will result in an overall scaling uncertainty due to the variability of the onchip resistors. Consequently, this practice is not recommended. VLOG may also swing below ground when dual supplies (VP and VN) are used. When VN = -0.5 V or more negative, the input pins INPT and IREF may be positioned at ground level simply by grounding VSUM. VLOG = VY log10 (104 × IPD / IREF)= VY log10 (IPD / IINTC) (6) where IINTC = IREF /104 Thus, the effective intercept current, IINTC, is only one tenthousandth of IREF, corresponding to 10 nA when using the recommended value of IREF = 100 µA. The slope can be reduced by attaching a resistor to the VLOG pin. This is strongly discouraged because the on-chip resistors will not ratio correctly to the added resistance. Also, it is rare that one would wish to lower the basic slope of 10 mV/dB; if this is necessary, it should be done at the low impedance output of the buffer, which is provided to avoid such miscalibration and allow higher slopes to be used. The ADL5306 buffer is essentially an uncommitted op amp with rail-to-rail output swing, good load driving capabilities, and a unity-gain bandwidth of >20 MHz. In addition to allowing the introduction of gain using standard feedback networks, thereby increasing the slope voltage, VY, the buffer can be used to implement multipole low-pass filters, threshold detectors, and a variety of other functions. For more details, see the AD8304 Data Sheet. RESPONSE TIME AND NOISE CONSIDERATIONS The response time and output noise of the ADL5306 are fundamentally a function of the signal current IPD. For small currents, the bandwidth is proportional to IPD. The output’s low frequency voltage-noise spectral density is a function of IPD, and increases for small values of IREF. For details of noise and bandwidth performance of translinear log amps, see the AD8304 Data Sheet. Rev. 0 | Page 10 of 16 ADL5306 APPLICATIONS The ADL5306 is easy to use in optical supervisory systems and in similar situations where a wide-ranging current is to be converted to its logarithmic equivalent (i.e., represented in decibel terms). Basic connections for measuring a single current input are shown in Figure 22, which includes various nonessential components, as will be explained. VPOS +5V NC 0.5 log10 VREF 2.5V 20kΩ RREF 200kΩ 0.5V 80kΩ Q2 12kΩ Q1 VBE1 I VLOG TEMPERATURE LOG COMPENSATION 451Ω 6.69kΩ 8kΩ 0.5V 1nF CFLT 10nF COMM VSUM 1nF SCAL BFIN VBE2 1nF IPD INPT VOUT BIAS GENERATOR 14.2kΩ 1kΩ 1kΩ PD COMM IREF VBIAS I ( 1nA ) VNEG COMM 03727-0-022 Figure 22. Basic Connections for Fixed Intercept Use The 2 V difference in voltage between VREF and INPT, in conjunction with the external 200 kΩ resistor RREF, provides a reference current IREF of 100 µA into Pin IREF. The internal reference raises the voltage at VLOG by 0.8 V, effectively lowering the intercept current IINTC by a factor of 104 to position it at 1 nA. Any temperature variation in RREF must be taken into account when estimating the stability of the intercept. Also, the overall noise will increase when using very low values of IREF. In fixed-intercept applications, there is little benefit in using a large reference current, since this only compresses the low current end of the dynamic range when operated from a single supply, shown here as 5 V. The capacitor between VSUM and ground is recommended to minimize the noise on this node and to help provide a clean reference current. Since the basic scaling at VLOG is 0.2 V/dec and a swing of 4 V at the buffer output would therefore correspond to 20 decades, it will often be useful to raise the slope to make better use of the rail-to-rail voltage range. For illustrative purposes, the circuit in Figure 22 provides an overall slope of 0.5 V/dec (25 mV/dB). Thus, using IREF = 100 µA, VLOG runs from 0.2 V at IPD = 100 nA to 0.8 V at IPD = 100 µA. The buffer output runs from 0.5 V to 2.0 V, corresponding to a dynamic range of 60 dB electrical (30 dB optical) power. frequency is 3.2 kHz. Such filtering is useful in minimizing the output noise, particularly when IPD is small. Multipole filters are more effective in reducing the total noise. For examples, see the AD8304 Data Sheet. The dynamic response of this overall input system is influenced by the external RC networks connected from the two inputs (INPT, IREF) to ground. These are required to stabilize the input systems over the full current range. The bandwidth changes with the input current due to the widely varying pole frequency. The RC network adds a zero to the input system to ensure stability over the full range of input current levels. The network values shown in Figure 22 will usually suffice, but some experimentation may be necessary when the photodiode’s capacitance is high. Although the two current inputs are similar, some care is needed to operate the reference input at extremes of current (