120 dB Range (3 nA to 3 mA)
Dual Logarithmic Converter
ADL5310
Data Sheet
FEATURES
FUNCTIONAL BLOCK DIAGRAM
2 independent channels optimized for photodiode interfacing
6-decade input dynamic range
Law conformance 0.3 dB from 3 nA to 3 mA
Temperature-stable logarithmic outputs
Nominal slope 10 mV/dB (200 mV/dec), externally scalable
Intercepts may be independently set by external resistors
User-configurable output buffer amplifiers
Single-supply or dual-supply operation
Space efficient, 24-lead 4 mm × 4 mm LFCSP
Low power: 3 µA; output referred
IPD = 3 µA
Min
Typ
3n
3n
0.46
0.5
0.030
Limited by VN = 0 V
4.375
Unit
3m
10 m
3m
0.54
A
A
A
V
mV/°C
mV
+20
−20
190
185
165
40
Max
200
300
0.1
0.3
0.5
1.5
1.7
0.10
5
210
215
535
1940
0.4
0.6
5.625
mV/dec
mV/dec
pA
pA
dB
dB
µV/√Hz
MHz
V
V
kΩ
Pin 7 and Pin 24 (internally shorted): VREF
–40°C < TA < +85°C
Sourcing (grounded load)
Load current < 10 mA
Pins 12 to 14 and 17 to 19: OUT2, SCL2, BIN2, BIN1, SCL1,
and OUT1
2.45
2.42
2.5
−20
+20
mV
µA
MΩ
Ω
V
V
mA
MHz
V/µs
12
11.5
V
mA
V
0.4
35
0.5
VP − 0.1
0.10
30
15
15
Load current < 10 mA; gain = 1
RL = 1 kΩ to ground
RL = 1 kΩ to ground
3
−5.5
Other values of logarithmic intercept can be achieved by adjustment of RREF.
Output noise and incremental bandwidth are functions of input current; measured using output buffer connected for GAIN = 1.
Rev. B | Page 3 of 20
V
V
mA
Ω
20
4
Flowing out of Pins 13, 14, 17, and 18
Gain = 1
0.2 V to 4.8 V output swing
Pins 8 and 9: VPOS; Pins 10, 11, and 20: VNEG
(VP – VN ) ≤ 12 V
Input currents < 10 µA
(VP – VN ) ≤ 12 V
2.55
2.58
5
9.5
0
ADL5310
Data Sheet
ABSOLUTE MAXIMUM RATINGS
Table 2.
Parameter
Supply Voltage VP − VN
Input Current
Internal Power Dissipation
θJA
Maximum Junction Temperature
Operating Temperature Range
Storage Temperature Range
Lead Temperature Range (Soldering 60 sec)
1
Rating
12 V
20 mA
500 mW
35°C/W 1
125°C
–40°C to +85°C
−65°C to +150°C
300°C
Stresses at or above those listed under Absolute Maximum
Ratings may cause permanent damage to the product. This is a
stress rating only; functional operation of the product at these
or any other conditions above those indicated in the operational
section of this specification is not implied. Operation beyond
the maximum operating conditions for extended periods may
affect product reliability.
ESD CAUTION
With paddle soldered down.
Rev. B | Page 4 of 20
Data Sheet
ADL5310
19 OUT1
21 COMM
20 VNEG
22 COMM
24 VREF
23 VRDZ
PIN CONFIGURATION AND FUNCTION DESCRIPTIONS
18 SCL1
VSUM 1
INP1 2
IRF2 4
INP2 5
17 BIN1
ADL5310
DUAL LOG AMP
TOP VIEW
(Not to Scale)
VSUM 6
16 LOG1
15 LOG2
14 BIN2
OUT2 12
VNEG 11
VPOS 9
VNEG 10
VREF 7
VPOS 8
13 SCL2
NOTES
1. EXPOSED PAD. THE EXPOSED PAD MUST
BE CONNECTED TO ANALOG GROUND
VIA A LOW IMPEDANCE PATH.
04415-0-002
IRF1 3
Figure 2. 24-Lead LFCSP Pin Configuration
Table 3. Pin Function Descriptions
Pin No.
1, 6
Mnemonic
VSUM
2
INP1
3
4
5
IRF1
IRF2
INP2
7, 24
8, 9
10, 11, 20
VREF
VPOS
VNEG
12
13
14
15
16
17
18
19
21, 22
23
OUT2
SCL2
BIN2
LOG2
LOG1
BIN1
SCL1
OUT1
COMM
VRDZ
EPAD
Function
Guard Pin. Used to shield the INP1 and INP2 input current lines, and for optional adjustment of the input
summing node potentials. Pin 1 and Pin 6 are internally shorted.
Channel 1 Numerator Input. Accepts (sinks) photodiode current IPD1. Usually connected to photodiode anode
such that photocurrent flows into INP1.
Channel 1 Denominator Input. Accepts (sinks) reference current, IRF1.
Channel 2 Denominator Input. Accepts (sinks) reference current, IRF2.
Channel 2 Numerator Input. Accepts (sinks) photodiode current IPD2. Usually connected to photodiode anode
such that photocurrent flows into INP2.
Reference Output Voltage of 2.5 V. Pin 7 and Pin 24 are internally shorted.
Positive Supply, (VP – VN) ≤ 12 V. Both pins must be connected externally.
Optional Negative Supply, VN. These pins are usually grounded. For more details, see the General Structure and
Applications Information sections. All VNEG pins must be connected externally.
Buffer Output for Channel 2.
Buffer Amplifier Inverting Input for Channel 2.
Buffer Amplifier Noninverting Input for Channel 2.
Output of the Logarithmic Front End for Channel 2.
Output of the Logarithmic Front End for Channel 1.
Buffer Amplifier Noninverting Input for Channel 1.
Buffer Amplifier Inverting Input for Channel 1.
Buffer Output for Channel 1.
Analog Ground. Pin 21 and Pin 22 are internally shorted.
Intercept Shift Reference Input. The top of a resistive divider network that offsets VLOG to position the intercept.
Normally connected to VREF; may also be connected to ground when bipolar outputs are to be provided.
Exposed Pad. The exposed pad must be connected to analog ground via a low impedance path.
Rev. B | Page 5 of 20
ADL5310
Data Sheet
TYPICAL PERFORMANCE CHARACTERISTICS
VP = 5 V, VN = 0 V, RREF = 665 kΩ, TA = 25°C, unless otherwise noted.
1.6
2.0
TA = –40°C, 0°C, +25°C, +70°C, +85°C
VIN = 0V
1.4
1.5
ERROR (dB (10mV/dB))
1.0
0.8
0.6
0.4
0.5
0
–0.5
0°C
–40°C
–1.0
1µ
100n
10µ
100µ
1m
10m
IINP (A)
–2.0
1n
1µ
10µ
100µ
1m
10m
Figure 6. Law Conformance Error vs. IINP for Multiple Temperatures,
Normalized to 25°C
2.0
TA = –40°C, 0°C, +25°C, +70°C, +85°C
VIN = 0V
1.6
100n
IINP (A)
Figure 3. VLOG vs. IINP for Multiple Temperatures
1.8
10n
04415-0-006
10n
04415-0-003
0
1n
1.5
ERROR (dB (10mV/dB))
1.4
1.2
1.0
0.8
0.6
0.4
1.0
+70°C
+85°C
0.5
+25°C
0
–0.5
–40°C
–1.0
0°C
–1.5
0.2
1n
10n
100n
1µ
10µ
100µ
1m
10m
IREF (A)
–2.0
1n
04415-0-004
0
10n
100n
1µ
10µ
100µ
1m
10m
IREF (A)
Figure 4. VLOG vs. IREF for Multiple Temperatures (IINP = 3 µA)
04415-0-007
VLOG (V)
+85°C
+70°C
+25°C
–1.5
0.2
Figure 7. Law Conformance Error vs. IREF for Multiple Temperatures,
Normalized to 25°C (IINP = 3 µA)
1.8
1.0
1.6
0.8
3mA
ERROR (dB (10mV/dB))
300nA
1.2
30nA
3nA
1.0
300µA
0.6
3µA
1.4
0.8
3mA
0.6
300µA
0.4
30µA
0.4
3µA
0.2
0
–0.2
300nA
–0.4
–0.6
30µA
0.2
3nA
–0.8
0
1n
10n
100n
1µ
10µ
100µ
1m
IINP (A)
10m
04415-0-005
VLOG (V)
1.0
–1.0
1n
10n
100n
1µ
10µ
100µ
30nA
1m
10m
IINP (A)
Figure 8. Law Conformance Error vs. IINP for Multiple Values of IREF,
Decade Steps from 3 nA to 3 mA
Figure 5. VLOG vs. IINP for Multiple Values of IREF,
Decade Steps from 3 nA to 3 mA
Rev. B | Page 6 of 20
04415-0-008
VLOG (V)
1.2
Data Sheet
ADL5310
1.8
1.0
1.6
0.8
1.4
0.6
3nA
30µA
1.2
300µA
1.0
3mA
0.8
3nA
0.6
30nA
300nA
0.4
300nA
0.4
3µA
0.2
3µA
0
3mA
–0.2
3mA
–0.4
300µA
–0.6
3µA
30µA
0.2
–0.8
1n
10n
100n
1µ
10µ
100µ
1m
10m
IREF (A)
–1.0
1n
04415-0-009
0
10n
100n
1µ
10µ
100µ
1m
10m
IREF (A)
Figure 9. VLOG vs. IREF for Multiple Values of IINP,
Decade Steps from 3 nA to 3 mA
04415-0-012
VLOG (V)
ERROR (dB (10mV/dB))
30nA
Figure 12. Law Conformance Error vs. IREF for Multiple Values of IINP,
Decade Steps from 3 nA to 3 mA
1.0
2.0
TA = 25°C
0.8
+5V, 0V
+12V, 0V
+12V, 0V
0.4
ERROR (dB (10mV/dB))
ERROR (dB (10mV/dB))
0.6
1.5
+9V, 0V
0.2
+3V, 0V
0
–0.2
+5V, –5V
+5V, –5V
–0.4
1.0
MEAN + 3σ
0.5
0
–0.5
MEAN – 3σ
–1.0
–0.6
10n
100n
1µ
10µ
100µ
1m
10m
IINP (A)
–2.0
1n
04415-0-010
–1.0
1n
10n
100n
1µ
10µ
100µ
1m
10m
IPD (A)
Figure 10. Law Conformance Error vs. IINP for Various Supply Conditions
04415-0-013
–1.5
–0.8
Figure 13. Law Conformance Error Distribution (3σ to Either Side of Mean)
2.0
4
TA = 0°C, 70°C
TA = –40°C, 85°C
1.5
3
ERROR (dB (10mV/dB))
0.5
0
MEAN ± 3σ AT 0°C
–0.5
–1.0
1
MEAN + 3σ AT +85°C
0
–1
–2
MEAN – 3σ AT 70°C
–1.5
MEAN – 3σ AT –40°C
–3
10n
100n
1µ
10µ
IPD (A)
100µ
1m
10m
–4
1n
04415-0-011
–2.0
1n
2
Figure 11. Law Conformance Error Distribution (3σ to Either Side of Mean)
10n
100n
1µ
10µ
IPD (A)
100µ
1m
10m
04415-0-014
ERROR (dB (10mV/dB))
MEAN + 3σ AT –40°C
MEAN + 3σ AT 70°C
1.0
Figure 14. Law Conformance Error Distribution (3σ to Either Side of Mean)
Rev. B | Page 7 of 20
ADL5310
Data Sheet
15
1.6
30nA
10
300nA
1.4
3nA
30µA
0
–5
–10
300µA
–15
–20
–25
–35
300µA TO 3mA
T-RISE < 1µs T-FALL < 1µs
30µA TO 300µA
T-RISE < 1µs T-FALL < 5µs
3µA TO 30µA
T-RISE < 5µs T-FALL < 10µs
300nA TO 3µA
T-RISE < 10µs T-FALL < 40µs
30nA TO 300nA
T-RISE < 30µs T-FALL < 80µs
3nA TO 30nA
1.0
0.8
0.6
3mA
–30
T-RISE < 1µs T-FALL < 1µs
1.2
VOUT (V)
NORMALIZED RESPONSE (dB)
5
0.4
3µA
–40
0.2
1k
10k
100k
1M
10M
100M
FREQUENCY (Hz)
0
04415-0-015
–50
100
0
40
60
80
100
120
140
160
180
200
TIME (µs)
Figure 15. Small Signal AC Response, IINP to VOUT (AV = 1)
(5% Sine Modulation, Decade Steps from 3 nA to 3 mA)
Figure 18. Pulse Response—IINP to VOUT (AV = 1)
in Consecutive 1-Decade Steps
1.6
15
30nA
10
300nA
5
1.4
3mA
0
T-RISE < 80µs T-FALL < 30µs
3nA TO 30nA
T-RISE < 40µs T-FALL < 10µs
30nA TO 300nA
T-RISE < 10µs T-FALL < 5µs
300nA TO 3µA
T-RISE < 1µs T-FALL < 1µs
3µA TO 30µA
T-RISE < 1µs T-FALL < 1µs
30µA TO 300µA
T-RISE < 1µs T-FALL < 1µs
300µA TO 3mA
1.2
–5
300µA
3nA
–10
VOUT (V)
NORMALIZED RESPONSE (dB)
20
04415-0-018
–45
–15
–20
1.0
0.8
3µA
–25
0.6
–30
30µA
0.4
–35
–40
0.2
1k
10k
100k
1M
10M
100M
FREQUENCY (Hz)
0
04415-0-016
–50
100
0
20
40
60
80
100
120
140
160
180
200
TIME (µs)
04415-0-019
–45
Figure 19. Pulse Response—IREF to VOUT (AV = 1)
in Consecutive 1-Decade Steps
Figure 16. Small Signal AC Response, IREF to VOUT (AV = 1)
(5% Sine Modulation, Decade Steps from 3 nA to 3 mA)
5.0
100
3nA
4.0
10
mV rms
3.0
1
300nA
3µA
2.0
0.1
1.0
0.01
100
1k
3mA
30µA
10k
100k
1M
10M
FREQUENCY (Hz)
Figure 17. Spot Noise Spectral Density at VOUT vs. Frequency (AV = 1)
for IINP in Decade Steps from 3 nA to 3 mA
0
1n
10n
100n
1µ
10µ
100µ
1m
10m
IINP (A)
Figure 20. Total Wideband Noise Voltage at VOUT vs. IINP (AV = 1)
Rev. B | Page 8 of 20
04415-0-020
300µA
04415-0-017
µV rms/ Hz
30nA
Data Sheet
ADL5310
25
5
20
4
15
3
2
VINPT DRIFT (mV)
MEAN + 3σ
5
0
–5
MEAN – 3σ
–10
0
MEAN – 3σ
–2
–4
–20
–5
10
30
20
40
50
60
70
80
90
–6
–40 –30 –20 –10
04415-0-021
0
0
10
20
30
40
50
60
70
80
90
TEMPERATURE (°C)
Figure 21. VREF Drift vs. Temperature (3σ to Either Side of Mean)
Normalized to 25°C
Figure 24. VINPT Drift vs. Temperature (3σ to Either Side of Mean)
Normalized to 25°C
6
7
5
6
4
5
04415-0-024
–3
TEMPERATURE (°C)
4
MEAN + 3σ
1
0
–1
–2
MEAN – 3σ
3
2
0
–1
–2
–3
–3
–4
–4
–5
–5
0
10
20
30
40
50
60
70
80
90
TEMPERATURE (°C)
MEAN – 3σ
–6
–40 –30 –20 –10
04415-0-022
–6
–40 –30 –20 –10
MEAN + 3σ
1
0
10
20
30
40
50
60
70
80
90
TEMPERATURE (°C)
Figure 22. Slope Drift vs. Temperature (3σ to Either Side of Mean)
Normalized to 25°C
04415-0-025
2
∆VY DRIFT (mV/dec)
3
Figure 25. Slope Mismatch Drift vs. Temperature
(VY1 – VY2, 3σ to Either Side of Mean) Normalized to 25°C
200
200
150
150
100
100
∆IZ DRIFT (pA)
MEAN + 3σ
50
0
MEAN – 3σ
–50
MEAN + 3σ
50
0
–50
MEAN – 3σ
–100
–100
–150
–150
–40 –30 –20 –10
0
10
20
30
40
50
60
70
80
TEMPERATURE (°C)
90
04415-0-023
IZ DRIFT (pA)
MEAN + 3σ
–1
–15
–25
–40 –30 –20 –10
VY DRIFT (mV/dec)
1
–200
–40 –30 –20 –10
0
10
20
30
40
50
60
70
80
90
TEMPERATURE (°C)
Figure 26. Intercept Mismatch Drift vs. Temperature
(IZ1 – IZ2, 3σ to Either Side of Mean) Normalized to 25°C
Figure 23. Intercept Drift vs. Temperature
(3σ to Either Side of Mean) Normalized to 25°C
Rev. B | Page 9 of 20
04415-0-026
VREF DRIFT (mV)
10
ADL5310
Data Sheet
450
700
400
600
350
500
400
COUNT
COUNT
300
300
250
200
150
200
100
100
200
205
210
SLOPE (mV/dec)
0
Figure 27. Distribution of Logarithmic Slope
–9
–6
–3
0
3
6
9
SLOPE MISMATCH (mV/dec)
04415-0-030
195
04415-0-027
0
190
50
Figure 30. Distribution of Channel-to-Channel Slope Mismatch (VY1 – VY2)
600
500
500
400
COUNT
COUNT
400
300
300
200
200
200
300
400
500
INTERCEPT (pA)
0
–300
04415-0-028
0
100
–200
–100
0
100
200
300
INTERCEPT MISMATCH (pA)
04415-0-031
100
100
Figure 31. Distribution of Channel-to-Channel Intercept Mismatch (IZ1 – IZ2)
Figure 28. Distribution of Logarithmic Intercept
500
700
600
400
COUNT
400
300
300
200
200
100
0
2.46
2.48
2.50
2.52
VREF VOLTAGE (V)
2.54
Figure 29. Distribution of VREF (RL = 100 kΩ)
0
–9
–6
–3
0
3
6
VINPT – VSUM VOLTAGE (mV)
Figure 32. Distribution of Offset Voltage (VINPT – VSUM)
Rev. B | Page 10 of 20
9
04415-0-032
100
04415-0-029
COUNT
500
Data Sheet
ADL5310
GENERAL STRUCTURE
The ADL5310 addresses a wide variety of interfacing conditions
to meet the needs of fiber optic supervisory systems and is useful
in many nonoptical applications. These notes explain the structure
of this unique style of translinear log amp. Figure 33 shows the
key elements of one of the two identical on-board log amps.
BIAS
GENERATOR
PHOTODIODE
2.5V
INPUT
CURRENT
80kΩ
IPD
0.5V
IREF
IREF
VBE2
20kΩ
COMM
VSUM
INP1
(INP2)
VBE1
VREF
TEMPERATURE
COMPENSATION
(SUBTRACT AND
DIVIDE BY T°K)
44µA/dec
0.5V
14.2kΩ 451Ω
VRDZ
VLOG
0.5V
VBE1
Q2
VNEG (NORMALLY GROUNDED)
VBE2
6.69kΩ
COMM
04415-0-033
Q1
Figure 33. Simplified Schematic of Single Log Amp
The photodiode current IPD is received at either Pin INP1 or
Pin INP2. The voltages at these nodes are approximately equal
to the voltage on the adjacent guard pins, VSUM, as well as reference
inputs IRF1 and IRF2, due to the low offset voltage of the JFET
operational amplifiers. Transistor Q1 converts IPD to a corresponding logarithmic voltage, as shown in Equation 1. A finite
positive value of VSUM is needed to bias the collector of Q1 for
the usual case of a single-supply voltage. This is internally set to
0.5 V, one-fifth of the 2.5 V reference voltage that appears on
Pin VREF. Both VREF pins are internally shorted, as are both
VSUM pins. The resistance at the VSUM pin is nominally 16 kΩ;
this voltage is not intended as a general bias source.
The ADL5310 also supports the use of an optional negative supply
voltage, VN, at Pin VNEG. When VN is 0.5 V or more negative,
VSUM may be connected to ground; thus, INP1, INP2, IRF1,
and IRF2 assume this potential. This allows operation as a voltageinput logarithmic converter by the inclusion of a series resistor
at either or both inputs. Note that the resistor setting IREF for
each channel needs to be adjusted to maintain the intercept value.
Also, note that the collector-emitter voltages of Q1 and Q2 are
the full VN and effects due to self-heating cause errors at large
input currents.
The input-dependent VBE1 of Q1 is compared with the reference
VBE2 of a second transistor, Q2, operating at IREF. IREF is generated
externally to a recommended value of 3 µA. However, other
values over a several-decade range can be used with a slight
degradation in law conformance.
THEORY
The base-emitter voltage of a bipolar junction transistor (BJT)
can be expressed by Equation 1, which immediately shows its
basic logarithmic nature:
VBE = kT/q ln(IC/IS)
(1)
where:
IC is the collector current.
IS is a scaling current, typically only 10–17 A.
kT/q is the thermal voltage, proportional to absolute
temperature (PTAT), and is 25.85 mV at 300 K.
IS is never precisely defined and exhibits an even stronger temperature dependence, varying by a factor of roughly a billion between
−35°C and +85°C. Thus, to make use of the BJT as an accurate
logarithmic element, both of these temperature dependencies
must be eliminated.
The difference between the base-emitter voltages of a matched
pair of BJTs, one operating at the photodiode current IPD and
the other operating at a reference current IREF, can be written as
VBE1 – VBE2 = kT/q ln(IPD/IS) – kT/q ln(IREF/IS)
= ln(10) kT/q log10(IPD/IREF)
= 59.5 mV log10(IPD/IREF) (T = 300 K)
(2)
The uncertain, temperature-dependent saturation current, IS,
that appears in Equation 1 has therefore been eliminated. To
eliminate the temperature variation of kT/q, this difference
voltage is processed by what is essentially an analog divider.
Effectively, it puts a variable under Equation 2. The output of
this process, which also involves a conversion from voltage
mode to current mode, is an intermediate, temperaturecorrected current:
ILOG = IY log10(IPD/IREF)
(3)
where IY is an accurate, temperature-stable scaling current that
determines the slope of the function (change in current per
decade).
For the ADL5310, IY is 44 µA, resulting in a temperatureindependent slope of 44 µA/decade for all values of IPD and IREF.
This current is subsequently converted back to a voltage-mode
output, VLOG, scaled 200 mV/decade.
It is apparent that this output is 0 for IPD = IREF and must swing
negative for smaller values of input current. To avoid this, IREF
would need to be as small as the smallest value of IPD. Accordingly,
an offset voltage is added to VLOG to shift it upward by 0.8 V when
VRDZ is directly connected to VREF. This moves the intercept
to the left by four decades (at 200 mV/decade), from 3 μA to
300 pA:
ILOG = IY log10(IPD/IINTC)
where IINTC is the operational value of the intercept current.
Rev. B | Page 11 of 20
(4)
ADL5310
Data Sheet
Because values of IPD < IINTC result in a negative VLOG, a negative
supply of sufficient value is required to accommodate this
situation.
Thus, the effective intercept current IINTC is only one tenthousandth of IREF, corresponding to 300 pA when using the
recommended value of IREF = 3 μA.
The voltage VLOG is generated by applying ILOG to an internal
resistance of 4.55 kΩ, formed by the parallel combination of a
6.69 kΩ resistor to ground and a 14.2 kΩ resistor to Pin VRDZ
(typically tied to the 2.5 V reference, VREF). At the LOG1
(LOG2) pin, the output current ILOG generates a voltage of
The slope can be reduced by attaching a resistor between the log
amp output pin, LOG1 or LOG2, and ground. This is strongly
discouraged given that the on-chip resistors do not ratio
correctly to the added resistance. In addition, it is rare that one
would wish to lower the basic slope of 10 mV/dB; if this is
needed, it should be effected at the low impedance output of the
buffer amps, which are provided to avoid such miscalibration
and to allow higher slopes to be used.
VLOG = ILOG × 4.55 kΩ
= 44 μA × 4.55 kΩ × log10(IPD/IINTC)
= VY log10(IPD/IINTC)
(5)
where VY = 200 mV/decade or 10 mV/dB.
Note that any resistive loading on LOG1 (LOG2) lowers this
slope and results in an overall scaling uncertainty. This is due to
the variability of the on-chip resistors compared to the off-chip
load. As a consequence, this practice is not recommended.
VLOG may also swing below ground when dual supplies (VP and
VN) are used. When VN = −0.5 V or larger, the input Pins INP1
(INP2) and IRF1 (INP2) may be positioned at ground level
simply by grounding VSUM. Care must be taken to limit the
power consumed by the input BJT devices when using a larger
negative supply, because self heating degrades the accuracy at
higher currents.
MANAGING INTERCEPT AND SLOPE
When using a single supply, VRDZ should be directly connected
to VREF to allow operation over the entire 6-decade input current
range. As noted in the Theory section, this introduces an accurate
offset voltage of 0.8 V at the LOG1 and LOG2 pins, equivalent
to four decades, resulting in a logarithmic transfer function that
can be written as
VLOG = VY log10(104 × IPD/IREF) = VY log10(IPD/IINTC)
Each buffer of the ADL5310 is essentially an uncommitted
operational amplifier with rail-to-rail output swing, good load
driving capabilities, and a typical unity-gain bandwidth of 15 MHz.
In addition to allowing the introduction of gain, using standard
feedback networks and thereby increasing the slope voltage VY,
the buffer can be used to implement multipole, low-pass filters,
threshold detectors, and a variety of other functions. Further
details on these applications can be found in the AD8304 data
sheet.
RESPONSE TIME AND NOISE CONSIDERATIONS
The response time and output noise of the ADL5310 are fundamentally a function of the signal current, IPD. For small currents,
the bandwidth is proportional to IPD, as shown in Figure 15. The
output low frequency voltage-noise spectral-density is a function
of IPD (see Figure 17) and increases for small values of IREF. Details
of the noise and bandwidth performance of translinear log amps
can be found in the AD8304 data sheet.
(6)
4
where IINTC = IREF/10 .
Rev. B | Page 12 of 20
Data Sheet
ADL5310
APPLICATIONS INFORMATION
5V
665kΩ
VREF
VSUM
VRDZ
VPOS
OUT1
IPD1
0.5log10 1nA
(
)
VOUT1
COMM
IRF1
12kΩ
IRF1
SCL1
2kΩ
6.69kΩ
4.7nF
VBIAS
VNEG
I
TEMPERATURE LOG
COMPENSATION
8kΩ
BIN1
LOG1
451Ω
CFLT1
10 nF
14.2kΩ
IPD1
INP1
1kΩ
OUT2
1nF
0.5V
20kΩ
REFERENCE
GENERATOR
2.5V
80kΩ
(
)
12kΩ
COMM
IRF2
SCL2
2kΩ
14.2kΩ
4.7nF
VBIAS
IPD2
0.5log10 1nA
VOUT2
VNEG
TEMPERATURE
COMPENSATION
ILOG
IRF2
8kΩ
BIN2
LOG2
451Ω
CFLT2
10 nF
6.69kΩ
IPD2
INP2
VSUM
1nF
VREF
VNEG
COMM
1nF
665kΩ
04415-0-034
1kΩ
COMM
Figure 34. Basic Connections for Fixed Intercept Use
The ADL5310 is easy to use in optical supervisory systems and in
similar situations where a wide-ranging current is to be converted
to its logarithmic equivalent, that is, represented in decibel terms.
Basic connections for measuring a single current at each input
are shown in Figure 34, which also includes various nonessential
components, as explained next.
The 2 V difference in voltage between the VREF and Input Pins
INP1 and INP2, in conjunction with the external 665 kΩ resistors
RRF1 and RRF2, provides 3 µA reference currents IRF1 and IRF2 into
Pins IRF1 and IRF2. Connecting VRDZ to VREF raises the
voltage at LOG1 and LOG2 by 0.8 V, effectively lowering each
intercept current IINTC by a factor of 104 to position it at 300 pA.
A wide range of other values for IREF, from 3 nA to 3 mA, may
be used. The effect of such changes is shown in Figure 5 and
Figure 8.
Any temperature variation in RRF1 (RRF2) must be taken into account
when estimating the stability of the intercept. Also, the overall
noise increases when using very low values of IRF1 (IRF2). In fixed
intercept applications, there is little benefit in using a large reference
current, because doing so only compresses the low current end
of the dynamic range when operated from a single supply. The
capacitor between VSUM and ground is strongly recommended
to minimize the noise on this node, to reduce channel-to-channel
crosstalk, and to help provide clean reference currents.
In addition, each input and reference pin (INP1, INP2, IRF1,
and IRF2) has a compensation network made up of a series
resistor and capacitor. The junction capacitance of the photodiode along with the network capacitance of the board artwork
around the input system creates a pole that varies widely with
input current. The RC network stabilizes the system by simultaneously reducing this pole frequency and inserting a zero to
compensate an additional pole inherent in the input system. In
general, the 1 nF, 1 kΩ network handles almost any photodiode
interface. In situations where larger active area photodiodes are
used, or when long input traces are used, the capacitor value may
need to be increased to ensure stability. Although the signal and
reference input systems are similar, additional care is required
to ensure stable operation of the reference inputs at temperature
extremes across the full current range of IRF1 (IRF2). It is recommended that filter components of 4.7 nF and 2 kΩ should be
used from Pin IRF1 (IRF2) to ground. Temperature-stable components should always be used in critical locations, such as the
compensation networks. Y5V-type chip capacitors are to be
avoided due to their poor temperature stability.
The optional capacitor from LOG1 (LOG2) to ground forms a
single-pole, low-pass filter in combination with the 5 kΩ resistance at this pin. For example, when using a CFLT of 10 nF, the
3 dB corner frequency is 3.2 kHz. Such filtering is useful in
Rev. B | Page 13 of 20
ADL5310
Data Sheet
minimizing the output noise, particularly when IPD is small.
Multipole filters are more effective in reducing the total noise;
examples are provided in the AD8304 data sheet.
Because the basic scaling at LOG1 (LOG2) is 0.2 V/decade, and
a 4 V swing at the buffer output would correspond to 20 decades,
it is often useful to raise the slope to make better use of the railto-rail voltage range. For illustrative purposes, both channels in
Figure 34 provide a 0.5 V/decade overall slope (25 mV/dB).
Thus, using IREF = 3 μA, VLOG runs from 0.2 V at IPD = 3 nA to
1.4 V at IPD = 3 mA; the buffer output runs from 0.5 V to 3.5 V,
corresponding to a dynamic range of 120 dB (electrical, that is,
60 dB optical power).
Further information on adjusting the slope and intercept, using
a negative supply, and additional operations can be found in the
AD8305 data sheet.
CALIBRATION
Each channel of the ADL5310 has a nominal slope and intercept
at LOG1 (LOG2) of 200 mV/decade and 300 pA, respectively,
when configured as shown in Figure 34. These values are
untrimmed and the slope alone may vary by as much as 7.5%
over temperature. For this reason, it is recommended that a
simple calibration be done to achieve increased accuracy. While
the ADL5310 offers improved slope and intercept matching
compared to a randomly selected pair of AD8305 log amps, the
specified accuracy can only be achieved by calibrating each
channel individually.
4
1.4
UNCALIBRATED ERROR
2
VLOG (V)
1.0
0.8
1
MEASURED OUTPUT
0
0.6
CALIBRATED ERROR
0.4
0.2
0
1n
–2
IDEAL OUTPUT
10n
100n
1µ
10µ
IPD (A)
–1
ERROR (dB (10mV/dB))
3
100µ
1m
–3
10m
04415-0-035
1.2
Figure 35. Using 2-Point Calibration to Increase Measurement Accuracy
Figure 35 shows the improvement in accuracy when using a
2-point calibration method. To perform this calibration, apply
two known currents, I1 and I2, in the linear operating range
between 10 nA and 1 mA. Measure the resulting output, V1 and
V2, respectively, and calculate the slope m and the intercept b:
m = (V1 – V2)/[log10(I1) – log10(I2)]
(7)
b = V1 – m × log10(I1)
(8)
The same calibration can be performed with two known optical
powers, P1 and P2. This allows for calibration of the entire
measurement system while providing a simplified relationship
between the incident optical power and VLOG voltage:
m = (V1 – V2)/(P1 – P2)
b = V1 – m × P1
(9)
(10)
The uncalibrated error line in Figure 35 was generated assuming
that the slope of the measured output was 200 mV/decade when
in fact it was actually 194 mV/decade. Correcting for this discrepancy decreased measurement error up to 3 dB.
MINIMIZING CROSSTALK
Combining two high-dynamic-range logarithmic converters in
one IC carries potential pitfalls concerning channel-to-channel
isolation. Special care must be taken in several areas to ensure
acceptable crosstalk performance, particularly when one or
both channels may operate at very low input currents. Fastidious
supply bypassing, which is also necessary for overall stability,
and careful board layout are important first steps for
minimizing crosstalk.
While the shared bias circuitry improves channel-to-channel
matching and reduces power consumption, it is also a source of
crosstalk that must be mitigated. The VSUM pins, which are internally shorted, should be bypassed with at least 1 nF to ground,
and 20 nF is recommended for operation at the lowest currents
(
