ADL5317ACPZ-REEL7

FEATURES FUNCTIONAL BLOCK DIAGRAM Accurately sets avalanche photodiode (APD) bias voltage Wide bias range from 6 V to 75 V 3 V-compatible control interface Monitors photodiode current (5:1 ratio) over six decades Linearity 0.25% from 10 nA to 1 mA, 0.5% from 5 nA to 5 mA Overcurrent protection and overtemperature shutdown Miniature 16-lead chip scale package (LFCSP 3 mm × 3 mm) APPLICATIONS 16 15 14 13 COMM COMM COMM COMM ADL5317 FALT 1 OVERCURRENT PROTECTION CURRENT MIRROR 5:1 THERMAL PROTECTION NC 12 VSET 30 × VSET 2 Optical power monitoring and biasing in APD systems Wide dynamic range voltage sourcing and current monitoring in high voltage systems IPDM 29 × R 11 IAPD 5 3 VPLV 4 VPHV VPHV 5 R NC 10 IAPD VCLH GARD 6 GARD 9 VAPD 7 8 05456-001 Data Sheet Avalanche Photodiode Bias Controller and Wide Range (5 nA to 5 mA) Current Monitor ADL5317 Figure 1. GENERAL DESCRIPTION The ADL5317 is a high voltage, wide dynamic range, biasing and current monitoring device optimized for use with avalanche photodiodes. When used with a stable high voltage supply (up to 80 V), the bias voltage at the VAPD pin can be varied from 6 V to 75 V using the 3 V-compatible VSET pin. The current sourced from the VAPD pin over a range of 5 nA to 5 mA is accurately mirrored with an attenuation of 5 and sourced from the IPDM monitor output. In a typical application, the monitor output drives a current input logarithmic amplifier to produce an output representing the optical power incident upon the photodiode. The photodiode anode can be connected to a high speed transimpedance amplifier for the extraction of the data stream. A signal of 0.2 V to 2.5 V with respect to ground applied at the VSET pin is amplified by a fixed gain of 30 to produce the 6 V to 75 V bias at Pin VAPD. The accuracy of the bias control interface of the ADL5317 allows for straightforward calibration, thereby maintaining a constant avalanche multiplication factor of the photodiode over temperature. The current monitor output, IPDM, maintains its high linearity vs. photodiode current over the full Rev. A range of APD bias voltage. The current ratio of 5:1 remains constant as VSET and VPHV are varied. The ADL5317 also offers a supply tracking mode compatible with adjustable high voltage supplies. The VAPD pin accurately follows 2.0 V below the VPHV supply pin when VSET is tied to a voltage from 3.0 V to 5.5 V (or higher with a current limiting resistor), and the VCLH pin is open. Protection from excessive input current at VAPD as well as excessive die temperature is provided. The voltage at VAPD falls rapidly from its setpoint when the input current exceeds 18 mA nominally. A die temperature in excess of 140°C will cause the bias controller and monitor to shut down until the temperature falls below 120°C. Either overstress condition will trigger a logic low at the FALT pin, an open collector output loaded by an external pull-up to an appropriate logic supply (1 mA max). The ADL5317 is available in a 16-lead LFCSP package and is specified for operation from −40°C to +85°C. Document Feedback Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective owners. One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. Tel: 781.329.4700 ©2005–2017 Analog Devices, Inc. All rights reserved. Technical Support www.analog.com ADL5317 Data Sheet TABLE OF CONTENTS Features .............................................................................................. 1 VCLH Interface .......................................................................... 10 Applications ....................................................................................... 1 Noise Performance ..................................................................... 10 Functional Block Diagram .............................................................. 1 Response Time............................................................................ 10 General Description ......................................................................... 1 Device Protection ....................................................................... 10 Table of Contents .............................................................................. 2 Applications Information .............................................................. 11 Specifications..................................................................................... 3 Supply Tracking Mode ............................................................... 11 Absolute Maximum Ratings ............................................................ 4 Translinear Log Amp Interfacing ............................................. 11 ESD Caution .................................................................................. 4 Characterization Methods ........................................................ 12 Pin Configuration and Function Descriptions ............................. 5 Evaluation Board ............................................................................ 14 Typical Performance Characteristics ............................................. 6 Outline Dimensions ....................................................................... 16 Theory of Operation ........................................................................ 9 Ordering Guide .......................................................................... 16 Bias Control Interface .................................................................. 9 GARD Interface ............................................................................ 9 REVISION HISTORY 10/2017—Rev. 0 to Rev. A Changed CP-16-3 to CP-16-21 .................................... Throughout Updated Outline Dimension ......................................................... 16 Changes to Ordering Guide .......................................................... 16 7/2005—Revision 0: Initial Version Rev. A | Page 2 of 16 Data Sheet ADL5317 SPECIFICATIONS VPHV = 78 V, VPLV = 5 V, VAPD = 60 V, IAPD = 5 µA, TA = 25°C, unless otherwise noted. Table 1. Parameter CURRENT MONITOR OUTPUT Current Gain from VAPD to IPDM Min Typ Max Unit 0.198 0.193 0.200 0.202 0.207 1.6 3.0 A/A Nonlinearity 0.25 0.5 2 2 10 Small-Signal Bandwidth Wideband Noise at IPDM Output Voltage Range APD BIAS CONTROL Specified VAPD Voltage Operating Range VAPD to GARD Offset Specified Input Current Range, IAPD VSET to VAPD Incremental Gain VSET Input Referred Offset, 1σ VSET Voltage Range Incremental Input Resistance at VSET Input Bias Current at VSET VAPD Settling Time, 5% VAPD Supply Tracking Offset (Below VPHV) OVERSTRESS PROTECTION VAPD Current Compliance Limit Thermal Shutdown Trip Point Thermal Hysteresis FALT Output Low Voltage POWER SUPPLIES Low Voltage Supply Quiescent Current High Voltage Supply Quiescent Current 1 % % kHz MHz nA 0 0 VPLV VAPD / 3 V V 6 VPHV − 35 VPHV − 35 VPHV − 1.5 VPHV − 1.5 75 100 0.3 20 V V V mV A V/V mV V MΩ µA µs 100 µs 3 5n 29.7 30 0.5 0.2 5m 30.3 5.5 1.90 2.0 2.15 V 14 18 140 20 21 0.8 mA °C °C V 6 0.84 80 2.9 4.5 V mA V mA mA 4 0.7 10 2.3 3.6 Tested 1.5 V < VSET < 2.5 V, guaranteed operation 0.2 V < VSET < 2.5 V. Rev. A | Page 3 of 16 Conditions IPDM (Pin 11) TA = 25°C −40°C < TA < +85°C 10 nA < IAPD < 1 mA 5 nA < IAPD < 5 mA IAPD = 5 nA, VPHV = 60 V, VAPD = 30 V IAPD = 5 µA, VPHV = 60 V, VAPD = 30 V IAPD = 5 µA, CGRD = 2 nF, BW = 10 MHz, VPHV = 40 V, VAPD = 30 V VAPD > 3 × VPLV VAPD < 3 × VPLV VSET (Pin 2), VAPD (Pin 8) 10 V < VPHV < 41 V 41 V < VPHV < 76.5 V 76.5 V < VPHV < 80 V Flows from VAPD pin 0.2 V < VSET < 2.5 V 1 VSET = 2.0 V VSET = 2.0 V, flows from VSET pin VSET = 1.6 V to 2.4 V, CGRD = 2 nF, VPHV = 60 V, VAPD = 30 V VSET = 2.4 V to 1.6 V, CGRD = 2 nF, VPHV = 60 V, VAPD = 30 V VSET = 5.0 V, 10 V < VPHV < 77 V FALT (Pin 1) VSET = 2.0 V, VAPD deviation of 500 mV Die temperature rising Fault condition, load current < 1 mA VPHV (Pin 4, Pin 5), VPLV (Pin 3) VPLV Independent of IAPD VPHV IAPD = 5 μA, VAPD = 60 V IAPD = 1 mA, VAPD = 60 V ADL5317 Data Sheet ABSOLUTE MAXIMUM RATINGS Table 2. Parameter Supply Voltage Input Current at VAPD Internal Power Dissipation θJA (Soldered Exposed Paddle) Maximum Junction Temperature Operating Temperature Range Storage Temperature Range Lead Temperature Range (Soldering 60 sec) Rating 80 V 25 mA 615 mW 65°C/W 125°C −40°C to +85°C −65°C to +150°C 300°C Stresses at or above those listed under Absolute Maximum Ratings may cause permanent damage to the product. This is a stress rating only; functional operation of the product at these or any other conditions above those indicated in the operational section of this specification is not implied. Operation beyond the maximum operating conditions for extended periods may affect product reliability. ESD CAUTION Rev. A | Page 4 of 16 Data Sheet ADL5317 13 COMM FALT 1 12 NC VSET 2 ADL5317 11 IPDM VPLV 3 TOP VIEW (Not to Scale) 10 NC 9 GARD VAPD 8 GARD 7 VCLH 6 VPHV 5 VPHV 4 NOTES 1. NC = NO CONNECT. 2. CONNECT THE EXPOSED PADDLE TO GROUND VIA A LOW IMPEDANCE PATH. 05456-002 14 COMM 16 COMM 15 COMM PIN CONFIGURATION AND FUNCTION DESCRIPTIONS Figure 2. Pin Configuration Table 3. Pin Function Descriptions Pin No. 1 2 3 4, 5 6 7, 9 Mnemonic FALT VSET VPLV VPHV VCLH GARD 8 10, 12 11 13 to 16 VAPD NC IPDM COMM EPAD Description Open Collector (Active Low) Logic Output. Indicates an overcurrent or overtemperature condition. APD Bias Voltage Setting Input. Short to VPLV for supply tracking mode. Low Voltage Supply, 4 V to 6 V. High Voltage Supply, 10 V to 80 V. Can be shorted to VPHV for extended linear operating range. No connect for supply tracking mode. Guard pin tracks VAPD pin and filters setpoint buffer noise (with External Capacitor CGRD to COMM). Optional shielding of VAPD trace. Capacitive load only. APD Bias Voltage Output and Current Input. Sources current only. Optional shielding of IPDM trace. No connection to die. Photodiode Monitor Current Output. Sources current only. Current at this node is equal to IAPD/5. Analog Ground. Exposed Pad. Connect the exposed paddle to ground via a low impedance path. Rev. A | Page 5 of 16 ADL5317 Data Sheet TYPICAL PERFORMANCE CHARACTERISTICS VPHV = 78 V, VPLV = 5 V, VAPD = 60 V, IAPD = 5 μA, TA = 25°C, unless otherwise noted. 1m 2.0 10m 1.5 1m 1.0 100 IPDM (Amperes) 10 0.5 1 0 100n –0.5 10n IPDM (Amperes) –40C +25C IPDM LINEARITY (%) +85C 100 2.0 VPHV = 78V, VAPD = 60V VPHV = 45V, VAPD = 32V VPHV = 10V, VAPD = 6V 1.5 1.0 VPHV = 78V, VAPD = 60V VPHV = 45V, VAPD = 32V 10 0.5 1 0 100n –0.5 VPHV = 10V, VAPD = 6V –1.0 10n –1.0 –1.5 1n –1.5 IPDM LINEARITY (%) 10m +85C +25C –40C 10n 100n 1 10 100 –2.0 10m 1m 100p 1n 05456-003 100p 1n IAPD (Amperes) 10n 100n 1 10 100 1m –2.0 10m 05456-004 1n IAPD (Amperes) Figure 6. IPDM Linearity for Multiple Values of VAPD and VPHV, Normalized to IAPD = 5 μA, VPHV =78 V, VAPD = 60 V Figure 3. IPDM Linearity for Multiple Temperatures, Normalized to IAPD = 5 μA, 25°C 31.0 80 VPHV = 45V, +85C VPHV = 45V, +25C VPHV = 45V, –40C 30.8 70 VPHV = 78V, +85C VPHV = 78V, +25C VPHV = 78V, –40C 30.6 60 VPHV = 78V, +85C VPHV = 78V, –40C 40 30 30.2 GAIN (V/V) VAPD (V) 30.4 VPHV = 78V, +25C 50 30.0 29.8 VPHV = 45V, –40C 29.6 20 VPHV = 45V, +85C VPHV = 45V, +25C 0 0.5 1.0 1.5 2.0 2.5 29.2 29.0 3.0 0.5 0 1.0 VSET (V) Figure 4. VAPD vs. VSET for Multiple Temperatures, VPHV = 78 V and VPHV = 45 V, IAPD = 5 μA 70 78/60 +25C 45/32 +25C 10/6 +25C 2.125 60 2.100 –40C 2.025 VAPD (V) VPHV – VAPD (V) +25C 2.050 2.000 1.975 2.0 2.5 3.0 Figure 7. Incremental Gain from VSET to VAPD vs. VSET for Multiple Temperatures, IAPD = 5 μA, VPHV = 78 V and 45 V 2.150 2.075 1.5 VSET (V) +85C 78/60 –40C 45/32 –40C 10/6 –40C 78/60 +85C 45/32 +85C 10/6 +85C VPHV = 78V, VAPD = 60V; +85C, +25C, –40C 0.030 0.020 50 0.010 40 0 30 –0.010 VPHV = 45V, VAPD = 32V; +85C, +25C, –40C 1.950 20 1.925 –0.020 VAPD VARIATION (V) 0 05456-007 05456-006 29.4 10 1.900 1.850 0 10 20 30 40 50 60 70 80 0 1n 90 VPHV (V) –0.030 VPHV = 10V, VAPD = 6V; +85C, +25C, –40C 10n 100n 1 10 IAPD (Amperes) Figure 5. VAPD Supply Tracking Offset vs. VPHV for Multiple Temperatures 100 1m –0.040 10m 05456-008 10 05456-005 1.875 Figure 8. VAPD vs. IAPD for Multiple Temperatures and Values of VPHV and VAPD Rev. A | Page 6 of 16 Data Sheet ADL5317 3 3 +85°C +25°C –40°C +85°C +25°C –40°C 2 IPDM LINEARITY (%) 1 0 –1 –2 0 –1 –2 05456-010 –3 1n 1 10n 100n 1µ 10µ 100µ 1m –3 1n 10m 05456-011 IPDM LINEARITY (%) 2 10n 100n 1µ IAPD (Amperes) Figure 9. IPDM Linearity for Multiple Temperatures and Devices VPHV =75 V, VAPD = 60 V, Normalized to IAPD = 5 µA, 25°C 10m 4.0 500µA 3.5 50µA 3.0 5µA 1pA 500nA (%) 2.0 50nA 100fA 2.5 1.5 0.5 05456-035 1fA 1k 1.0 5nA 10fA 10k 100k 1M 05456-036 (AMPERES rms/√Hz) 1m 4.5 5mA 0 1n 10M 10n 100n 10µ 100µ 1m Figure 13. Output Wideband Current Noise as a Percentage of IPDM vs. IPDM, CGARD = 2 nF, VPHV = 40 V, VAPD = 30 V, BW = 10 MHz Figure 10. Output Current Noise Density vs. Frequency for Multiple Values of IAPD, CGARD = 2 nF, VPHV = 40 V, VAPD = 30 V 10 30 +3 SIGMA 0 –10 –3 SIGMA –40 –40 –30 –20 –10 05456-042 –30 0 10 20 30 40 50 60 70 80 0 5µA –5 5nA –15 –20 50nA –25 –30 10 90 TEMPERATURE (°C) 500nA –10 05456-043 NORMALIZED RESPONSE (dB) AVERAGE –20 50µA 5 20 10 1µ IPDM (Amperes) FREQUENCY (Hz) VAPD DRIFT (mV) 100µ Figure 12. IPDM Linearity for Multiple Temperatures and Devices VPHV = 45 V, VAPD = 32 V, Normalized to IAPD = 5 µA, 25°C 100pA 10pA 10µ IAPD (Amperes) 100 1k 10k 100k 1M 10M 100M FREQUENCY (Hz) Figure 14. Small Signal AC Response from IAPD to IPDM, for IAPD in Decades from 5 nA to 50 μA, VPHV = 60 V, VAPD = 30 V Figure 11. Temperature Drift of VAPD, 3 σ to Either Side of Mean Rev. A | Page 7 of 16 ADL5317 Data Sheet 75 10m 1m 70 100µA TO 1mA: T-RISE =