ADL5331-EVALZ

1 MHz to 1.2 GHz VGA with 30 dB Gain Control Range ADL5331 Data Sheet FUNCTIONAL BLOCK DIAGRAM GAIN ENBL VPS2 VPS2 VPS1 COM1 INHI INLO COM1 COM2 Transmit and receive power control at RF and IF CATV distribution NC OUTPUT OPHI (TZ) STAGE OPLO RFOUT COM2 BIAS AND VREF VPS2 VPS1 APPLICATIONS VPS2 VPS2 INPUT GM STAGE RFIN VPS2 ADL5331 GAIN CONTROL CONTINUOUSLY VARIABLE ATTENUATOR Voltage-controlled amplifier/attenuator Operating frequency: 1 MHz to 1.2 GHz Optimized for controlling output power High linearity: OIP3 47 dBm @ 100 MHz Output noise floor: −149 dBm/Hz @ maximum gain Input impedance: 50 Ω Output impedance: 20 Ω Wide gain-control range: 30 dB Linear-in-dB gain control function: 40 mV/dB Single-supply voltage: 4.75 V to 5.25 V IPBS OPBS COM2 COM2 COM2 07593-001 FEATURES Figure 1. GENERAL DESCRIPTION The ADL5331 is a high performance, voltage-controlled variable gain amplifier/attenuator for use in applications with frequencies up to 1.2 GHz. The balanced structure of the signal path maximizes signal swing, eliminates common-mode noise and minimizes distortion while it also reduces the risk of spurious feed-forward at low gains and high frequencies caused by parasitic coupling. The 50 Ω differential input system converts the applied differential voltage at INHI and INLO to a pair of differential currents with high linearity and good common-mode rejection. The signal currents are then applied to a proprietary voltagecontrolled attenuator providing precise definition of the overall gain under the control of the linear-in-dB interface. The GAIN pin accepts a voltage from 0 V at a minimum gain to 1.4 V at a full gain with a 40 mV/dB scaling factor over most of the range. Rev. A The output of the high accuracy wideband attenuator is applied to a differential transimpedance output stage. The output stage provides a differential output at OPHI and OPLO, which must be pulled up to the supply with RF chokes or a center-tapped balun. The ADL5331 consumes 240 mA of current including the output pins and operates off a single supply ranging from 4.75 V to 5.25 V. A power-down function is provided by applying a logic low input on the ENBL pin. The current consumption in power-down mode is 250 μA. The ADL5331 is fabricated on an Analog Devices, Inc., proprietary high performance, complementary bipolar IC process. The ADL5331 is available in a 24-lead (4 mm × 4 mm), Pb-free LFCSP package and is specified for operation from ambient temperatures of −40°C to +85°C. An evaluation board is also available. Document Feedback Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective owners. One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. Tel: 781.329.4700 ©2009–2017 Analog Devices, Inc. All rights reserved. Technical Support www.analog.com ADL5331 Data Sheet TABLE OF CONTENTS Features .............................................................................................. 1 Theory of Operation .........................................................................8 Applications ....................................................................................... 1 Applications Information .................................................................9 Functional Block Diagram .............................................................. 1 Basic Connections .........................................................................9 General Description ......................................................................... 1 Gain Control Input..................................................................... 10 Revision History ............................................................................... 2 CMTS Transmit Application .................................................... 12 Specifications..................................................................................... 3 Interfacing to an IQ Modulator ................................................ 13 Absolute Maximum Ratings ............................................................ 4 Soldering Information ............................................................... 13 ESD Caution .................................................................................. 4 Evaluation Board Schematic ......................................................... 14 Pin Configuration and Function Descriptions ............................. 5 Outline Dimensions ....................................................................... 15 Typical Performance Characteristics ............................................. 6 Ordering Guide .......................................................................... 15 REVISION HISTORY 10/2017—Rev. 0 to Rev. A Changed CP-24-2 to CP-24-14 .................................... Throughout Change to General Description ...................................................... 1 Change to Figure 2 and Table 3 ...................................................... 5 Updated Outline Dimensions ....................................................... 15 Changes to Ordering Guide .......................................................... 15 5/2009—Revision 0: Initial Version Rev. A | Page 2 of 15 Data Sheet ADL5331 SPECIFICATIONS VS = 5 V; TA = 25°C; M/A-COM ETC1-1-13 1:1 balun at input and output for single-ended 50 Ω match. Table 1. Parameter GENERAL Usable Frequency Range Nominal Input Impedance Nominal Output Impedance FREQUENCY INPUT = 100 MHz Gain Control Span Minimum Gain Maximum Gain Gain Flatness vs. Frequency Gain Control Slope Gain Control Intercept Output IP3 Output Noise Floor Noise Figure FREQUENCY INPUT = 400 MHz Gain Control Span Minimum Gain Maximum Gain Gain Flatness vs. Frequency Gain Control Slope Gain Control Intercept Output IP3 Output Noise Floor Noise Figure FREQUENCY INPUT = 900 MHz Gain Control Span Minimum Gain Maximum Gain Gain Flatness vs. Frequency Gain Control Slope Gain Control Intercept Third-Order Harmonic Output IP3 Output Noise Floor Noise Figure GAIN CONTROL INPUT Gain Control Voltage Range 1 Incremental Input Resistance Response Time POWER SUPPLIES Voltage Current, Nominal Active ENBL, Logic 1, Device Enabled ENBL, Logic 0, Device Disabled Current, Disabled 1 Conditions Min Typ Max Unit 1.2 50 20 GHz Ω Ω 30 −14 17 0.09 40 700 47 −149 9 dB dB dB dB mV/dB mV dBm dBm/Hz dB 30 −15 15 0.09 39.5 730 39 −150 9 dB dB dB dB mV/dB mV dBm dBm/Hz dB 35 −18 15 0.09 37 800 −75 32 −150 9 dB dB dB dB mV/dB mV dBc dBm dBm/Hz dB 0.001 ±3 dB gain law conformance VGAIN = 0.1 V VGAIN = 1.4 V ±30 MHz around center frequency, VGAIN = 1.0 V (differential output) Gain = 0 dB, gain = slope (VGAIN − intercept) VGAIN = 1.4 V, input −13 dBm per tone, two tone measurement VGAIN = 1.4 V VGAIN = 1.4 V ±3 dB gain law conformance VGAIN = 0.1 V VGAIN = 1.4 V ±30 MHz around center frequency, VGAIN = 1.0 V (differential output) Gain = 0 dB, gain = slope (VGAIN − intercept) VGAIN = 1.4 V, input −13 dBm per tone, two tone measurement 20 MHz carrier offset, VGAIN = 1.4 V VGAIN = 1.4 V ±3 dB gain law conformance VGAIN = 0.1 V VGAIN = 1.4 V ±30 MHz around center frequency, VGAIN = 1.0 V (differential output) Gain = 0 dB, gain = slope (VGAIN − intercept) −8 dBm output at 900 MHz fundamental VGAIN = 1.4 V, input −13 dBm per tone, two tone measurement 20 MHz carrier offset, VGAIN = 1.4 V VGAIN = 1.4 V Pin GAIN 0.1 Pin GAIN to Pin COM1 Full scale, to within 1 dB of final gain 3 dB gain step, POUT to within 1 dB of final gain Pin VPS1, Pin VPS2, Pin COM1, Pin COM2, Pin ENBL 1.4 V MΩ ns ns 5.25 V mA V V µA 1 380 20 4.75 5 240 2.3 0.8 ENBL = Logic 0 250 Minimum gain voltage varies with frequency (see Figure 3, Figure 4, and Figure 5). Rev. A | Page 3 of 15 ADL5331 Data Sheet ABSOLUTE MAXIMUM RATINGS Table 2. Parameter Supply Voltage VPS1 Supply Voltage VPS2 VPS2 to VPS1 RF Input Power OPHI, OPLO ENBL GAIN Internal Power Dissipation θJA (with Pad Soldered to Board) Maximum Junction Temperature Operating Temperature Range Storage Temperature Range Rating 5.5 V 5.5 V ±200 mV 5 dBm at 50 Ω 5.5 V VPS1 VPS1 1.2 W 56.1°C/W 150°C −40°C to +85°C −65°C to +150°C Stresses at or above those listed under Absolute Maximum Ratings may cause permanent damage to the product. This is a stress rating only; functional operation of the product at these or any other conditions above those indicated in the operational section of this specification is not implied. Operation beyond the maximum operating conditions for extended periods may affect product reliability. ESD CAUTION Rev. A | Page 4 of 15 Data Sheet ADL5331 20 VPS2 19 VPS2 22 VPS2 21 VPS2 24 GAIN 23 ENBL PIN CONFIGURATION AND FUNCTION DESCRIPTIONS VPS1 1 18 VPS2 COM1 2 17 COM2 COM1 5 ADL5331 16 OPHI TOP VIEW (Not to Scale) 15 OPLO 14 COM2 VPS1 6 COM2 12 COM2 11 OPBS 9 COM2 10 NC 7 IPBS 8 13 VPS2 NOTES 1. NC = NO CONNECT. 2. EXPOSED PAD. THE EXPOSED PAD MUST BE CONNECTED TO GROUND VIA A LOW IMPEDANCE PATH, BOTH THERMALLY AND ELECTRICALLY. 07593-002 INHI 3 INLO 4 Figure 2. Pin Configuration Table 3. Pin Function Descriptions Pin No. 1, 6 2, 5 3, 4 7 8 9 10 to 12, 14, 17 13, 18 to 22 15, 16 23 24 Mnemonic VPS1 COM1 INHI, INLO NC IPBS OPBS COM2 VPS2 OPLO, OPHI ENBL GAIN EPAD Description Positive Supply. Nominally equal to 5 V. Common for the Input Stage. Differential Inputs, AC-Coupled. No Connect. Input Bias. Normally ac-coupled to VPS1. A 10 nF capacitor is recommended. Output Bias. Internally compensated, do not connect externally. Common for the Output Stage. Positive Supply. Nominally equal to 5 V. Differential Outputs. Bias to VPOS with RF chokes. Device Enable. Apply logic high for normal operation. Gain Control Voltage Input. Nominal range is 0 V to 1.4 V. Exposed Pad. Exposed pad must be connected to via a low impedance path, both thermally and electrically. Rev. A | Page 5 of 15 ADL5331 Data Sheet TYPICAL PERFORMANCE CHARACTERISTICS VS = 5 V; TA = 25°C; M/A-COM ETC1-1-13 1:1 balun at input and output for single-ended 50 Ω match. 2 5 1 0 0 –5 –1 –10 –2 –15 –3 0.5 0.7 0.9 VGAIN (V) 1.1 1.3 –4 15 10 5 0 0.1 4 15 3 10 2 5 1 0 0 –5 –1 –10 –2 –15 –3 15 –4 10 0.5 0.5 0.7 0.9 VGAIN (V) 1.1 1.3 50 45 OIP3 (dBm) ERROR (dB) 40 35 30 25 20 Figure 4. Gain and Gain Law Conformance vs. VGAIN over Temperature at 400 MHz 45 15 3 40 10 2 5 1 0 0 –5 –1 –10 –2 –15 –3 15 –4 10 0.5 0.5 0.7 0.9 VGAIN (V) 1.1 1.3 0.7 0.8 0.9 1.0 VGAIN (V) 1.1 1.2 1.3 1.4 1.3 1.4 OIP3 (dBm) ERROR (dB) 35 30 25 20 07593-005 GAIN (dB) 4 0.3 0.6 Figure 7. Output IP3 vs. VGAIN at 100 MHz 20 –20 0.1 1k 100 55 07593-004 GAIN (dB) 20 0.3 10 FREQUENCY (MHz) Figure 6. Gain Slope vs. Frequency, RFIN = −20 dBm @ 500 MHz, VGAIN = 1 V Figure 3. Gain and Gain Law Conformance vs. VGAIN over Temperature at 100 MHz –20 0.1 1 07593-007 0.3 20 Figure 5. Gain and Gain Law Conformance vs. VGAIN over Temperature at 900 MHz 0.6 0.7 0.8 0.9 1.0 VGAIN (V) 1.1 1.2 Figure 8. Output IP3 vs. VGAIN at 400 MHz Rev. A | Page 6 of 15 07593-008 –20 0.1 25 07593-006 10 SLOPE (mV/dB) 3 ERROR (dB) 15 30 07593-003 4 GAIN (dB) 20 Data Sheet ADL5331 40 25 OIP3 (dBm) 30 25 20 15 20 VGAIN = 1.4V 15 VGAIN = 1.2V 10 VGAIN = 1.0V 5 VGAIN = 0.8V 0 VGAIN = 0.6V –5 VGAIN = 0.4V –10 VGAIN = 0.2V –15 –20 0.6 0.7 0.8 0.9 1.0 VGAIN (V) 1.1 1.2 1.3 1.4 VGAIN = 0V –25 50 07593-009 10 0.5 Figure 9. Output IP3 vs. VGAIN at 900 MHz 07593-012 GAIN (dB), 50Ω DIFFERENTIAL SOURCE AND LOAD 35 1000 500 FREQUENCY (MHz) Figure 12. Gain vs. Frequency (Differential 100 Ω Output Load) –148 100MHz 400MHz 900MHz MEAN(C1) 1.358V 2 AMPL(C1) 3.36V CH3 200mV Ω CH2 500mV 07593-010 AMPL(C2) 900mV M 2.0µs 25.0MS/s 40.0ns/pt A CH1 150mV Figure 10. Step Response of Gain Control Input 25 VGAIN = 1.2V 10 5 VGAIN = 1.0V 0 VGAIN = 0.8V –5 VGAIN = 0.6V –10 VGAIN = 0.4V –15 VGAIN = 0.2V –20 –25 –30 50 VGAIN = 0V 500 1000 FREQUENCY (MHz) 07593-011 GAIN (dB), 50Ω DIFFERENTIAL SOURCE AND LOAD VGAIN = 1.4V 15 –154 –156 –158 –160 0.1 0.3 0.5 0.7 0.9 VGAIN (V) 1.1 Figure 13. Output Noise Spectral Density vs. VGAIN 30 20 –152 Figure 11. Gain vs. Frequency (Differential 50 Ω Output Load) Rev. A | Page 7 of 15 1.3 07593-028 t1: 2.24µs t2: 1.2µs Δt: –1.04µs 1/Δt: –961.5kHz NOISE (dBm/Hz) –150 ADL5331 Data Sheet THEORY OF OPERATION The ADL5331 is a high performance, voltage-controlled variable gain amplifier/attenuator for use in applications with frequencies up to 1.2 GHz. This device is intended to serve as an output variable gain amplifier (OVGA) for applications where a reasonably constant input level is available and the output level adjusts over a wide range. One aspect of an OVGA is that the output metrics, OIP3 and OP1dB, decrease with decreasing gain. The signal path is fully differential throughout the device to provide the usual benefits of differential signaling, including reduced radiation, reduced parasitic feedthrough, and reduced susceptibility to common-mode interference with other circuits. Figure 14 provides a simplified schematic of the ADL5331. TRANSIMPEDANCE AMPLIFIER INHI INLO The output of the ladder attenuator is passed into a fixed-gain transimpedance amplifier (TZA) to provide gain and to buffer the ladder terminating impedance from load variations. The TZA uses feedback to improve linearity and to provide controlled 50 Ω differential output impedance. The quiescent current of the output amplifier is adaptive; it is controlled by an output level detector, which biases the output stage for signal levels above a threshold. The outputs of the ADL5331 require external dc bias to the positive supply voltage. This bias is typically supplied through external inductors. The outputs are best taken differentially to avoid any common-mode noise that is present, but, if necessary, can be taken single-ended from either output. The output impedance is 20 Ω differential and can drive a range of impedances from 75 Ω. Back series terminations can be used to pad the output impedance to a desired level. OPHI OPLO Gm STAGE If only a single output is used, it is still necessary to provide a bias to the unused output pin and it is advisable to arrange a reasonably equivalent ac load on the unused output. Differential output can be taken via a 1:1 balun into a 50 Ω environment. In virtually all cases, it is necessary to use dc blocking in the output signal path. 07593-016 GAIN CONTROL Linear-in-dB gain control is accomplished by the application of a voltage in the range of 0 V dc to 1.4 V dc to the gain control pin, with maximum gain occurring at the highest voltage. Figure 14. Simplified Schematic A controlled input impedance of 50 Ω is achieved through a combination of passive and active (feedback-derived) termination techniques in an input Gm stage. Note that the inputs of the Gm stage are internally biased to a dc level and dc blocking capacitors are generally needed on the inputs to avoid upsetting the operation of the device. The currents from the Gm stage are then injected into a balanced ladder attenuator at a deliberately diffused location along the ladder, wherein the location of the centroid of the injection region is dependent on the applied gain control voltage. The steering of the current injection into the ladder is accomplished by proprietary means to achieve linear-in-dB gain control and low distortion. At high gain settings, the noise floor is set by the input stage, in which case the noise figure (NF) of the device is essentially independent of the gain setting. Below a certain gain setting, however, the input stage noise that reaches the output of the attenuator falls below the input-equivalent noise of the output stage. In such a case, the output noise is dominated by the output stage itself; therefore, the overall NF of the device gets worse on a dB-per-dB basis as the gain is lowered, because the gain is reduced below the critical value. Figure 7 through Figure 9 provide details of this behavior. Rev. A | Page 8 of 15 Data Sheet ADL5331 APPLICATIONS INFORMATION VPOS VPOS INHI VPS2 VPS2 VPS2 VPS2 ADL5331 INLO VPS2 C5 10nF COM2 OPHI COM2 VPS1 VPS2 C10 10nF RFOUT OPLO COM1 C6 10nF C7 100pF C8 0.1µF C9 10nF 07593-017 C11 100pF COM1 L1 0.68µH L2 0.68µH COM2 C12 0.1µF C4 100pF COM2 VPOS C14 10nF C2 100pF OPBS RFIN VPS1 C3 0.1µF COM2 C13 10nF GAIN C16 100pF IPBS C15 0.1µF NC VPOS ENBL GAIN C1 0.1µF VPOS Figure 15. Basic Connections Figure 15 shows the basic connections for operating the ADL5331. There are two positive supplies, VPS1 and VPS2, which must be connected to the same potential. Connect COM1 and COM2 (common pins) to a low impedance ground plane. Apply a power supply voltage between 4.75 V and 5.25 V to VPS1 and VPS2. Connect decoupling capacitors with 100 pF and 0.1 µF power supplies close to each power supply pin. The VPS2 pins (Pins 13 and Pin 18 through Pin 22) can share a pair of decoupling capacitors because of their proximity to each other. The outputs of the ADL5331, OPHI and OPLO, are open collectors that need to be pulled up to the positive supply with 120 nH RF chokes. The ac-coupling capacitors and the RF chokes are the principle limitations for operation at low frequencies. For example, to operate down to 1 MHz, use 0.1 µF ac coupling capacitors and 1.5 µH RF chokes. Note that in some circumstances, the use of substantially larger inductor values results in oscillations. Because the differential outputs are biased to the positive supply, ac-coupling capacitors (preferably 100 pF) are needed between the ADL5331 outputs and the next stage in the system. Similarly, the INHI and INLO input pins are at bias voltages of about 3.3 V above ground. The nominal input and output impedance looking into each individual RF input/output pin is 25 Ω. Consequently, the differential impedance is 50 Ω. To enable the ADL5331, the ENBL pin must be pulled high. Taking ENBL low puts the ADL5331 in sleep mode, reducing current consumption to 250 µA at an ambient temperature. The voltage on ENBL must be greater than 1.7 V to enable the device. When enabled, the device draws 100 mA at low gain to 215 mA at maximum gain. The ADL5331 is primarily designed for differential signals; however, there are several configurations that can be implemented to interface the ADL5331 to single-ended applications. Figure 16 and Figure 17 show options for differential-to-singleended interfaces. Both configurations use ac-coupling capacitors at the input/output and RF chokes at the output. +5V 120nH 120nH ADL5331 RF VGA 10nF RFIN 10nF ETC1-1-13 10nF INHI OPHI INLO OPLO RFOUT 10nF ETC1-1-13 07593-018 BASIC CONNECTIONS Figure 16. Differential Operation with Balun Transformers Figure 16 illustrates differential balance at the input and output using a transformer balun. Input and output baluns are recommended for optimal performance. Much of the characterization for the ADL5331 was completed using 1:1 baluns at the input and output for a single-ended 50 Ω match. Operation using M/A-COM ETC1-1-13 transmission line transformer baluns is recommended for a broadband interface; however, narrowband baluns can be used for applications requiring lower insertion loss over smaller bandwidths. Rev. A | Page 9 of 15 ADL5331 Data Sheet 5V Note that the ADL5331, because of its positive gain slope, in an AGC application requires a detector with a negative VOUT/ RFIN slope. As an example, the AD8319 in the example in Figure 19 has a negative slope. The AD8362 rms detector, however, has a positive slope. Extra circuitry is necessary to compensate for this. 120nH 120nH RFIN 10nF ADL5331 RF VGA INHI OPHI INLO OPLO 10nF RFOUT 10nF ETC1-1-13 07593-019 10nF Figure 17. Single-Ended Drive with Balanced Output The device can be driven single-ended with similar performance, as shown in Figure 17. The single-ended input interface can be implemented by driving one of the input terminals and terminating the unused input to ground. To achieve the optimal performance, the output must remain balanced. In the case of Figure 17, a transformer balun is used at the output. GAIN CONTROL INPUT When the VGA is enabled, the voltage applied to the GAIN pin sets the gain. The input impedance of the GAIN pin is 1 MΩ. The gain control voltage range is between 0.1 V and 1.4 V, which corresponds to a typical gain range between −15 dB and +15 dB. The 1 dB input compression point remains constant at 3 dBm through the majority of the gain control range, as shown in Figure 7 through Figure 9. The output compression point increases decibel for decibel with increasing gain setting. The noise floor is constant up to VGAIN = 1 V where it begins to rise. To operate the ADL5331 in an AGC loop, a sample of the output RF must be fed back to the detector (typically using a directional coupler and additional attenuation). A setpoint voltage is applied to the VSET input of the detector while VOUT is connected to the GAIN pin of the ADL5331. Based on the detector’s defined linear-in-dB relationship between VOUT and the RFIN signal, the detector adjusts the voltage on the GAIN pin (the detector’s VOUT pin is an error amplifier output) until the level at the RF input corresponds to the applied setpoint voltage. The VGAIN setting settles to a value that results in the correct balance between the input signal level at the detector and the setpoint voltage. The detector’s error amplifier uses CLPF, a ground-referenced capacitor pin, to integrate the error signal (in the form of a current). A capacitor must be connected to CLPF to set the loop bandwidth and to ensure loop stability. 5V 5V VPOS RFIN INHI INLO COMM OPHI ADL5331 OPLO The bandwidth on the gain control pin is approximately 3 MHz. Figure 10 shows the response time of a pulse on the VGAIN pin. GAIN Although the ADL5331 provides accurate gain control, precise regulation of output power can be achieved with an automatic gain control (AGC) loop. Figure 18 shows the ADL5331 in an AGC loop. The addition of a log amp or a TruPwr™ detector (such as the AD8362) allows the AGC to have improved temperature stability over a wide output power control range. VOUT ATTENUATOR LOG AMP OR TruPwr DETECTOR VSET RFIN CLPF 07593-020 DAC Figure 18. ADL5331 in AGC Loop Rev. A | Page 10 of 15 DIRECTIONAL COUPLER Data Sheet ADL5331 +5V +5V RFIN SIGNAL VPOS 10nF INHI 10nF INLO 120nH COMM RFOUT SIGNAL 120nH 10nF OPHI ADL5331 10nF OPLO 10dB DIRECTIONAL COUPLER GAIN 390Ω 10dB ATTENUATOR +5V 1kΩ DAC SETPOINT VOLTAGE VOUT VPOS VSET INHI 1nF AD8319 LOG AMP INLO 1nF COMM 07593-021 220pF CLPF A coupler/attenuation of 21 dB is used to match the desired maximum output power from the VGA to the top end of the linear operating range of the AD8319 (approximately −5 dBm at 900 MHz). Figure 20 shows the transfer function of the output power vs. the VSET voltage over temperature for a 100 MHz sine wave with an input power of −1.5 dBm. Note that the power control of the AD8319 has a negative sense. Decreasing VSET, which corresponds to demanding a higher signal from the ADL5331, increases gain. This AGC loop is capable of controlling signals of ~30 dB, which is the gain range limitation on the ADL5331. Across the top 25 dB range of output power, the linear conformance error is within ±0.5 dB over temperature. Rev. A | Page 11 of 15 20 3.00 15 2.25 10 1.50 5 0.75 +85°C 0 0 +25°C –5 –0.75 –40°C –10 –1.50 –15 –2.25 –20 0.6 0.7 0.8 0.9 1.0 1.1 1.2 VSET (V) 1.3 1.4 1.5 –3.00 1.6 Figure 20. ADL5331 Output Power vs. AD8319 Setpoint Voltage, PIN = 0 dBm at 100 MHz 07593-022 The gain of the ADL5331 is controlled by the output pin of the AD8319. The voltage, VOUT, has a range of 0 V to near VPOS. To avoid overdrive recovery issues, the AD8319 output voltage can be scaled down using a resistive divider to interface with the 0.1 V to 1.4 V gain control range of the ADL5331. OUTPUT POWER (dBm) Figure 19 shows the basic connections for operating the AD8319 log detector in an automatic gain control (AGC) loop with the ADL5331. ERROR FROM STRAIGHT LINE AT 25°C (dB) Figure 19. AD8319 Operating in Controller Mode to Provide Automatic Gain Control Functionality in Combination with the ADL5331 ADL5331 Data Sheet For the AGC loop to remain in equilibrium, the AD8319 must track the envelope of the output signal of the ADL5331 and provide the necessary voltage levels to the gain control input of the ADL5331. Figure 21 shows an oscilloscope of the AGC loop depicted in Figure 19. A 100 MHz sine wave with 50% AM modulation is applied to the ADL5331. The output signal from the VGA is a constant envelope sine wave with amplitude corresponding to a setpoint voltage at the AD8319 of 1.3 V. The gain control response of the AD8319 to the changing input envelope is also shown in Figure 21. CURS1 POS 4.48µs CURS2 POS 2.4µs t1: 4.48µs t2: 2.4µs ∆t: –2.08µs 1/∆t: –480.8kHz 2 MEAN(C1) 440.3mV AMPL(C1) 3.36V T AM MODULATED INPUT CH2 500mV T CH3 200mV Ω M 4.0µs 12.5MS/s 80.0ns/pt A CH1 150mV 07593-024 AMPL(C2) 900mV Figure 22. Oscilloscope Showing theResponse Time of the AGC Loop 1 Response time and the amount of signal integration are controlled by CLPF. This functionality is analogous to the feedback capacitor around an integrating amplifier. While it is possible to use large capacitors for CLPF, in most applications, values under 1 nF provide sufficient filtering. AD8319 OUTPUT 2 More information on the use of AD8319 in an AGC application can be found in the AD8319 data sheet. CMTS TRANSMIT APPLICATION 3 Interfacing to AD9789 Because of its broadband operating range, the ADL5331 VGA can also be used in direct-launch cable modem termination systems (CMTS) applications in the 50 MHz to 860 MHz cable band. The ADL5331 makes an excellent choice as a post-DAC VGA in a CMTS application when used with the Analog Devices AD9789 wideband DAC. The AD9789 also contains digital signal processing specifically designed to process DOCSIS type CMTS signals. A typical AD9789-to-ADL5331 interface is shown in Figure 23. M2.00ms A CH4 T 0.00000s 1.80V Figure 21. Oscilloscope Showing an AM Modulated Input Signal and the Response from the AD8319 Figure 22 shows the response of the AGC RF output to a pulse on VSET. As VSET decreases from 1.5 V to 0.4 V, the AGC loop responds with an RF burst. In this configuration, the input signal to the ADL5331 is a 1 GHz sine wave at a power level of −15 dBm. AD9789 DAC SERIES 5V TERMINATION VGA 16mA 70Ω 25Ω 50Ω 20Ω 16mA 55Ω Figure 23. Block Diagram of AD9789 interface to ADL5331 in a DOCSIS Type Application Rev. A | Page 12 of 15 07593-025 CH1 250mV Ω CH2 200mV CH3 250mV Ω 07593-023 ADL5331 OUTPUT Data Sheet ADL5331 quadrature modulators. These modulators can provide outputs from 500 MHz to 4 GHz. INTERFACING TO AN IQ MODULATOR The basic connections for interfacing the ADL5331 with the ADL5385 are shown in Figure 24. The ADL5385 is an RF quadrature modulator with an output frequency range of 50 MHz to 2.2 GHz. It offers excellent phase accuracy and amplitude balance, enabling high performance direct RF modulation for communication systems. SOLDERING INFORMATION On the underside of the chip scale package, there is an exposed compressed paddle. This paddle is internally connected to the chip’s ground. Solder the paddle to the low impedance ground plane on the printed circuit board to ensure specified electrical performance and to provide thermal relief. It is also recommended that the ground planes on all layers under the paddle be stitched together with vias to reduce thermal impedance. The output of the ADL5385 is designed to drive 50 Ω loads and easily interfaces with the ADL5331. The input to the ADL5331 can be driven single-ended, as shown in Figure 17. Similar configurations are possible with the ADL537x family of 5V 5V 68µH 5V 68µH DAC COMM VPOS IBBN ADL5385 VOUT IQ MOD QBBP DAC QBBN 10nF INHI INLO COMM ADL5331 RF VGA 10nF OPHI RF OUTPUT OPLO 10nF 10nF ETC1-1-13 100pF LO 100pF GAIN CONTROL 07593-030 DIFFERENTIAL I/Q BASEBAND INPUTS VPOS IBBP Figure 24. ADL5385 Quadrature Modulator and ADL5331 Interface Rev. A | Page 13 of 15 ADL5331 Data Sheet EVALUATION BOARD SCHEMATIC VPS1A 2 R1A 0Ω GAINA R3A 1kΩ 4 C11A AGNDA 10nF T1A 2 1 3 4 3 AGNDA R4A 0Ω C3A 0.1µF C12A 10nF AGNDA 5 6 C4A 100pF VS1A VPS2A VPS2 20 19 VPS2 COM2 COM1 INHI OPHI Z1A ADL5331 INLO OPLO COM1 COM2 VPS1 VPS2 7 8 9 VS1A IPBSA 21 VPS2 ENBL 22 C15A 10nF VPS1A 2 VPS1 23 COM2 5 1 24 OPBS INHIA RSA 0Ω AGNDA GAIN VPS1A C7A 100pF VPS1A 10 11 EPAD 18 17 L1A 0.68µH C11A C12A 15 AGNDA 13 25 12 1 P1A 2 P1A 3 R14A 0Ω P1A 4 P1A 5 IPBSA P1A 6 OPBSA P1A 7 VREFA P1A 8 AGNDA 16 14 P1A GAINA VS2A IPBS AGNDA C8A 0.1µF ENBLA AGNDA NC AGNDA AGNDA VPS2A R2A 0Ω C1A 100pF R16A 0Ω TESTLOOP BLACK AGNDA AGNDA GNA C17A 1000pF VPS1A VPS2A C2 0.1µF TESTLOOP RED AGNDA L2A 0.68µH 3 1 T2A 4 2 AGNDA R6A 0Ω C10A 100pF 5 OPHIA R12A 0Ω C13A 100pF VPS2A C14A 0.1µF VPS2A C9A 0.1µF AGNDA C16A 10nF VS2A R9A 0Ω 07593-026 ENBLA VPS2 1 GNDA VPS2A TESTLOOP BLUE AGNDA COM2 ENB_A SW1A VPS2 3 COM2 VPS1A R17A 10kΩ OPBSA Figure 25. ADL5331 Single-Ended Input/Output Evaluation Board Rev. A | Page 14 of 15 Data Sheet ADL5331 OUTLINE DIMENSIONS DETAIL A (JEDEC 95) PIN 1 INDICATOR 0.30 0.25 0.20 1 0.50 BSC 2.44 2.30 SQ 2.16 EXPOSED PAD 13 TOP VIEW 0.80 0.75 0.70 0.50 0.40 0.30 6 12 BOTTOM VIEW 0.05 MAX 0.02 NOM COPLANARITY 0.08 0.203 REF PKG-003994/5111 SEATING PLANE PIN 1 INDIC ATOR AREA OPTIONS (SEE DETAIL A) 24 19 18 7 0.20 MIN FOR PROPER CONNECTION OF THE EXPOSED PAD, REFER TO THE PIN CONFIGURATION AND FUNCTION DESCRIPTIONS SECTION OF THIS DATA SHEET. COMPLIANT TO JEDEC STANDARDS MO-220-WGGD-8 03-09-2017-B 4.10 4.00 SQ 3.90 Figure 26. 24-Lead Lead Frame Chip Scale Package [LFCSP] 4 mm × 4 mm Body and 0.75 mm Package Height (CP-24-14) Dimensions shown in millimeters ORDERING GUIDE Model 1 ADL5331ACPZ-R7 ADL5331-EVALZ 1 Temperature Range −40°C to +85°C Package Description 24-Lead Lead Frame Chip Scale Package [LFCSP] ADL5331 Evaluation Board Z = RoHS Compliant Part. ©2009–2017 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. D07593-0-10/17(A) Rev. A | Page 15 of 15 Package Option CP-24-14 Ordering Quantity 1,500