ADL5360XCPZ-WP

Preliminary Technical Data FEATURES RF Frequency 700MHz to 1000MHz IF Frequency 50MHZ to 350MHz Power Conversion Gain of 8.5dB SSB Noise Figure of 9.5dB SSB NF with +10dBm blocker of 16.5dB Input IP3 of 26dBm Input P1dB of 10 dBm Typical LO Drive of 0 dBm Single-ended, 50Ω RF and LO Input Ports High Isolation SPDT LO Input Switch Single Supply Operation: 3.3 to 5 V Exposed Paddle 6 x 6 mm, 36 Lead LFCSP Package Dual 900MHz Balanced Mixer with Low Side LO Buffer, IF Amp, and RF Balun ADL5360 APPLICATIONS Cellular Base Station Receivers Main and Diversity Receiver Designs Radio Link Downconverters GENERAL DESCRIPTION The ADL5360 utilizes two highly linear doubly balanced passive mixer cores along with integrated RF and LO balancing circuitry to enable single-ended operation. The ADL5360 incorporates two RF baluns allowing for optimal main and diversity mixer performance over a 700 to 1000 MHz RF input frequency range using low-side LO injection. The balanced passive mixer arrangement provides good LO to RF leakage, typically better than -25dBm, and excellent intermodulation performance. The balanced mixer cores also provide extremely high input linearity allowing the device to be used in demanding cellular applications where in-band blocking signals may otherwise result in the degradation of dynamic performance. High linearity IF buffer amps follow the passive mixer cores, to yield a typical power conversion gain of 9.5dB. (For a higher IIP3 version of the dual mixer without the IF amplifiers, please contact the factory). The ADL5360 provides two switched LO paths that can be utilized in TDD applications where it is desirable to rapidly alternate between two local oscillators. LO current can be externally set using a resistor to minimize DC current REV. PrA Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective companies. Figure 1. Functional Block Diagram commensurate with the desired level of performance. An additional 3V logic pin is provided to power down (20dB over a limited bandwidth 700 Differential impedance, f = 200 MHz 40 Externally generated 4.75 -6 Tunable to >20dB over a limited bandwidth VS 0 12 50 200 1000 MHz Ω 450 5.25 +10 MHz V dBm dB Ω MHz Input Impedance LO Frequency Range DYNAMIC PERFORMANCE Power Conversion Gain Voltage Conversion Gain SSB Noise Figure SSB Noise Figure Under-Blocking Input Third Order Intercept Input Second Order Intercept Input 1 dB Compression Point LO to IF Output Leakage LO to RF Input Leakage RF to IF Output Isolation RFI1 to RFI2 Channel Isolation IF/2 Spurious IF/3 Spurious POWER INTERFACE Supply Voltage Quiescent Current 1 Low Side LO injection 250 960 Including 4:1 IF port transformer and PCB loss ZSOURCE = 50Ω, Differential ZLOAD = 200Ω Differential Including 4:1 IF port transformer and PCB loss 8dBm Blocker present +/-10MHz from wanted RF input, LO source filtered fRF1 = 899.5 MHz, fRF2 = 900.5 MHz, fLO = 703 MHz, each RF tone at -10 dBm fRF1 = 899.5 MHz, fRF2 = 900.5 MHz, fLO = 703 MHz, each RF tone at -10 dBm 8.5 15 9.2 18 26 55 11 dB dB dB dB dBm dBm dBm dBm dBm dBc Unfiltered IF Output, Improves substantially with external filter components. -20 -33 Unfiltered IF Output, Improves substantially with external filter components. 33 50 -10 dBm Input Power -10 dBm Input Power -65 -74 dBc dBc 5 Resistor Programmable 380 V mA Supply voltage must be applied from external circuit through external inductors. REV. PrA | Page 2 of 9 Preliminary Technical Data ADL5360—Specifications at VS=3.3v Table 2. VS = 3.3 V, TA = 25°C, fRF = 900 MHz, fLO = 703 MHz, LO power = 0 dBm, Zo = 50Ω, unless otherwise noted Parameter DYNAMIC PERFORMANCE Power Conversion Gain Voltage Conversion Gain SSB Noise Figure Input Third Order Intercept Input Second Order Intercept Input 1 dB Compression Point POWER INTERFACE Supply Voltage Quiescent Current Resistor Programmable 3.0 3.3 265 3.6 Including 4:1 IF port transformer and PCB loss ZSOURCE = 50Ω, Differential ZLOAD = 200Ω Differential Including 4:1 IF port transformer and PCB loss fRF1 = 899.5 MHz, fRF2 = 900.5 MHz, fLO = 703 MHz, each RF tone at -10 dBm fRF1 = 899.5 MHz, fRF2 = 900.5 MHz, fLO = 703 MHz, each RF tone at -10 dBm 9.5 16 8.6 19 50 6 Conditions Min Typ Max ADL5360 Unit dB dB dB dBm dBm dBm V mA REV. PrA | Page 3 of 9 ADL5360 ABSOLUTE MAXIMUM RATINGS Table 2. Parameter Supply Voltage, VPOS PWDN, LOSW, VGS0, VGS1, VGS2 RF Input Power, DVIN, MNIN Internal Power Dissipation θJA (Exposed Paddle Soldered Down) θJC (At Exposed Paddle) Maximum Junction Temperature Operating Temperature Range Storage Temperature Range Rating 5.5 V 3.3 V TBD TBD TBD TBD TBD −40°C to +85°C −65°C to +150°C Preliminary Technical Data Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. ESD CAUTION REV. PrA | Page 4 of 9 Preliminary Technical Data PIN CONFIGURATION AND FUNCTION DESCRIPTIONS ADL5360 Figure 2. Pin Configuration Table 3. Pin Function Descriptions Pin No. 1 2 3, 5, 7, 12, 20, 34 4,, 6, 10, 16, 21, 30, 36 8 9 11 13, 14 15 17 18, 28 19, 22 23 24, 25, 26 27 29 31 32, 33 35 Mnemonic MNIN MNCT COMM Function RF Input for Main Channel. Internally matched to 50Ω. Must be ac-coupled. Center Tap for Main Channel Input Balun. Should be bypassed to ground using low inductance capacitor. Device Common (DC Ground). VPOS Positive Supply Voltage. DVCT DVIN DVGM DVOP, DVON DVLE DVLG NC L0I1 PWDN LOSW VGS0, VGS1, VGS2 LOI2 MNLG MNLE MNOP, MNON MNGM Center Tap for Diversity Channel Input Balun. Should be bypassed to ground using low inductance capacitor. RF Input for Diversity Channel. Internally matched to 50Ω. Must be ac-coupled. Diverstiy Amplifier Bias Setting. Connect 1.2kΩ resistor to ground for typical operation. Diversity Channel Differential Open-Collector Outputs. DVOP and DVON should be pulled-up to VCC using pull-up choke inductors. Diversity Channel External Inductor. Connect 10nH inductor to ground for typical operation. Diverstiy Channel LO Buffer Bias Setting. Connect 390Ω resistor to ground for typical operation. No Connect. Local Oscillator Input 1. Internally matched to 50Ω. Must be ac-coupled. Connect to Ground for Normal Operation. Connect pin to 3.3V for disable mode. Local Oscillator Input Selection Switch. Set LOSW high to select LOI1, and set low to select LOI2. Gate to Source Control Voltages. For typical operation set VGS2 high and VGS0 and VGS1 to low logic level. Local Oscillator Input 2. Internally matched to 50Ω. Must be ac-coupled. Main Channel LO Buffer Bias Setting. Connect 390Ω resistor to ground for typical operation. Main Channel External Inductor. Connect 10nH inductor to ground for typical operation. Main Channel Differential Open-Collector Outputs. MNOP and MNON should be pulled-up to VCC using pullup choke inductors. Main Amplifier Bias Setting. Connect 1.2kΩ resistor to ground for typical operation. REV. PrA | Page 5 of 9 ADL5360 Preliminary Technical Data TYPICAL PERFORMANCE CHARACTERISTICS–PRELIMINARY DATA VS = 5 V, TA = 25°C, as measured using typical circuit schematic with low-side LO unless otherwise noted. Figure 3. Conversion Gain versus RF Frequency Figure 6. Single-Sideband NF versus RF Frequency Figure 4. IIP3 versus RF Frequency Figure 7. Single-Sideband NF versus Blocker Level at 1900MHz Figure 5. IP1dB versus RF Frequency Figure 8. LO to RF Leakage versus LO Frequency REV. PrA | Page 6 of 9 Preliminary Technical Data EVALUATION BOARD SCHEMATIC ADL5360 Figure 9. Evaluation Board Schematic. REV. PrA | Page 7 of 9 ADL5360 Table 3. Eval Board Configuration Components C1, C4, C5, C8, C10, C12, C13, C15, C18, C21, C22, C23, C24, C25, C26 Function Power Supply Decoupling. Nominal supply decoupling consists a 0.01 μF capacitor to ground in parallel with 10pF capacitors to ground positioned as close to the device as possible. Preliminary Technical Data Z1-Z4, C2, C3, C6, C7, C9, C22 T1, T2, C17, C19, C20, C27, C28, C29, C30, C31, C32, C33, L1, L2, L4, L5, R3, R6, R9, R10 C14, C16, R15, LOSEL R19, PWDN R1, R2, R4, R5,L3, L6, R7, R8, R11, R12, R13, R14, R16, R17, C34 RF Main and Diversity Input Interface. Main and Diversity input channels are ac-coupled through C9 and C22. Z1-Z4 provides additional component placement for external matching/filter networks. C2, C3, C6, and C7 provide bypassing for the center taps of the main and diversity on-chip input baluns. IF Main and Diversity Output Interface. The open collector IF output interfaces are biased through pull-up choke inductors L1, L2, L4, and L5, with R3 and R6 available for additional supply bypassing. T1 and T2 are 4:1 impedance transformers used to provide a single ended IF output interface, with C27 and C28 providing center-tap bypassing. C17, C19, C20, C29, C30, C31, C32, and C33 ensure an ac-coupled output interface. R9 and R10 should be removed for balanced output operation. LO Interface. C14 and C16 provide ac-coupling for the LOI1 and LOI2 local oscillator inputs. LOSEL selects the appropriate LO input for both mixer cores. R15 provides a pull-down to ensure LOI2 is enabled when the LOSEL jumper is removed. Jumper can be removed to allow LOSEL interface to be excercised using external logic generator. PWDN Interface. When the PWDN 2-pin shunt is inserted the ADL5356 is powered down. When open R19 pulls the PWDN logic low and enables the device. Jumper can be removed to allow PWDN interface to be excercised using external logic generator. It is permissible to ground the pwrdn pin for nominal operation. Bias Control. R16 and R17 form a voltage divider to provide a 3V for logic control, bypassed to ground through C34. R7, R8, R11, R12, R13, and R14 provide resistor programmability of VGS0, VGS1 and VGS2. Typically these nodes can be hard-wired for nominal operation. It is permissible to ground these pins for nominal operation. R2 and R5 set the bias point for the internal LO buffers. R1 and R4 set the bias point for the internal IF amplifiers. L3 and L6 are external inductors used to improve isolation and common mode rejection. Default Conditions C10 = 4.7 μF (size 3216) C1, C8, C12, C21 = 150pF (size 0402) C4, C5, C22, C23, C24, C25, C26 = 10pF (size 0402) C13, C15, C18 = 0.1 μ (size 0402) C2, C7 = 10pF (size 0402) C3, C6 = 0.01 μF (size 0402) C9, C22 = 22pF (size 0402) Z1-Z4 = open (size 0402) C17, C19, C20, C29-C33 = 0.001 μF (size 0402) C27, C28 = 150pF (size 0402) T1, T2 = TC4-1T+ (MiniCircuits) L1, L2, L4, L5 = 330 nH (size 0805) R3, R6, R9, R10 = 0 Ω (size 0402) C14, C16 = 10pF (size 0402) R15 = 10kΩ (size 0402) LOSEL = 2-pin shunt R19 = 10kΩ (size 0402) PWDN = 2-pin shunt R1, R4 = 1.2kΩ (size 0402) R2, R5 = 390Ω (size 0402) L3, L6 = 10nH (size 0603) R7, R13, R14 = open (size 0402) R8, R11, R12 = 0Ω (size 0402) R16 = 10kΩ (size 0402) R17 = 15kΩ (size 0402) C34 = 1nF (size 0402) REV. PrA | Page 8 of 9 Preliminary Technical Data OUTLINE DIMENSIONS ADL5360 Figure 10. 36-Lead Lead Frame Chip Scale Package [LFCSP_VQ] 6mm × 6 mm Body, Very Thin Quad (CP-36-1)) Dimensions shown in millimeters ORDERING GUIDE Models ADL5360XCPZ-R7 ADL5360XCPZ-WP ADL5360-EVALZ Temperature Range −40°C to +85°C −40°C to +85°C Package Description 36-Lead Lead Frame Chip Scale Package [LFCSP_VQ] 36-Lead Lead Frame Chip Scale Package [LFCSP_VQ] Evaluation Board Package Option CP-36-1 CP-36-1 Branding TBD TBD Transport Media Quantity TBD, Reel TBD, Waffle Pack 1 REV. PrA | Page 9 of 9 PR07884-0-10/08(PrA)