ADL5375-15-EVALZ

400 MHz to 6 GHz Broadband Quadrature Modulator ADL5375 Data Sheet FEATURES FUNCTIONAL BLOCK DIAGRAM IBBP ADL5375 IBBN LOIP LOIN QUADRATURE PHASE SPLITTER RFOUT DSOP QBBN 07052-001 Output frequency range: 400 MHz to 6 GHz 1 dB output compression: ≥9.4 dBm from 450 MHz to 4 GHz Output return loss ≤ 12 dB from 450 MHz to 4.5 GHz Noise floor: −160 dBm/Hz at 900 MHz Sideband suppression: ≤−50 dBc at 900 MHz Carrier feedthrough: ≤−40 dBm at 900 MHz IQ3dB bandwidth: ≥ 750 MHz Baseband input bias level ADL5375-05: 500 mV ADL5375-15: 1500 mV Single supply: 4.75 V to 5.25 V 24-lead LFCSP_VQ package QBBP Figure 1. APPLICATIONS Cellular communication systems GSM/EDGE, CDMA2000, W-CDMA, TD-SCDMA WiMAX/LTE broadband wireless access systems Satellite modems GENERAL DESCRIPTION The ADL5375 is a broadband quadrature modulator designed for operation from 400 MHz to 6 GHz. Its excellent phase accuracy and amplitude balance enable high performance intermediate frequency or direct radio frequency modulation for communication systems. The ADL5375 features a broad baseband bandwidth, along with an output gain flatness that varies no more than 1 dB from 450 MHz to 3.5 GHz. These features, coupled with a broadband output return loss of ≤−12 dB, make the ADL5375 ideally suited for broadband zero IF or low IF-to-RF applications, Rev. D broadband digital predistortion transmitters, and multiband radio designs. The ADL5375 accepts two differential baseband inputs and a single-ended LO. It generates a single-ended 50 Ω output. The two versions offer input baseband bias levels of 500 mV (ADL5375-05) and 1500 mV (ADL5375-15). The ADL5375 is fabricated using an advanced silicon-germanium bipolar process. It is available in a 24-lead, exposed paddle, leadfree, LFCSP_VQ package. Performance is specified over a −40°C to +85°C temperature range. A lead-free evaluation board is also available. Document Feedback Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective owners. One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. Tel: 781.329.4700 ©2007–2014 Analog Devices, Inc. All rights reserved. Technical Support www.analog.com ADL5375 Data Sheet TABLE OF CONTENTS Features .............................................................................................. 1 LO Input ...................................................................................... 20 Applications ....................................................................................... 1 RF Output .................................................................................... 20 Functional Block Diagram .............................................................. 1 Output Disable ............................................................................ 21 General Description ......................................................................... 1 Applications Information .............................................................. 22 Revision History ............................................................................... 2 Carrier Feedthrough Nulling .................................................... 22 Specifications..................................................................................... 3 Sideband Suppression Optimization ....................................... 22 Absolute Maximum Ratings............................................................ 7 Interfacing the ADF4350 PLL to the ADL5375 ..................... 23 ESD Caution .................................................................................. 7 DAC Modulator Interfacing ..................................................... 24 Pin Configuration and Function Descriptions ............................. 8 GSM/EDGE Operation ............................................................. 27 Typical Performance Characteristics ............................................. 9 W-CDMA Operation ................................................................. 28 ADL5375-05 .................................................................................. 9 LO Generation Using PLLs ....................................................... 29 ADL5375-15 ................................................................................ 14 Transmit DAC Options ............................................................. 29 Theory of Operation ...................................................................... 19 Modulator/Demodulator Options ........................................... 29 Circuit Description..................................................................... 19 Evaluation Board ............................................................................ 30 Basic Connections .......................................................................... 20 Characterization Setup .................................................................. 33 Power Supply and Grounding ................................................... 20 Outline Dimensions ....................................................................... 35 Baseband Inputs.......................................................................... 20 Ordering Guide .......................................................................... 35 REVISION HISTORY 6/14—Rev. C to Rev. D Changes to Figure 2 .......................................................................... 8 Changes to Figure 13, Figure 14, and Figure 15 ......................... 10 Changes to Figure 38, Figure 39, and Figure 40 ......................... 15 Changes to Table 9 .......................................................................... 31 Changes to Ordering Guide .......................................................... 35 7/13—Rev. B to Rev. C Changed CP-24-3 to CP-24-7 ........................................... Universal 9/11—Rev. A to Rev. B Changes to Features Section............................................................ 1 Replaced Table 1 ............................................................................... 3 Changes to Typical Performance Characteristics Section ........... 9 Updated Output Disable Section .................................................. 21 Changes to Application Information Section ............................ 22 Changes to Evaluation Board Section.......................................... 30 Changes to Figure 80...................................................................... 34 Added Exposed Pad Notation to Outline Dimensions ............. 35 11/08—Rev. 0 to Rev. A Change AD9779 to AD9779A .......................................... Universal Added Endnote, I/Q Input Bias Level and Absolute Voltage Level Parameters, Table 1 ...................................................6 Added Absolute Voltage Level Parameter, Table 1 ........................6 12/07—Revision 0: Initial Version Rev. D | Page 2 of 36 Data Sheet ADL5375 SPECIFICATIONS VS = 5 V; TA = 25°C; LO = 0 dBm single-ended drive; baseband I/Q amplitude = 1 V p-p differential sine waves in quadrature with a 500 mV (ADL5375-05) or 1500 mV (ADL5375-15) dc bias; baseband I/Q frequency (fBB) = 1 MHz, unless otherwise noted. Table 1. Parameter OPERATING FREQUENCY RANGE Low frequency High frequency LO = 450 MHz Output Power, POUT Modulator Voltage Gain Output P1dB Output Return Loss Carrier Feedthrough Sideband Suppression Quadrature Error I/Q Amplitude Balance Second Harmonic ADL5375-05 ADL5375-15 Third Harmonic ADL5375-05 ADL5375-15 Output IP2 Output IP3 Noise Floor LO = 900 MHz Output Power, POUT Modulator Voltage Gain Output P1dB Output Return Loss Carrier Feedthrough Sideband Suppression Quadrature Error I/Q Amplitude Balance Second Harmonic ADL5375-05 ADL5375-15 Third Harmonic ADL5375-05 ADL5375-15 Output IP2 Output IP3 Noise Floor ADL5375-05 Min Typ Max Conditions VIQ = 1 V p-p differential RF output divided by baseband input voltage POUT − (fLO + (2 × fBB)) POUT =0.85 dBm POUT = 0.47 dBm POUT − (fLO + (3 × fBB)) POUT = 0.85 dBm POUT = 0.47 dBm f1BB = 3.5 MHz, f2BB = 4.5 MHz, baseband I/Q amplitude per tone = 0.5 V p-p differential f1BB = 3.5 MHz, f2BB = 4.5 MHz, baseband I/Q amplitude per tone = 0.5 V p-p differential I/Q inputs = 0 V differential with a dc bias only, 20 MHz carrier offset VIQ = 1 V p-p differential RF output divided by baseband input voltage POUT − (fLO + (2 × fBB)) POUT = 0.75 dBm POUT = 0.41 dBm POUT − (fLO + (3 × fBB)) POUT = 0.75 dBm POUT = 0.41 dBm f1BB = 3.5 MHz, f2BB = 4.5 MHz, baseband I/Q amplitude per tone = 0.5 V p-p differential f1BB = 3.5 MHz, f2BB = 4.5 MHz, baseband I/Q amplitude per tone = 0.5 V p-p differential I/Q inputs = 0 V differential with a dc bias only, 20 MHz carrier offset Rev. D | Page 3 of 36 ADL5375-15 Min Typ Max Unit 400 6000 400 6000 MHz MHz 0.85 −3.1 9.6 −16.4 −47.5 −37.6 1.7 0.07 −75.9 0.47 −3.5 10 −15.2 -42.5 −38 1.49 0.10 −81.5 dBm dB dBm dB dBm dBc Degrees dB dBc −51.5 −81.6 dBc 65.4 64.7 dBm 26.6 23.6 dBm −160.5 −157.0 dBm/Hz 0.75 −3.2 9.6 −15.7 −45.1 −52.8 0.01 0.07 −75.8 0.41 −3.5 10 −14.7 −39.9 −49.9 0.20 0.10 −77.2 dBm dB dBm dB dBm dBc Degrees dB dBc −50.7 −72.7 dBc 62.6 64.5 dBm 25.9 23.4 dBm −160.0 −157.1 dBm/Hz ADL5375 Parameter LO = 1900 MHz Output Power, POUT Modulator Voltage Gain Output P1dB Output Return Loss Carrier Feedthrough Sideband Suppression Quadrature Error I/Q Amplitude Balance Second Harmonic ADL5375-05 ADL5375-15 Third Harmonic ADL5375-05 ADL5375-15 Output IP2 Output IP3 Noise Floor LO = 2150 MHz Output Power, POUT Modulator Voltage Gain Output P1dB Output Return Loss Carrier Feedthrough Sideband Suppression Quadrature Error I/Q Amplitude Balance Second Harmonic ADL5375-05 ADL5375-15 Third Harmonic ADL5375-05 ADL5375-15 Output IP2 Output IP3 Noise Floor LO = 2600 MHz Output Power, POUT Modulator Voltage Gain Output P1dB Output Return Loss Carrier Feedthrough Sideband Suppression Quadrature Error I/Q Amplitude Balance Second Harmonic Data Sheet ADL5375-05 Min Typ Max Conditions VIQ = 1 V p-p differential RF output divided by baseband input voltage POUT − (fLO + (2 × fBB)) POUT = 0.53dBm POUT = 0.49dBm POUT − (fLO + (3 × fBB)) POUT = 0.53dBm POUT = 0.49dBm f1BB = 3.5 MHz, f2BB = 4.5 MHz, baseband I/Q amplitude per tone = 0.5 V p-p differential f1BB = 3.5 MHz, f2BB = 4.5 MHz, baseband I/Q amplitude per tone = 0.5 V p-p differential I/Q inputs = 0 V differential with a dc bias only, 20 MHz carrier offset VIQ = 1 V p-p differential RF output divided by baseband input voltage POUT − (fLO + (2 × fBB)) POUT = 0.73 dBm POUT = 0.57 dBm POUT − (fLO + (3 × fBB)) POUT = 0.73 dBm POUT = 0.57 dBm f1BB = 3.5 MHz, f2BB = 4.5 MHz, baseband I/Q amplitude per tone = 0.5 V p-p differential f1BB = 3.5 MHz, f2BB = 4.5 MHz, baseband I/Q amplitude per tone = 0.5 V p-p differential I/Q inputs = 0 V differential with a dc bias only, 20 MHz carrier offset VIQ = 1 V p-p differential RF output divided by baseband input voltage POUT − (fLO + (2 × fBB)) Rev. D | Page 4 of 36 ADL5375-15 Min Typ Max Unit 0.53 −3.4 9.9 −16.2 −40.3 −50.2 0.02 0.07 −67.9 0.49 −3.4 10.5 −15.5 −35.5 −49.4 0.21 0.10 −72.1 dBm dB dBm dB dBm dBc Degrees dB dBc −51.8 −62.8 dBc 62.6 61 dBm 24.3 22.1 dBm −160.0 −158.2 dBm/Hz 0.73 −3.2 10.0 −17.1 −39.7 −47.3 −0.16 0.07 −71.3 0.57 −3.4 10.6 −16.1 −34.2 −50.2 −0.18 0.10 −81.7 dBm dB dBm dB dBm dBc Degrees dB dBc −52.4 −65.3 dBc 61.6 61.8 dBm 24.2 22.3 dBm −159.5 −157.9 dBm/Hz 0.61 −3.4 9.6 −19.3 −36.5 −48.3 −0.37 0.07 −60.9 0.62 −3.3 10.6 −18 −33.3 −48.5 0.19 0.11 −55.9 dBm dB dBm dB dBm dBc Degrees dB dBc Data Sheet Parameter ADL5375-05 ADL5375-15 Third Harmonic ADL5375-05 ADL5375-15 Output IP2 Output IP3 Noise Floor LO = 3500 MHz Output Power, POUT Modulator Voltage Gain Output P1dB Output Return Loss Carrier Feedthrough Sideband Suppression Quadrature Error I/Q Amplitude Balance Second Harmonic ADL5375-05 ADL5375-15 Third Harmonic ADL5375-05 ADL5375-15 Output IP2 Output IP3 Noise Floor LO = 5800 MHz Output Power, POUT Modulator Voltage Gain Output P1dB Output Return Loss Carrier Feedthrough Sideband Suppression Quadrature Error I/Q Amplitude Balance Second Harmonic ADL5375-05 ADL5375-15 Third Harmonic ADL5375-05 ADL5375-15 Output IP2 Output IP3 Noise Floor ADL5375 Conditions POUT = 0.61 dBm POUT = 0.62 dBm POUT − (fLO + (3 × fBB)) POUT = 0.61 dBm POUT = 0.62 dBm f1BB = 3.5 MHz, f2BB = 4.5 MHz, baseband I/Q amplitude per tone = 0.5 V p-p differential f1BB = 3.5 MHz, f2BB = 4.5 MHz, baseband I/Q amplitude per tone = 0.5 V p-p differential I/Q inputs = 0 V differential with a dc bias only, 20 MHz carrier offset VIQ = 1 V p-p differential RF output divided by baseband input voltage POUT − (fLO + (2 × fBB)) POUT = 0.21 dBm POUT = 0.87 dBm POUT − (fLO + (3 × fBB)) POUT = 0.21 dBm POUT = 0.87 dBm f1BB = 3.5 MHz, f2BB = 4.5 MHz, baseband I/Q amplitude per tone = 0.5 V p-p differential f1BB = 3.5 MHz, f2BB = 4.5 MHz, baseband I/Q amplitude per tone = 0.5 V p-p differential I/Q inputs = 0 V differential with a dc bias only, 20 MHz carrier offset VIQ = 1 V p-p differential RF output divided by baseband input voltage POUT − (fLO + (2 × fBB)) POUT = -1.36 dBm POUT = 0.16 dBm POUT − (fLO + (3 × fBB)) POUT = -1.36 dBm POUT = 0.16 dBm f1BB = 3.5 MHz, f2BB = 4.5 MHz, baseband I/Q amplitude per tone = 0.5 V p-p differential f1BB = 3.5 MHz, f2BB = 4.5 MHz, baseband I/Q amplitude per tone = 0.5 V p-p differential I/Q inputs = 0 V differential with a dc bias only, 20 MHz carrier offset Rev. D | Page 5 of 36 ADL5375-05 Min Typ Max ADL5375-15 Min Typ Max Unit −51.3 −57.6 dBc 55.0 50.1 dBm 22.7 20.7 dBm −159.0 −157.6 dBm/Hz 0.21 −3.8 9.6 −20.7 −30.4 −48.3 0.01 0.08 −55.8 0.87 −3.1 10.2 −19.4 −28.6 −48.8 0.13 0.11 −63 dBm dB dBm dB dBm dBc Degrees dB dBc −50.2 −56.2 dBc 51.1 57.9 dBm 23.1 20.2 dBm −157.6 −156.3 dBm/Hz −1.36 −5.3 4.9 −7.4 −19.5 −38.2 −0.51 −0.05 −52.6 0.16 −3.8 4.4 −8.6 −16.7 −39 −0.50 −0.70 −50 dBm dB dBm dB dBm dBc Degrees dB dBc −45.7 −48.4 dBc 39.1 38.7 dBm 14.6 11.2 dBm −153.0 −153.4 dBm/Hz ADL5375 Parameter LO INPUTS LO Drive Level Input Return Loss BASEBAND INPUTS I/Q Input Bias Level 1 Absolute Voltage Level1 Input Bias Current Input Offset Current Differential Input Impedance Bandwidth (0.1 dB) OUTPUT DISABLE Off Isolation Turn-On Settling Time Turn-Off Settling Time DSOP High Level (Logic 1) DSOP Low Level (Logic 0) POWER SUPPLIES Voltage Supply Current 1 Data Sheet ADL5375-05 Min Typ Max ADL5375-15 Min Typ Max Characterization performed at typical level 500 MHz < fLO < 3.3 GHz See Figure 7 and Figure 32 for return loss vs. frequency Pin IBBP, Pin IBBN, Pin QBBP, Pin QBBN −6 +6 −6 On Pin IBBP, Pin IBBN, Pin QBBP, Pin QBBN Current sourcing from each baseband input 0 1 1 Conditions 0 ≤−10 500 LO = 1900 MHz, baseband input = 500 mV p-p sine wave Pin DSOP POUT (DSOP low) − POUT (DSOP high) DSOP high, LO leakage, LO = 2150 MHz DSOP high to low (90% of envelope) DSOP low to high (10% of envelope) 0 ≤−10 +6 1500 Unit dBm dB 41 0.1 60 32 0.1 100 mV V µA µA kΩ 95 80 MHz 84 −55 220 100 85 −53 220 100 dB dBm ns ns V V 2.0 2 2.0 0.8 0.8 Pin VPS1 and Pin VPS2 4.75 DSOP = low DSOP = high 5.25 194 126 4.75 5.25 203 127 The input bias level can vary as long as the voltages on the individual IBBP, IBBN, QBBP, and QBBN pins remain within the specified absolute voltage level. Rev. D | Page 6 of 36 V mA mA Data Sheet ADL5375 ABSOLUTE MAXIMUM RATINGS Table 2. Parameter Supply Voltage, VPOS IBBP, IBBN, QBBP, QBBN LOIP and LOIN Internal Power Dissipation ADL5375-05 ADL5375-15 θJA (Exposed Paddle Soldered Down)1 Maximum Junction Temperature Operating Temperature Range Storage Temperature Range Rating 5.5 V 0 V to 2 V 13 dBm 1500 mW 1200 mW 54°C/W 150°C −40°C to +85°C −65°C to +150°C Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. ESD CAUTION Per JDEC standard JESD 51-2. For information on optimizing thermal impedance, see the Thermal Grounding and Evaluation Board Layout section. 1 Rev. D | Page 7 of 36 ADL5375 Data Sheet 24 23 22 21 20 19 VPS2 COMM IBBN IBBP COMM COMM PIN CONFIGURATION AND FUNCTION DESCRIPTIONS 1 2 3 4 5 6 ADL5375 TOP VIEW (Not to Scale) EXPOSED PAD 18 17 16 15 14 13 VPS1 COMM RFOUT NC COMM NC NOTES 1. NC = NO CONNECT. DO NOT CONNECT TO THIS PIN. 2. CONNECT EXPOSED PAD TO THE GROUND LANE VIA A LOW IMPEDANCE PATH. 07052-003 NC 7 COMM 8 QBBN 9 QBBP 10 COMM 11 COMM 12 DSOP COMM LOIP LOIN COMM NC Figure 2. Pin Configuration Table 3. Pin Function Descriptions Pin No. 1 Mnemonic DSOP 2, 5, 8, 11, 12, 14, 17, 19, 20, 23 3, 4 COMM 6, 7, 13, 15, 9, 10, 21, 22 NC QBBN, QBBP, IBBP, IBBN 16 18, 24 RFOUT VPS1, VPS2 LOIP, LOIN EP Description Output Disable. A logic high on this pin disables the RF output. Connect this pin to ground or leave it floating to enable the output. Input Common Pins. Connect to the ground plane via a low impedance path. Local Oscillator Inputs. Single-ended operation: The LOIP pin is driven from the LO source through an ac-coupling capacitor while the LOIN pin is ac-coupled to ground through a capacitor. Differential operation: The LOIP and LOIN pins must be driven differentially through ac-coupling capacitors in this mode of operation. No Connect. These pins can be left open or tied to ground. Differential In-Phase and Quadrature Baseband Inputs. These high impedance inputs should be dcbiased to the recommended level depending on the version. ADL5375-05: 500 mV ADL5375-15: 1500 mV These inputs should be driven from a low impedance source. Nominal characterized ac signal swing is 500 mV p-p on each pin. This results in a differential drive of 1 V p-p. These inputs are not self-biased and have to be externally biased. RF Output. Single-ended, 50 Ω internally biased RF output. RFOUT must be ac-coupled to the load. Positive Supply Voltage Pins. All pins should be connected to the same supply (VS). To ensure adequate external bypassing, connect 0.1 µF and 100 pF capacitors between each pin and ground. Exposed Paddle. Connect to the ground plane via a low impedance path. Rev. D | Page 8 of 36 Data Sheet ADL5375 TYPICAL PERFORMANCE CHARACTERISTICS ADL5375-05 VS = 5 V; TA = 25°C; LO = 0 dBm single-ended drive; baseband I/Q amplitude = 1 V p-p differential sine waves in quadrature with a 500 mV dc bias; baseband I/Q frequency (fBB) = 1 MHz, unless otherwise noted. 12 5 VS = 5.25V 1dB OUTPUT COMPRESSION (dBm) SSB OUTPUT POWER (dBm) 4 3 TA = –40°C 2 TA = +25°C 1 0 –1 TA = +85°C –2 –3 VS = 5.0V 10 8 VS = 4.75V 6 4 2 0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0 LO FREQUENCY (GHz) 0 07052-052 –5 0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0 LO FREQUENCY (GHz) 07052-055 –4 Figure 6. SSB Output 1dB Compression Point (OP1dB) vs. LO Frequency (fLO) and Supply Figure 3. Single-Sideband (SSB) Output Power (POUT) vs. LO Frequency (fLO) and Temperature 90 5 3 150 2 3 1 2 S11 6GHz 75.88 – j76.94Ω 400MHz 0 180 –1 0 1 400MHz VS = 5.0V VS = 4.75V –2 2 4 210 6GHz 6GHz 330 3 S22 400MHz 40.01 + j9.20Ω 4 S22 6GHz 30.52 – j30.09Ω –3 S11 S22 0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0 LO FREQUENCY (GHz) 07052-053 240 –5 300 07052-097 –4 270 Figure 7. Smith Chart of LOIP (LOIN AC-Coupled to Ground) S11 and RFOUT S22 from 450 MHz to 6000 MHz Figure 4. Single-Sideband (SSB) Output Power (POUT) vs. LO Frequency (fLO) and Supply 14 0 LOIP 12 –5 TA = –40°C 8 TA = +85°C RETURN LOSS (dB) 10 TA = +25°C 6 4 2 –10 –15 RFOUT –20 –25 0 0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 LO FREQUENCY (GHz) 4.5 5.0 5.5 6.0 07052-054 1dB OUTPUT COMPRESSION (dBm) 1 400MHz 25.73 – j8.14Ω 30 VS = 5.25V –30 0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 FREQUENCY (GHz) Figure 5. SSB Output 1dB Compression Point (OP1dB) vs. LO Frequency (fLO) and Temperature 4.5 5.0 5.5 6.0 07052-056 SSB OUTPUT POWER (dBm) 60 120 4 Figure 8. Return Loss of LOIP (LOIN AC-Coupled to Ground) S11 and RFOUT S22 from 450 MHz to 6000 MHz Rev. D | Page 9 of 36 ADL5375 Data Sheet 0 0 –5 TA = +85°C –15 SIDEBAND SUPPRESSION (dBc) CARRIER FEEDTHROUGH (dBm) –10 –10 TA = +25°C –20 –25 –30 TA = –40°C –35 –40 –45 –50 –20 –30 TA = +25°C –40 TA = +85°C –50 –60 –70 –55 TA = –40°C 2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0 LO FREQUENCY (GHz) 0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0 Figure 12. Sideband Suppression vs. LO Frequency (fLO) and Temperature After Nulling at 25°C; Multiple Devices Shown –10 SECOND-ORDER DISTORTION, THIRD-ORDER DISTORTION, CARRIER FEEDTHROUGH, AND SIDEBAND SUPPRESSION 0 –10 CARRIER FEEDTHROUGH (dBm) 1.0 LO FREQUENCY (GHz) Figure 9. Carrier Feedthrough vs. LO Frequency (fLO) and Temperature; Multiple Devices Shown –20 TA = +85°C –30 –40 TA = –40°C –50 TA = +25°C –60 –70 0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0 LO FREQUENCY (GHz) 10 SSB OUTPUT POWER (dBm) –20 –30 5 CARRIER FEEDTHROUGH (dBm) –40 –50 0 –60 –70 –5 –80 SIDEBAND SUPPRESSION (dBc) –10 –90 –100 SECOND-ORDER DISTORTION (dBc) THIRD-ORDER DISTORTION (dBc) –15 –110 0.2 07052-058 –80 1 4 BASEBAND DIFFERENTIAL INPUT VOLTAGE (V p-p) Figure 10. Carrier Feedthrough vs. LO Frequency (fLO) and Temperature After Nulling at 25°C; Multiple Devices Shown Figure 13. Second- and Third-Order Distortion, Carrier Feedthrough, Sideband Suppression, and SSB POUT vs. Baseband Differential Input Level (fLO = 900 MHz) –10 SECOND-ORDER DISTORTION, THIRD-ORDER DISTORTION, CARRIER FEEDTHROUGH, AND SIDEBAND SUPPRESSION 0 –10 –20 TA = +85°C –30 –40 –50 –60 TA = –40°C –70 TA = +25°C –80 0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 LO FREQUENCY (GHz) 4.5 5.0 5.5 6.0 Figure 11. Sideband Suppression vs. LO Frequency (fLO) and Temperature; Multiple Devices Shown 10 SSB OUTPUT POWER (dBm) –20 –30 CARRIER FEEDTHROUGH (dBm) 5 –40 –50 0 –60 –5 SIDEBAND SUPPRESSION (dBc) –70 –80 –90 –100 –110 0.2 07052-059 SIDEBAND SUPPRESSION (dBc) 0.5 07052-060 2.0 SSB OUTPUT POWER (dBm) 1.5 07052-061 1.0 SSB OUTPUT POWER (dBm) 0.5 –10 SECOND-ORDER DISTORTION (dBc) THIRD-ORDER DISTORTION (dBc) –15 1 4 BASEBAND DIFFERENTIAL INPUT VOLTAGE (V p-p) Figure 14. Second- and Third-Order Distortion, Carrier Feedthrough, Sideband Suppression, and SSB POUT vs. Baseband Differential Input Level (fLO = 2150 MHz) Rev. D | Page 10 of 36 07052-062 0 –80 07052-057 –60 Data Sheet ADL5375 30 5 –30 –40 0 –50 THIRD-ORDER –60 DISTORTION (dBc) –5 SIDEBAND SUPPRESSION (dBc) –70 SECOND-ORDER DISTORTION (dBc) –80 OUTPUT THIRD-ORDER INTERCEPT (dBm) CARRIER FEEDTHROUGH (dBm) –20 SSB OUTPUT POWER (dBm) –10 –10 –90 –15 –100 0.2 1 4 BASEBAND DIFFERENTIAL INPUT VOLTAGE (V p-p) TA = +85°C 10 5 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0 LO FREQUENCY (GHz) TA = +85°C TA = –40°C –50 –60 SECOND-ORDER TA = +25°C –70 0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0 LO FREQUENCY (GHz) –1.5 SIDEBAND SUPPRESSION (dBc) –60 –2.5 SECOND-ORDER DISTORTION (dBc) –3.5 100 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0 BASEBAND FREQUENCY (MHz) Figure 17. Second-Order Distortion, Carrier Feedthrough, Sideband Suppression, and SSB POUT vs. Baseband Frequency (fBB); fLO = 2140 MHz 2 SSB OUTPUT POWER (dBm) –30 1 CARRIER FEEDTHROUGH (dBm) –40 0 –50 –1 –60 THIRD-ORDER DISTORTION (dBc) SIDEBAND SUPPRESSION (dBc) –2 SECOND-ORDER DISTORTION (dBc) –70 –3 –80 07052-098 10 10 –20 SECOND-ORDER DISTORTION, THIRD-ORDER DISTORTION,SIDEBAND SUPPRESSION (dBc), AND CARRIER FEEDTHROUGH (dBm) –0.5 TA = +85°C 20 Figure 19. OIP2 vs. LO Frequency (fLO) and Temperature (POUT ≈ −5 dBm) SSB OUTPUT POWER (dBm) –40 0.5 30 LO FREQUENCY (GHz) 1.5 CARRIER FEEDTHROUGH (dBm) TA = +25°C 0 SSB OUTPUT POWER (dBm) –30 40 0 Figure 16. Second- and Third-Order Distortion vs. LO Frequency (fLO) and Temperature (Baseband I/Q Amplitude = 1 V p-p Differential) –20 TA = –40°C 50 SSB OUTPUT POWER (dBm) THIRD-ORDER 60 –4 –6 –4 –2 0 2 4 6 LO AMPLITUDE (dBm) Figure 20. Second- and Third-Order Distortion, Carrier Feedthrough, Sideband Suppression, and SSB POUT vs. LO Amplitude (fLO = 900 MHz) Rev. D | Page 11 of 36 07052-065 –40 70 07052-088 OUTPUT SECOND-ORDER INTERCEPT (dBm) –30 07052-064 SECOND-ORDER DISTORTION AND THIRD-ORDER DISTORTION (dBc) TA = +25°C 80 –80 SECOND-ORDER DISTORTION, CARRIER FEEDTHROUGH, SIDEBAND SUPPRESSION (dB) 15 0 –20 1 TA = –40°C 0 –10 –70 20 Figure 18. OIP3 vs. LO Frequency (fLO) and Temperature (POUT ≈ −5 dBm) Figure 15. Second- and Third-Order Distortion, Carrier Feedthrough, Sideband Suppression, and SSB POUT vs. Baseband Differential Input Level (fLO = 3500 MHz) –50 25 07052-087 10 SSB OUTPUT POWER (dBm) 07052-063 SECOND-ORDER DISTORTION, THIRD-ORDER DISTORTION, CARRIER FEEDTHROUGH, AND SIDEBAND SUPPRESSION 0 ADL5375 Data Sheet 2 18 SSB OUTPUT POWER (dBm) –40 0 CARRIER FEEDTHROUGH (dBm) –50 –1 SIDEBAND SUPPRESSION (dBc) –60 –2 THIRD-ORDER DISTORTION (dBc) –70 16 14 12 QUANTITY 1 SSB OUTPUT POWER (dBm) –30 4 –4 –4 –2 0 2 4 6 0 –160.5 –160.3 –160.1 –159.9 –159.7 –159.5 –159.3 –159.1 LO AMPLITUDE (dBm) NOISE (dBm/Hz) 07052-089 2 SECOND-ORDER DISTORTION (dBc) –6 Figure 24. 20 MHz Offset Noise Floor Distribution at fLO = 900 MHz (I/Q Amplitude = 0 mV p-p with 500 mV DC Bias) Figure 21. Second- and Third-Order Distortion, Carrier Feedthrough, Sideband Suppression, and SSB POUT vs. LO Amplitude (fLO = 2150 MHz) 1 –10 8 0 SSB OUTPUT POWER (dBm) –30 –1 SIDEBAND SUPPRESSION (dBc) –40 –2 –50 –3 3 0 2 4 6 LO AMPLITUDE (dBm) 0 –160.5 Figure 22. Second- and Third-Order Distortion, Carrier Feedthrough, Sideband Suppression, and SSB POUT vs. LO Amplitude (fLO = 3500 MHz) –160.1 –159.7 –159.3 –158.9 –158.5 NOISE (dBm/Hz) 07052-090 1 –5 –2 4 2 SECOND-ORDER DISTORTION (dBc) –70 –4 5 –4 THIRD-ORDER DISTORTION (dBc) –6 6 Figure 25. 20 MHz Offset Noise Floor Distribution at fLO = 2140 MHz (I/Q Amplitude = 0 mV p-p with 500 mV DC Bias) 210 10 VS = 5.25V 205 9 8 200 VS = 5.0V 7 QUANTITY 195 190 185 VS = 4.75V 180 6 5 4 3 2 170 1 165 –40 25 85 TEMPERATURE (°C) 07052-068 175 0 –158.9 –158.5 –158.1 –157.7 –157.3 NOISE (dBm/Hz) –156.9 –156.5 07052-099 –60 7 QUANTITY CARRIER FEEDTHROUGH (dBm) SSB OUTPUT POWER (dBm) –20 07052-067 SECOND-ORDER DISTORTION, THIRD-ORDER DISTORTION,SIDEBAND SUPPRESSION (dBc), AND CARRIER FEEDTHROUGH (dBm) 8 –3 –80 SUPPLY CURRENT (mA) 10 6 07052-066 SECOND-ORDER DISTORTION, THIRD-ORDER DISTORTION,SIDEBAND SUPPRESSION (dBc), AND CARRIER FEEDTHROUGH (dBm) –20 Figure 26. 20 MHz Offset Noise Floor Distribution at fLO = 3500 MHz (I/Q Amplitude = 0 mV p-p with 500 mV DC Bias) Figure 23. Power Supply Current vs. Temperature Rev. D | Page 12 of 36 Data Sheet ADL5375 0 SSB OUTPUT POWER ISOLATION (dB) 85 –20 83 –30 82 –40 –50 81 CARRIER FEEDTHROUGH (dBm) 80 –60 79 –70 78 0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 CARRIER FEEDTHROUGH (dBm) –10 88 –80 6.0 07052-091 SSB OUTPUT POWER ISOLATION (dB) 86 LO FREQUENCY (GHz) Figure 27. SSB POUT Isolation and Carrier Feedthrough with DSOP High Rev. D | Page 13 of 36 ADL5375 Data Sheet ADL5375-15 VS = 5 V; TA = 25°C; LO = 0 dBm single-ended drive; baseband I/Q amplitude = 1 V p-p differential sine waves in quadrature with a 1500 mV dc bias; baseband I/Q frequency (fBB) = 1 MHz, unless otherwise noted. 12 5 1dB OUTPUT COMPRESSION (dBm) SSB OUTPUT POWER (dBm) 4 3 2 TA = –40°C TA = +25°C 1 0 TA = +85°C –1 –2 –3 VS = 5.25V VS = 5.0V 10 8 VS = 4.75V 6 4 2 0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0 LO FREQUENCY (GHz) 0 07052-069 –5 0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0 LO FREQUENCY (GHz) Figure 28. Single-Sideband (SSB) Output Power (POUT) vs. LO Frequency (fLO) and Temperature 07052-072 –4 Figure 31. SSB Output 1dB Compression Point (OP1dB) vs. LO Frequency (fLO) and Supply 90 5 SSB OUTPUT POWER (dBm) 60 120 4 3 2 150 VS = 4.75V 1 VS = 5.0V 3 0 180 0 400MHz 1 –1 2 VS = 5.25V –2 1 S11 400MHz 25.07 – j7.11Ω 30 400MHz 6GHz 4 6GHz 210 –3 330 2 S11 6GHz 96.98 – j74.75Ω 3 S22 400MHz 38.63 + j10.34Ω 4 S22 6GHz 34.35 – j30.63Ω –4 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0 LO FREQUENCY (GHz) S11 S22 240 Figure 29. Single-Sideband (SSB) Output Power (POUT) vs. LO Frequency (fLO) and Supply 300 07052-102 0 07052-070 –5 270 Figure 32. Smith Chart of LOIP (LOIN AC-Coupled to Ground) S11 and RFOUT S22 from 450 MHz to 6000 MHz 12 0 10 –5 TA = +25°C LOIP RETURN LOSS (dB) 8 TA = +85°C 6 4 2 –10 –15 RFOUT –20 0 0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 LO FREQUENCY (GHz) 4.5 5.0 5.5 6.0 Figure 30. SSB Output 1dB Compression Point (OP1dB) vs. LO Frequency (fLO) and Temperature –30 0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 FREQUENCY (GHz) 4.5 5.0 5.5 6.0 07052-073 –25 07052-071 1dB OUTPUT COMPRESSION (dBm) TA = –40°C Figure 33. Return Loss of LOIP (LOIN AC-Coupled to Ground) S11 and RFOUT S22 from 450 MHz to 6000 MHz Rev. D | Page 14 of 36 Data Sheet ADL5375 0 0 –5 SIDEBAND SUPPRESSION (dBc) CARRIER FEEDTHROUGH (dBm) –10 –10 TA = +85°C –15 –20 –25 TA = –40°C –30 –35 TA = +25°C –40 –45 –50 –20 TA = +85°C –30 TA = –40°C –40 –50 –60 –70 –55 2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0 LO FREQUENCY (GHz) Figure 34. Carrier Feedthrough vs. LO Frequency (fLO) and Temperature; Multiple Devices Shown 0 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0 Figure 37. Sideband Suppression vs. LO Frequency (fLO) and Temperature After Nulling at 25°C; Multiple Devices Shown 0 SECOND-ORDER DISTORTION, THIRD-ORDER DISTORTION, CARRIER FEEDTHROUGH, AND SIDEBAND SUPPRESSION –10 CARRIER FEEDTHROUGH (dBm) 0.5 LO FREQUENCY (GHz) 0 –20 –30 TA = –40°C –40 –50 TA = +85°C TA = +25°C –60 –80 0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0 LO FREQUENCY (GHz) Figure 35. Carrier Feedthrough vs. LO Frequency (fLO) and Temperature After Nulling at 25°C; Multiple Devices Shown 10 SSB OUTPUT POWER (dBm) –10 SIDEBAND –20 SUPPRESSION (dBc) 5 CARRIER FEEDTHROUGH (dBm) –30 –40 0 –50 –60 –5 –70 –10 –80 SECOND-ORDER DISTORTION (dBc) THIRD-ORDER DISTORTION (dBc) –90 –15 –100 0.2 07052-075 –70 1 4 BASEBAND DIFFERENTIAL INPUT VOLTAGE (V p-p) Figure 38. Second- and Third-Order Distortion, Carrier Feedthrough, Sideband Suppression, and SSB POUT vs. Baseband Differential Input Level (fLO = 900 MHz) 0 SECOND-ORDER DISTORTION, THIRD-ORDER DISTORTION, CARRIER FEEDTHROUGH, AND SIDEBAND SUPPRESSION 0 –10 SIDEBAND SUPPRESSION (dBc) TA = +25°C –80 –20 –30 TA = +25°C –40 TA = –40°C –50 TA = +85°C –60 –80 0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 LO FREQUENCY (GHz) 4.5 5.0 5.5 6.0 Figure 36. Sideband Suppression vs. LO Frequency (fLO) and Temperature; Multiple Devices Shown –10 10 SIDEBAND SUPPRESSION (dBc) –20 SSB OUTPUT POWER (dBm) 5 CARRIER FEEDTHROUGH (dBm) –30 –40 0 –50 –60 –5 –70 –80 –90 –100 0.2 07052-076 –70 07052-077 2.0 SSB OUTPUT POWER (dBm) 1.5 07052-078 1.0 –10 SECOND-ORDER DISTORTION (dBc) THIRD-ORDER DISTORTION (dBc) SSB OUTPUT POWER (dBm) 0.5 –15 1 4 BASEBAND DIFFERENTIAL INPUT VOLTAGE (V p-p) Figure 39. Second- and Third-Order Distortion, Carrier Feedthrough, Sideband Suppression, and SSB POUT vs. Baseband Differential Input Level (fLO = 2150 MHz) Rev. D | Page 15 of 36 07052-079 0 07052-074 –60 ADL5375 Data Sheet 10 0 –40 –50 –5 –60 SIDEBAND SUPPRESSION (dBc) –70 –80 THIRD-ORDER DISTORTION (dBc) –90 SECOND-ORDER DISTORTION (dBc) –10 –15 –100 0.2 1 4 BASEBAND DIFFERENTIAL INPUT VOLTAGE (V p-p) 0 SECOND-ORDER DISTORTION AND THIRD-ORDER DISTORTION (dBc) –10 –20 –30 THIRD-ORDER –40 TA = +25°C –50 –60 TA = +85°C –70 TA = –40°C 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0 LO FREQUENCY (GHz) –0.5 –50 –1.5 CARRIER FEEDTHROUGH (dBm) –60 –2.5 SECOND-ORDER DISTORTION (dBc) 1 10 TA = +85°C 6 4 2 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0 70 60 TA = –40°C 50 40 TA = +25°C 30 TA = +85°C 20 10 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0 Figure 44. OIP2 vs. LO Frequency (fLO) and Temperature (POUT ≈ −5 dBm at fLO = 900 MHz) –3.5 100 BASEBAND FREQUENCY (MHz) Figure 42. Second-Order Distortion, Carrier Feedthrough, Sideband Suppression, and SSB POUT vs. Baseband Frequency (fBB); fLO = 2140 MHz 2 –30 CARRIER FEEDTHROUGH (dBm) SSB OUTPUT POWER (dBm) 1 –40 –50 0 SIDEBAND SUPPRESSION (dBc) –60 THIRD-ORDER DISTORTION (dBc) –70 –1 –80 –90 07052-103 –70 8 Figure 43. OIP3 vs. LO Frequency (fLO) and Temperature (POUT ≈ −5 dBm at fLO = 900 MHz) SECOND-ORDER DISTORTION, THIRD-ORDER DISTORTION, CARRIER FEEDTHROUGH, AND SIDEBAND SUPPRESSION (dBc) –40 10 –20 SSB OUTPUT POWER (dBm) SECOND-ORDER DISTORTION, CARRIER FEEDTHROUGH, SIDEBAND SUPPRESSION SIDEBAND SUPPRESSION (dBc) TA = +25°C 12 LO FREQUENCY (GHz) 1.5 0.5 14 0 SSB OUTPUT POWER (dBm) –30 16 0 Figure 41. Second- and Third-Order Distortion vs. LO Frequency (fLO) and Temperature (Baseband I/Q Amplitude = 1 V p-p Differential) –20 TA = –40°C 18 LO FREQUENCY (GHz) 07052-081 0 20 0 SECOND-ORDER –80 22 0 OUTPUT SECOND-ORDER INTERCEPT (dBm) Figure 40. Second- and Third-Order Distortion, Carrier Feedthrough, Sideband Suppression, and SSB POUT vs. Baseband Differential Input Level (fLO = 3500 MHz) 24 07052-092 –30 26 07052-093 5 SSB OUTPUT POWER (dBm) –20 28 SSB OUTPUT POWER (dBm) CARRIER FEEDTHROUGH (dBm) SECOND-ORDER DISTORTION (dBc) –6 –4 –2 –2 0 2 4 6 LO AMPLITUDE (dBm) Figure 45. Second- and Third-Order Distortion, Carrier Feedthrough, Sideband Suppression, and SSB POUT vs. LO Amplitude (fLO = 900 MHz) Rev. D | Page 16 of 36 07052-082 –10 OUTPUT THIRD-ORDER INTERCEPT (dBm) 30 SSB OUTPUT POWER (dBm) 07052-080 SECOND-ORDER DISTORTION, THIRD-ORDER DISTORTION, CARRIER FEEDTHROUGH, AND SIDEBAND SUPPRESSION 0 Data Sheet ADL5375 CARRIER FEEDTHROUGH (dBm) 16 –40 SIDEBAND SUPPRESSION (dBc) 0 –50 THIRD-ORDER DISTORTION (dBc) –60 –1 14 12 QUANTITY 1 SSB OUTPUT POWER (dBm) SSB OUTPUT POWER (dBm) 4 2 SECOND-ORDER DISTORTION (dBc) –2 –80 –4 –2 2 0 6 4 LO AMPLITUDE (dBm) –20 0 –158.0 –157.8 –157.6 –157.4 –157.2 –157.0 –156.8 –156.6 NOISE (dBm/Hz) Figure 49. 20 MHz Offset Noise Floor Distribution at fLO = 900 MHz (I/Q Amplitude = 0 mV p-p with 1500 mV DC Bias) Figure 46. Second- and Third-Order Distortion, Carrier Feedthrough, Sideband Suppression, and SSB POUT vs. LO Amplitude (fLO = 2150 MHz) 2.0 12 CARRIER FEEDTHROUGH (dBm) 1.5 SSB OUTPUT POWER (dBm) 10 1.0 SIDEBAND SUPPRESSION (dBc) 0.5 –50 0 –0.5 –60 THIRD-ORDER DISTORTION (dBc) –1.0 SECOND-ORDER DISTORTION (dBc) 8 4 –70 2 –1.5 –80 –2.0 –6 –4 –2 0 2 4 6 6 0 –158.5 –158.3 –158.1 –157.9 –157.7 –157.5 –157.3 –157.1 LO AMPLITUDE (dBm) Figure 47. Second- and Third-Order Distortion, Carrier Feedthrough, Sideband Suppression, and SSB POUT vs. LO Amplitude (fLO = 3500 MHz) NOISE (dBm/Hz) 07052-095 –40 QUANTITY SSB OUTPUT POWER (dBm) –30 07052-084 SECOND-ORDER DISTORTION, THIRD-ORDER DISTORTION, CARRIER FEEDTHROUGH, AND SIDEBAND SUPPRESSION (dBc) 8 6 –70 –6 10 07052-094 –30 07052-083 SECOND-ORDER DISTORTION, THIRD-ORDER DISTORTION, CARRIER FEEDTHROUGH, AND SIDEBAND SUPPRESSION (dBc) 18 2 –20 Figure 50. 20 MHz Offset Noise Floor Distribution at fLO = 2140 MHz (I/Q Amplitude = 0 mV p-p with 1500 mV DC Bias) 0.230 9 8 0.220 VS = 5.25V VS = 5.0V QUANTITY 6 0.200 VS = 4.75V 0.190 5 4 3 0.180 2 0.170 0.160 –40 25 85 TEMPERATURE (°C) Figure 48. Power Supply Current vs. Temperature 0 –157.5 –157.1 –156.7 –156.3 NOISE (dBm/Hz) –155.9 –155.5 07052-104 1 07052-085 SUPPLY CURRENT (A) 7 0.210 Figure 51. 20 MHz Offset Noise Floor Distribution at fLO = 3500 MHz (I/Q Amplitude = 0 mV p-p with 500 mV DC Bias) Rev. D | Page 17 of 36 ADL5375 Data Sheet 0 –20 84 –30 82 –40 –50 80 CARRIER FEEDTHROUGH (dBm) –60 78 –70 76 74 CARRIER FEEDTHROUGH (dBm) –10 SSB OUTPUT POWER ISOLATION (dB) 86 –80 0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 –90 6.0 07052-096 SSB OUTPUT POWER ISOLATION (dB) 88 LO FREQUENCY (GHz) Figure 52. SSB POUT Isolation and Carrier Feedthrough with DSOP High Rev. D | Page 18 of 36 Data Sheet ADL5375 THEORY OF OPERATION CIRCUIT DESCRIPTION V-to-I Converter The ADL5375 can be divided into five circuit blocks: the LO interface, the baseband voltage-to-current (V-to-I) converter, the mixers, the differential-to-single-ended (D-to-S) stage, and the bias circuit. A block diagram of the device is shown in Figure 53. The differential baseband inputs (QBBP, QBBN, IBBN, and IBBP) present a high impedance. The voltages applied to these pins drive the V-to-I stage that converts baseband voltages into currents. The differential output currents of the V-to-I stages feed each of their respective mixers. The dc common-mode voltage at the baseband inputs sets the currents in the two mixer cores. Varying the baseband common-mode voltage influences the current in the mixer and affects overall modulator performance. The recommended dc voltage for the baseband common-mode voltage is 500 mV dc for the ADL5375-05 and 1500 mV for the ADL5375-15. LOIP LOIN PHASE SPLITTER IBBP IBBN QBBP Mixers RFOUT DSOP QBBN 07052-028 Σ Figure 53. Block Diagram The LO interface generates two LO signals in quadrature. These signals are used to drive the mixers. The I/Q baseband input signals are converted to currents by the V-to-I stages, which then drive the two mixers. The outputs of these mixers combine to feed the output balun, which provides a singleended output. The bias cell generates reference currents for the V-to-I stage. LO Interface The ADL5375 has two double-balanced mixers: one for the in-phase channel (I channel) and one for the quadrature channel (Q-channel). The output currents from the two mixers sum together into an internal load. The signal developed across this load is used to drive the D-to-S stage. D-to-S Stage The output D-to-S stage consists of an on-chip active balun that converts the differential signal to a single-ended signal. The balun presents 50 Ω impedance to the output (VOUT). Therefore, no matching network is needed at the RF output for optimal power transfer in a 50 Ω environment. Bias Circuit The LO interface consists of a polyphase quadrature splitter and a limiting amplifier. The LO input impedance is set by the polyphase splitter. Each quadrature LO signal then passes through a limiting amplifier that provides the mixer with a limited drive signal. The LO input can be driven single-ended or differentially. For applications above 3 GHz, improved OIP2 and LO leakage may result from driving the LO input differentially. An on-chip band gap reference circuit is used to generate a proportional-to-absolute temperature (PTAT) reference current for the V-to-I stage. DSOP The DSOP pin can be used to disable the output stage of the modulator. If the DSOP pin is connected to ground or left unconnected, the part operates normally. If the DSOP pin is connected to the positive voltage supply, the output stage is disabled and the LO leakage is also reduced. Rev. D | Page 19 of 36 ADL5375 Data Sheet BASIC CONNECTIONS IBBN IBBP COMM 19 COMM 20 IBBN IBBP 21 S1 B VPOS COMM 16 4 15 5 14 EXPOSED PADDLE QBBN 8 6 NC 7 COMM NC 3 17 13 VPS1 C4 0.1µF COMM RFOUT NC COMM RFOUT C1 100pF NC 12 C7 100pF Z1 ADL5375 2 11 LOIN 18 C2 100pF COMM LOIP 1 10 LOIP COMM COMM C6 100pF 9 DSOP QBBP A 22 24 C3 100pF 23 COMM C5 0.1µF VPOS VPS2 VPOS QBBN QBBP 07052-029 GND Figure 54. Basic Connections for the ADL5375 Figure 54 shows the basic connections for the ADL5375. POWER SUPPLY AND GROUNDING Pin VPS1 and Pin VPS2 should be connected to the same 5 V source. Each pin should be decoupled with a 100 pF and 0.1 μF capacitor. These capacitors should be located as close as possible to the device. The power supply can range between 4.75 V and 5.25 V. The ten COMM pins should be tied to the same ground plane through low impedance paths. The exposed paddle on the underside of the package should also be soldered to a ground plane with low thermal and electrical impedance. If the ground plane spans multiple layers on the circuit board, they should be stitched together with nine vias under the exposed paddle as illustrated in the Evaluation Board section. The AN-772 Application Note discusses the thermal and electrical grounding of the LFCSP (QFN) package in detail. BASEBAND INPUTS The baseband inputs (IBBP, IBBN, QBBP, and QBBN) should be driven from a differential source. The nominal drive level used in the characterization of the ADL5375 is 1 V p-p differential (or 500 mV p-p on each pin). All the baseband inputs must be externally dc biased. The recommended common-mode level is dependent on the version of the ADL5375.  ADL5375-05: 500 mV  ADL5375-15: 1500 mV LO INPUT The LO input is designed to be driven from a single-ended source. The LO source is ac-coupled through a series capacitor to the LOIP pin while the LOIN pin is ac-coupled to ground through a second capacitor. The typical LO drive level, which was used for the characterization of the ADL5375, is 0 dBm. Differential operation is also possible, in which case both sides of the differential LO source should be ac-coupled through a pair of series capacitors to the LOIP and LOIN pins. RF OUTPUT The RF output is available at the RFOUT pin (Pin 16), which can drive a 50 Ω load. The internal balun provides a low dc path to ground. In most situations, the RFOUT pin must be ac-coupled to the load. Rev. D | Page 20 of 36 Data Sheet ADL5375 OUTPUT DISABLE The ADL5375 incorporates an output disable pin feature that shuts down the output amplifier stage to isolate the modulator from the load. This output is disabled when the voltage on the DSOP exceeds 2 V. The output is enabled when the DSOP pin is either tied to ground or left unconnected. Asserting DSOP further reduces LO leakage (see Figure 27 and Figure 52) and drives the broadband noise of the device down to just above the KT thermal noise level. Asserting DSOP also reduces the supply current of the ADL5375 from 200 mA to 127 mA. The time delay between when DSOP pin going low and the output power being restored is approximately 200 ns. The time delay when DSOP going high and output being disabled is less than 100 ns. Rev. D | Page 21 of 36 ADL5375 Data Sheet APPLICATIONS INFORMATION IN inputs can be slightly different. Using Figure 55 as an example, after LO leakage nulling, the average dc level on IP and IN can be 500.25 mV and 499.75 mV. LO leakage results from minute dc offsets that occur on the differential baseband inputs. In an IQ modulator, non-zero differential offsets mix with the LO and result in LO leakage to the RF output. In addition to this effect, some of the signal power at the LO input couples directly to the RF output (this may be a result of bond-wire to bond-wire coupling or coupling through the silicon substrate). The net LO leakage at the RF output is the vector combination of the signals that appear at the output as a result of these two effects. The device’s nominal carrier feedthrough can be nulled by adding small external differential offset voltages on the I and Q inputs. Nulling the carrier feedthrough is a multistep process. Initially, with the I-channel offset held constant (at 0 mV), the Qchannel offset is varied until a minimum LO leakage level is obtained. This Q-channel offset voltage is then held constant, while the offset on the I-channel is adjusted until a new minimum is reached. Through two iterations of this process, the LO leakage can be reduced to an arbitrarily low level. This level is only limited by the available offset voltage steps and by the modulator’s noise floor. Figure 55 illustrates the typical relationship between LO leakage and dc offset at 1900 MHz. In this case, differential offset voltages of approximately +0.5 mV and −0.5 mV on the I and Q inputs, respectively, result in the lowest carrier feedthrough. It is important to note that the required offset nulling voltage changes in polarity and magnitude from device to device and overtemperature and frequency. To ensure that all devices in a mass production environment can be adequately nulled, an offset adjustment range of approximately ±10 mV should be provided. –57 Q OFFSET SWEEP I OFFSET SWEEP VIBBP = VIBBN = 1500 mV. It is often desirable to perform a one-time carrier null. This is usually performed at a given frequency. After this factory calibration, the IQ modulator operates over a frequency range on each side of the calibration frequency. The nulled LO leakage level degrades somewhat because the LO frequency is moved away from the calibration frequency. Despite this degradation, the overall LO leakage across a frequency band can be expected to be better than when no nulling is performed. This assumes an operating frequency band that is in the 30 MHz to 60 MHz range. LO leakage nulling is discussed further in AN-1039, Correcting Imperfections in IQ Modulators to Improve RF Signal Fidelity. SIDEBAND SUPPRESSION OPTIMIZATION Sideband suppression results from relative gain and relative phase offsets between the I-channel and Q-channel and can be suppressed through adjustments to those two parameters. Figure 56 illustrates how sideband suppression is affected by the gain and phase imbalances. 0 –10 2.5dB –20 1.25dB –30 0.5dB 0.25dB –40 0.125dB –50 0.05dB 0.025dB –60 0.0125dB –70 0dB –80 –67 –90 0.01 1 10 100 PHASE ERROR (Degrees) –72 Figure 56. Sideband Suppression vs. Quadrature Phase Error for Various Quadrature Amplitude Offsets –77 –82 –0.8 –0.6 –0.4 –0.2 0 0.2 0.4 0.6 I AND Q OFFSET VOLTAGE (µV) 0.8 1.0 Figure 55. Example of Typical Carrier Feedthrough vs. DC Offset Voltage It is important to note that the carrier feedthrough is not affected by the dc bias levels (also called the common-mode level) on the I and Q inputs. A differential offset voltage must be applied, so after nulling, the average voltage on the IP and 07052-031 –87 –92 –1.0 0.1 07052-032 CARRIER FEEDTHROUGH (dBm) –62 The same applies to the Q-channel. For the ADL5375-15, the same theory applies except that SIDEBAND SUPPRESSION (dBc) CARRIER FEEDTHROUGH NULLING Figure 56 underlines the fact that adjusting only one parameter improves the sideband suppression only to a point, unless the other parameter is also adjusted. For example, if the amplitude offset is 0.25 dB, improving the phase imbalance by better than 1° does not yield any improvement in the sideband suppression. For optimum sideband suppression, an iterative adjustment between phase and amplitude is required. The sideband suppression nulling can be performed either through adjusting the gain for each channel or through the modification of the phase and gain of the digital data coming from the baseband signal processor. Rev. D | Page 22 of 36 Data Sheet ADL5375 Sideband suppression is discussed further in AN-1100, Wireless Transmitter IQ Balance and Sideband Suppression, as well as in AN-1039, Correcting Imperfections in IQ Modulators to Improve RF Signal Fidelity. INTERFACING THE ADF4350 PLL TO THE ADL5375 With an output frequency range of 137.5 to 4.4 GHz, a high performance integrated VCO and an LO output power level that can be programmed from −4 dBm to +5 dBm, the ADF4350 wideband synthesizer is ideally suited to drive the ADL5375 LO port. of Figure 57. Because filtering of the third harmonic is most critical, and to ensure wide frequency range coverage, the 3 dB corner of the filters have been set to approximately 1.2~1.5 times the maximum desired LO frequency. A Chebyshev filter topology at 100 Ω differential source impedance and 50 Ω differential load impedance was used for optimal performance. 3.3V 120pF 120pF 0.1µF Care must be taken to adequately suppress the harmonics of the LO signal from the PLL. VCOs typically have a third harmonic power of approximately −10 dBc. A large third harmonic on the LO degrades the quality of the quadrature generation inside the IQ Modulator. The third harmonic should be suppressed to a level of –30 dBc or lower to prevent quadrature degradation. So approximately 20 dB of attenuation is required to get the third harmonic below −30 dBc. Figure 57 shows PLL modulator interfaces schematic that for this operation at four different frequencies, and Table 4 shows the optimized components value C1a L1 RFOUTA+ 12 R1 ZBIAS C1c L1 RFOUTA– 13 C1a ADF4350 C2a L2 C2c L2 C2a C3a 1nF 3 LOIP C3c 1nF 4 LOIN C3a ADL5375 07052-111 ZBIAS Figure 57. PLL-Modulator Interface Schematic Table 4. PLL Modulator Interface Components Values (DNI = Do Not Insert) Frequency Range (MHz) 500 to 1300 850 to 2450 1250 to 2800 2800 to 4400 Zbias (nH) 27 19 7.5 3.9 R1 (Ω) 100 100 100 100 L1 (nH) 3.9 2.7 0Ω 0Ω L2 (nH) 3.9 2.7 3.6 0Ω C1a (pF) DNI 3.3 DNI DNI Rev. D | Page 23 of 36 C1c (pF) 4.7 DNI DNI DNI C2a DNI 4.7 2.2 DNI C2c (pF) 5.6 DNI DNI DNI C3a (pF) DNI 3.3 1.5 DNI C3c (pF) 3.3 DNI DNI DNI ADL5375 Data Sheet IOUT1P The ADL5375 evaluation board can be reconfigured for differential drive and also includes component pads in its LO path to accommodate a harmonic filter. The ADF4350 evaluation board can also be configured to provide a differential output and can be connected directly to the ADL5375 evaluation board. Optimizing the interface between a PLL LO and I/Q modulator is discussed further in CN-0134 Broadband Low EVM Direct Conversion Transmitter: How to Optimize the Interface Between a PLL LO and I/Q Modulator. DAC MODULATOR INTERFACING Driving the ADL5375-05 with a TXDAC® The ADL5375-05 is designed to interface with minimal components to members of the Analog Devices, Inc. TxDAC families. These dual-channel differential current output DACs feature an output current swing from 0 mA to 20 mA. The interface described in this section can be used with any DAC that has a similar output. 67 21 RBIP 50Ω IOUT1N The output power from the ADF4350 can be set to −4 dBm, −1 dBm,+2 dBm, and +5 dBm using Register 4 Bits[D2:D1] and −6 dBm to +7 dBm LO drive level for ADL5375 is recommended. IOUT2N 66 RBIN 50Ω 22 59 9 IBBP IBBN QBBN RBQN 50Ω IOUT2 58 RBQP 50Ω 10 QBBP 07052-112 If the physical distance between the PLL and the IQ modulator is significant, the filter should be placed adjacent to the IQ modulator, and two 50 Ω traces should be run between the devices (since there is a 50 Ω impedance looking from each of the filter inputs back to each of the PLL outputs). ADL5375-05 AD9122 Figure 58. Interface Between the AD9122 and ADL5375-05 with 50 Ω Resistors to Ground to Establish the 500 mV DC Bias for the ADL5375-05 Baseband Inputs The AD9122 output currents have a swing that ranges from 0 mA to 20 mA. With the 50 Ω resistors in place, the ac voltage swing going into the ADL5375-05 baseband inputs ranges from 0 V to 1 V. A full-scale sine wave out of the AD9122 can be described as a 1 V p-p single-ended (or 2 V p-p differential) sine wave with a 500 mV dc bias. Limiting the AC Swing There are situations in which it is desirable to reduce the ac voltage swing for a given DAC output current. This can be achieved through the addition of another resistor to the interface. This resistor is placed in the shunt between each side of the differential pair, as shown in Figure 59. It has the effect of reducing the ac swing without changing the dc bias already established by the 50 Ω resistors. ADL5375-05 AD9122 An example of an interface using the AD9122 TxDAC is shown in Figure 58. The baseband inputs of the ADL5375-05 require a dc bias of 500 mV. The nominal midscale current on each of the outputs of the AD9122 is 10 mA. Therefore, a single 50 Ω resistor to ground from each of the DAC outputs results in an average current of 10 mA flowing through each of the resistors, thus producing the desired 500 mV dc bias for the inputs to the ADL5375-05. IOUT1P 67 21 RBIP 50Ω IOUT1N IOUT2N 66 RBIN 50Ω IOUT2 RLI 100Ω 22 9 59 RBQN 50Ω 58 RBQP 50Ω IBBP IBBN QBBN RLQ 100Ω 10 QBBP Figure 59. AC Voltage Swing Reduction Through the Introduction of a Shunt Resistor Between Differential Pair Rev. D | Page 24 of 36 07052-113 The two pull-up inductors of the Zbias provide two 50 Ω source impedances in combination with R1 resistor in parallel for the filter. While the ADL5375 is specified to be driven by a singleended LO, the LOIP and LOIN input pins are naturally differential. Therefore, the differential LO drive from the ADF4350 is more desirable. Data Sheet ADL5375 The value of this ac voltage swing limiting resistor is chosen based on the desired ac voltage swing. Figure 60 shows the relationship between the swing-limiting resistor and the peakto-peak ac swing that it produces when 50 Ω bias-setting resistors are used. The differential peak-to-peak swing at the modulator input is 0 36 [2 × R B × R L ] VSIGNAL = I FS × [2 × R B + R L ] 30 –20 24 GROUP DELAY –30 18 –40 12 –50 6 GROUP DELAY (ns) MAGNITUDE (dB) MAGNITUDE –10 2.0 1.6 1 10 07052-037 0 100 –60 1.4 FREQUENCY (MHz) 1.2 Figure 62. Frequency Response for DAC Modulator Interface with 10 MHz Third-Order Bessel Filter 1.0 0.8 Complex IF Operation 0.6 The ADL5375 can be used with a DAC, generating a complexIF (CIF), as well as a zero-IF signal (ZIF). The −1 dB bandwidth of the ADL5375 is approximately more than 400 MHz (Figure 63 and Figure 64 show the baseband frequency response of the ADL5375, facilitating high CIF and providing sufficient flat bandwidth for digital predistortion (DPD) algorithms). Using a CIF places the LO leakage and the undesired sideband outside the signal band at the modulator output where they can be easily removed with a bandpass filter. 0 10 100 1000 10000 RL (Ω) 07052-035 0.2 Figure 60. Relationship Between the AC Swing-Limiting Resistor and the Peak-to-Peak Voltage Swing with 50 Ω Bias-Setting Resistors Filtering It is necessary to place an antialiasing filter between the DAC and modulator to filter out Nyquist images, common mode noise, and broadband DAC noise. The interface for setting up the biasing and ac swing discussed in the Limiting the AC Swing section lends itself well to the introduction of such a filter. The filter can be inserted between the dc bias setting resistors and the ac swing-limiting resistor. With this configuration, the dc bias setting resistors and the signal scaling resistors conveniently set the source and load resistances for the filter. Figure 61 shows a third-order, Bessel low-pass filter with a 3 dB frequency of 10 MHz. Matching input and output impedances make the filter design easier, so the shunt resistor chosen is 100 Ω, producing an ac swing of 1 V p-p differential. The frequency response of this filter is shown in Figure 62. AD9122 350.1pF C2I LNI 771.1nH –4 –5 IBBN 59 9 QBBN RBQN 50Ω 58 RBQP 50Ω 53.62pF C1Q 350.1pF LPQ C2Q 771.1nH RSLQ 100Ω 10 QBBP 100 1k Figure 63. ADL5375-05 Baseband Frequency Response Normalized to Response for 1 MHz 22 LNQ 771.1nH 10 BASEBAND FREQUENCY (MHz) RSLI 100Ω IOUT2N IOUT2 –3 07052-114 IOUT1N 53.62pF C1I –2 1 IBBP RBIN 66 50Ω –1 –6 21 IOUT1P RBIP 50Ω 0 ADL5375-05 LPI 771.1nH 67 1 Figure 61. DAC Modulator Interface with 10 MHz Third-Order, Bessel Filter Rev. D | Page 25 of 36 07052-115 0.4 BASEBANE FREQUENCY RESPONSE (dB) DIFFERENTIAL SWING (V p-p) 1.8 ADL5375 Data Sheet 3.5 0 –5 MAGNITUDE (dB) –2 –3 2.5 –10 2.0 –15 1.5 GROUP DELAY (ns) 3.0 –1 1.0 –4 –20 0.5 –5 1 10 100 1k BASEBAND FREQUENCY (MHz) Figure 64. ADL5375-15 Baseband Frequency Response Normalized to Response for 1 MHz Even a purely differential filter can work well, splitting the filter capacitors into two and grounding at filter topology as like C2 and C4 in Figure 65 divert common mode currents to ground and result in additional common-mode rejection of high frequency signals to a purely differential filter. C2PI 22pF IOUT1P 67 RBIP 50Ω IOUT1N 66 RBIN 50Ω C1I 3.6pF L1PI 33nH L1NI 33nH C2NI 22pF L2PI 33nH C3I 6pF C4PI 3pF Level-shifting can be achieved with either a passive network or an active circuit. A passive network of resistors is shown in Figure 67. In this network, the dc bias of the DAC remains at 500 mV while the input to the ADL5375-15 is 1500 mV. It should be noted that this passive level-shifting network introduces approximately 2 dB of loss in the ac signal. IOUT1P IBBP IBBN IOUT1N C4NI 3pF IOUT2N IOUT2N 59 RBQN 50Ω IOUT2 RBQP 58 50Ω C1Q 3.6pF L1NQ 33nH L1PQ 33nH C2PQ 22pF L2NQ 33nH C3Q 6pF C4NQ 3pF 9 IOUT2 RSLQ 100Ω 10 L2PQ 33nH QBBN QBBP C4PQ 3pF Figure 65. Recommended DAC Modulator Interface Topology with FC = 300 MHz Fifth-Order, Butterworth Filter 21 RBIP 45.3Ω RLIP 3480Ω RBIN 66 45.3Ω RSIP RLIN 1kΩ 3480Ω 59 RSQN 1kΩ 5V 22 9 RBQN 45.3Ω RLQN 3480Ω RBQP 58 45.3Ω RSQP RLQP 1kΩ 3480Ω IBBP IBBN QBBN 5V 10 QBBP Figure 67. Passive Level-Shifting Network For Biasing ADL5375-15 from TxDAC 07052-117 C2NQ 22pF ADL5375-15 RSIN 1kΩ 67 RSLI 100Ω 22 L2NI 33nH The ADL5375-15 requires a 1500 mV dc bias and therefore requires a slightly more complex interface that performs a dc level shift on the baseband signals. It is necessary to level-shift the DAC output from a 500 mV dc bias to the 1500 mV dc bias that the ADL5375-15 requires. AD9122 ADL5375-05 21 FREQUENCY (Hz) Figure 66. Frequency Response for DAC Modulator Interface with 300 MHz Fifth-Order Butterworth Filter Driving the ADL5375-15 with a TXDAC In CIF applications, a low-pass filter between the DAC and modulator is still favored to filter out images, noises discussed in the Filtering section as well as to preserve dc bias level from DAC to ADL5375-05. Figure 65 shows a fifth order Butterworth filter with a 300 MHz corner frequency and the frequency response of this filter is shown in Figure 66. AD9122 0 500M 100M 07052-119 –6 10M 07052-118 –25 1M 07052-116 BASEBANE FREQUENCY RESPONSE (dB) 4.0 0 1 The active level shifting circuit involves the use of the ADA4938 dual-differential amplifier. This device has a VOCM pin that sets the output dc bias. Through this pin, the output commonmode of the amplifier can be easily set to the requisite 1.5 V for biasing the ADL5375-15 baseband inputs. Rev. D | Page 26 of 36 Data Sheet ADL5375 Using the AD9122 DAC For Carrier Feedthrough and Unwanted Sideband Nulling 07052-121 The AD9122 features an auxiliary DACs (Register 0x42, Register 0x43, Register 0x46, and Register 0x47) or the digital dc offset adjustments (Register 0x3C through Register 0x3F) that can be used to null the carrier feedthrough by applying the dc offset voltage at each main DAC channels. Unwanted sideband suppression can be done by adjusting the I/Q phase (Register 0x38 through Register 0x3B) and DAC FS (Register 0x40 and Register 0x44) registers. GSM/EDGE OPERATION The performance of the ADL5375-05 in a Multi-Carriers GSM/EDGE environment is shown in Figure 68 and Figure 69. Figure 69. ADL5375-05 GSM/EDGE(8-PSK) 6 Carriers Adjacent and Alternate Channel Power Performance at 950 MHz; Output Power(1 Carrier/100 KHz) = −24.4 dBm LO Drive = 0 dBm Figure 68 illustrates the 6 MHz offset noise floor of the ADL5375-05 at the six carriers MCGSM/EDGE(8-PSK) operating condition vs. output power, and Figure 69 demonstrates IMD performance of the same six carriers MCGSM/EDGE(8-PSK) for the ADL5375-05 at 950 MHz. It is configured, as shown at Figure 65, for this measurement. The AD9122 is set at −3 dB digital FS back off, FDATA = 368.64 MSPS, 2× interpolation, and PLL and inverse sync off. Complex IF at 174.32 MHz is generated at NCO of the AD9122 and fed into the ADL5375-05 through a fifth order Butterworth filter. Special care must be taken not to be affected by the noise power of images through proper DAC setup at the selection of IF Frequency, FDATA, FDAC, and so on for such a low IMD and noise level measurement. Be sure to load clean LO signals and use equipment that allows enough dynamic range capability and noise correction feature to compensated the noise originated by equipment itself. The performance of the ADL5375 in a GSM/EDGE environment is shown in Figure 70 and Figure 71. –104.5 –75 –76 –105.0 –77 –105.5 –78 –79 –106.0 –80 –106.5 –81 –82 –107.0 –83 6MHz OFFSET NOISE FLOOR (dBm/100kHz) –74 –30 –28 –26 –24 –22 OUTPUT POWER (1 CARRIER/100kHz) (dBm) –101 –102 ADL5375-15 –103 –104 ADL5375-05 –105 –106 –107 –5 –4 –3 –2 OUTPUT POWER (dBm) –1 0 Figure 70. GSM/Edge (8-PSK) 6 MHz Offset Noise at 940 MHz vs. Output Power, LO Drive = 0 dBm 07052-120 –107.5 –84 –100 07052-122 6MHz OFFSET NOISE FLOOR (dBc/100kHz) –99 –104.0 –73 6MHz OFFSET NOISE FLOOR (dBc/100kHz) Figure 70 illustrates the 6 MHz offset noise of the ADL5375-05 and ADL5375-15 vs. output power at 940 MHz. Figure 71 demonstrates how the 6 MHz offset noise is affected by variations in LO drive level for both version of the ADL5375 at 940 MHz. Figure 68. ADL5375-05 GSM/EDGE(8-PSK) 6 Carriers 6 MHz Offset Noise Floor at 950 MHz vs Output Power(1 Carrier/100 KHz), LO Drive = 0 dBm Rev. D | Page 27 of 36 ADL5375 Data Sheet –59 ADJACENT AND ALTERNATE CHANNEL POWER RATIOS (dB) –61 –102 –103 –104 –105 ADL5375-15 –106 –107 ADL5375-05 –108 –63 –65 –67 –69 ADJACENT CPR –71 –73 –75 –77 –79 ALTERNATE CPR –81 –83 1 2 3 4 5 6 7 LO DRIVE (dBm) –87 –20 –14 –12 –10 –8 –6 –4 Figure 73. ADL5375-15 Single-Carrier W-CDMA Adjacent and Alternate Channel Power vs. Output Power at 2140 MHz; LO Power = 0 dBm W-CDMA OPERATION The ADL5375 is suitable for W-CDMA operation. Figure 72 and Figure 73 show the adjacent and alternate channel power ratios for the ADL5375-05 and ADL5375-15, respectively, at an LO frequency of 2140 MHz. Figure 72 and Figure 73 show that both versions of the ADL5375 are able to deliver about or better than −73 dB ACPR at an output power of −10 dBm. Figure 74 illustrate the sensitivity of the EVM to variations in LO drive at 2140 MHz for the ADL5375-05 and ADL5375-15. 6.0 –59 –61 5.5 –63 5.0 –65 4.5 –67 COMPOSITE EVM (%) ADJACENT AND ALTERNATE CHANNEL POWER RATIOS (dB) –16 OUTPUT POWER (dBm) Figure 71. GSM/Edge (8-PSK) 6 MHz Offset Noise at 940 MHz vs. LO Drive, Output Power = 0 dBm ADJACENT CPR –69 –71 –73 –75 –77 –79 4.0 ADL5375-15 3.5 3.0 ADL5375-05 2.5 2.0 1.5 –81 1.0 ALTERNATE CPR –83 0.5 –85 –18 –16 –14 –12 –10 –8 –6 –4 OUTPUT POWER (dBm) Figure 72. ADL5375-05 Single-Carrier W-CDMA Adjacent and Alternate Channel Power vs. Output Power at 2140 MHz; LO Power = 0 dBm 0 –6 07052-124 –87 –20 –18 –4 –2 0 LO DRIVE (dBm) 2 4 6 07052-125 0 07052-110 –85 –109 07052-123 6MHz OFFSET NOISE FLOOR (dBc/100kHz) –101 Figure 74. Single Carrier W-CDMA Composite EVM vs. LO Drive at 2140 MHz; Output Power = −10 dBm The EVM exhibits improvements with a local feedthrough nulling operation. Rev. D | Page 28 of 36 Data Sheet ADL5375 LO GENERATION USING PLLS Analog Devices has a line of PLLs that can be used for generating the LO signal. Table 5 lists the PLLs together with their maximum frequency and phase noise performance. Table 5. Analog Devices PLL Selection Part ADF4110 ADF4111 ADF4112 ADF4113 ADF4116 ADF4117 ADF4118 Frequency, fIN (MHz) 550 1200 3000 4000 550 1200 3000 Phase Noise at 1 kHz Offset and 200 kHz PFD (dBc/Hz) −91 at 540 MHz −87 at 900 MHz −90 at 900 MHz −91 at 900 MHz −89 at 540 MHz −87 at 900 MHz −90 at 900 MHz Table 6. ADF4350 Phase Noise at Various Frequencies Frequency (MHz) 2200 3300 4400 MODULATOR/DEMODULATOR OPTIONS Table 8 lists other Analog Devices modulators and demodulators. Table 8. Modulator/Demodulator Options The ADF4350 is a fractional-N PLL which offers broadband operation from 137.5 MHz to 4.4 GHz and contains an integrated high performance VCO. Part ADF4350 ADF4350 ADF4350 All DACs listed have nominal bias levels of 0.5 V and use the same simple DAC modulator interface that is shown in Figure 75. Phase Noise at 10 kHz (dBc/Hz) 25 MHz PFD, 40 KHz Loop BW −97 −92 −90 TRANSMIT DAC OPTIONS The AD9122 recommended in the previous sections of this data sheet is by no means the only DAC that can be used to drive the ADL5375. There are other appropriate DACs, depending on the level of performance required. Table 7 lists the dual TxDAC offered by Analog Devices. Part No. Modulator/ Demodulator Frequency Range (MHz) AD8345 AD8346 AD8349 ADL5390 Modulator Modulator Modulator Modulator 140 to 1000 800 to 2500 700 to 2700 20 to 2400 ADL5385 ADL5386 Modulator Modulator 50 to 2200 50 to 2200 ADL5370 ADL5371 ADL5372 ADL5373 ADL5374 AD8347 AD8348 ADL5387 ADL5380 ADL5382 AD8340 Modulator Modulator Modulator Modulator Modulator Demodulator Demodulator Demodulator Demodulator Demodulator Vector modulator Vector modulator 300 to 1000 500 to 1500 1500 to 2500 2300 to 3000 3000 to 4000 800 to 2700 50 to 1000 50 to 2000 400 to 6000 700 to 2700 700 to 1000 AD8341 Table 7. Dual TxDAC Selection Part AD9709 AD9761 AD9763 AD9765 AD9767 AD9773 AD9775 AD9777 AD9776 AD9778 AD9779A Resolution (Bits) 8 10 10 12 14 12 14 16 12 14 16 Update Rate (MSPS Minimum) 125 40 125 125 125 160 160 160 1000 1000 1000 Rev. D | Page 29 of 36 1500 to 2400 Comments External quadrature Includes VVA and AGC ADL5375 Data Sheet EVALUATION BOARD 0 Ω resistor in the R2 pad, the modulator’s output can be fed to the RF driver amplifier. Populated RoHS-compliant evaluation boards are available for evaluation of the ADL5375. The ADL5375 package has an exposed paddle on the underside. This exposed paddle should be soldered to the board for good thermal and electrical grounding. The evaluation board is designed to minimize LO feedthrough to RFOUT through PCB by placing LO block on the underside. And it can be configured to allow differential LO driving through balun or direct interfacing to the PLL evaluation board. It also reserves component pads in its LO path to accommodate a harmonic filter. One side placement of baseband inputs is to interface directly to DAC evaluation board. The ADL5375 evaluation board also includes an RF driver amplifier. The modulator output can be measured directly at the MOD_OUT SMA connector. Alternatively, by removing R1, and installing a The evaluation board ships, installed with an ADL5320 driver amplifier (400 MHz to 2700 MHz RF driver amplifier). This device requires external matching components (C100 and C101) and is tuned by default for operation from 1805 MHz to 2170 MHz. For details on tuning component values for other frequencies, please refer to the ADL5320 data sheet (the driver amplifier section of the ADL5375 Evaluation Board is identical to the ADL5320 Evaluation Board). For higher frequency operation, the ADL5320 should be replaced by the ADL5321, which is specified to operate from 2.3 GHz to 4 GHz. If a broadband matched device is desired, the ADL5601 (15 dB) or ADL5602 (20 dB) broadband gain blocks can be used. IBBN IBBP AGND AGND R7 100Ω C3 100pF AGND LOIN C7 100pF COMM R17* AGND 0Ω 2 3 4 C10 10nF AGND (2) C11 22pF AGND EXPOSED PADDLE NC 6 R1*** D.N.I C1 100pF λ1 C100 (C3) 0.5pF AGND 13 NC 1 2 AGND RFOUT L1 15nH R2 0Ω RFOUT 15 NC COMM 14 U1 5 COMM RFIN 16 VPS1 3 λ2 λ3 λ4 C12 22pF AMP_OUT C101 (C7) 1.5pF AGND AGND AGND AGND GND BLACK AGND JOHANSON TECHNOLOGY** T2 3600BL14M050 T2A 5400BL15B050 * SINGLE-ENDED LO DRIVING AT LOIP. ** DIFFERENTIAL LO DRIVING AT LOIP WITH T1 OR T2. *** ADL5320 STAND-ALONE TEST. C9 10µF AGND AGND AGND R12 100Ω QBBN AGND QBBP AGND Figure 75. ADL5375 Evaluation Board Schematic Rev. D | Page 30 of 36 07052-126 1 VPOS_AMP RED 12 4 ADL5375 3 11 5 R13 0Ω COMM NC 6 17 COMM AGND R20 D.N.I LOIP 18 9 R22** D.N.I TC1-1-43A+** 6 1 T1 AGND AMP_IN MOD_OUT 2 10 R19 D.N.I VPOS AGND 1 QBBP AGND R16 D.N.I C16 D.N.I COMM QBBN LOIN C17 D.N.I C6 100pF 8 AGND C18 D.N.I 3 7 LOIP DSOP 4 AGND C4 0.1µF U2 ADL5320 R21* 0Ω AGND R18 0Ω DSOP YELLOW NC R14 0Ω R6 10kΩ COMM R15 49.9Ω B 24 S1 VPS2 C5 0.1µF AGND 23 COMM IBBN 22 IBBP 21 COMM 20 COMM 19 VPOS VPOS RED A VPOS C2 100pF Data Sheet ADL5375 Table 9. Evaluation Board Description and Configuration Options Component VPOS, GND Test Points S1 Switch, R6, R15 Description Power supply and ground test points for clip leads DSOP output disable select R7, R12 C16 to C18, R14, R16, R18, R19 AC limiting resistors LO input filter components Default Condition/Option Settings Red = 5 V, black = GND Position A = output enabled Position B = output disabled R15 = 49.9 Ω (0603) R6 = 10 kΩ (0603) R7, R12 = 100 Ω (0603) R14 , R18 = 0 Ω (0603) LO driving capacitor Single-ended local oscillator input R16, R19, C16 to C18 = open (0603) C6, C7 = 100 pF (0402) R17 = 0 Ω (0603) Optional differential LO input at LOIN R20 = open (0402) R21 = 0 Ω (0402) R22 = open (0603) T1, T2, T2A = open R16, R19 = 0 Ω (0603) C6, C7 LOIP SMA, R17, R20, R21, R22, T1, T2, T2A LOIN SMA, R16, R17, R19, R20, R21, R22, T1, T2, T2A R20, R21 = 0 Ω (0402) R17, R22 = open (0603) T1, T2, T2A = open LOIP SMA, T1 (or T2, T2A), R17, R20, R21, R22 Optional differential LO driving with Balun at LOIP R17 = open (0603) R20, R21 = open (0402) R22 = 0 Ω (0603) T1 = TC1-1-43A+ or C100, C101 Frequency tuning capacitors for RF driver amplifier Refer to the ADL5320 datasheet for the exact position according to the frequency C1 R2 AC-coupling capacitor connects ADL5375 RF output to MOD_OUT RF connector or to ADL5320 RF input Resistor connects ADL5375 RF output to MOD_OUT (AMP_IN) SMA To check ADL5375 performance itself, a 0 Ω should be inserted at R1 and open R2. To check ADL5320 performance itself, a 0 Ω should be inserted at R1 and R2 Resistor connects ADL5375 RF output to ADL5320 RF input U1 U2 L1 C2, C3, C4, C5, C9, C10, C11 ADL5375 quadrature modulator SOT-89 RF driver amplifier DC bias Inductor Power supply bypassing capacitors R13 Resistor to share power supply between the ADL5375 and the ADL5320. To turn on the ADL5320, a 0 Ω resistor should be installed in this location. EP Exposed Paddle. Connect to the ground plane via a low impedance path. R1 Rev. D | Page 31 of 36 T2 = 3600BL14M050 or T2A = 5400BL15B050 Tuning for 1805 MHz to 2170 MHz C100 = 0.5 pF (0402) C101 = 1.5 pF (0402) C1 = 100 pF (0402) R1 = open (0402) R2 = 0 Ω (0402) ADL5375-05 or ADL5375-15 ADL5320 L1 = 15 nH(0603) C2, C3 = 100 pF (0402) C4, C5 = 0.1 µF (0402) C9 = 10 µF (1206) C10 = 10 nF (0603) C11 = 22 pF (0603) R13 = 0 Ω (0603) ADL5375 Data Sheet Thermal Grounding and Evaluation Board Layout The package for the ADL5375 features an exposed paddle on the underside that should be well soldered to a low thermal and electrical impedance ground plane. This paddle is typically soldered to an exposed opening in the solder mask on the evaluation board. Figure 78 illustrates the dimensions used in the layout of the ADL5375 footprint on the ADL5375 Evaluation Board (1 mil. = 0.0254 mm). Notice the use of nine via holes on the exposed paddle. These ground vias should be connected to all other ground layers on the evaluation board to maximize heat dissipation from the device package. 12 mil. 25 mil. 23 mil. 07052-127 82 mil. Figure 76. Evaluation Board Layout, Top Layer 12 mil. 98.4 mil. 133.8 mil. 07052-046 19.7 mil. Figure 78. Dimensions for Evaluation Board Layout for the ADL5375 Package 07052-128 Under these conditions, the thermal impedance of the ADL5375 was measured to be approximately 30°C/W in still air. Figure 77. Evaluation Board Layout, Bottom Layer Rev. D | Page 32 of 36 Data Sheet ADL5375 CHARACTERIZATION SETUP AEROFLEX IFR 3416 250kHz TO 6GHz SIGNAL GENERATOR ROHDE & SCHWARTZ SPECTRUM ANALYZER FSU 20Hz TO 8GHz RF OUT FREQ 1MHz LEVEL 0dBm BIAS 0.5V GAIN 0.5V BIAS 0.5V GAIN 0.5V LO CONNECT TO BACK OF UNIT I OUT I/AM Q OUT Q/FM 90° RF IN 0° Q I +6dBm AGILENT 34401A MULTIMETER MOD TEST SETUP 0.194 ADC IP MOD LO VPOS +5V IN QP AGILENT E3631A POWER SUPPLY OUT OUTPUT QN VPOS GND 0.194A ±25V 6V + – + COM – 07052-049 5.000 Figure 79. Characterization Bench Setup The primary setup used to characterize the ADL5375 is shown in Figure 79. This setup was used to evaluate the product as a single-sideband modulator. The aeroflex signal generator supplied the LO and differential I and Q baseband signals to the device under test (DUT). The typical LO drive was 0 dBm. The I-channel is driven by a sine wave, and the Q-channel is driven by a cosine wave. The lower sideband is the single-sideband (SSB) output. The majority of characterization for the ADL5375 was performed using a 1 MHz sine wave signal with a 500 mV (ADL5375-05) or 1500 mV (ADL5375-15) common-mode voltage applied to the baseband signals of the DUT. The baseband signal path was calibrated to ensure that the VIOS and VQOS offsets on the baseband inputs were minimized as close as possible to 0 V before connecting to the DUT. See the Carrier Feedthrough Nulling section for the definitions of VIOS and VQOS. Rev. D | Page 33 of 36 ADL5375 Data Sheet TEKTRONIX AFG3252 DUAL FUNCTION ARBITRARY FUNCTION GENERATOR CH2 1MHz AMPL 500mV p-p PHASE 90° 0° CH2 OUTPUT CH1 1MHz AMPL 500mV p-p PHASE 0° CH1 OUTPUT AEROFLEX IFR 3416 250kHz TO 6GHz SIGNAL GENERATOR I Q RF OUT LEVEL 0dBm LO 90° SINGLE-TO-DIFFERENTIAL CIRCUIT BOARD AGILENT E3631A POWER SUPPLY MOD TEST RACK 5.000 0.350A 6V VPOS ++5V– + Q IN AC ±25V COM +5V IP IP VPOSB VPOSA IN IN TSEN –5V GND AGND IN1 IN1 VN1 VP1 I IN DCCM VPOS +5V MOD CHAR BD Q IN DCCM – I IN AC QP OUTPUT OUT QN GND VPOS QP QN AGILENT E3631A POWER SUPPLY 0.500 LO ROHDE & SCHWARTZ SPECTRUM ANALYZER FSU 20Hz TO 8GHz 0.010A 6V + ±25V – + COM – RF IN VCM = 0.5V AGILENT 34401A MULTIMETER 07052-050 0.200 ADC Figure 80. Setup for Baseband Frequency Sweep and Undesired Sideband Nulling The setup used to evaluate baseband frequency sweep and undesired sideband nulling of the ADL5375 is shown in Figure 80. The interface board has circuitry that converts the single-ended I input and Q input from the arbitrary function generator to differential I and Q baseband signals with a dc bias of 500 mV (ADL5375-05) or 1500 mV (ADL5375-15). Undesired sideband nulling was achieved through an iterative process of adjusting amplitude and phase on the Q-channel. See Sideband Suppression Optimization section for a detailed description on sideband nulling. Rev. D | Page 34 of 36 Data Sheet ADL5375 OUTLINE DIMENSIONS 0.30 0.25 0.18 0.50 BSC PIN 1 INDICATOR 24 19 18 1 EXPOSED PAD TOP VIEW 0.80 0.75 0.70 0.50 0.40 0.30 13 12 2.65 2.50 SQ 2.45 6 7 0.25 MIN BOTTOM VIEW 0.05 MAX 0.02 NOM FOR PROPER CONNECTION OF THE EXPOSED PAD, REFER TO THE PIN CONFIGURATION AND FUNCTION DESCRIPTIONS SECTION OF THIS DATA SHEET. COPLANARITY 0.08 SEATING PLANE 04-12-2012-A PIN 1 INDICATOR 4.10 4.00 SQ 3.90 0.20 REF COMPLIANT TO JEDEC STANDARDS MO-220-WGGD. Figure 81. 24-Lead Lead Frame Chip Scale Package [LFCSP_WQ] 4 mm × 4 mm Body, Very Very Thin Quad (CP-24-7) Dimensions shown in millimeters ORDERING GUIDE Model 1 ADL5375-05ACPZ-R7 ADL5375-05ACPZ-R2 ADL5375-05-EVALZ ADL5375-15ACPZ-R7 ADL5375-15ACPZ-WP ADL5375-15-EVALZ 1 Temperature Range −40°C to +85°C −40°C to +85°C −40°C to +85°C −40°C to +85°C Package Description 24-Lead LFCSP_WQ, 7” Tape and Reel 24-Lead LFCSP_WQ, 7” Tape and Reel Evaluation Board 24-Lead LFCSP_WQ, 7” Tape and Reel 24-Lead LFCSP_WQ, Waffle Pack Evaluation Board Z = RoHS Compliant Part. Rev. D | Page 35 of 36 Package Option CP-24-7 CP-24-7 Ordering Quantity 1,500 250 CP-24-7 CP-24-7 1,500 64 ADL5375 Data Sheet NOTES ©2007–2014 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. D07052-0-6/14(D) Rev. D | Page 36 of 36