FEATURES
FUNCTIONAL BLOCK DIAGRAM
−3 dB bandwidth of 4.3 GHz
High performance (HP), low power (LP), and power down modes
Preset 20 dB gain can be reduced by adding external resistors
Channel to channel gain error: 0.04 dB at 500 MHz
Channel to channel phase error: 0.6° at 500 MHz
Differential or single-ended input to differential output
Internally dc-coupled inputs and outputs
Low noise input stage: 7.4 dB noise figure at 500 MHz
Low broadband distortion for supply = 5 V, HP mode, and 2 V p-p
200 MHz: −94 dBc (HD2), −103 dBc (HD3)
500 MHz: −82 dBc (HD2), −82 dBc (HD3)
IMD3 of −104 dBc at 200 MHz and −90 dBc at 500 MHz
Low single-ended input distortion
Slew rate: 20 V/ns
Maintains low distortion for output common-mode voltage
down to 1.25 V
Single-supply operation: 3.3 V or 5 V
Low dc power consumption: 148 mA at 5 V (HP mode), and
80 mA at 3.3 V (LP mode)
ENBL1
VCCx
RF
VON1
VIP1
VIN1
RG
VCOM1
RG
VOP1
PM1
RF
RF
PM2
VON2
VIP2
VIN2
RG1
VCOM2
RG1
VOP2
APPLICATIONS
RF
ADL5567
Differential ADC drivers
Single-ended to differential conversions
RF/IF gain blocks
SAW filter interfacing
GND
ENBL2
13858-001
Data Sheet
4.3 GHz, Ultrahigh Dynamic Range,
Dual Differential Amplifier
ADL5567
Figure 1.
GENERAL DESCRIPTION
The ADL5567 is a high performance, dual differential amplifier
optimized for intermediate frequencies (IF) and dc applications.
The amplifier offers a low noise of 1.29 nV/√Hz and excellent
distortion performance over a wide frequency range, making it
an ideal driver for high speed 16-bit analog-to-digital converters
(ADCs). The ADL5567 is ideally suited for use in high performance
zero-IF and complex IF receiver designs. In addition, this device
has excellent low distortion for single-ended input driver
applications.
The ADL5567 provides a gain of 20 dB. For the single-ended input
configuration, the gain is reduced to 18 dB. Using two external
series resistors for each amplifier expands the gain flexibility of
the amplifier and allows for any gain selection from 0 dB to 20 dB
for a differential input and 0 dB to 18 dB for a single-ended input.
In addition, this device maintains low distortion down to output
common-mode levels of 1.25 V, and therefore providing an added
capability for driving CMOS ADCs at ac levels up to 2 V p-p.
Rev. A
The quiescent current of the ADL5567 using a 5 V supply is
typically 74 mA per amplifier in high performance mode. When
disabled, each amplifier consumes only 3.5 mA, and has 58 dB
input to output isolation at 100 MHz.
The device is optimized for wideband, low distortion, and low
noise operation, giving it unprecedented performance for overall
spurious-free dynamic range (SFDR). These attributes, together
with its adjustable gain capability, make this device the amplifier
of choice for driving a wide variety of ADCs, mixers, pin diode
attenuators, SAW filters, and multielement discrete devices.
Fabricated on an Analog Devices, Inc., high speed silicon
germanium (SiGe) process, the ADL5567 is supplied in a
compact 4 mm × 4 mm, 24-lead LFCSP package and operates
over the −40°C to +85°C temperature.
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Technical Support
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ADL5567
Data Sheet
TABLE OF CONTENTS
Features .............................................................................................. 1
Applications Information .............................................................. 15
Applications ....................................................................................... 1
Basic Connections ...................................................................... 15
Functional Block Diagram .............................................................. 1
Input and Output Interfacing ................................................... 16
General Description ......................................................................... 1
Input and Output Equivalent Circuits ..................................... 17
Revision History ............................................................................... 2
Gain Adjustment and Interfacing ............................................ 17
Specifications..................................................................................... 3
Effect of Load Capacitance ....................................................... 17
Absolute Maximum Ratings............................................................ 6
ADC Interfacing ......................................................................... 18
Thermal Resistance ...................................................................... 6
Soldering Information and Recommended Land Pattern .... 20
ESD Caution .................................................................................. 6
Evaluation Board ........................................................................ 20
Pin Configuration and Function Descriptions ............................. 7
Outline Dimensions ....................................................................... 23
Typical Performance Characteristics ............................................. 8
Ordering Guide .......................................................................... 23
Theory of Operation ...................................................................... 14
REVISION HISTORY
8/2018—Rev. 0 to Rev. A
Changes to Gain Adjustment and Interfacing Section .............. 17
Updated Outline Dimensions ....................................................... 23
7/2016—Revision 0: Initial Version
Rev. A | Page 2 of 23
Data Sheet
ADL5567
SPECIFICATIONS
Supply voltage (VS) = 3.3 V or 5 V, high performance (HP) mode, output common-mode voltage (VCOM) = VS/2, source impedance (RS) =
100 Ω differential, load impedance (RL) = 200 Ω differential, output voltage (VOUT) = 2 V p-p, frequency = 200 MHz, TA = 25°C, parameters
specified for differential input and differential output, signal spacing = 2 MHz for two-tone measurements, unless otherwise noted.
Table 1.
Parameter
DYNAMIC PERFORMANCE
−3 dB Bandwidth
Bandwidth, 0.1 dB Flatness
Voltage Gain (AV)
Differential Input
Single-Ended Input
Gain Accuracy
Channel to Channel Gain Error
Channel to Channel Phase Error
Gain Supply Sensitivity
Gain Temperature Sensitivity
Slew Rate
Settling Time
Overdrive Recovery Time
Reverse Isolation (SDD12)
Input to Output Isolation When
Disabled
Channel to Channel Isolation
INPUT/OUTPUT CHARACTERISTICS
Input Common-Mode Range
Input Resistance
Differential
Single-Ended
Input Capacitance (Single-Ended)
Common-Mode Rejection Ratio
(CMRR)
Output Common-Mode Range
Output Common-Mode Offset
Output Common-Mode Drift
Output Differential Offset Voltage
Output Differential Offset Drift
Output Resistance (Differential)
Maximum Output Voltage Swing
POWER INTERFACE
Supply Voltage
Digital Input Voltage
Logic High (VIH)
Logic Low (VIL)
ENBL1/ENBL2 Input Current
PM1/PM2 Input Current
Test Conditions/
Comments
Min
VS = 3.3 V
Typ
Max
Min
VS = 5 V
Typ
Max
Unit
VOUT ≤ 0.5 V p-p
VOUT ≤ 1.0 V p-p
4.3
410
4.3
420
GHz
MHz
RL = open
RL = 200 Ω differential
RL = 200 Ω differential
20
19
18
±0.2
0.04
20
19
18
±0.2
0.04
dB
dB
dB
dB
dB
0.6
0.6
Degrees
7.1
1.5
18
19
380
6
13.9
1.3
19
20
380
4
mdB/V
mdB/°C
V/ns
V/ns
ps
ns
100 MHz; ENBLx = low
57
58
57
58
dB
dB
Channel A to Channel B
69
69
dB
Frequency = 500 MHz,
Channel A to Channel B
Frequency = 500 MHz,
Channel A to Channel B
VS ± 5%
TA = −40°C to +85°C
Rising, VOUT = 2 V step
Falling, VOUT = 2 V step
2 V step to 1%
Differential input voltage
step from 2 V to 0 V, for
VOUT ≤ ±10 mV
1.2
VCOM1 and VCOM2 pins
Referenced to VCOM (VS/2)
TA = −40°C to +85°C
1.25
−25
−20
TA = −40°C to +85°C
1 dB compressed
3.15
ENBLx = 3 V
ENBLx = 0 V
PMx = 3 V
PMx = 0 V
1.3
100
91.7
0.25
48
Frequency = 500 MHz
ENBL1/ENBL2, PM1/PM2
1.8
±7
1.61
±8
±15
10
5.4
3.3
2.1
0
−7
−70
62
−0.1
Rev. A | Page 3 of 23
3.5
100
91.7
0.25
48
1.8
+25
1.25
−25
+20
−20
3.45
4.75
3.45
1.0
2.1
0
±8
1.42
±8
±6
10
8.6
5
−7
−70
62
−0.1
V
Ω
Ω
pF
dB
3
+40
+20
V
mV
mV/°C
mV
µV/°C
Ω
V p-p
5.25
V
3.45
1.0
V
V
µA
µA
µA
µA
ADL5567
Parameter
Supply Current (ISUPPLY)
High Performance Mode
Low Power Mode
Disabled (Power Down)
NOISE/HARMONIC PERFORMANCE
10 MHz
Second Harmonic Distortion (HD2)
Third Harmonic Distortion (HD3)
Output Third-Order Intercept
(OIP3)
Third-Order Intermodulation
Distortion (IMD3)
Output Second-Order Intercept
(OIP2)
Second-Order Intermodulation
Distortion (IMD2)
Output 1 dB Compression Point
(OP1dB)
Noise Figure (NF)
Noise Spectral Density (NSD),
Referred to Input (RTI) 1
100 MHz
HD2
HD3
OIP3
IMD3
OIP2
IMD2
OP1dB
NF
NSD, RTI1
200 MHz
HD2
HD3
OIP3
IMD3
OIP2
IMD2
OP1dB, Referred to Output (RTO)
NF
NSD, RTI
500 MHz 2
HD2
HD3
OIP3
IMD3
OIP2
IMD2
NF
NSD, RTI
Data Sheet
Test Conditions/
Comments
Total for two channels
ENBLx = high, PMx = low
ENBLx = high, PMx = high
ENBLx = low, PMx = don't
care
Min
VS = 3.3 V
Typ
138
80
7
Max
150
Min
VS = 5 V
Typ
148
85
9
Max
Unit
160
mA
mA
mA
−88
−90
42.6
−93
−94
46.3
dBc
dBc
dBm
−89
−97
dBc
90.2
90.9
dBm
−92
−93
dBc
12.8
16.6
dBm
6.7
1.21
6.8
1.23
dB
nV/√Hz
−88
−89
42.5
−89
84.5
−87
13.0
6.8
1.23
−94
−101
46.5
−97
94.2
−96
16.9
6.8
1.23
dBc
dBc
dBm
dBc
dBm
dBc
dBm
dB
nV/√Hz
−88
−86
43.5
−91
80.7
−83
12.6
7.0
1.27
−94
−103
49.8
−104
88.8
−91
16.7
7.1
1.29
dBc
dBc
dBm
dBc
dBm
dBc
dBm
dB
nV/√Hz
−77
−70
37
−78
76.7
−79
7.3
1.32
−82
−82
42.8
−90
82.0
−84
7.4
1.34
dBc
dBc
dBm
dBc
dBm
dBc
dB
nV/√Hz
Rev. A | Page 4 of 23
Data Sheet
Parameter
1000 MHz2
HD2
HD3
OIP3
IMD3
OIP2
IMD2
NF
NSD, RTI
1500 MHz2
HD2
HD3
OIP3
IMD3
OIP2
IMD2
NF
NSD, RTI
2000 MHz2
HD2
HD3
OIP3
IMD3
OIP2
IMD2
NF
NSD, RTI
1
ADL5567
Test Conditions/
Comments
Min
VS = 3.3 V
Typ
Max
Min
VS = 5 V
Typ
Max
Unit
−59
−49
29
−62
62.1
−64
8.1
1.48
−70
−55
32
−68
65.4
−67
8.2
1.50
dBc
dBc
dBm
dBc
dBm
dBc
dB
nV/√Hz
−44
−47
21.3
−47
50.2
−52
8.3
1.52
−50
−51
25.3
−55
51.8
−54
8.4
1.54
dBc
dBc
dBm
dBc
dBm
dBc
dB
nV/√Hz
−49
−44
17.5
−39
43.3
−45
9.6
1.8
−50
−44
19
−42
51.4
−53
9.7
1.83
dBc
dBc
dBm
dBc
dBm
dBc
dB
nV/√Hz
NSD RTI is calculated from NF, as follows:
NSD (RTI) = ½ × 4 kT × 10 NF/10 − 1× RIN
where:
k is Boltzmann's constant, which equals 1.381 × 10−23J/K.
T is the standard absoltute temperature for evaluating noise figure, which equals 290 K.
RIN is the differential input impedance of each amplifier, which equals 100 Ω.
2
OP1dB is not specified above 500 MHz, as the output level exceeds absolute maximum level allowed (see Table 2).
Rev. A | Page 5 of 23
ADL5567
Data Sheet
ABSOLUTE MAXIMUM RATINGS
THERMAL RESISTANCE
Table 2.
Parameter
Output Voltage Swing × Bandwidth Product
High Performance Mode
Low Power Mode
Supply Voltage (VS) at VCC1, VCC2
VIPx, VINx
±IOUT Maximum (VIPx and VINx Pins)
Internal Power Dissipation
Maximum Junction Temperature
Operating Temperature Range
Storage Temperature Range
Thermal performance is directly linked to printed circuit board
(PCB) design and operating environment.
Rating
5 V-GHz
3 V-GHz
5.25 V
VS + 0.5 V
±30 mA
900 mW
135°C
−40°C to +85°C
−65°C to +150°C
Careful attention to PCB thermal design is required.
Table 3. Thermal Resistance
Package Type
CP-24-19
1
2
θJA1
56
θJC2
2.2
Measured on Analog Devices evaluation board.
Based on simulation with JEDEC standard JESD51.
ESD CAUTION
Stresses at or above those listed under Absolute Maximum
Ratings may cause permanent damage to the product. This is a
stress rating only; functional operation of the product at these
or any other conditions above those indicated in the operational
section of this specification is not implied. Operation beyond
the maximum operating conditions for extended periods may
affect product reliability.
Rev. A | Page 6 of 23
Unit
°C/W
Data Sheet
ADL5567
20 VCC1
19 NC
21 VCOM1
22 ENBL1
23 PM1
24 NC
PIN CONFIGURATION AND FUNCTION DESCRIPTIONS
VIN1 1
18 VON1
VIP1 2
17 VOP1
NC 3
ADL5567
16 NC
NC 4
TOP VIEW
(Not to Scale)
15 NC
VIP2 5
14 VOP2
VIN2 6
NOTES
1. NC = NO CONNECT. THESE PINS SHOULD BE
CONNECTED TO GROUND.
2. THE EXPOSED PAD IS INTERNALLY CONNECTED TO
GND AND MUST BE SOLDERED TO A LOW IMPEDANCE
GROUND PLANE.
13858-002
NC 12
VCC2 11
VCOM2 10
9
ENBL2
NC 7
PM2 8
13 VON2
Figure 2. Pin Configuration
Table 4. Pin Function Descriptions
Pin No.
1
2
3, 4, 7, 12, 15,
16, 19, 24
5
6
8
Mnemonic
VIN1
VIP1
NC
Description
Negative Side of Balanced Differential Inputs for Amplifier 1. This pin is biased to VVCC1/2, and is typically ac-coupled.
Positive Side of Balanced Differential Inputs for Amplifier 1. This pin is biased to VVCC1/2, and is typically ac-coupled.
No Functional Connection. Connect these pins to ground.
VIP2
VIN2
PM2
9
ENBL2
10
VCOM2
11
13
14
17
18
20
21
VCC2
VON2
VOP2
VOP1
VON1
VCC1
VCOM1
22
ENBL1
23
PM1
EP
GND
Positive Side of Balanced Differential Inputs for Amplifier 2. This pin is biased to VVCC2/2, and is typically ac-coupled.
Negative Side of Balanced Differential Inputs for Amplifier 2. This pin is biased to VVCC2/2, and is typically ac-coupled.
Power Mode Control for Amplifier 2. This pin is internally pulled down to GND through a 30 kΩ resistor. A logic low on
this pin sets the device to high performance mode, and a logic high (2.1 V < VPM2 < 3.3 V) sets the device to low
power mode.
Enable for Amplifier 2. This pin is internally pulled up to about 2.8 V. A logic high on this pin (2.1 V < VENBL2 < 3.3 V)
enables the device.
Common-Mode Voltage. A voltage applied to this pin sets the common-mode voltage of the inputs and outputs of
Amplifier 2. If left open, VVCOM2 = VCC2/2. Decouple this pin to ground with a 0.1 µF capacitor.
Positive Supply for Amplifier 2.
Negative Side of Balanced Differential Outputs for Amplifier 2. This pin is biased to VVCOM2, and is typically ac-coupled.
Positive Side of Balanced Differential Outputs for Amplifier 2. This pin is biased to VVCOM2, and is typically ac-coupled.
Positive Side of Balanced Differential Outputs for Amplifier 1. This pin is biased to VVCOM1, and is typically ac-coupled.
Negative Side of Balanced Differential Outputs for Amplifier 1. This pin is biased to VVCOM1, and is typically ac-coupled.
Positive Supply for Amplifier 1.
Common-Mode Voltage. A voltage applied to this pin sets the common-mode voltage of the inputs and outputs of
Amplifier 1. If left open, VVCOM1 = VCC1/2. Decouple this pin ground with a 0.1 µF capacitor.
Enable for Amplifier 1. This pin is internally pulled up to about 2.8 V. A logic high on this pin (2.1 V < VENBL1 < 3.45 V)
enables the device.
Power Mode Control for Amplifier 1. This pin is internally pulled down to GND through a 30 kΩ resistor. A logic low on this
pin sets the device to high performance mode, and a logic high (2.1 V < VPM1 < 3.45 V) sets the device to low power mode.
Exposed Pad. The exposed pad is internally connected to GND and must be soldered to a low impedance ground plane.
Rev. A | Page 7 of 23
ADL5567
Data Sheet
TYPICAL PERFORMANCE CHARACTERISTICS
VS = 3.3 V or 5 V, HP mode, VCOM = VS/2, RS = 100 Ω differential, RL = 200 Ω differential, VOUT = 2 V p-p, frequency = 200 MHz, TA = 25°C,
parameters specified for differential input and differential output, signal spacing = 2 MHz for two-tone measurements, unless otherwise noted.
25
0.20
GAIN MISMATCH CHA – CHB (dB)
0.15
15
10
5
10M
100M
1G
10G
FREQUENCY (Hz)
1G
1M
10M
100M
1G
10G
2.5
2.0
1.5
DUT
DUT
DUT
DUT
DUT
DUT
1,
1,
2,
2,
3,
3,
3.3V HP
5V HP
3.3V HP
5V HP
3.3V HP
5V HP
1.0
0.5
0
–0.5
–1.0
–1.5
–2.0
–2.5
–3.0
1M
10M
100M
13858-007
PHASE MISMATCH CHA – CHB (Degrees)
5V HP, +85°C
5V LP, +85°C
5V HP, +25°C
5V LP, +25°C
5V HP, –40°C
5V LP, –40°C
13858-004
GAIN (dB)
10
FREQUENCY (Hz)
1G
FREQUENCY (Hz)
Figure 7. Channel to Channel Phase Mismatch CHA – CHB vs. Frequency
Figure 4. Gain vs. Frequency over Temperature at VS = 5 V
25
25
20
5V HP, +25°C
5V HP, +85°C
5V HP, –40°C
5V LP, +25°C
5V LP, –40°C
5V LP, +85°C
OP1dB (dBm)
20
15
10
3.3V HP, +85°C
3.3V LP, +85°C
3.3V HP, +25°C
3.3V LP, +25°C
3.3V HP, –40°C
3.3V LP, –40°C
1M
3.3V HP, +25°C
3.3V HP, –40°C
3.3V HP, +85°C
3.3V LP, +25°C
3.3V LP, –40°C
3.3V LP, +85°C
15
10
5
10M
100M
1G
10G
FREQUENCY (Hz)
13858-005
GAIN (dB)
100M
10M
3.0
15
0
100k
–0.10
FREQUENCY (Hz)
20
5
–0.05
–0.20
1M
25
0
100k
0
Figure 6. Channel to Channel Gain Mismatch CHA – CHB vs. Frequency
Figure 3. Gain vs. Frequency over Power Modes
5
0.05
13858-006
1M
0.10
–0.15
13858-003
0
100k
5V HP
5V LP
3.3V HP
3.3V LP
1
2
3
4
5
0
0
50
100
150
200
250
300
350
400
450
FREQUENCY (MHz)
Figure 8. OP1dB vs. Frequency over Temperature
Figure 5. Gain vs. Frequency over Temperature at VS = 3.3 V
Rev. A | Page 8 of 23
500
13858-008
GAIN (dB)
20
DUT
DUT
DUT
DUT
DUT
12.0
11.5
11.0
10.5
10.0
9.5
9.0
8.5
8.0
7.5
7.0
6.5
6.0
5.5
ADL5567
80
5V HP MODE
3.3V HP MODE
OIP3 (dBm)
60
50
40
5V HP, +85°C
5V LP, +85°C
3.3V HP, +85°C
3.3 LP, +85°C
5V HP, +25°C
5V LP, +25°C
3.3V HP, +25°C
3.3V LP, +25°C
5V HP, –40°C
5V LP, –40°C
3.3V HP, –40°C
3.3V LP, –40°C
30
20
100M
1G
0
FREQUENCY (Hz)
0
0.2
0.4
0.6
0.8
1.0
1.2
1.4
1.6
1.8
2.0
FREQUENCY (GHz)
Figure 9. Noise Figure vs. Frequency over VS, HP Mode
13858-012
10
5.0
4.5
4.0
10M
Figure 12. OIP3 vs. Frequency over Temperature, Supply Voltage,
and Power Modes
60
2.5
5V HP MODE
3.3V HP MODE
40
2.0
20
0
1.5
IMD3 (dBc)
NOISE SPECTRAL DENSITY (nV/√Hz)
OIP3,
OIP3,
OIP3,
OIP3,
OIP3,
OIP3,
OIP3,
OIP3,
OIP3,
OIP3,
OIP3,
OIP3,
70
13858-009
NOISE FIGURE (dB)
Data Sheet
1.0
–20
–40
OIP3,
OIP3,
OIP3,
OIP3,
OIP3,
OIP3,
OIP3,
OIP3,
OIP3,
OIP3,
OIP3,
OIP3,
5V HP, +85°C
5V LP, +85°C
3.3V HP, +85°C
3.3 LP, +85°C
5V HP, +25°C
5V LP, +25°C
3.3V HP, +25°C
3.3V LP, +25°C
5V HP, –40°C
5V LP, –40°C
3.3V HP, –40°C
3.3V LP, –40°C
0.2
0.4
–60
–80
0.5
100M
–120
13858-010
0
10M
1G
FREQUENCY (Hz)
0
50
40
40
20
1.0
1.2
1.4
1.6
1.8
2.0
Figure 13. IMD3 vs. Frequency over Temperature, Supply Voltage,
and Power Modes
5V HP MODE,
5V HP MODE,
5V HP MODE,
5V HP MODE,
CH 1,
CH 2,
CH 1,
CH 2,
RL =
RL =
RL =
RL =
200Ω
200Ω
100Ω
100Ω
30
OIP3, 5V HP, 25°C
OIP3, 5V LP, 25°C
OIP3, 3.3V HP, 25°C
OIP3, 3.3V LP, 25°C
IMD3, 5V HP, 25°C
IMD3, 5V LP, 25°C
IMD3, 3.3V HP, 25°C
IMD3, 3.3V LP, 25°C
–60
–10
–80
–20
–100
–30
–120
0
0.2
0.4
0.6
0.8
1.0
1.2
FREQUENCY (GHz)
1.4
1.6
1.8
2.0
–40
Figure 11. IMD3 and OIP3 vs. Frequency over Supply Voltage and Power Modes
Rev. A | Page 9 of 23
0
500
1000
1500
FREQUENCY (MHz)
Figure 14. IMD3 vs. Frequency for RL = 100 Ω
2000
13858-015
0
IMD3 (dBc)
–40
10
OIP3 (dBm)
–20
20
13858-011
0
IMD3 (dBc)
0.8
FREQUENCY (GHz)
Figure 10. Noise Spectral Density (NSD) vs. Frequency over VS, HP Mode
60
0.6
13858-014
–100
ADL5567
Data Sheet
–10
100
20
5V HP, HD2, +25°C
5V LP, HD2, +25°C
5V HP, HD2, –40°C
5V HP, HD2, +85°C
5V LP, HD2, –40°C
5V LP, HD2, +85°C
–20
80
0
–60
–50
HD2 (dBc)
40
OIP2 (dBm)
IMD2 (dBc)
–40
–40
60
5V HP, OIP2
5V LP, OIP2
3.3V HP, OIP2
3.3V LP, OIP2
5V HP, IMD2
5V LP, IMD2
3.3V HP, IMD2
3.3V LP, IMD2
–20
–30
–60
–70
20
–80
–90
0
–80
3.3V LP, HD2, +25°C
3.3V HP, HD2, +25°C
3.3V LP, HD2, +85°C
3.3V LP, HD2, –40°C
3.3V HP, HD2, –40°C
3.3V HP, HD2, +85°C
0.2
0.4
0.6
0.8
1.0
1.2
1.4
1.6
1.8
2.0
–110
FREQUENCY (GHz)
0
–10
–20
–30
–40
–40
–50
–50
HD3 (dBc)
HD2 (dBc)
–30
–60
–70
–80
–90
–100
–100
400
600
800
1000 1200 1400 1600 1800 2000
FREQUENCY (MHz)
–110
13858-018
200
0
200
1000 1200 1400 1600 1800 2000
400
600
800
0
–20
–30
HD2 AND HD3 (dBc)
–40
HD3 (dBc)
5V HP, HD3, +25°C
5V LP, HD3, +25°C
5V HP, HD3, +85°C
5V HP, HD3, –40°C
5V LP, HD3, +85°C
5V LP, HD3, –40°C
Figure 19. HD3 vs. Frequency over Temperature, Supply Voltage,
and Power Modes
5V HP, HD3
5V LP, HD3
3.3V HP, HD3
3.3V LP, HD3
–20
3.3V HP, HD3, +25°C
3.3V LP, HD3, +25°C
3.3V HP, HD3, +85°C
3.3V HP, HD3, –40°C
3.3V LP, HD3, –40°C
3.3V LP, HD3, +85°C
FREQUENCY (MHz)
Figure 16. HD2 vs. Frequency over Supply Voltage and Power Modes
–10
1000 1200 1400 1600 1800 2000
–70
–90
0
800
–60
–80
–110
600
Figure 18. HD2 vs. Frequency over Temperature, Supply Voltage,
and Power Modes
5V HP, HD2
5V LP, HD2
3.3V HP, HD2
3.3V LP, HD2
–20
400
FREQUENCY (MHz)
Figure 15. IMD2 and OIP2 vs. Frequency over Supply Voltage and Power Modes
–10
200
13858-021
0
13858-017
–20
–100
13858-020
–100
–50
–60
–70
–80
–90
5V HP, HD2
5V HP, HD3
3.3V LP, HD2
3.3V LP, HD3
–40
–60
–80
–100
0
200
400
600
800
1000 1200 1400 1600 1800 2000
FREQUENCY (MHz)
–120
13858-019
–110
Figure 17. HD3 vs. Frequency over Supply Voltage and Power Modes
–2
0
2
4
6
POUT PER TONE (dBm)
8
10
13858-022
–100
Figure 20. HD2 and HD3 vs. Output Power (POUT) per Tone, 3.3 V LP Mode
and 5 V HP Mode
Rev. A | Page 10 of 23
Data Sheet
0
–20
–20
–40
–40
–60
–60
–80
–80
–100
–100
–6
–4
–2
0
2
4
6
8
10
POUT PER TONE (dBm)
Figure 21. IMD3 vs. POUT per Tone for 3.3 V LP Mode and 5 V HP Modes
0
–20
–120
0.12
13858-023
–120
3.3V HP
5V HP
DUT
DUT
DUT
DUT
DUT
DUT
DUT
DUT
–30
HD2 AND HD3 (dBc)
HD2 AND HD3 (dBc)
–40
–80
0.15
0.16
0.17
Figure 24. IMD3 vs. Supply Current (ISUPPLY) Distribution, 200 MHz, VS = 5 V
–20
–60
0.14
ISUPPLY (A)
5V HP, HD2
5V HP, HD3
3.3V LP, HD2
3.3 LP, HD3
–40
0.13
13858-026
5V HP, 25°C
3.3V LP, 25°C
IMD3 (dBc)
IMD3 (dBc)
0
ADL5567
–50
1,
1,
1,
1,
2,
2,
2,
2,
CH 1,
CH 1,
CH 2,
CH 2,
CH 1,
CH 1,
CH 2,
CH 2,
HD2
HD3
HD2
HD3
HD2
HD3
HD2
HD3
–60
–70
–80
–90
–100
1.0
1.5
2.0
2.5
3.0
VCOM (V)
0
100
200
300
400
500
600
700
800
900
1000
FREQUENCY (MHz)
Figure 25. HD2 and HD3 vs. Frequency for VS = 2.8 V, LP Mode (Two Devices)
Figure 22. Harmonic Distortion (HD2 and HD3) vs. VCOM for VS = 5 V,
High Performance Mode and VS = 3.3 V, Low Power Mode
0
–110
13858-024
–120
0.5
5V HP
3.3V LP
–20
IMD3 (dBc)
–40
M1
–60
–80
0.5
1.0
1.5
2.0
2.5
3.0
VCOM (V)
13858-025
0
C4 500mV/DIV 50Ω
M1 200mV 2.0ns
B
W
25GS/s 4ps/pt
A CH4
1.64V
13858-027
4
–100
–120
13858-013
–100
Figure 26. Disable Time Response, VS = 3.3 V, Low Power Mode
Figure 23. IMD3 vs. VCOM for 3.3 V LP Mode and 5 V HP Mode
Rev. A | Page 11 of 23
ADL5567
–20
Data Sheet
5V HP MODE
5V LP MODE
3.3V HP MODE
3.3V LP MODE
–30
OUTPUT
–40
HD2 (dB)
–50
INPUT
R1
M1
–60
–70
–80
200
400
600
800
1000 1200 1400 1600 1800 2000
FREQUENCY (Hz)
M1 300mV 2.0ns
R1 600mV 2.0ns
100
COMMON-MODE REJECTION RATIO (dB)
5V HP MODE
5V LP MODE
3.3V HP MODE
3.3V LP MODE
–40
–50
–70
–80
–90
200
400
600
800
1000 1200 1400 1600 1800 2000
FREQUENCY (Hz)
1
2
3
4
90
80
500MHz
1.0GHz
1.5GHz
3.0GHz
48.685dB
38.205dB
31.706dB
27.942dB
70
60
50
1
40
3
2
30
4
20
10
0
13858-138
–100
0
0V
0
0.6
1.2
1.8
2.4
3.0
3.6
4.2
4.8
5.4
6.0
FREQUENCY (GHz)
Figure 31. Common-Mode Rejection Ratio (CMRR) vs. Frequency,
VS = 5 V, High Performance Mode
Figure 28. HD3 vs. Frequency for Single-Ended Input Circuit
2.0n
1
2
3
4
1.8n
1.6n
500MHz
1.0GHz
1.5GHz
3.0GHz
580.56ps
617.40ps
655.06ps
599.63ps
1.4n
GROUP DELAY
1.2n
M1
1.0n
800p
600p
HP
400p
4
200p
B
W
25GS/s 4ps/pt
A CH4
1.64V
0
13858-028
C4 500mV/DIV 50Ω
M1 200mV 2.0ns
Figure 29. Enable Time Response, VS = 3.3 V, Low Power Mode
0
0.5
1.0
1.5
2.0
2.5
3.0
3.5
4.0
FREQUENCY (GHz)
4.5
5.0
5.5
6.0
13858-031
HD3 (dB)
–60
–110
A CH1
Figure 30. Large Signal Pulse Response, VOUT = 4 V p-p, VS = 3.3 V
Figure 27. HD2 vs. Frequency for Single-Ended Input Circuit
–30
25GS/s 20ps/pt
13858-029
0
13858-030
–100
13858-137
–90
Figure 32. Group Delay vs. Frequency, VS = 5 V, High Performance (HP) and
Low Power (LP) Modes
Rev. A | Page 12 of 23
Data Sheet
ADL5567
0
1.0
0.5
REVERSE ISOLATION (dB)
–10
2.0
RLC
–20
6GHz
0.2
–30
5.0
SDD22
–40
0
–50
10MHz
–60
5.0
300M
3G
0.5
2.0
13858-034
30M
FREQUENCY (Hz)
1.0
Figure 35. Differential Output Equivalent RLC Network vs. SDD22 (ZO = 100 Ω)
Figure 33. Reverse Isolation (SDD12) vs. Frequency
1.0
CHANNEL TO CHANNEL ISOLATION (dB)
0
2.0
0.5
0.2
5.0
SDD11
10MHz
0
0.2
6GHz
RLC
5.0
5V HP, A-B
5V LP, A-B
3.3V HP, A-B
3.3V LP, A-B
5V HP, B-A
5V LP, B-A
3.3V HP, B-A
3.3V LP, B-A
–20
–40
–60
–80
–100
–120
100k
1M
10M
100M
1G
10G
FREQUENCY (Hz)
0.5
13858-135
3M
1.0
13858-033
2.0
Figure 34. Differential Input Equivalent RLC Network vs. SDD11 (ZO = 100 Ω)
Figure 36. Channel to Channel Isolation vs. Frequency
0.16
0.14
SUPPLY CURRENT (A)
0.12
0.10
0.08
0.06
0.04
0.02
0
–40
5V HP MODE
5V LP MODE
3.3V HP MODE
3.3V LP MODE
–20
0
20
40
TEMPERATURE (°C)
60
80
100
13858-136
–70
300k
13858-032
0.2
Figure 37. Supply Current vs. Temperature over VS and Power Modes
Rev. A | Page 13 of 23
ADL5567
Data Sheet
THEORY OF OPERATION
The ADL5567 is composed of a pair of fully differential amplifiers
with on-chip feedback and feedforward resistors. The gain is fixed
at 20 dB, but it can be reduced by adding two resistors in series with
the two inputs (see the Gain Adjustment and Interfacing section).
The amplifier provides a high differential open-loop gain and has
an output common-mode circuit that enables the user to change
the output common-mode voltage by applying a voltage to a
VCOMx pin.
Each amplifier provides superior low distortion for frequencies
near dc to beyond 500 MHz, with low noise and low power
consumption. The low distortion and noise are realized with a
3.3 V power supply at 140 mA. This amplifier achieves an IMD3
of −104 dBc at 200 MHz, and −90 dBc IMD3 at 500 MHz for
2 V p-p operation. In addition, the ADL5567 can deliver 5 V p-p
operation under heavy loads. The internal gain is set at 20 dB,
and the device has a noise figure of 7.1 dB and a RTI voltage
NSD of 1.29 nV/√Hz at 200 MHz. When comparing noise
figure and distortion performance, this amplifier delivers the
best in category spurious-free dynamic range (SFDR).
The ADL5567 is very flexible in terms of input/output coupling.
It can be ac-coupled or dc-couplied. For dc coupling, the output
common-mode voltage can be adjusted (using the VCOMx pins)
from 1.25 V to 1.8 V for VS at 3.3 V, and up to 3 V with VS at 5 V.
The distortion performance as a function of common-mode
voltage is shown in Figure 22 and Figure 23. Note that the input
common-mode voltage follows the output common-mode
voltage when at the inputs are ac-coupled.
500Ω
0.1µF
½
RS
50Ω
AC
50Ω
5Ω
+
½
ADL5567
–
RL
5Ω
½
RS
0.1µF
0.1µF
0.1µF
500Ω
13858-035
The ADL5567 is a high gain, fully differential dual amplifier/
ADC driver that operates on a single power supply voltage (VS) of
3.3 V or 5 V. Internal resistors preset the gain to 20 dB, and external
resistors can be added to reduce this gain. The −3 dB bandwidth is
4.3 GHz, and it has a differential input impedance of 100 Ω. It has
a differential output impedance of 10 Ω and an operating output
common-mode voltage range of 1.25 V to 3 V with 5 V supply.
Figure 38. Basic Structure
For dc-coupled inputs, the input common-mode voltage must
stay between 1.2 V and 1.8 V for a 3.3 V supply and 1.3 V to 3.5 V
for a 5 V supply. Note again that for ac-coupled applications with
series capacitors at the inputs, as shown in Figure 38, the input
common-mode level is set to be the same as the voltage at VCOMx.
Due to the wide input common-mode range, this device can
easily be dc-coupled to many types of mixers, demodulators,
and amplifiers. Forcing a higher input common-mode level does
not affect the output common-mode level in dc-coupled operations. If the outputs are ac-coupled, no external VCOMx voltage
adjustment is required because the amplifier output commonmode level is set to VS/2.
Rev. A | Page 14 of 23
Data Sheet
ADL5567
APPLICATIONS INFORMATION
The Amplifier 1 input pins, Pin 1 (VIN1) and Pin 2 (VIP1), and
output pins, Pin 18 (VON1) and Pin 17 (VOP1), are biased by
applying a voltage to Pin 21 (VCOM1). If VCOM1 is left open,
VCOM1 equals ½ of VS. The Amplifier 2 input pins, Pin 5 (VIP2)
and Pin 6 (VIN2), and the output pins, Pin 13 (VON2) and Pin 14
(VOP2), are biased by applying a voltage to VCOM2. If VCOM2
is left open, VCOM2 equals ½ of VS.
BASIC CONNECTIONS
Figure 39 shows the basic connections for operating the ADL5567.
Apply a voltage between 3 V and 5 V to the VCC1 and VCC2 pins
through a 5.1 nH inductor and decouple the supply side of the
inductor with at least one low inductance, 0.1 μF surface-mount
ceramic capacitor. This inductor, together with the internal
capacitance at the VCCx pins, results in a two-pole, low-pass
network and reduces the noise from the power supply.
The ADL5567 can be ac-coupled as shown in Figure 39, or can
be dc-coupled if within the specified input and output commonmode voltage ranges. Pulling the ENBL1/ENBL2 pins low puts
the ADL5567 in sleep mode, reducing the current consumption
to 7 mA at ambient temperature.
Decouple the VCOM1 and VCOM2 pins (Pin 21 and Pin 10)
using a 0.1 μF capacitor. The ENBL1 and ENBL2 pins (Pin 22
and Pin 9) are tied to logic high, respectively, to enable each
amplifier. A differential signal is applied to Amplifier 1 through
Pin 1 (VIN1) and Pin 2 (VIP1) and to Amplifier 2 through Pin 5
(VIP2) and Pin 6 (VIN2). Each amplifier has a gain of 20 dB.
0.01µF
5.1nH
VCC2
0.01µF
+
VS
10µF
5.1nH
VCC1
18
11
18
20
EXPOSED PAD
RF
½
RS
18
0.01µF
BALANCED
AC
½
RS
VIP1
VIN1
2
1
0.01µF
RG
21
RG
17
3.3V
ENBL1
VON1
0.01µF
VCOM1
0.01µF
BALANCED
LOAD
VOP1
RF
0.01µF
22
2
ADL5567
ENBL2
1
9
RF
13
½
RS
VIP2
BALANCED
AC
VIN2
5
6
½
RS
RG
10
RG
14
VON2
VCOM2
0.01µF
0.01µF
8
23
Figure 39. Basic Connections
Rev. A | Page 15 of 23
PM1
3.3V
24
NC
19
NC
16
NC
15
NC
12
NC
7
NC
4
NC
3
NC
PM2
BALANCED
LOAD
VOP2
RF
3.3V
0.01µF
13858-036
3.3V
ADL5567
Data Sheet
INPUT AND OUTPUT INTERFACING
The ADL5567 can be configured as a differential input to differential output driver, as shown in Figure 40. The 50 Ω resistors, R1
and R2, combined with the input balun, provide a 50 Ω input match
for the 100 Ω input impedance. The input and output 0.1 µF
capacitors isolate the VCCX/2 bias from the source and balanced
load. The load equals 200 Ω to provide the expected ac performance (see the Specifications section).
VS
R2
50Ω
AC
½ RL
½
ADL5567
0.1µF
0.1µF
R2 × RIN
R2 + RIN
Thus,
R2 = RIN × RS /(RIN − RS)
(3)
The last step is to calculate the gain path rebalancing resistor,
R1 (see Figure 42), using the following formula:
+
50Ω
RS =
When RS = 50 Ω and RIN = 91.7 Ω, R2 = 109 Ω.
0.1µF
0.1µF
1:1 BALUN
The next step is to calculate the termination of Resistor R2 (see
Figure 42). Because RS must be equal to the parallel equivalent
resistance of R2 and RIN,
R1 =
½ RL
–
RS + R2
Thus, R1 = 34.0 Ω.
13858-037
R1
50Ω
RS × R2
RF
500Ω
Figure 40. Differential Input to Differential Output Configuration
0.1µF
AV =
500
50
×
RS
R2
0.1µF
(1)
10 + RL
5Ω
+
AC
RL
RG
50Ω
RG
50Ω
½
ADL5567
–
R1
0.1µF
½
RL
5Ω
0.1µF
½
RL
RF
500Ω
13858-039
The differential gain of the ADL5567 is dependent on the source
impedance and load, as shown in Figure 41. The differential
gain (AV) can be determined by
500Ω
0.1µF
Figure 42. Single-Ended Input to Differential Output Configuration
50Ω
AC
50Ω
+
½
ADL5567
–
5Ω
0.1µF
5Ω
0.1µF
RL
See the AN-0990 Application Note for more information on
terminating single-ended inputs. The single-ended gain
configuration of the ADL5567 is dependent on the source
impedance and load, as shown in Figure 43.
½
RS
0.1µF
RF
500Ω
13858-038
500Ω
0.1µF
Figure 41. Differential Input Loading Circuit
RS
Single-Ended Input to Differential Output
The single-ended circuit configuration can be accomplished in
three steps (see Figure 42), assuming a 50 Ω RS source. First,
calculate the input impedance (RIN) of the amplifier using the
following formula:
R IN =
RG
RF
1 –
2 × (RG + RF )
(2)
5Ω
0.1µF
½
RL
+
R2
109Ω
0.1µF
The ADL5567 can also be configured in a single-ended input to
differential output driver, as shown in Figure 42. In this configuration, the gain of the device is reduced due to the application of the
signal to only one side of the amplifier. The input and output 0.1 µF
capacitors isolate the VCCx/2 bias from the source and the
balanced load.
RG
50Ω
AC
RG
50Ω
½
ADL5567
5Ω
0.1µF
–
R1
34.2Ω
½
RL
RF
500Ω
13858-040
½
RS
Figure 43. Single-Ended Input Loading Circuit
Determine the single-ended gain (AV1) using the following two
equations:
RMATCH =
R2 × RIN
R2 + RIN
(4)
where RMATCH is the input resistance value that matches RS,
calculated as follows:
AV1 =
Thus, RIN = 91.7 Ω.
Rev. A | Page 16 of 23
R
+ RSS
500
R2
RL
×
× MATCH
×
RS × R2 RS + R2
10 + RL
R MATCH
50 +
RS + R2
(5)
Data Sheet
–20
ADL5567
RSHUNT =
3.3V LP, SE
3.3V LP, DIFF
5V HP, SE
5V HP, DIFF
–30
RS
–40
HD2 (dBc)
–60
–70
–80
–90
−
(7)
1
2RSERIES + 100
To calculate the gain (AV) for a given RSERIES and RL, use the
following equation:
–100
200
400
600
800
1000 1200 1400 1600 1800 2000
RL
500
×
AV =
R
SERIES + 50 10 + RL
13858-046
0
FREQUENCY (MHz)
Figure 44. HD2 for Single-Ended (SE) and Differential (DIFF) Configurations
vs. Frequency, VOUT = 2 V p-p, RL = 200 Ω
The differential input and outptut impedance can be modeled
by simple RLC equivalent circuits as shown in Figure 45. Figure 34
shows the comparison of the measured and modeled impedances
for the input network. Likewise, Figure 35 shows the same
comparison for the output network.
Table 5. Differential Gain Adjustment Using Series Resistor
Target Voltage Gain (dB)
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
VOP
VIP
L3
0.4nF
L1
R5 12nF
50Ω
C1
0.3pF
L6
1.5nF
R3
100Ω
R1
10Ω
L4
R2 1.4nF
22Ω
C2
0.8pF
VIN
13858-133
VON
L5
1.4nF
L2
0.4nF
Figure 45. Model of Differential Input and Output Circuit
GAIN ADJUSTMENT AND INTERFACING
The effective gain of the ADL5567 can be reduced by adding two
resistors in series with the inputs to reduce the gain.
500Ω
0.1µF
½
RS
RSERIES
RSHUNT
RSERIES
50Ω
50Ω
+
½
ADL5567
5Ω
0.1µF
5Ω
0.1µF
RL
–
½
RS
500Ω
13858-042
0.1µF
Figure 46. Gain Adjustment Using a Series Resistor
To find RSERIES for a given AV gain and RL, use the following
equation:
500 RL
RSERIES =
×
− 50
AV 10 + RL
(6)
The necessary shunt component, RSHUNT, to match to the source
impedance, RS, can be expressed as
(8)
Note that Equation 8 only gives the absolute gain and does not
take into account that the circuit introduces a 180° phase shift.
To account for this phase shift, multiply the product of
Equation 8 by −1.
INPUT AND OUTPUT EQUIVALENT CIRCUITS
AC
1
The shunt resistor values for multiple target voltage gains are listed
in Table 5. The source resistance and input impedance need
careful attention when using Equation 5. The input impedance
of the ADL5567 and the reactance of the ac coupling capacitors
must be considered before assuming that they make a negligible
contribution.
–50
–110
1
RS (Ω)
50
50
50
50
50
50
50
50
50
50
50
50
50
50
50
50
50
50
50
50
RSERIES (Ω)
426.1
374.4
328.2
287.1
250.4
217.7
188.6
162.7
139.5
118.9
100.5
84.2
69.6
56.6
45
34.6
25.4
17.2
9.9
3.4
RSHUNT (Ω)
52.7
53.1
53.5
54
54.5
55.1
55.8
56.6
57.5
58.6
59.9
61.4
63.2
65.3
67.8
70.9
74.7
79.5
85.7
93.7
EFFECT OF LOAD CAPACITANCE
Load capacitance, including stray capacitance from PCB traces,
affect the bandwidth and flatness of the ADL5567 frequency
response, resulting in excessive peaking. Adding external series
resistors to each output isolates the load capacitance from the
outputs, and reduces the peaking effectively. Respective frequency
responses resulting from the addition of 1.5 pF and 3 pF differential
load capacitance (CLD) as well as series resistance (RSE) of 15 Ω
are shown in Figure 47.
Rev. A | Page 17 of 23
ADL5567
Data Sheet
27.5
59
25.0
58
20.0
57
BRD-4, AC-COUPLED, SMA-CLK
BRD-8, DC-COUPLED, CRYSTEK, ADF, CLK
BRD-4, AC-COUPLED, CRYSTEK, 2.5GHz, CLK
BRD-5, DC-COUPLED, BALUN CRYSTEK, 2.5GHz
BRD-5, DC-COUPLED, SIG-GEN
BRD-5, DC-COUPLED,ADF
BRD-2, REVB, FINAL
17.5
56
SNRFS (dBFS)
15.0
12.5
10.0
7.5
5.0
55
54
2.5
100M
52
AD9625 DATASHEET
BRD-4, AC-COUPLED, CRYSTEK, ADF, CLK
BRD-5, DC-COUPLED, ON-BOARD, OSC, CLKAMP, ADC
BRD-5, DC-COUPLED, CRYSTEK, 2.5GHz
BRD-2, AC-COUPLED, CRYSTEK, 2.6GHz, ADC
BRD-5, DC-COUPLED, CRYSTEK
BRD-3, DC-COUPLED, 2.5GHz, CRYSTEK
51
1G
10G
FREQUENCY (Hz)
50
0
200
400
600
800
1000 1200 1400 1600 1800 2000
FREQUENCY (MHz)
13858-048
–7.5
–10.0
10M
CLD = 0pF
CLD = 3pF, RSE = 0Ω
CLD = 1.5pF, RSE = 0Ω
CLD = 3pF, RSE = 15Ω
CLD = 1.5pF, RSE = 15Ω
Figure 48. ADC System SNR (Referred to Full Scale)
Figure 47. Frequency Response for Various Load Capacitances,
VS = 5 V, High Performance Mode, RL = 200 Ω
0
ADC INTERFACING
BRD-5, DC-COUPLED
BRD-4, AC-COUPLED
–10
The signal-to-noise ratios with respect to full scale of the ADC
system (SNR FS), using various sources for sampling clock on
several circuit boards (such as the BRD-2, BRD-4, or BRD-5)
are shown in Figure 48. Two-tone intermodulation distortion
performance is shown in Figure 49, and the relative frequency
responses for this ADC system with different output filter
capacitors, are shown in Figure 50.
–20
IMD3 (dBc)
–30
–40
–50
–60
–70
–80
–90
–100
0
200
400
600
800
1000
1200
1400
1600
1800
FREQUENCY (MHz)
Figure 49. Measured Two-Tone IMD3 Performance
5
0
RELATIVE GAIN (dB)
A wideband data acquisition system (AD-FMCADC7-EBZ) using
the ADL5567 together with the AD9625 2.6 GSPS, 12-bit ADC
is shown in Figure 51. The RC filter after the amplifier works
with the pole formed by the ADC input capacitance to attenuate
the broadband noise and out-of-band harmonics generated by
the amplifier, as well as blocking the sharp switching pulses from
reaching the amplifier outputs and creating nonlinear effects.
Component values for different acquisition bandwidth are listed
in Table 6. An additional filter more specific to the system rejection
requirements is also needed ahead of the ADL5567 amplifier to
prevent unwanted signals from compressing the amplifier as
well as from reaching the ADC.
13858-049
–2.5
–5.0
53
–5
–10
–15
–20
–25
–30
10M
BRD-3, DUAL-AMP
BRD-3, DUAL-AMP, 2.2PF
BRD-5, DC-COUPLED, SIG-GEN
100M
1G
FREQUENCY (Hz)
Figure 50. Measured Relative Frequency Response
Rev. A | Page 18 of 23
10G
13858-050
0
13858-047
FREQUENCE RESPONSE (dB)
22.5
Data Sheet
ADL5567
Table 6. Example RC Values for Various Bandwidth Limits
Value/Device
½ ADL5567
10 Ω
Description/Comments
One channel
Small value to minimize loss
3 GHz
1 pF
Wide BW allows undersampling operation
Final value depends on PCB parasitics
1.8 GHz
2.2 pF
AD9625
Filters noise and harmonics above Nyquist frequency
Final value depends on PCB parasitics
2.6 GSPS, 12-bit ADC
AVDD 3.3V
20Ω
MINI-CIRCUITS
Bias-TEE
ZFBT-4R2GW
ANALOG
INPUT
AVDD
3.3V
95Ω
AVDD
M2V
20Ω
AD9625
10kΩ
VCOM
10kΩ
51Ω
DC OFFSET:
550mV
10Ω
VIP
DRVDD
ADL5567
PM
VIN
0.1µF
100Ω
10Ω
0.75pF
ADC
INTERNAL
INPUT Z
20Ω
VCM
CFILTER
1pF
AVDD –2V
1µF
AVDD –2V
PAD
Figure 51. Wideband ADC Interfacing Example: ADL5567 Driving the AD9625
VS
0.1µF
5nH
ETC1-1
50Ω
0.1µF
50Ω
0.1µF
AC
50Ω
0.1µF
VIN1
84.5Ω
ETC1-1
34.8Ω
ADL5567
AMPLIFIER 1
VIP1
0.1µF
84.5Ω
34.8Ω
Figure 52. General-Purpose Characterization Circuit
Rev. A | Page 19 of 23
50Ω
ANALYZER
13858-052
INPUT
Z = 50Ω
AVDD
CFILTER
1pF
13858-051
Component
Amplifier
RSERIES
Wideband Configuration
BW
CFILTER (See Figure 51)
Nyquist Band Configuration
BW
CFILTER (See Figure 51)
ADC
ADL5567
Data Sheet
SOLDERING INFORMATION AND RECOMMENDED
LAND PATTERN
EVALUATION BOARD
Figure 53 shows the recommended land pattern for the ADL5567.
The ADL5567 is contained in a 4 mm × 4 mm LFCSP package,
which has an exposed ground pad (EP). This pad is internally
connected to the ground of the chip. To minimize thermal
impedance and ensure electrical performance, solder the pad to
the low impedance ground plane on the PCB. To further reduce
thermal impedance, it is recommended that the ground planes
on all layers under the paddle be stitched together with vias.
For more information on land pattern design and layout, refer
to the AN-772 Application Note, A Design and Manufacturing
Guide for the Lead Frame Chip Scale Package (LFCSP).
The land pattern on the ADL5567 evaluation board provides a
simulated thermal resistance (θJA) of 56 °C/W.
Figure 54 shows the schematic of the ADL5567 evaluation board.
The evaluation board is powered by a single supply in the 3 V to
5 V range. The power supply is decoupled by 10 µF and 0.1 µF
capacitors. Inductors L1 and L2 decouple the ADL5567 from the
power supply. Table 7 details the various configuration options of
the evaluation board.
Figure 55 and Figure 56 show the component and circuit side
layouts of the evaluation board.
The balanced input and output interfaces are converted to singleended with a pair of baluns (Mini-Circuits TCM1-43X+). The
baluns at the input, T1 and T2, provide a 50 Ω single-ended to
differential transformation. The output baluns, T3 and T4, and the
matching components are configured to provide a 200 Ω to 50 Ω
impedance transformation with an insertion loss of about 11 dB.
91 MILS
13 MILS
13.7 MILS
39 MILS
19.7 MILS
12 MILS
10916-050
98.4 MILS
157.4 MILS
91 MILS
Figure 53. Recommended Land Pattern
Rev. A | Page 20 of 23
3 2
2
1
3
2
Rev. A | Page 21 of 23
3
2
1
AGND
JOHNSON142-0701-851 5 4
DNI
VINB
AGND
JOHNSON142-0701-851 5 4
1
VIP2
AGND
3
VIP1
DNI
AGND
5 4
JOHNSON142-0701-851 5 4
JOHNSON142-0701-851
1
VIN1
R3
0
0
R2
AGND
R4
0
AGND
0
R1
DNI
DNI
2
NC
4
1
2
AGND
5
6
T2
AGND
3
TCM1-43X+
5
R9
C14
50
AGND
50
R12
R11
AGND
50
0.01UF
C16
0.01UF
C15
0.01UF
VPM2
R8
Figure 54. Evaluation Board Schematic
3
1
2
ENBL2
2
3
1
0
R24
0
R21
0
VPOSB
R6
AGND
1K
R7
22K
2
3
4
VPM1
1
AGND
0
R5
1
NC
0.01UF
C13
6
T1
50
R10
3
TCM1-43X+
AGND
VPOSB
22K
R23
1K
R22
C3
AGND
0.1UF
C9
AGND
0.1UF
AGND
C4
0.1UF
AGND
0.1UF
C8
AGND
AGND
AGND
6
5
4
1
2
3
VIN1
VIP1
1
AGND
0.1UF
C2
RED
VCOM-2
AGND
VIN2
NC
NC
VIP2
NC
PM2
7
8
1
DUT
AGND
C7
0.1UF
5.1NH
L2
AGND
ADL5567
18
17
16
NC
15
NC
14
VOP2
13
VON2
L1
VPOSB
5.1NH
VPOSB
AGND
0.1UF
C5
AGND
0.1UF
C6
RED
VCOM-1
VON1
VOP1
VCC2
NC
9
10
11
ENBL2
VCOM2
PAD
PAD
24
NC
23
PM1
22
ENBL1
21
VCOM1
20
VCC1
19
NC
12
AGND
3
AGND
1
2
C18
AGND
1
GND
0.01UF
C19
0.01UF
C20
BLK
0.01UF
C17
0.01UF
R14
1
AGND
N
P
34.8
R17
R18
34.8
R19
34.8
34.5
R20
C21
10UF
RED
VCCB
AGND
AGND
AGND
AGND
VPOSB
8 4.5
R15
84.5
R16
84.5
R13
84.5
4
6
T4
4
6
5
NC
AGND
AGND
5
NC
TCM1-43X+
TCM1-43X+
T3
1
2
3
2
1
3
AGND
R26
0
0
DNI
R28
AGND
0
R25
0
DNI
R27
1
5
AGND
JOHNSON142-0701-851
JOHNSON142-0701-851
JOHNSON142-0701-851
DNI
JOHNSON142-0701-851
DNI
4 3 2
1
VOP2
AGND
5 4
3 2
VON2
AGND
3 2
VON1
5 4
1
3 2
AGND
5 4
1
VOP1
13858-053
ENBL_1
Data Sheet
ADL5567
ADL5567
Data Sheet
Table 7. Evaluation Board Configuration Options
Component
VCCB, GND
C5, C7, C21, L1,
L2
VIN1, VIP1, VIP2,
VIN2, R1, R2, R3,
R4, R5, R8, R9,
R10, R11, R12,
R21, R24, C13,
C1, C12, C14,
C15, C16, T1, T2
VOP1, VON1,
VON2, VOP2,
C10, C11, C17,
C18, C19, C20,
R13, R14, R15,
R16, R17, R18,
R19, R20, R25,
R26, R27, R28,
T3, T4
ENBL_1,
ENBL_2, C3, C4
VCOM-1,
VCOM-2, C2, C6
Default Condition
VCCB, GND = installed
C21 = 10 µF (Size D),
C5, C7 = 0.1 µF (Size 0402),
L1, L2 = 5.1 nH (Size 0603)
VIN1, VIP2 = installed,
VIP1, VIN2 = not installed,
R1, R2 = do not install (DNI),
R3, R4, R5, R8, R21, R24 = 0 Ω
(Size 0402),
R9, R10, R11, R12 = 50 Ω (Size 0402),
C13, C14, C15, C16 = 0.01 µF
(Size 0402),
C1, C12 = DNI,
T1, T2 = TCM1-43+ (Mini-Circuits®)
VOP1, VON2 = installed,
VON1, VOP2 = not installed,
R13, R14, R15, R16 = 84.5 Ω
(Size 0402),
R17, R18, R19, R20 = 34.8 Ω
(Size 0402),
R25, R26 = 0 Ω (Size 0402),
R27, R28 = DNI (Size 0402),
C10, C11 = DNI (Size 0402),
C17, C18 = 0.01 µF (Size 0402),
C19, C20 = 0.01 μF (Size 0402),
T3, T4 = TCM1-43+ (Mini-Circuits)
ENBL_1, ENBL_2 = installed,
C3, C4 = 0.1 µF (Size 0402)
VCOM-1, VCOM-2 = installed
C2, C6 = 0.1 µF (Size 0402)
PM1, PM2 = installed
13858-057
PM1, PM2
Description
Supply and ground test loops.
Power supply decoupling. The supply decoupling consists of a 10 µF capacitor (C21) and
two 0.1 μF capacitors, C5 and C7, connected between the supply lines and ground.
L1 and L2 decouple the ADL5567 from the power supply.
Input interface. The SMA labeled VIN1 is the input to Amplifier 1. T1 is a 1:1
impedance ratio balun to transform a single-ended input into a balanced differential
signal. Removing R3, installing R1 (0 Ω), and installing an SMA connector (VIP1) allows
driving from a differential source. C13 and C14 provide ac coupling. C12 is an optional
bypass capacitor. R9 and R10 provide a differential 50 Ω input termination. The SMA
labeled VIP2 is the input to Amplifier 2. T2 is a 1:1 impedance ratio balun to transform a
single-ended input into a balanced differential signal. Removing R4, installing R2 (0 Ω),
and installing an SMA connector (VIN2) allows driving from a differential source. C15
and C16 provide ac coupling. C1 is an optional bypass capacitor. R11 and R12 provide a
differential 50 Ω input termination.
Output interface. The SMA labeled VOP1 is the output for Amplifier 1. T3 is a 1:1
impedance ratio balun used to transform a balanced differential signal to a singleended signal. Removing R25, installing R27 (0 Ω), and installing an SMA connector
(VON1) allows differential loading. C10 is an optional bypass capacitor. C17 and C18
provide ac coupling. R13, R14, R17, and R16 are provided for generic placement of
matching components.
The SMA labeled VON2 is the output for Amplifier 2. T4 is a 1:1 impedance ratio balun
used to transform a balanced differential signal to a single-ended signal. Removing R26,
installing R28 (0 Ω), and installing an SMA connector (VOP2) allows differential loading.
C11 is an optional bypass capacitor. C19 and C20 provide ac coupling. R15, R16, R19,
and R20 are provided for generic placement of matching components.
The evaluation board is configured to provide a 50 Ω source impedance to the external
output, as well as a 200 Ω load to the device, with a voltage divide ratio of 17 dB.
Device enable. ENBL_1 is the enable input for Amplifier 1. Placing the jumper
between Position 1 and Position 2 enables Amplifier 1. C3 is a bypass capacitor for
the ENBL_1 input. ENBL_2 is the enable for Amplifier 2. Placing the jumper between
Position 1 and Position 2 enables Amplifier 2. C4 is a bypass capacitor for the
ENBL_2 pin.
Common-mode voltage interface. VCOM-1 is the common-mode interface for
Amplifier 1. A voltage applied to this pin sets the common-mode voltage of the output
of Amplifier 1. VCOM-2 is the common-mode interface for Amplifier 2. A voltage applied
to this pin sets the common-mode voltage of the output of Amplifier 2. Typically
decoupled to ground with a 0.1 µF capacitor (C2 and C6). With no reference applied,
input and output common mode levels float to midsupply (VS/2).
Power mode control. Each amplifier has a power mode control that lowers the
current in the amplifier to lower the power consumption.
13858-056
Figure 56. Layout of Evaluation Board, Circuit Side
Figure 55. Layout of Evaluation Board, Component Side
Rev. A | Page 22 of 23
Data Sheet
ADL5567
OUTLINE DIMENSIONS
DETAIL A
(JEDEC 95)
0.28
0.23
0.18
1
0.50
BSC
2.20
2.10 SQ
2.00
EXPOSED
PAD
13
TOP VIEW
0.80
0.75
0.70
SIDE VIEW
PKG-004084
SEATING
PLANE
0.45
0.40
0.35
PIN 1
INDIC ATOR AREA OPTIONS
(SEE DETAIL A)
24
19
18
6
12
7
BOTTOM VIEW
0.05 MAX
0.02 NOM
COPLANARITY
0.08
0.203 REF
0.20 MIN
FOR PROPER CONNECTION OF
THE EXPOSED PAD, REFER TO
THE PIN CONFIGURATION AND
FUNCTION DESCRIPTIONS
SECTION OF THIS DATA SHEET.
COMPLIANT TO JEDEC STANDARDS MO-220-WGGD-6
04-17-2018-A
PIN 1
INDICATOR
4.10
4.00 SQ
3.90
Figure 57. 24-Lead Lead Frame Chip Scale Package [LFCSP]
4 mm × 4 mm Body and 0.75 mm Package Height
(CP-24-19)
Dimensions shown in millimeters
ORDERING GUIDE
Model 1
ADL5567ACPZN-R7
ADL5567-EVALZ
1
Temperature Range
−40°C to + 85°C
Package Description
24-Lead Lead Frame Chip Scale Package [LFCSP], 7” Tape and Reel
Evaluation Board
Z = RoHS Compliant Part.
©2016–2018 Analog Devices, Inc. All rights reserved. Trademarks and
registered trademarks are the property of their respective owners.
D13858-0-8/18(A)
Rev. A | Page 23 of 23
Package Option
CP-24-19
