700 MHz to 1000 MHz,
1 W RF Driver Amplifier
ADL5605
Data Sheet
14 NC
15 NC
16 NC
Operation from 700 MHz to 1000 MHz
Gain of 23 dB at 943 MHz
OIP3 of 44.2 dBm at 943 MHz
P1dB of 30.9 dBm at 943 MHz
Noise figure of 4.8 dB at 943 MHz
Power supply: 5 V
Power supply current: 307 mA typical
Internal active biasing
Fast power-up/power-down function
Compact 4 mm × 4 mm, 16-lead LFCSP
ESD rating of ±1 kV (Class 1C)
Pin-compatible with the ADL5606 (1800 MHz to 2700 MHz)
13 NC
FUNCTIONAL BLOCK DIAGRAM
FEATURES
12 RFOUT
RFIN 1
PWDN
DISABLE 2
VCC 3
11 RFOUT
10 RFOUT
VBIAS
VBIAS 4
9
09353-001
RFOUT
NC 7
NC 8
NC 6
NC 5
ADL5605
Figure 1.
APPLICATIONS
Wireless infrastructure
Automated test equipment
ISM/AMR applications
0
GENERAL DESCRIPTION
–10
The ADL5605 is fabricated on a GaAs HBT process and is
packaged in a compact 4 mm × 4 mm, 16-lead LFCSP that
uses an exposed paddle for excellent thermal impedance. The
ADL5605 operates from −40°C to +85°C. A fully populated
evaluation board tuned to 943 MHz is also available.
Rev. B
–30
–40
–50
–60
–70
946MHz
–80
–90
0
2
4
6
8
10
12
14
16
18
20
22
POUT (dBm)
09353-002
The ADL5605 operates on a 5 V supply voltage and a supply
current of 307 mA. The driver also incorporates a fast powerup/power-down function for TDD applications, applications
that require a power saving mode, and applications that
intermittently transmit data.
–20
ACPR (dBc)
The ADL5605 is a broadband, two-stage, 1 W RF driver
amplifier that operates over a frequency range of 700 MHz
to 1000 MHz.
Figure 2. ACPR vs. Output Power, 3GPP, TM1-64, at 946 MHz
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ADL5605
Data Sheet
TABLE OF CONTENTS
Features .............................................................................................. 1
881 MHz Frequency Tuning Band ..............................................9
Applications ....................................................................................... 1
943 MHz Frequency Tuning Band ........................................... 10
General Description ......................................................................... 1
General......................................................................................... 11
Functional Block Diagram .............................................................. 1
Applications Information .............................................................. 13
Revision History ............................................................................... 2
Basic Layout Connections ......................................................... 13
Specifications..................................................................................... 3
ADL5605 Matching .................................................................... 14
Typical Scattering Parameters ..................................................... 5
ACPR and EVM ......................................................................... 15
Absolute Maximum Ratings............................................................ 6
Thermal Considerations............................................................ 15
Thermal Resistance ...................................................................... 6
ESD Caution .................................................................................. 6
Soldering Information and Recommended PCB Land
Pattern .......................................................................................... 15
Pin Configuration and Function Descriptions ............................. 7
Evaluation Board ............................................................................ 16
Typical Performance Characteristics ............................................. 8
Outline Dimensions ....................................................................... 18
748 MHz Frequency Tuning Band ............................................. 8
Ordering Guide .......................................................................... 18
REVISION HISTORY
9/2017—Rev. A to Rev. B
Changed CP-16-10 to CP-16-20 .................................. Throughout
Changes to Figure 1 .......................................................................... 1
Changes to Figure 3 .......................................................................... 7
Updated Outline Dimensions ....................................................... 18
Changes to Ordering Guide .......................................................... 18
11/2013—Rev. 0 to Rev. A
Added Figure 29, Renumbered Sequentially .............................. 12
Updated Outline Dimensions ....................................................... 18
7/2011—Revision 0: Initial Version
Rev. B | Page 2 of 18
Data Sheet
ADL5605
SPECIFICATIONS
VCC1 = 5 V and TA = 25°C, unless otherwise noted. 1
Table 1.
Parameter
OVERALL FUNCTION
Frequency Range
FREQUENCY = 748 MHz ± 20 MHz
Gain
vs. Frequency
vs. Temperature
vs. Supply
Output 1 dB Compression Point (P1dB)
vs. Frequency
vs. Temperature
vs. Supply
Output Third-Order Intercept (OIP3)
vs. Frequency
vs. Temperature
vs. Supply
Noise Figure
FREQUENCY = 881 MHz ± 13 MHz
Gain
vs. Frequency
vs. Temperature
vs. Supply
Output 1 dB Compression Point (P1dB)
vs. Frequency
vs. Temperature
vs. Supply
Output Third-Order Intercept (OIP3)
vs. Frequency
vs. Temperature
vs. Supply
Noise Figure
FREQUENCY = 943 MHz ± 18 MHz
Gain
vs. Frequency
vs. Temperature
vs. Supply
Output 1 dB Compression Point (P1dB)
vs. Frequency
vs. Temperature
vs. Supply
Adjacent Channel Power Ratio (ACPR)
Output Third-Order Intercept (OIP3)
vs. Frequency
vs. Temperature
vs. Supply
Noise Figure
Test Conditions/Comments
Min
Typ
700
±20 MHz
−40°C ≤ TA ≤ +85°C
4.75 V to 5.25 V
±20 MHz
−40°C ≤ TA ≤ +85°C
4.75 V to 5.25 V
∆f = 1 MHz, POUT = 14 dBm per tone
±20 MHz
−40°C ≤ TA ≤ +85°C
4.75 V to 5.25 V
±13 MHz
−40°C ≤ TA ≤ +85°C
4.75 V to 5.25 V
±13 MHz
−40°C ≤ TA ≤ +85°C
4.75 V to 5.25 V
∆f = 1 MHz, POUT = 14 dBm per tone
±13 MHz
−40°C ≤ TA ≤ +85°C
4.75 V to 5.25 V
±18 MHz
−40°C ≤ TA ≤ +85°C
4.75 V to 5.25 V
±18 MHz
−40°C ≤ TA ≤ +85°C
4.75 V to 5.25 V
POUT = 18 dBm, one-carrier W-CDMA,
64 DPCH, frequency = 946 MHz
∆f = 1 MHz, POUT = 14 dBm per tone
±18 MHz
−40°C ≤ TA ≤ +85°C
4.75 V to 5.25 V
Rev. B | Page 3 of 18
Max
Unit
1000
MHz
24.3
+0.01/−0.19
±0.8
±0.07
31.4
−0.68/+0.08
+0.94/−1.99
−0.24/−0.05
41.9
−0.22/+0.16
+0.07/−1.56
+0.04/+0.09
4.8
dB
dB
dB
dB
dBm
dB
dB
dB
dBm
dB
dB
dB
dB
23.0
−0.03/−0.08
±0.7
±0.05
31.4
−0.18/−0.11
±0.6
−0.4/+0.3
43.4
−0.32/+0.40
−0.19/−0.99
+0.21/−0.03
4.7
dB
dB
dB
dB
dBm
dB
dB
dB
dBm
dB
dB
dB
dB
23.0
+0.28/−0.04
±0.8
±0.04
30.9
+0.39/−0.08
+0.7/−0.9
−0.43/+0.35
51
dB
dB
dB
dB
dBm
dB
dB
dB
dBc
44.2
−0.47/−0.10
+0.7/−1.6
−0.08/+0.07
4.8
dBm
dB
dB
dB
dB
ADL5605
Parameter
POWER-DOWN INTERFACE
Logic Level to Enable
Logic Level to Disable
DISABLE Pin Current
VCC1 Pin Current1
Enable Time
Disable Time
POWER INTERFACE
Supply Voltage
Supply Current
vs. Temperature
1
Data Sheet
Test Conditions/Comments
DISABLE pin
VDISABLE decreasing
VDISABLE increasing
VDISABLE = 5 V
VDISABLE = 5 V
10% of control pulse to 90% of RFOUT
10% of control pulse to 90% of RFOUT
RFOUT pin
Min
1.4
4.75
−40°C ≤ TA ≤ +85°C
VCC1 is the supply to the DUT through the RFOUT pins.
Rev. B | Page 4 of 18
Typ
Max
Unit
0
5
1.4
5.5
75
20
1.1
V
V
mA
mA
ns
ns
5
307
−20/+1
5.25
385
V
mA
mA
Data Sheet
ADL5605
TYPICAL SCATTERING PARAMETERS
VCC1 = 5 V and TA = 25°C; the effects of the test fixture have been de-embedded up to the pins of the device. 1
Table 2.
Frequency
(MHz)
100
150
200
250
300
350
400
450
500
550
600
650
700
750
800
850
900
950
1000
1050
1100
1150
1200
1250
1300
1350
1400
1450
1500
1550
1600
1650
1700
1750
1800
1850
1900
1950
2000
1
S11
Magnitude (dB)
−2.38
−2.63
−2.95
−3.50
−4.41
−4.58
−5.11
−6.82
−7.26
−7.66
−8.25
−8.86
−9.58
−10.59
−11.75
−13.27
−15.44
−18.94
−26.34
−26.92
−18.87
−15.30
−13.83
−13.51
−13.68
−14.26
−14.96
−15.76
−16.83
−17.90
−19.28
−20.56
−22.42
−24.45
−26.42
−28.73
−29.99
−29.61
−27.80
Angle (°)
162.05
153.17
144.23
135.13
127.84
124.74
110.20
108.32
106.20
101.35
95.77
89.58
82.66
75.33
66.62
57.13
46.13
29.27
−2.06
−130.02
−171.63
163.88
145.18
129.85
117.81
108.51
99.61
92.58
86.52
79.79
73.87
67.65
60.60
51.72
38.39
21.43
−4.11
−32.34
−55.73
S21
Magnitude (dB)
5.53
14.11
18.99
22.75
25.46
23.14
17.94
22.16
21.56
20.40
19.42
18.55
17.89
17.40
17.07
16.89
16.84
16.93
16.96
16.77
16.17
14.89
13.13
11.09
8.95
6.91
4.91
3.04
1.23
−0.47
−2.09
−3.63
−5.10
−6.53
−7.92
−9.27
−10.56
−11.84
−13.07
Angle (°)
133.84
95.13
67.83
39.76
−7.79
−63.51
−30.49
−61.71
−87.12
−105.19
−118.96
−130.30
−140.88
−150.63
−160.56
−170.83
178.03
165.27
150.36
132.88
113.62
94.11
76.86
62.33
50.66
41.54
33.49
26.87
21.09
16.01
11.40
7.32
3.62
0.23
−3.05
−6.05
−8.66
−11.11
−13.38
VCC1 is the supply to the DUT through the RFOUT pins.
Rev. B | Page 5 of 18
S12
Magnitude (dB)
−48.08
−47.50
−55.96
−55.27
−61.09
−61.80
−52.49
−67.98
−62.64
−61.53
−61.21
−61.13
−59.03
−61.26
−57.17
−56.35
−56.74
−54.82
−52.26
−54.70
−54.77
−53.44
−55.60
−55.37
−57.24
−59.07
−60.44
−61.45
−57.41
−62.00
−56.83
−57.60
−59.47
−58.70
−55.11
−58.19
−61.08
−57.28
−56.29
Angle (°)
12.48
2.17
−119.96
52.76
77.07
140.72
171.89
−27.39
−21.99
34.70
99.93
129.82
107.89
91.70
92.00
107.58
99.86
107.20
73.48
68.96
47.54
43.95
11.97
33.66
20.12
24.50
14.20
45.66
62.21
53.37
57.90
58.62
77.96
76.85
66.53
37.40
43.12
78.91
83.05
S22
Magnitude (dB)
−1.30
−0.55
−0.68
−1.24
−1.10
−1.06
−1.15
−1.11
−0.87
−0.92
−0.78
−0.87
−0.87
−0.90
−0.93
−0.93
−0.96
−0.96
−0.98
−0.94
−0.81
−0.76
−0.72
−0.66
−0.68
−0.66
−0.69
−0.63
−0.69
−0.66
−0.69
−0.68
−0.68
−0.67
−0.68
−0.67
−0.68
−0.67
−0.68
Angle (°)
−147.53
−172.43
−173.81
−171.76
−176.42
−177.13
−176.29
−177.02
−177.37
−179.14
179.80
179.43
178.46
178.01
177.54
177.22
176.90
176.66
176.43
176.27
176.15
175.49
174.79
173.83
173.19
172.57
171.85
171.46
170.87
170.42
169.98
169.51
168.99
168.59
168.10
167.72
167.18
166.94
166.45
ADL5605
Data Sheet
ABSOLUTE MAXIMUM RATINGS
THERMAL RESISTANCE
Table 3.
Parameter
Supply Voltage, VCC11
Input Power (50 Ω Impedance)
Internal Power Dissipation (Paddle Soldered)
Maximum Junction Temperature
Lead Temperature (Soldering 60 sec)
Operating Temperature Range
Storage Temperature Range
1
Rating
6.5 V
20 dBm
2W
150°C
240°C
−40°C to +85°C
−65°C to +150°C
Table 4 lists the junction-to-air thermal resistance (θJA) and the
junction-to-paddle thermal resistance (θJC) for the ADL5605.
For more information, see the Thermal Considerations section.
Table 4. Thermal Resistance
Package Type
16-Lead LFCSP (CP-16-20)
ESD CAUTION
VCC1 is the supply to the DUT through the RFOUT pins.
Stresses at or above those listed under Absolute Maximum
Ratings may cause permanent damage to the product. This is a
stress rating only; functional operation of the product at these
or any other conditions above those indicated in the operational
section of this specification is not implied. Operation beyond
the maximum operating conditions for extended periods may
affect product reliability.
Rev. B | Page 6 of 18
θJA
52.1
θJC
12.1
Unit
°C/W
Data Sheet
ADL5605
13 NC
14 NC
16 NC
15 NC
PIN CONFIGURATION AND FUNCTION DESCRIPTIONS
RFIN 1
12 RFOUT
DISABLE 2
ADL5605
11 RFOUT
VCC 3
TOP VIEW
(Not to Scale)
10 RFOUT
9
NOTES
1. NC = NO CONNECT. DO NOT CONNECT TO THIS PIN.
2. THE EXPOSED PADDLE SHOULD BE SOLDERED TO
A LOW IMPEDANCE ELECTRICAL AND THERMAL
GROUND PLANE.
09353-003
NC 7
RFOUT
NC 8
NC 5
NC 6
VBIAS 4
Figure 3. Pin Configuration
Table 5. Pin Function Descriptions
Pin No.
1
2
Mnemonic
RFIN
DISABLE
3
VCC
4
5, 6, 7, 8, 13,
14, 15, 16
9, 10, 11, 12
VBIAS
NC
RFOUT
EP
Description
RF Input. Requires a dc blocking capacitor.
Connect this pin to 5 V to disable the part. In the disabled state, the part draws approximately 5 mA
of current from the power supply and 1.4 mA from the DISABLE pin.
Under normal operation, this pin is connected to the power supply and draws a combined 307 mA
of current. When this pin is grounded along with the VBIAS pin, the device is disabled and draws
approximately 1.4 mA from the DISABLE pin.
Applying 5 V to this pin enables the bias circuit. When this pin is grounded, the device is disabled.
No Connect. Do not connect to this pin.
RF Output. DC bias is provided to this pin through an inductor that is connected to the 5 V power
supply. The RF path requires a dc blocking capacitor.
The exposed paddle should be soldered to a low impedance electrical and thermal ground plane.
Rev. B | Page 7 of 18
ADL5605
Data Sheet
TYPICAL PERFORMANCE CHARACTERISTICS
748 MHZ FREQUENCY TUNING BAND
42
45
46
–40°C
40
OIP3 (dBm)
40
44
38
42
+25°C
36
P1dB (dBm)
GAIN (dB)
25
20
38
–40°C
32
36
+25°C
NF (dB)
738
743
748
32
26
5
733
34
+85°C
28
10
0
728
34
30
15
40
+85°C
753
758
763
768
FREQUENCY (MHz)
OIP3 (dBm)
P1dB (dBm)
30
30
24
728
733
738
743
748
753
758
28
768
763
09353-007
35
09353-004
NOISE FIGURE, GAIN, P1dB, OIP3 (dB, dBm)
50
FREQUENCY (MHz)
Figure 4. Noise Figure, Gain, P1dB, and OIP3 vs. Frequency
(OIP3 at POUT = 14 dBm per Tone)
Figure 7. P1dB and OIP3 vs. Frequency and Temperature
(OIP3 at POUT = 14 dBm per Tone)
44
28
27
43
768MHz
26
–40°C
42
OIP3 (dBm)
GAIN (dB)
25
+25°C
24
+85°C
23
748MHz
728MHz
41
40
22
733
738
743
748
753
758
763
768
FREQUENCY (MHz)
38
–2
09353-005
20
728
0
2
4
6
8
10
12
14
16
18
POUT PER TONE (dBm)
Figure 5. Gain vs. Frequency and Temperature
09353-008
39
21
Figure 8. OIP3 vs. POUT and Frequency
0
7
S22
–10
6
NOISE FIGURE (dB)
–20
–30
–40
5
+25°C
4
–40°C
S12
733
738
743
748
753
758
763
768
FREQUENCY (MHz)
2
728
738
748
758
FREQUENCY (MHz)
Figure 9. Noise Figure vs. Frequency and Temperature
Figure 6. Input Return Loss (S11), Output Return Loss (S22),
and Reverse Isolation (S12) vs. Frequency
Rev. B | Page 8 of 18
768
09353-009
–60
728
+85°C
3
–50
09353-006
S-PARAMETERS (dB)
S11
Data Sheet
ADL5605
881 MHZ FREQUENCY TUNING BAND
40
46
+25°C
OIP3 (dBm)
45
44
38
40
36
35
+85°C
–40°C
42
P1dB (dBm)
30
GAIN (dB)
25
20
15
34
40
–40°C
+25°C
38
32
+85°C
30
OIP3 (dBm)
P1dB (dBm)
36
10
NF (dB)
34
28
5
873
878
883
888
893
FREQUENCY (MHz)
26
32
868 870 872 874 876 878 880 882 884 886 888 890 892 894
09353-013
0
868
09353-010
NOISE FIGURE, GAIN, P1dB, OIP3 (dB, dBm)
50
FREQUENCY (MHz)
Figure 13. P1dB and OIP3 vs. Frequency and Temperature
(OIP3 at POUT = 14 dBm per Tone)
Figure 10. Noise Figure, Gain, P1dB, and OIP3 vs. Frequency
(OIP3 at POUT = 14 dBm per Tone)
45
27
894MHz
26
44
881MHz
25
OIP3 (dBm)
GAIN (dB)
43
–40°C
24
+25°C
23
+85°C
22
868MHz
42
41
21
FREQUENCY (MHz)
39
–2
09353-011
19
868 870 872 874 876 878 880 882 884 886 888 890 892 894
0
2
4
6
8
10
12
14
16
POUT PER TONE (dBm)
Figure 11. Gain vs. Frequency and Temperature
18
09353-014
40
20
Figure 14. OIP3 vs. POUT and Frequency
0
7
S22
S11
NOISE FIGURE (dB)
6
–20
–30
–40
873
878
5
+25°C
–40°C
4
883
888
893
FREQUENCY (MHz)
Figure 12. Input Return Loss (S11), Output Return Loss (S22),
and Reverse Isolation (S12) vs. Frequency
2
868
878
888
FREQUENCY (MHz)
Figure 15. Noise Figure vs. Frequency and Temperature
Rev. B | Page 9 of 18
09353-015
–60
868
+85°C
3
S12
–50
09353-012
S-PARAMETERS (dB)
–10
ADL5605
Data Sheet
943 MHZ FREQUENCY TUNING BAND
40
48
OIP3 (dBm)
38
46
+25°C
–40°C
40
36
35
44
P1dB (dBm)
+85°C
P1dB (dBm)
30
GAIN (dB)
25
20
15
42
34
+25°C
–40°C
32
40
30
OIP3 (dBm)
45
38
+85°C
10
36
28
NF (dB)
5
930
935
945
940
950
955
960
FREQUENCY (MHz)
26
925
930
935
940
945
950
34
960
955
09353-019
0
925
09353-016
NOISE FIGURE, GAIN, P1dB, OIP3 (dB, dBm)
50
FREQUENCY (MHz)
Figure 16. Noise Figure, Gain, P1dB, and OIP3 vs. Frequency
(OIP3 at POUT = 14 dBm per Tone)
Figure 19. P1dB and OIP3 vs. Frequency and Temperature
(OIP3 at POUT = 14 dBm per Tone)
46
27
26
45
943MHz
25
OIP3 (dBm)
GAIN (dB)
44
–40°C
24
+25°C
23
+85°C
22
925MHz
960MHz
43
42
21
930
935
940
945
950
955
960
FREQUENCY (MHz)
40
–2
09353-017
19
925
0
2
4
6
8
10
12
14
16
18
POUT PER TONE (dBm)
Figure 17. Gain vs. Frequency and Temperature
09353-020
41
20
Figure 20. OIP3 vs. POUT and Frequency
0
7
S22
–10
6
NOISE FIGURE (dB)
–20
–30
–40
S12
930
935
940
5
+25°C
–40°C
4
945
950
955
960
FREQUENCY (MHz)
Figure 18. Input Return Loss (S11), Output Return Loss (S22),
and Reverse Isolation (S12) vs. Frequency
2
925
930
935
940
945
950
955
FREQUENCY (MHz)
Figure 21. Noise Figure vs. Frequency and Temperature
Rev. B | Page 10 of 18
960
09353-021
–60
925
+85°C
3
–50
09353-018
S-PARAMETERS (dB)
S11
Data Sheet
ADL5605
35
30
30
25
25
PERCENTAGE (%)
35
15
20
15
10
10
5
5
0
43.7 43.8 43.9 44.0 44.1 44.2 44.3 44.4 44.5 44.6 44.7 44.8
OIP3 (dBm)
0
4.45
4.60
4.55
4.65
4.70
4.75
4.80
NOISE FIGURE (dB)
Figure 22. OIP3 Distribution at 943 MHz, 14 dBm per Tone
Figure 25. Noise Figure Distribution at 943 MHz
40
0
35
–10
–20
30
–30
25
ACPR (dBc)
PERCENTAGE (%)
4.50
09353-025
20
09353-022
PERCENTAGE (%)
GENERAL
20
15
–40
–50
–60
10
–70
946MHz
5
30.5
30.6 30.7 30.8 30.9 31.0 31.1 31.2 31.3 31.4 31.5
P1dB (dBm)
–90
09353-023
0
0
4
6
8
10
12
14
16
18
20
22
POUT (dBm)
Figure 26. ACPR vs. POUT, 3GPP, TM1-64, at 946 MHz
Figure 23. P1dB Distribution at 943 MHz
40
3.5
35
3.0
30
2.5
EVM (%)
25
20
2.0
1.5
15
1.0
10
946MHz
0
22.7
22.8
22.9
23.0
23.1
23.2
23.3
GAIN (dB)
23.4
0
–10
–5
0
5
10
15
20
POUT (dBm)
Figure 27. EVM vs. POUT, 3GPP, TM1-64, at 946 MHz
Figure 24. Gain Distribution at 943 MHz
Rev. B | Page 11 of 18
25
09353-027
0.5
5
09353-024
PERCENTAGE (%)
2
09353-026
–80
ADL5605
Data Sheet
320
SUPPLY CURRENT (mA)
5.25V
5V
310
4.75V
300
3
290
0
10
20
30
40
50
60
70
80
TEMPERATURE (°C)
Figure 28. Supply Current vs. Temperature and Supply Voltage at 943 MHz
860
CH3 1V Ω
CH2 1V Ω
M20ns 10GS/s
A CH2
2.5V
IT 4ps/pt
09353-029
280
–40 –30 –20 –10
09353-028
2
Figure 30. Turn-Off Time, 10% of Control Pulse to 90% of RFOUT
+25°C
660
560
3
460
2
+85°C
–40°C
260
–6 –4 –2 0 2 4 6 8 10 12 14 16 18 20 22 24 26 28 30 32 34
POUT (dBm)
Figure 29. Supply Current vs. POUT and Temperature at 943 MHz, VCC = 5 V
Rev. B | Page 12 of 18
CH3 1V Ω
CH2 1V Ω
M20ns 10GS/s
A CH2
2.5V
IT 4ps/pt
09353-030
360
09353-100
SUPPLY CURRENT (mA)
760
Figure 31. Turn-On Time, 10% of Control Pulse to 90% of RFOUT
Data Sheet
ADL5605
APPLICATIONS INFORMATION
BASIC LAYOUT CONNECTIONS
For complete information about component values and spacing
for the different frequency tuning bands, see the ADL5605
Matching section.
The basic connections for operating the ADL5605 are shown
in Figure 32. The RF matching components correspond to the
943 MHz frequency tuning band.
RF Output Interface
Pin 9 to Pin 12 are the RF output pins. Inductor L2, the shunt
capacitor, COUT, and the inductance from the microstrip line are
used to match the RF output to 50 Ω. For complete information
about component values and spacing for the different frequency
tuning bands, see the ADL5605 Matching section.
Power Supply
The voltage supply for the ADL5605, which ranges from 4.75 V
to 5.25 V, should be connected to the VCC1 test pin. The dc bias
to the output stage is supplied through L1 and is connected to the
RFOUT pin. Three decoupling capacitors (C7, C8, and C9) are
used to prevent RF signals from propagating on the dc lines. The
VBIAS and VCC pins can be directly connected to the main
supply voltage. Additional decoupling capacitors (C5, C6, C11,
C12, C13, and C14) are required on the VCC and VBIAS pins.
Power-Down
The ADL5605 can be disabled by connecting the DISABLE pin
to 5 V. When disabled, the ADL5605 draws approximately 5 mA
of current from the power supply and 1.4 mA from the DISABLE
pin. Decoupling Capacitor C3 is recommended to prevent the
propagation of RF signals. To completely shut down the device,
connect the VCC pin, the VBIAS pin, and the VCC1 test pin to
ground. In this state, the part draws approximately 1.4 mA from
the DISABLE pin.
RF Input Interface
Pin 1 is the RF input pin for the ADL5605. The RF input is easily
matched to 50 Ω with only one shunt capacitor and the microstrip line used as an inductor. For the 881 MHz and 943 MHz
frequency tuning bands, the input requires no external matching
components.
C1
100pF
RFIN
16
15
14
13
NC
NC
NC
NC
1
RFIN
RFOUT 12
2
DISABLE
RFOUT 11
ADL5605
C3
10pF
DISABLE
VCC
C11
10µF
C6
0.01µF
C5
100pF
3
VCC
4
VBIAS
RFOUT 10
RFOUT 9
NC
NC
NC
NC
5
6
7
8
COUT
8pF
C2
100pF RFOUT
L2
1.6nH
L1
18nH
C7
100pF
C8
0.01µF
C14
10µF
C13
0.01µF
C12
100pF
C9
10µF
VCC1
Figure 32. Basic Connections
Rev. B | Page 13 of 18
09353-031
VBIAS
ADL5605
Data Sheet
ADL5605 MATCHING
Figure 33 to Figure 35 show the matching networks.
The RF input of the ADL5605 can be easily matched to 50 Ω
with at most one external component and the microstrip line
used as an inductor. The RF output requires one series inductor,
one shunt capacitor, and the microstrip line used as an inductor.
Table 6 lists the required matching component values. Capacitors CIN and COUT are Murata GRM155 series (0402 size), and
Inductor L2 is a Coilcraft® 0603CS series (0603 size).
Table 6. Recommended Components for Basic Connections
Frequency (MHz)
728 to 768
868 to 894
925 to 961
CIN
2.4pF
λ1
L2 (nH)
2.7
1.6
1.6
COUT (pF)
12.0
8.0
8.0
Table 7. Matching Component Spacing
For all frequency tuning bands, the placement of CIN, L2, and
COUT is critical. Table 7 lists the recommended component
spacing for the various frequency tuning bands. The component
spacing is referenced from the center of the component to the
edge of the package.
C1
RFIN 100pF
CIN (pF)
2.4
N/A
N/A
Frequency (MHz)
728 to 768
868 to 894
925 to 961
16
15
14
13
NC
NC
NC
NC
1
RFIN
RFOUT 12
2
DISABLE
RFOUT 11
ADL5605
RFOUT 10
COUT
12pF
λ3
λ2
λ2 (mils)
94.5
94.5
94.5
L2
2.7nH
RFOUT
C2
100pF
L1
18nH
9
09353-032
RFOUT
λ1 (mils)
63
N/A
N/A
Figure 33. ADL5605 Match Parameters, 748 MHz Frequency Tuning Band
C1
RFIN 100pF
16
15
14
13
NC
NC
NC
NC
1
RFIN
RFOUT 12
2
DISABLE
RFOUT 11
CIN
OPEN
ADL5605
RFOUT 10
λ2
L2
1.6nH
RFOUT
C2
100pF
L1
18nH
9
09353-033
RFOUT
COUT
8pF
λ3
Figure 34. ADL5605 Match Parameters, 881 MHz Frequency Tuning Band
C1
RFIN 100pF
16
15
14
13
NC
NC
NC
NC
1
RFIN
RFOUT 12
2
DISABLE
RFOUT 11
CIN
OPEN
ADL5605
RFOUT 10
9
λ2
L2
1.6nH
RFOUT
C2
100pF
L1
18nH
09353-034
RFOUT
COUT
8pF
λ3
Figure 35. ADL5605 Match Parameters, 943 MHz Frequency Tuning Band
Rev. B | Page 14 of 18
λ3 (mils)
169
268
240
Data Sheet
ADL5605
All adjacent channel power ratio (ACPR) and error vector
magnitude (EVM) measurements were made using a single
W-CDMA carrier and Test Model 1-64.
The signal is generated by a very low ACPR source and is measured at the output by a high dynamic range spectrum analyzer.
For ACPR measurements, the filter setting was chosen for low
ACPR; for EVM measurements, the low EVM setting was selected.
The spectrum analyzer incorporates an instrument noise correction function, and highly linear amplifiers were used to boost
the power levels for ACPR measurements.
Figure 26 shows ACPR vs. POUT at 946 MHz. For power levels
up to 18 dBm, an ACPR of 51 dBc or better can be achieved
at 946 MHz.
Figure 27 shows EVM vs. POUT at 946 MHz. The EVM measured
is 0.5% for power levels up to 18 dBm at 946 MHz. The baseline
composite EVM for the signal source was approximately 0.5%.
When operated in the linear region, there is little or no contribution to EVM by the amplifier.
THERMAL CONSIDERATIONS
For optimal performance, it is recommended that the thermal
vias be filled with a conductive paste of the equivalent thermal
conductivity specified earlier in this section; alternatively, an
external heat sink can be used to dissipate heat quickly without
affecting the die junction temperature. It is also recommended
that the ground pattern be extended above and below the device
to improve thermal efficiency (see Figure 36).
SOLDERING INFORMATION AND RECOMMENDED
PCB LAND PATTERN
Figure 36 shows the recommended land pattern for the ADL5605.
To minimize thermal impedance, the exposed paddle on the
4 mm × 4 mm LFCSP is soldered to a ground plane along with
Pin 5 to Pin 8 and Pin 13 to Pin 16. To improve thermal dissipation, 25 thermal vias are arranged in a 5 × 5 array under the
exposed paddle. Areas above and below the paddle are tied with
regular vias. If multiple ground layers exist, they should be tied
together using vias. For more information about land pattern
design and layout, see the AN-772 Application Note, A Design
and Manufacturing Guide for the Lead Frame Chip Scale Package
(LFCSP).
The ADL5605 is packaged in a thermally efficient 4 mm ×
4 mm, 16-lead LFCSP. The thermal resistance from junction
to air (θJA) is 52.1°C/W. The thermal resistance for the product
was extracted assuming a standard 4-layer JEDEC board with
25 copper plated thermal vias. The thermal vias are filled with
conductive copper paste (AE3030 with thermal conductivity of
7.8 W/mK and thermal expansion α1 of 4 × 10−5/°C and α2 of
8.6 × 10−5/°C). The thermal resistance from junction to case (θJC)
is 12.1°C/W, where the case is the exposed pad of the lead frame
package.
For the best thermal performance, it is recommended that as
many thermal vias as possible be added under the exposed pad
of the LFCSP. The thermal resistance values assume a minimum
of 25 thermal vias arranged in a 5 × 5 array with a via diameter
of 8 mils, via pad of 16 mils, and a pitch of 20 mils. The vias are
plated with copper, and the drill hole is filled with a conductive
copper paste.
16
13
RFIN
RFOUT
16 MIL VIA PAD
WITH 8 MIL VIA
5
8
09353-035
ACPR AND EVM
Figure 36. Recommended Land Pattern
Rev. B | Page 15 of 18
ADL5605
Data Sheet
EVALUATION BOARD
The evaluation board has a short, non-50 Ω line on its output
to accommodate the four output pins and to allow for easier low
inductance output matching. The pads for Pin 9 to Pin 12 are
included on this microstrip line and are included in all matches.
The evaluation board uses numbers as identifiers to aid in the
placement of matching components at both the RF input and
RF output of the device. Figure 38 and Figure 39 show images
of the board layout.
The schematic of the ADL5605 evaluation board is shown in
Figure 37. The evaluation board uses 25 mils wide, 50 Ω traces
and is made from IS410 material with a 20 mils gap to ground.
The evaluation board is tuned for operation at 943 MHz. The
inputs and outputs should be ac-coupled with appropriately
sized capacitors; therefore, for low frequency applications, the
value of C1 and C2 may need to be increased. DC bias is
provided to the output stage via an inductor (L1) connected
to the RFOUT pin. A bias voltage of 5 V is recommended.
C1
100pF
1
CIN
N/A
16
15
14
13
NC
NC
NC
NC
RFIN
RFOUT 12
2 DISABLE
COUT
8pF
RFOUT 11
ADL5605
C10
OPEN
DISABLE
C4
OPEN
C3
10pF
R4
OPEN
C11
10µF
VCC3
R1
0Ω
C6
0.01µF
3
VCC
RFOUT 10
4
VBIAS
RFOUT 9
C5
100pF
NC
NC
NC
NC
5
6
7
8
L1
18nH
L2
1.6nH
C7
100pF
C8
0.01µF
VCC2
R5
OPEN
C2
100pF RFOUT
C14
10µF
C13
0.01µF
C12
100pF
C9
10µF
R2
0Ω
VCC1
09353-036
RFIN
Figure 37. Evaluation Board, 943 MHz Frequency Tuning Band
Table 8. Evaluation Board Configuration Options, 943 MHz Frequency Tuning Band
Component
C1, C2
C3, C4, C5, C6, C7,
C8, C9, C10, C11,
C12, C13, C14
Function/Notes
Input/output dc blocking capacitors.
Power supply decoupling capacitors. Power supply decoupling capacitors are required to
filter out the high frequency noise on the power supply. The smallest capacitor should be the
closest to the ADL5605. The main bias that goes through RFOUT is the most sensitive to noise
because the bias is connected directly to the RF output.
CIN
Input matching capacitor. To match the ADL5605 at the 943 MHz or 881 MHz frequency tuning
band, CIN is not required. For the 748 MHz frequency tuning band, CIN is set at a specific distance
from the device so that the microstrip line can act as inductance for the matching network
(see Table 7). If space is at a premium, an inductor can take the place of the microstrip line.
Output matching capacitor. The output match is set for 943 MHz and is easily changed for
other frequency tuning bands. The tolerance of this capacitor should be tight. COUT is set at
a specific distance from the device so that the microstrip line can act as inductance for the
matching network (see Table 7). If space is at a premium, an inductor can take the place of the
microstrip line. A short length of low impedance line on the output is embedded in the match.
Output matching inductor. The output match is set for 943 MHz and is easily changed for other
frequency tuning bands. A high Q Coilcraft inductor with tight tolerance is recommended.
The main bias for the ADL5605 comes through L1 to the output stage. L1 should be high
impedance for the frequency of operation while providing low resistance for the dc current.
The evaluation board uses a Coilcraft 0603HP-18NX_LU inductor; this 18 nH inductor provides
some of the match at 943 MHz.
To provide bias to all stages through just one supply, set R1 and R2 to 0 Ω, and leave R4 and
R5 open. To provide separate bias to stages, set R1 and R2 to open and R4 and R5 to 0 Ω.
The paddle should be connected to both thermal and electrical ground.
COUT
L2
L1
R1, R2, R4, R5
Exposed Paddle
Rev. B | Page 16 of 18
Default Value
C1, C2 = 100 pF
C3 = 10 pF
C5, C7, C12 = 100 pF
C6, C8, C13 = 0.01 µF
C9, C11, C14 = 10 µF
C4, C10 = open
CIN = open
COUT = 8.0 pF HQ
L2 = 1.6 nH HQ
L1 = 18 nH
R1, R2 = 0 Ω
R4, R5 = open
ADL5605
09353-038
09353-037
Data Sheet
Figure 39. Evaluation Board Layout, Bottom
Figure 38. Evaluation Board Layout, Top
Rev. B | Page 17 of 18
ADL5605
Data Sheet
OUTLINE DIMENSIONS
DETAIL A
(JEDEC 95)
4.10
4.00 SQ
3.90
PIN 1
INDICATOR
0.35
0.30
0.25
0.65
BSC
PIN 1
INDIC ATOR AREA OPTIONS
(SEE DETAIL A)
16
13
1
12
*2.40
EXPOSED
PAD
2.35 SQ
2.30
4
9
0.80
0.75
0.70
SIDE VIEW
PKG-004024
SEATING
PLANE
0.50
0.40
0.30
5
8
BOTTOM VIEW
0.05 MAX
0.02 NOM
COPLANARITY
0.08
0.20 REF
0.25 MIN
FOR PROPER CONNECTION OF
THE EXPOSED PAD, REFER TO
THE PIN CONFIGURATION AND
FUNCTION DESCRIPTIONS
SECTION OF THIS DATA SHEET.
*COMPLIANT TO JEDEC STANDARDS MO-220-WGGC-3
WITH EXCEPTION TO THE EXPOSED PAD.
03-30-2017-B
TOP VIEW
Figure 40. 16-Lead Lead Frame Chip Scale Package [LFCSP]
4 mm × 4 mm Body and 0.75 mm Package Height
(CP-16-20)
Dimensions shown in millimeters
ORDERING GUIDE
Model 1
ADL5605ACPZ-R7
ADL5605-EVALZ
1
Temperature Range
−40°C to +85°C
Package Description
16-Lead Lead Frame Chip Scale Package [LFCSP]
Evaluation Board
Z = RoHS Compliant Part.
©2011–2017 Analog Devices, Inc. All rights reserved. Trademarks and
registered trademarks are the property of their respective owners.
D09353-0-9/17(B)
Rev. B | Page 18 of 18
Package Option
CP-16-20
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