Dual Channel, High IP3,
100 MHz to 6 GHz Active Mixer
ADL5802
Data Sheet
FEATURES
FUNCTIONAL BLOCK DIAGRAM
APPLICATIONS
VPOS RF1+ RF1– GND RF2+ RF2–
24
22
21
20
19
GND
1
18
GND
GND
2
17
GND
OP1+
3
16
OP2+
OP1–
4
15
OP2–
GND
5
14
GND
13
VPOS
VPOS
Cellular base station receivers
Main and diversity receiver designs
Radio link downconverters
23
6
IP3
BIAS
ADL5802
7
8
9
10
11
12
ENBL GND LOIP LOIN GND VSET
07882-001
Power conversion gain of 1.6 dB
Wideband RF, LO, and IF ports
SSB noise figure of 11 dB
Input IP3 of 28 dBm
Input P1dB of 12 dBm
Typical LO drive of 0 dBm
Low LO leakage
Single supply operation: 5 V @ 240 mA
Exposed paddle, 4 mm × 4 mm, 24-lead LFCSP package
Figure 1.
GENERAL DESCRIPTION
The ADL5802 uses high linearity, double-balanced, active
mixer cores with integrated LO buffer amplifiers to provide
high dynamic range frequency conversion from 100 MHz to
6 GHz. The mixers benefit from a proprietary linearization
architecture that provides enhanced input IP3 performance
when subject to high input levels. A bias adjust feature allows
the input linearity, SSB noise figure, and dc current to be
optimized using a single control pin. The high input linearity
allows the device to be used in demanding cellular applications
where in-band blocking signals may otherwise result in
degradation in dynamic perform-ance. The balanced active
mixer arrangement provides superb LO to RF and LO to IF
Rev. C
leakage, typically better than −30 dBm. The IF outputs are
designed for a 200 Ω source impedance and provide a typical
voltage conversion gain of 7.6 dB when loaded into a 200 Ω
load.
The ADL5802 is fabricated using a SiGe high performance IC
process. The device is available in a compact 4 mm × 4 mm,
24-lead LFCSP package and operates over a −40°C to +85°C
temperature range. An evaluation board is also available.
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Tel: 781.329.4700 ©2009–2020 Analog Devices, Inc. All rights reserved.
Technical Support
www.analog.com
ADL5802
Data Sheet
TABLE OF CONTENTS
Features .............................................................................................. 1
Performance Up to 8 GHz ......Error! Bookmark not defined.
Applications ...................................................................................... 1
Circuit Description ........................................................................ 24
Functional Block Diagram .............................................................. 1
LO Amplifier and Splitter ......................................................... 24
General Description ......................................................................... 1
RF Voltage to Current (V-to-I) Converter ............................. 24
Revision History ............................................................................... 2
Mixer Cores................................................................................. 24
Specifications .................................................................................... 3
Mixer Load .................................................................................. 24
Absolute Maximum Ratings ........................................................... 5
Bias Circuit .................................................................................. 24
ESD Caution.................................................................................. 5
Applications Information ............................................................. 25
Pin Configuration and Function Descriptions ............................ 6
Basic Connections ...................................................................... 25
Typical Performance Characteristics ............................................. 7
RF and LO Ports ......................................................................... 25
Downconverter Mode Using a Broadband Balun ................... 7
IF Port .......................................................................................... 26
Downconverter Mode Using a Johanson 2.5 GHz Balun..... 12
Performance Up to 8 GHz ........................................................ 27
Downconverter Mode Using a Johanson 3.5 GHz Balun..... 15
Evaluation Board ............................................................................ 28
Downconverter Mode Using a Johanson 5.5 GHz Balun..... 18
Outline Dimensions ....................................................................... 30
Spur Performance....................................................................... 21
Ordering Guide .......................................................................... 30
REVISION HISTORY
10/2020—Rev. B to Rev. C
Changes to Figure 1.......................................................................... 1
Changes to Figure 2.......................................................................... 6
Added Performance Up to 8 GHz Section and Table 5;
Renumbered Sequentially ............................................................. 27
Updated Outline Dimensions ....................................................... 30
Changes to Ordering Guide .......................................................... 30
2/2015—Rev. A to Rev. B
Updated Outline Dimensions ....................................................... 29
Changes to Ordering Guide .......................................................... 29
6/2012—Rev. 0 to Rev. A
Changes to Downconverter Mode Using a Broadband Balun
Section and Figure 6 ......................................................................... 7
Changes to Figure 11 ....................................................................... 8
Changes to Figure 17, Figure 18, Figure 19, and Figure 20 ........ 9
Changes to Figure 27 ..................................................................... 11
Changed Downconverter Mode Using a Johanson 2.7 GHz
Balun Section to Downconverter Mode Using a Johanson 2.5 GHz
Balun Section .................................................................................. 12
Changes to Downconverter Mode Using a Johanson 2.5 GHz
Balun Section and Figure 31 ......................................................... 12
Changes o Figure 35 and Figure 36 ............................................. 13
Changes to Figure 40 ..................................................................... 14
Changes to Downconverter Mode Using a Johanson 3.5 GHz
Balun Section and Figure 44 ......................................................... 15
Changes to Figure 48 and Figure 49 ............................................ 16
Changes to Figure 53 ..................................................................... 17
Changed Downconverter Mode Using a Johanson 5.7 GHz
Balun Section to Downconverter Mode Using a Johanson 5.5 GHz
Balun Section .................................................................................. 18
Changes to Downconverter Mode Using a Johanson 5.5 GHz
Balun Section .................................................................................. 18
Changes to Figure 61 and Figure 62 ............................................ 19
Changes to Figure 20 ..................................................................... 20
Changes to 900 MHz Performance Section and 2090 MHz
Performance Section ...................................................................... 21
Changes to 2600 MHz Performance Section and 3500MHz
Performance Section ...................................................................... 22
Changes to 5800 MHz Performance Section.............................. 23
Updated Outline Dimensions ...................................................... 29
11/2009—Revision 0: Initial Version
Rev. C | Page 2 of 33
Data Sheet
ADL5802
SPECIFICATIONS
VS = 5 V, VSET = 4 V, TA = 25°C, fLO = (fRF − 153) MHz, LO power = 0 dBm, Z0 1 = 50 Ω, unless otherwise noted.
Table 1.
Parameter
RF INPUT INTERFACE
Return Loss
Input Impedance
RF Frequency Range
OUTPUT INTERFACE
Output Impedance
IF Frequency Range
DC Bias Voltage 2
LO INTERFACE
LO Power
Return Loss
Input Impedance
LO Frequency Range
POWER INTERFACE
Supply Voltage
Quiescent Current
Disable Current
Enable Time
Disable Time
DYNAMIC PERFORMANCE at fRF = 900 MHz/1900 MHz
Power Conversion Gain 3
Voltage Conversion Gain 4
SSB Noise Figure
SSB Noise Figure Under Blocking 5
Input Third Order Intercept 6
Input Second Order Intercept 7
Input 1 dB Compression Point
LO to IF Output Leakage
LO to RF Input Leakage
RF to IF Output Isolation
RFI1 to RFI2 Channel Isolation
IF/2 Spurious 8
IF/3 Spurious8
IF/2 Spurious8
IF/3 Spurious8
DYNAMIC PERFORMANCE at fRF = 2500 MHz 9
Power Conversion Gain 10
Voltage Conversion Gain4
SSB Noise Figure
SSB Noise Figure Under Blocking 11
Input Third Order Intercept6
Test Conditions/Comments
Min
Tunable to >20 dB over a limited bandwidth
Typ
VS
0
18
50
100
4.75
fRF = 900 MHz
fRF = 1900 MHz
fRF = 900 MHz
fRF = 1900 MHz
fCENT = 900 MHz
fCENT = 1900 MHz
fCENT = 900 MHz
fCENT = 1900 MHz
fCENT = 890 MHz
fCENT = 1890 MHz
fCENT = 890 MHz
fCENT = 1890 MHz
fRF = 900 MHz
fRF = 1900 MHz
Unfiltered IF output
6000
dB
Ω
MHz
600
5.25
Ω
MHz
V
240
LF
4.75
−10
Resistor programmable
ENBL pin low
Time from ENBL pin low to power-up
Time from ENBL pin high to power-down
Unit
18
50
100
Differential impedance, f = 200 MHz
Can be matched externally to 3000 MHz
Externally generated
Max
+10
6000
5
220
170
182
28
5.25
300
dBm
dB
Ω
MHz
V
mA
mA
ns
ns
0 dBm input power, fRF = 900 MHz
0 dBm input power, fRF = 900 MHz
0 dBm input power, fRF = 1900 MHz
0 dBm input power, fRF = 1900 MHz
1.5
1.6
7.5
7.6
10
11
18
22
26
28
60
45
12
12
−35
−30
25
45
−68
−67
−53
−59
dB
dB
dB
dB
dB
dB
dB
dB
dBm
dBm
dBm
dBm
dBm
dBm
dBm
dBm
dBc
dBc
dBc
dBc
dBc
dBc
fCENT = 2145 MHz
fCENT = 2500 MHz
−0.5
5.67
11.5
18
30
dB
dB
dB
dB
dBm
Rev. C | Page 3 of 33
ADL5802
Parameter
Input Second Order Intercept7
Input 1 dB Compression Point
LO to IF Output Leakage
LO to RF Input Leakage
RF to IF Output Isolation
RFI1 to RFI2 Channel Isolation
IF/2 Spurious8
IF/3 Spurious8
DYNAMIC PERFORMANCE at fRF = 3500 MHz 12
Power Conversion Gain 13
Voltage Conversion Gain4
SSB Noise Figure
SSB Noise Figure Under Blocking 14
Input Third Order Intercept5
Input Second Order Intercept7
Input 1 dB Compression Point
LO to IF Output Leakage
LO to RF Input Leakage
RF to IF Output Isolation
RFI1 to RFI2 Channel Isolation
IF/2 Spurious8
IF/3 Spurious8
DYNAMIC PERFORMANCE at fRF = 5500 MHz 15
Power Conversion Gain 16
Voltage Conversion Gain4
SSB Noise Figure
SSB Noise Figure Under Blocking 17
Input Third Order Intercept5
Input Second Order Intercept7
Input 1 dB Compression Point
LO to IF Output Leakage
LO to RF Input Leakage
RF to IF Output Isolation
RFI1 to RFI2 Channel Isolation
IF/2 Spurious8
IF/3 Spurious8
Data Sheet
Test Conditions/Comments
fCENT = 2500 MHz
Unfiltered IF output
0 dBm input power
0 dBm input power
fCENT = 3500 MHz
fCENT = 3500 MHz
fCENT = 3500 MHz
Unfiltered IF output
0 dBm input power
0 dBm input power
fCENT = 5800 MHz
fCENT = 5500 MHz
fCENT = 5500 MHz
Unfiltered IF output
0 dBm input power
0 dBm input power
Min
Typ
47
13
36
31
26
42
−52
−56
Max
−0.5
5.5
12.5
18
25
39
13
33
28
31
39
−46
−63
dB
dB
dB
dB
dBm
dBm
dBm
dBm
dBm
dBc
dBc
dBc
dBc
−3
5.67
14
17
23
35
13
42
27
50
33
−49
−64
dB
dB
dB
dB
dBm
dBm
dBm
dBm
dBm
dBc
dBc
dBc
dBc
Z0 is the characteristic impedance assumed for all measurements and the PCB.
Supply voltage must be applied from an external circuit through choke inductors.
3
Excluding 4:1 IF port transformer (TC4-1W+), RF and LO port transformers (TC1-1-13M+), and PCB loss.
4
ZSOURCE = 50 Ω, differential; ZLOAD = 200 Ω, differential 5 dBm; ZSOURCE is the impedance of the source instrument; ZLOAD is the load impedance at the output.
5
fRF1 = fCENT, fBLOCKER = (fCENT − 5) MHz, fLO = (fCENT − 153) MHz, blocker level = 0 dBm.
6
fRF1 = (fCENT − 1) MHz, fRF2 = fCENT, fLO = (fCENT − 153) MHz, each RF tone at −10 dBm.
7
fRF1 = fCENT, fRF2 = (fCENT + 100) MHz, fLO = (fCENT − 153) MHz, each RF tone at −10 dBm.
8
For details, see the Spur Performance section.
9
VS = 5 V, VSET = 4.5 V, TA = 25°C, fLO = (fRF − 211) MHz, LO power = 0 dBm, Z0 = 50 Ω.
10
Excluding 4:1 IF port transformer (TC4-1W+), RF and LO port transformers (2500BL14M050), and PCB loss.
11
fRF1 = fCENT, fBLOCKER = (fCENT − 5) MHz, fLO = (fCENT − 235) MHz, blocker level = 0 dBm.
12
VS = 5 V, VSET = 5 V, TA = 25°C, fLO = (fRF − 153) MHz, LO power = 0 dBm, Z0 = 50 Ω.
13
Including 4:1 IF port transformer (TC4-1W+), RF and LO port transformers (3600BL14M050), and PCB loss.
14
fRF1 = fCENT, fBLOCKER = (fCENT − 5) MHz, fLO = (fCENT − 153) MHz, blocker level = −20 dBm.
15
VS = 5 V, VSET = 4.8 V, TA = 25°C, fLO = (fRF − 380) MHz, LO power = 0 dBm, Z0 = 50 Ω.
16
Including 4:1 IF port transformer (TC4-1W+), RF and LO port transformers (5400BL15B050), and PCB loss.
17
fRF1 = fCENT, fBLOCKER = (fCENT − 5) MHz, fLO = (fCENT − 300) MHz, blocker level = −20 dBm.
1
2
Rev. C | Page 4 of 33
Unit
dBm
dBm
dBm
dBm
dBc
dBc
dBc
dBc
Data Sheet
ADL5802
ABSOLUTE MAXIMUM RATINGS
Table 2.
Parameter
Supply Voltage, VPOS
VSET, ENBL
OP1+, OP1−, OP2+, OP2−
RF Input Power
Internal Power Dissipation
θJA (Exposed Paddle Soldered Down)1
θJC (at Exposed Paddle)
Maximum Junction Temperature
Operating Temperature Range
Storage Temperature Range
1
Stresses at or above those listed under Absolute Maximum
Ratings may cause permanent damage to the product. This is a
stress rating only; functional operation of the product at these
or any other conditions above those indicated in the
operational section of this specification is not implied.
Operation beyond the maximum operating conditions for
extended periods may affect product reliability.
Rating
5.5 V
5.5 V
5.5 V
20 dBm
1.6 W
26.5°C/W
8.7°C/W
150°C
−40°C to +85°C
−65°C to +150°C
ESD CAUTION
As measured on the evaluation board. For details, see the Evaluation Board
section.
Rev. C | Page 5 of 33
ADL5802
Data Sheet
20 RF2+
19 RF2–
22 RF1–
21 GND
24 VPOS
23 RF1+
PIN CONFIGURATION AND FUNCTION DESCRIPTIONS
18 GND
GND 1
GND 2
17 GND
OP1+ 3
ADL5802
16 OP2+
OP1– 4
TOP VIEW
(Not to Scale)
15 OP2–
NOTES
1. EXPOSED PADDLE. MUST BE SOLDERED
TO GROUND.
07882-002
GND 11
VSET 12
LOIP 9
LOIN 10
13 VPOS
GND 8
14 GND
VPOS 6
ENBL 7
GND 5
Figure 2. Pin Configuration
Table 3. Pin Function Descriptions
Pin No.
1, 2, 5, 8, 11,
14, 17, 18, 21
3, 4
Mnemonic
GND
Function
Device Common (DC Ground).
OP1+, OP1−
6, 13, 24
7
9, 10
12
VPOS
ENBL
LOIP, LOIN
VSET
15, 16
OP2−, OP2+
19, 20
22, 23
RF2−, RF2+
RF1−, RF1+
EPAD
Channel 1 Mixer Differential Output Terminals. Bias must be applied through pull-up choke inductors or
the center tap of the IF transformer.
Positive Supply Voltage. 5.0 V nominal.
Device Enable. Pull low or leave disconnected to enable the device; pull high to disable the device.
Differential LO Input Terminals. Internally matched to 50 Ω; must be ac-coupled.
High Input IP3 Bias Control. For high input IP3 performance, apply ~4 V to 5 V. Improved noise figure (NF)
performance and lower supply current can be set by applying ~2 V to 3 V to the VSET pin. A resistor can be
connected to the supply to raise the voltage, whereas a resistor to GND lowers the voltage.
Channel 2 Mixer Differential Output Terminals. Bias must be applied through pull-up choke inductors or
the center tap of the IF transformer.
Differential RF Input Terminals for Channel 2. Internally matched to 50 Ω; must be ac-coupled.
Differential RF Input Terminals for Channel 1. Internally matched to 50 Ω; must be ac-coupled.
Exposed Paddle. Must be soldered to ground.
Rev. C | Page 6 of 33
Data Sheet
ADL5802
TYPICAL PERFORMANCE CHARACTERISTICS
DOWNCONVERTER MODE USING A BROADBAND BALUN
VS = 5 V, TA = 25°C, VSET = 4 V, IF = 153 MHz, as measured using a typical circuit schematic with low-side local oscillator (LO), unless
otherwise noted. Insertion loss of input and output baluns (TC1-1-13M+, TC4-1W+) is extracted from the gain measurement.
35
4.0
GAIN = 900MHz
GAIN = 1900MHz
INPUT IP3 = 900MHz
INPUT IP3 = 1900MHz
3.5
4
TA = –40°C
3
TA = +25°C
GAIN (dB)
GAIN (dB)
2
1
0
TA = +85°C
–1
07882-003
–2
–3
–4
0
500
1000
1500
2000
2500
RF FREQUENCY (MHz)
3000
3.0
25
2.5
20
2.0
15
1.5
10
5
1.0
–15
3500
30
INPUT IP3 (dBm)
5
–10
–5
0
5
LO POWER (dBm)
10
07882-006
6
15
Figure 6. Power Conversion Gain and Input IP3 vs. LO Power
Figure 3. Power Conversion Gain vs. RF Frequency
4.0
100
MEAN = 1.5
SD = 0.039
3.5
80
FREQUENCY (%)
3.0
GAIN (dB)
2.5
2.0
900MHz
1.5
1900MHz
60
40
1.0
07882-004
1.96
1.80
1.88
1.72
1.64
1.56
1.48
1.40
0
250
1.24
200
1.32
100
150
IF FREQUENCY (MHz)
1.08
50
1.00
0
1.16
0
07882-007
20
0.5
GAIN (dB)
Figure 7. Power Conversion Gain Distribution
2.5
0.25
2.0
0.20
0.15
1.5
0.10
1.0
GAIN = 900MHz
GAIN = 1900MHz
IPOS = 900MHz
IPOS = 1900MHz
0
0
1
2
TA = +25°C
3
VSET (V)
4
5
1.5
TA = +85°C
1.0
0.5
0.05
0
TA = –40°C
2.0
07882-005
0.5
2.5
6
Figure 5. Power Conversion Gain and IPOS vs. VSET
0
4.7
07882-008
0.30
GAIN (dB)
3.0
SUPPLY CURRENT (A)
GAIN (dB)
Figure 4. Power Conversion Gain vs. IF Frequency
4.8
4.9
5.0
SUPPLY (V)
5.1
5.2
Figure 8. Power Conversion Gain vs. Supply Voltage
Rev. C | Page 7 of 33
5.3
ADL5802
Data Sheet
VS = 5 V, TA = 25°C, VSET = 4 V, IF = 153 MHz, as measured using a typical circuit schematic with low-side local oscillator (LO), unless
otherwise noted. Insertion loss of input and output baluns (TC1-1-13M+, TC4-1W+) is extracted from the gain measurement.
80
40
TA = –40°C
TA = +25°C
70
35
TA = +85°C
60
30
15
50
40
30
10
20
5
10
0
0
500
1000
1500
2000
2500
RF FREQUENCY (MHz)
3000
TA = +25°C
07882-012
INPUT IP2 (dBm)
TA = –40°C
20
07882-009
INPUT IP3 (dBm)
TA = +85°C
25
0
0
3500
Figure 9. Input IP3 vs. RF Frequency
3000
2500
1500
2000
1000
RF FREQUENCY (MHz)
500
3500
Figure 12. Input IP2 vs. RF Frequency
40
80
70
35
900MHz
30
INPUT IP2 (dBm)
INPUT IP3 (dBm)
60
1900MHz
25
900MHz
50
1900MHz
40
30
20
20
15
10
0
50
100
150
IF FREQUENCY (MHz)
200
07882-013
07882-010
10
0
0
250
100
150
IF FREQUENCY (MHz)
200
250
Figure 13. Input IP2 vs. IF Frequency
Figure 10. Input IP3 vs. IF Frequency
80
35
70
30
900MHz
60
INPUT IP2 (dBm)
25
20
15
10
50
40
1900MHz
30
20
5
0
0
1
2
3
VSET (V)
10
4
5
07882-014
INPUT IP3 = 900MHz
INPUT IP3 = 1900MHz
NF = 900MHz
NF = 1900MHz
07882-011
INPUT IP3 (dBm) AND SSB NOISE FIGURE (dB)
50
0
0
6
1
2
3
VSET (V)
4
Figure 14. Input IP2 vs. VSET
Figure 11. Input IP3, Noise Figure vs. VSET
Rev. C | Page 8 of 33
5
6
Data Sheet
ADL5802
VS = 5 V, TA = 25°C, VSET = 4 V, IF = 153 MHz, as measured using a typical circuit schematic with low-side local oscillator (LO), unless
otherwise noted. Insertion loss of input and output baluns (TC1-1-13M+, TC4-1W+) is extracted from the gain measurement.
25
20
18
20
TA = –40°C
14
TA = +85°C
NOISE FIGURE (dB)
12
10
TA = +25°C
8
6
NF vs. IF, RF = 1900MHz
15
10
NF vs. IF, RF = 900MHz
5
07882-015
4
2
0
0
500
1000
1500
2000
2500
RF FREQUENCY (MHz)
3000
07882-018
INPUT P1dB (dBm)
16
0
0
3500
100
200
300
400
500
IF FREQUENCY (MHz)
600
700
Figure 18. SSB Noise Figure vs. IF Frequency (VSET = 2.0 V)
Figure 15. Input P1dB vs. RF Frequency
20
30
18
25
14
NOISE FIGURE (dB)
900MHz
12
1900MHz
10
8
6
NF, RF 1846MHz,
IF 153MHz, BLOCKER 1841MHz
15
10
NF, RF 951MHZ,
IF 153MHz, BLOCKER 946MHz
4
0
0
50
100
150
IF FREQUENCY (MHz)
200
0
–30
250
18
20
16
18
NOISE FIGURE (dB)
TA = +25°C
10
TA = –40°C
8
6
12
10
900MHz
6
07882-017
2
0
3000
1900MHz
8
2
1000
1500
2000
2500
RF FREQUENCY (MHz)
5
0
10
4
500
–10
–5
–15
BLOCKER LEVEL (dBm)
14
4
0
–20
16
TA = +85°C
12
–25
Figure 19. SSB Noise Figure vs. Blocker Level (VSET = 2.0 V)
Figure 16. Input P1dB vs. IF Frequency
14
07882-019
07882-016
5
2
NOISE FIGURE (dB)
20
0
–15
3500
Figure 17. SSB Noise Figure vs. RF Frequency (VSET = 2.0 V)
07882-020
INPUT P1dB (dBm)
16
–10
–5
0
5
LO LEVEL (dBm)
10
Figure 20. SSB Noise Figure vs. LO Drive (VSET = 2.0 V)
Rev. C | Page 9 of 33
15
ADL5802
Data Sheet
VS = 5 V, TA = 25°C, VSET = 4 V, IF = 153 MHz, as measured using a typical circuit schematic with low-side local oscillator (LO), unless
otherwise noted. Insertion loss of input and output baluns (TC1-1-13M+, TC4-1W+) is extracted from the gain measurement.
–10
–0
RF RETURN LOSS 5500MHz BALUN:
5400BL15B050 3pF INPUT CAPACITANCE
–15
–5
LO TO IF LEAKAGE (dBm)
–20
RETURN LOSS (dB)
–10
–15
–20
RF RETURN LOSS 3500MHz BALUN:
3600BL14M050 1.5pF INPUT CAPACITANCE
–25
RF RETURN LOSS 2500MHz BALUN:
2500BL14M050 3pF INPUT CAPACITANCE
–30
TA = –40°C
–25
TA = +25°C
–30
–35
–40
TA = +85°C
–45
07882-021
RF RETURN LOSS 900MHz AND 1900MHz BALUN:
TC1-1-13M+ 100pF INPUT CAPACITANCE
–40
0
1000
2000
3000
4000
5000
FREQUENCY (MHz)
6000
07882-024
–50
–35
–55
–60
7000
0
Figure 21. RF Return Loss Measured Differentially at the RF Port
3500
–15
–20
LO TO RF LEAKAGE (dBm)
–10
–15
LO RETURN LOSS BALUN:
TC1-1-13M+ 100pF
INPUT CAPACITANCE
–20
TA = +85°C
–25
TA = +25°C
–30
–35
TA = –40°C
–40
–45
–50
–25
07882-022
LO RETURN LOSS 3500MHz BALUN:
3600BL14M050 1.5pF
INPUT CAPACITANCE
–30
0
1000
2000
3000
4000
5000
FREQUENCY (MHz)
6000
07882-025
RETURN LOSS (dB)
3000
–10
LO RETURN LOSS 2500MHz BALUN:
2500BL14M050 3pF
LO RETURN LOSS 5500MHz BALUN:
INPUT CAPACITANCE
5400BL15B050 3pF
INPUT CAPACITANCE
–5
–55
–60
0
7000
Figure 22. LO Return Loss Measured Differentially at the LO Port
400
6
300
4
RESISTANCE
200
2
1000
3000
3500
Figure 25. LO to RF Leakage vs. LO Frequency
07882-023
0
100
IF FREQUENCY (MHz)
1000
1500
2000
2500
LO FREQUENCY (MHz)
0
CAPACITANCE
100
500
–2
3000
–10
–20
TA = +25°C
–30
TA = +85°C
–40
TA = –40°C
–50
07882-026
8
RF TO IF OUTPUT ISOLATION (dBc)
500
CAPACITANCE (pF)
RESISTANCE (Ω)
1000
1500
2000
2500
LO FREQUENCY (MHz)
Figure 24. LO to IF Leakage vs. LO Frequency
0
0
10
500
–60
0
Figure 23. IF Differential Output Impedance (R Parallel C Equivalent)
Rev. C | Page 10 of 33
500
1000
1500
2000
2500
RF FREQUENCY (MHz)
3000
Figure 26. RF to IF Output Isolation vs. RF Frequency
3500
Data Sheet
ADL5802
VS = 5 V, TA = 25°C, VSET = 4 V, IF = 153 MHz, as measured using a typical circuit schematic with low-side local oscillator (LO), unless
otherwise noted. Insertion loss of input and output baluns (TC1-1-13M+, TC4-1W+) is extracted from the gain measurement.
65
60
TA = –40°C
55
TA = +25°C
50
45
TA = +85°C
40
35
30
07882-027
CHANNEL-TO-CHANNEL ISOLATION (dB)
70
25
20
0
500
1000
1500
2000
2500
RF FREQUENCY (MHz)
3000
3500
Figure 27. Channel-to-Channel Isolation
Rev. C | Page 11 of 33
ADL5802
Data Sheet
DOWNCONVERTER MODE USING A JOHANSON 2.5 GHZ BALUN
VS = 5 V, TA = 25°C, VSET = 4.5 V, IF = 211 MHz, as measured using a typical circuit schematic with low-side LO, unless otherwise
noted. Insertion loss of input and output baluns (2500BL14M050, TC4-1W+) is included in the gain measurement.
35
4
3
TA = –40°C
1
TA = +25°C
0
–1
–2
TA = +85°C
07882-028
–3
–4
–5
1900
2100
2300
2500
2700
RF FREQUENCY (MHz)
2900
25
INPUT IP3
20
15
NOISE FIGURE
10
5
0
0
3100
5
0.30
4
0.27
0.09
–3
0.06
–4
0.03
3
VSET (V)
4
5
TA = –40°C
50
45
TA = +25°C
40
30
1900
6
2100
2300
2500
2700
RF FREQUENCY (MHz)
2900
3100
5
6
Figure 32. Input IP2 vs. RF Frequency
Figure 29. Power Conversion Gain and IPOS vs. VSET
35
6
35
0
–5
INPUT IP2 (dBm)
–2
07882-029
0.12
2
5
TA = +85°C
SUPPLY CURRENT (A)
0.15
GAIN
–1
50
TA = +85°C
TA = +25°C
48
30
46
25
44
INPUT IP2 (dBm)
TA = –40°C
20
15
42
40
38
36
10
0
1900
2100
2300
2500
2700
RF FREQUENCY (MHz)
2900
07882-033
34
5
07882-030
INPUT IP3 (dBm)
GAIN (dB)
0.18
1
1
4
55
0.21
2
0
3
VSET (V)
60
0.24
IPOS
0
2
Figure 31. Input IP3, Noise Figure vs. VSET
Figure 28. Power Conversion Gain vs. RF Frequency
3
1
07882-032
GAIN (dB)
2
30
07882-031
INPUT IP3 (dBm) AND SSB NOISE FIGURE (dB)
5
32
30
3100
0
1
2
3
VSET (V)
4
Figure 33. Input IP2 vs. VSET
Figure 30. Input IP3 vs. RF Frequency
Rev. C | Page 12 of 33
Data Sheet
ADL5802
VS = 5 V, TA = 25°C, VSET = 4.5 V, IF = 211 MHz, as measured using a typical circuit schematic with low-side LO, unless otherwise
noted. Insertion loss of input and output baluns (2500BL14M050, TC4-1W+) is included in the gain measurement
15
0
TA = +25°C
TA = +85°C
–5
14
INPUT P1dB (dBm)
13
TA = –40°C
12
11
10
–15
–20
–25
TA = –40°C
–30
–35
TA = +25°C
–40
8
1900
07882-034
9
2100
2300
2500
2700
RF FREQUENCY (MHz)
2900
TA = +85°C
–45
–50
1900
3100
07882-037
LO TO IF LEAKAGE (dBm)
–10
2100
2300
2500
2700
2900
3100
LO FREQUENCY (MHz)
Figure 37. LO to IF Leakage vs. LO Frequency
Figure 34. Input P1dB vs. RF Frequency
20
–30
18
–31
16
–32
TA = +85°C
TA = +85°C
TA = +25°C
12
10
TA = –40°C
8
6
TA = –40°C
–34
–35
–36
–37
–38
07882-035
4
2
0
1800
–33
2000
2200
2400
2600
RF FREQUENCY (MHz)
2800
07882-038
NOISE FIGURE (dB)
14
LO TO RF LEAKAGE (dBm)
TA = +25°C
–39
–40
1900
3000
2500
2700
2300
LO FREQUENCY (MHz)
2100
2900
3100
Figure 38. LO to RF Leakage vs. LO Frequency
Figure 35. SSB Noise Figure vs. RF Frequency (VSET = 2.0 V)
30
20
NF, RF 2145MHz,
IF 230MHz, BLOCKER 2140MHz
15
10
5
0
–60
07882-036
NOISE FIGURE (dB)
25
–50
–40
–30
–20
–10
0
–23
TA = –40°C
–25
–27
TA = +85°C
–29
–31
–33
–35
1900
10
BLOCKER LEVEL (dBm)
Figure 36. SSB Noise Figure vs. Blocker Level (VSET = 2.0 V)
TA = +25°C
07882-039
RF TO IF OUTPUT ISOLATION (dBc)
–21
2100
2300
2500
2700
RF FREQUENCY (MHz)
2900
Figure 39. RF to IF Output Isolation vs. RF Frequency
Rev. C | Page 13 of 33
3100
ADL5802
Data Sheet
VS = 5 V, TA = 25°C, VSET = 4.5 V, IF = 211 MHz, as measured using a typical circuit schematic with low-side LO, unless otherwise
noted. Insertion loss of input and output baluns (2500BL14M050, TC4-1W+) is included in the gain measurement
48
46
TA = –40°C
44
42
40
TA = +25°C
38
TA = +85°C
36
34
07882-040
CHANNEL-TO-CHANNEL ISOLATION (dB)
50
32
30
1900
2100
2300
2500
2700
RF FREQUENCY (MHz)
2900
3100
Figure 40. Channel-to-Channel Isolation
Rev. C | Page 14 of 33
Data Sheet
ADL5802
DOWNCONVERTER MODE USING A JOHANSON 3.5 GHZ BALUN
VS = 5 V, TA = 25°C, VSET = 5 V, IF = 153 MHz, as measured using a typical circuit schematic with low-side LO, unless otherwise noted.
Insertion loss of input and output baluns (3600BL14M050, TC4-1W+) is included in the gain measurement.
25
5
30
4
INPUT IP3
INPUT IP3 (dBm)
2
TA = –40°C
1
GAIN (dB)
SSB NOISE FIGURE (dB)
25
20
3
TA = +25°C
0
–1
20
15
NOISE FIGURE
10
15
5
10
–2
07882-041
–4
3100
3300
3500
3700
RF FREQUENCY (MHz)
3900
5
0
0
4100
1
5
0.30
4
0.27
48
3
0.24
46
0.15
GAIN
0.12
–2
0.09
–3
0.06
–4
0.03
–5
0
2
3
VSET (V)
4
5
5
6
TA = –40°C
42
40
TA = +85°C
38
TA = +25°C
36
34
07882-042
–1
44
INPUT IP2 (dBm)
0.18
0
32
30
2900
6
3100
3300
3500
3700
RF FREQUENCY (MHz)
3900
4100
5
6
Figure 45. Input IP2 vs. RF Frequency
Figure 42. Power Conversion Gain and IPOS vs. VSET
30
50
TA = +85°C
48
TA = +25°C
25
46
TA = –40°C
44
INPUT IP2 (dBm)
20
15
10
40
38
3100
3300
3500
3700
RF FREQUENCY (MHz)
3900
07882-046
34
5
0
2900
42
36
07882-043
INPUT IP3 (dBm)
GAIN (dB)
0.21
1
1
4
50
SUPPLY CURRENT (A)
IPOS
0
3
VSET (V)
Figure 44. Input IP3, Noise Figure vs. VSET
Figure 41. Power Conversion Gain vs. RF Frequency
2
2
07882-045
–5
2900
07882-044
TA = +85°C
–3
32
30
4100
0
Figure 43. Input IP3 vs. RF Frequency
1
2
3
VSET (V)
4
Figure 46. Input IP2 vs. VSET
Rev. C | Page 15 of 33
ADL5802
Data Sheet
VS = 5 V, TA = 25°C, VSET = 5 V, IF = 153 MHz, as measured using a typical circuit schematic with low-side LO, unless otherwise noted.
Insertion loss of input and output baluns (3600BL14M050, TC4-1W+) is included in the gain measurement.
–20
15
TA = +85°C
TA = +25°C
14
LO TO IF LEAKAGE (dBm)
–25
12
TA = –40°C
11
10
TA = +25°C
–35
TA = +85°C
TA = –40°C
–40
07882-047
3100
3300
3500
3700
RF FREQUENCY (MHz)
3900
–50
2900
4100
3900
4100
–24
LO TO RF LEAKAGE (dBm)
14
12
10
TA = –40°C
TA = +25°C
8
6
4
TA = –40°C
–26
–28
–30
TA = +25°C
TA = +85°C
–32
–34
07882-048
–36
2
2900
3100
3300
3500
3700
3900
RF FREQUENCY (MHz)
4100
07882-051
NOISE FIGURE (dB)
3700
–22
TA = +85°C
16
–38
–40
2900
4300
Figure 48. SSB Noise Figure vs. RF Frequency (VSET = 2.0 V)
3100
3300
3500
3700
LO FREQUENCY (MHz)
3900
4100
Figure 51. LO to RF Leakage vs. LO Frequency
45
–10
RF TO IF OUTPUT ISOLATION (dBc)
40
35
30
25
NF, RF 3805MHz,
IF 300MHz, BLOCKER 3800MHz
15
10
07882-049
NOISE FIGURE (dB)
3500
–20
18
5
0
–60
3300
Figure 50. LO to IF Leakage vs. LO Frequency
20
20
3100
LO FREQUENCY (MHz)
Figure 47. Input P1dB vs. RF Frequency
0
2700
07882-050
–45
9
8
2900
–30
–50
–40
–30
–20
–10
0
–15
–20
–25
–30
TA = –40°C
TA = +25°C
TA = +85°C
–35
–40
–45
–50
2900
10
BLOCKER LEVEL (dBm)
07882-052
INPUT P1dB (dBm)
13
3100
3300
3500
3700
3900
RF FREQUENCY (MHz)
Figure 49. SSB Noise Figure vs. Blocker Level (VSET = 2.0 V)
Figure 52. RF to IF Output Isolation vs. RF Frequency
Rev. C | Page 16 of 33
4100
Data Sheet
ADL5802
VS = 5 V, TA = 25°C, VSET = 5 V, IF = 153 MHz, as measured using a typical circuit schematic with low-side LO, unless otherwise noted.
Insertion loss of input and output baluns (3600BL14M050, TC4-1W+) is included in the gain measurement.
48
46
44
42
TA = +25°C
40
38
TA = –40°C
36
TA = +85°C
34
07882-053
CHANNEL-TO-CHANNEL ISOLATION (dB)
50
32
30
2900
3100
3300
3500
3700
RF FREQUENCY (MHz)
3900
4100
Figure 53. Channel-to-Channel Isolation
Rev. C | Page 17 of 33
ADL5802
Data Sheet
DOWNCONVERTER MODE USING A JOHANSON 5.5 GHZ BALUN
VS = 5 V, TA = 25°C, VSET = 4.8 V, IF = 380 MHz, as measured using a typical circuit schematic with low-side LO, unless otherwise
noted. Insertion loss of input and output baluns (5400BL15B050, TC4-1W+) is included in the gain measurement.
25
30
2
20
24
–2
–4
18
15
NOISE FIGURE
10
12
TA = +25°C
6
5
07882-054
–6
5100
5300
5500
5700
RF FREQUENCY (MHz)
5900
0
0
6100
0
55
3
0.24
50
2
0.21
0.18
0
0.15
–1
0.12
0.09
–2
GAIN
0
3
VSET (V)
4
5
TA = +85°C
40
TA = +25°C
35
TA = –40°C
30
10
4900
6
5700
5500
5300
RF FREQUENCY (MHz)
5100
5900
Figure 58. Input IP2 vs. RF Frequency
Figure 55. Power Conversion Gain and IPOS vs. VSET
50
TA = –40°C
TA = +25°C
45
INPUT IP2 (dBm)
25
TA = +85°C
15
10
40
35
30
07882-056
5100
5700
5300
5500
RF FREQUENCY (MHz)
5900
20
1.5
6100
Figure 56. Input IP3 vs. RF Frequency
07882-059
25
5
0
4900
6
15
30
20
5
20
07882-055
0.03
–5
2
4
25
0.06
–4
1
45
INPUT IP2 (dBm)
IPOS
SUPPLY CURRENT (A)
0.27
INPUT IP3 (dBm)
GAIN (dB)
0.30
4
0
3
VSET (V)
60
5
–3
2
Figure 57. Input IP3, Noise Figure vs. VSET
Figure 54. Power Conversion Gain vs. RF Frequency
1
1
07882-058
–8
4900
07882-057
INPUT IP3 (dBm)
TA = +85°C
TA = –40°C
GAIN (dB)
IP3
NOISE FIGURE (dB)
0
2.0
2.5
3.0
3.5
4.0
VSET (V)
Figure 59. Input IP2 vs. VSET
Rev. C | Page 18 of 33
4.5
5.0
5.5
Data Sheet
ADL5802
VS = 5 V, TA = 25°C, VSET = 5 V, IF = 153 MHz, as measured using a typical circuit schematic with low-side LO, unless otherwise noted.
Insertion loss of input and output baluns (3600BL14M050, TC4-1W+) is included in the gain measurement.
16
–10
–15
LO TO IF LEAKAGE (dBm)
TA = +85°C
INPUT P1dB (dBm)
14
TA = +25°C
13
12
TA = –40°C
11
10
–20
–25
–30
–35
TA = –40°C
TA = +25°C
–40
–45
TA = +85°C
–50
8
4900
07882-060
9
5100
5300
5500
5700
RF FREQUENCY (MHz)
5900
07882-063
15
–55
–60
4900
6100
Figure 60. Input P1dB vs. RF Frequency
5100
5300
5500
5700
LO FREQUENCY (MHz)
5900
6100
Figure 63. LO to IF Leakage vs. LO Frequency
–15
25
–17
LO TO RF LEAKAGE (dBm)
15
10
TA = –40°C
TA = +25°C
TA = +85°C
5
–21
–23
TA = –40°C
TA = +25°C
–25
–27
–29
TA = +85°C
5100
5300
5500
5700
RF FREQUENCY (MHz)
5900
–33
–35
4900
6100
–30
40
–35
RF TO IF OUTPUT ISOLATION (dBc)
45
30
25
NF, RF 5805MHz,
IF 380MHz, BLOCKER 5800MHz
15
10
07882-062
NOISE FIGURE (dB)
35
5
0
–60
–50
–40
–30
–20
BLOCKER LEVEL (dBm)
–10
5100
5300
5500
5700
LO FREQUENCY (MHz)
5900
6100
Figure 64. LO to RF Leakage vs. LO Frequency
Figure 61. SSB Noise Figure vs. RF Frequency (VSET = 2.0 V)
20
07882-064
–31
07882-061
0
4900
–19
–40
TA = –40°C
–50
TA = +85°C
–55
–60
–65
–70
4900
0
TA = +25°C
–45
07882-065
NOISE FIGURE (dB)
20
5100
5300
5500
5700
5900
RF FREQUENCY (MHz)
Figure 62. SSB Noise Figure vs. Blocker Level (VSET = 2.0 V)
Figure 65. RF to IF Output Isolation vs. RF Frequency
Rev. C | Page 19 of 33
6100
ADL5802
Data Sheet
VS = 5 V, TA = 25°C, VSET = 5 V, IF = 153 MHz, as measured using a typical circuit schematic with low-side LO, unless otherwise noted.
Insertion loss of input and output baluns (3600BL14M050, TC4-1W+) is included in the gain measurement.
43
41
39
37
35
33
31
29
27
25
4900
TA = –40°C
TA = +25°C
TA = +85°C
5100
5300
5500
5700
RF FREQUENCY (MHz)
07882-066
CHANNEL-TO-CHANNEL ISOLATION (dB)
45
5900
6100
Figure 66. Channel-to-Channel Isolation
Rev. C | Page 20 of 33
Data Sheet
ADL5802
SPUR PERFORMANCE
All spur tables are (N × fRF) − (M × fLO) and were measured using the standard evaluation board (see the Evaluation Board section).
Mixer spurious products are measured in decibels relative to the carrier (dBc) from the IF output power level. Data was measured for
frequencies less than 6 GHz only. The typical noise floor of the measurement system is −100 dBm.
900 MHz Performance
VS = 5 V, VSET = 4 V, TA = 25°C, RF power = 0 dBm, LO power = 0 dBm, fRF = 900 MHz, fLO = 703 MHz, Z0 = 50 Ω.
0
N
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
−34.3
−49.1
−86.7
−91.8
≤−100
≤−100
1
−35.9
0.0
−69.2
−79.6
≤−100
≤−100
≤−100
≤−100
2
−25.5
−46.3
−68.2
≤−100
−96.4
≤−100
≤−100
≤−100
≤−100
3
−47.3
−19.8
−61.6
−67.3
≤−100
≤−100
≤−100
≤−100
≤−100
≤−100
4
−27.4
−64.3
−68.7
−98.0
≤−100
≤−100
≤−100
≤−100
≤−100
≤−100
5
−51.5
−30.0
−80.7
−71.0
≤−100
≤−100
≤−100
≤−100
≤−100
≤−100
≤−100
6
−37.5
−75.6
−67.5
≤−100
≤−100
≤−100
≤−100
≤−100
≤−100
≤−100
≤−100
≤−100
M
7
−62.1
−45.0
−88.1
−86.3
≤−100
≤−100
≤−100
≤−100
≤−100
≤−100
≤−100
≤−100
≤−100
8
−47.5
−67.8
−79.1
≤−100
≤−100
≤−100
≤−100
≤−100
≤−100
≤−100
≤−100
≤−100
≤−100
9
−55.3
−82.6
≤−100
≤−100
≤−100
≤−100
≤−100
≤−100
≤−100
≤−100
≤−100
≤−100
≤−100
10
11
12
13
14
−91.5
≤−100
≤−100
≤−100
≤−100
≤−100
≤−100
≤−100
≤−100
≤−100
≤−100
≤−100
≤−100
≤−100
−98.4
≤−100
≤−100
≤−100
≤−100
≤−100
≤−100
≤−100
≤−100
≤−100
≤−100
≤−100
≤−100
≤−100
≤−100
≤−100
≤−100
≤−100
≤−100
≤−100
≤−100
≤−100
≤−100
≤−100
≤−100
≤−100
≤−100
≤−100
≤−100
≤−100
≤−100
≤−100
≤−100
≤−100
≤−100
≤−100
≤−100
≤−100
≤−100
≤−100
≤−100
≤−100
≤−100
≤−100
≤−100
≤−100
≤−100
≤−100
≤−100
13
14
2090 MHz Performance
VS = 5 V, VSET = 4 V, TA = 25°C, RF power = 0 dBm, LO power = 0 dBm, fRF = 2090 MHz, fLO = 1842 MHz, Z0 = 50 Ω.
M
0
N
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
−26.8
−59.8
1
−43.0
0.0
−71.9
−67.6
2
−23.7
−59.6
−53.8
−97.6
≤−100
3
−52.9
−42.2
−67.5
−59.3
≤−100
≤−100
4
−80.5
−68.2
−92.2
−93.7
≤−100
≤−100
5
−84.1
−79.3
−97.8
−96.1
≤−100
≤−100
6
≤−100
≤−100
≤−100
≤−100
≤−100
≤−100
7
8
≤−100
≤−100
≤−100
≤−100
≤−100
≤−100
≤−100
≤−100
≤−100
≤−100
≤−100
Rev. C | Page 21 of 33
9
10
≤−100
≤−100
≤−100
≤−100
≤−100
≤−100
≤−100
≤−100
≤−100
≤−100
≤−100
11
≤−100
≤−100
≤−100
≤−100
≤−100
≤−100
12
≤−100
≤−100
≤−100
≤−100
≤−100
≤−100
≤−100
≤−100
≤−100
≤−100
≤−100
≤−100
≤−100
≤−100
≤−100
≤−100
≤−100
≤−100
ADL5802
Data Sheet
2600 MHz Performance
VS = 5 V, VSET = 4.5 V, TA = 25°C, RF power = 0 dBm, LO power = 0 dBm, fRF = 2600 MHz, fLO = 2350 MHz, Z0 = 50 Ω.
M
0
N
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
−27.5
−75.5
1
−37.9
0.0
−59.7
−75.0
2
−31.5
−62.6
−52.2
−88.7
≤−100
3
4
−36.3
−65.8
−56.3
≤−100
≤−100
−68.8
−86.8
−82.5
≤−100
5
−90.5
−92.1
−94.4
≤−100
6
≤−100
≤−100
≤−100
≤−100
7
8
≤−100
≤−100
≤−100
≤−100
≤−100
≤−100
≤−100
≤−100
≤−100
9
≤−100
≤−100
≤−100
≤−100
≤−100
10
≤−100
≤−100
≤−100
≤−100
≤−100
11
≤−100
≤−100
≤−100
≤−100
≤−100
12
≤−100
≤−100
≤−100
≤−100
≤−100
13
14
≤−100
≤−100
≤−100
≤−100
≤−100
≤−100
≤−100
≤−100
≤−100
13
14
3500 MHz Performance
VS = 5 V, VSET= 5 V, TA = 25°C, RF power = 0 dBm, LO power = 0 dBm, fRF = 3500 MHz, fLO = 3800 MHz, Z0 = 50 Ω.
M
0
N
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
−26.8
−59.8
1
−43.0
0.0
−71.9
−67.6
2
−23.7
−59.6
−53.8
−97.6
≤−100
3
−52.9
−42.2
−67.5
−59.3
≤−100
≤−100
4
−80.5
−68.2
−92.2
−93.7
≤−100
≤−100
5
−84.1
−79.3
−97.8
−96.1
≤−100
≤−100
6
≤−100
≤−100
≤−100
≤−100
≤−100
≤−100
7
8
≤−100
≤−100
≤−100
≤−100
≤−100
≤−100
≤−100
≤−100
≤−100
≤−100
≤−100
Rev. C | Page 22 of 33
9
10
≤−100
≤−100
≤−100
≤−100
≤−100
≤−100
≤−100
≤−100
≤−100
≤−100
≤−100
11
≤−100
≤−100
≤−100
≤−100
≤−100
≤−100
12
≤−100
≤−100
≤−100
≤−100
≤−100
≤−100
≤−100
≤−100
≤−100
≤−100
≤−100
≤−100
≤−100
≤−100
≤−100
≤−100
≤−100
≤−100
Data Sheet
ADL5802
5800 MHz Performance
VS = 5 V, VSET= 4.8 V, TA = 25°C, RF power = −10 dBm, LO power = 0 dBm, fRF = 5800 MHz, fLO = 5600 MHz, Z0 = 50 Ω.
M
0
N
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
−63.6
1
−28.3
0.0
2
−80.5
−48.6
3
−92.6
−64.2
4
−98.7
−90.5
5
−98.3
≤−100
6
−99.4
−81.6
7
−98.0
−87.2
Rev. C | Page 23 of 33
8
−95.9
−84.0
9
−99.5
≤−100
10
≤−100
≤−100
11
≤−100
≤−100
12
≤−100
≤−100
13
−99.6
≤−100
14
−99.8
≤−100
ADL5802
Data Sheet
CIRCUIT DESCRIPTION
The ADL5802 provides two double-balanced active mixers.
These mixers are designed for a 50 Ω input impedance and a
200 Ω output impedance. Both are driven from a common local
oscillator (LO) amplifier. The RF inputs and LO outputs are
differential, providing maximum usable bandwidth at the input
and output ports. The LO also operates with a 50 Ω input
impedance and can, optionally, be operated differentially or
single-ended. The input, output, and LO ports can be operated
over an exceptionally wide frequency range. The ADL5802 can
be configured as a downconvert mixer or as an upconvert mixer.
The ADL5802 can be divided into the following sections: the
local oscillator (LO) amplifier and splitter, the RF voltage-tocurrent (V-to-I) converter, the mixer cores, the output loads,
and the bias circuit. A simplified block diagram of the device is
shown in Figure 67. The LO block generates a pair of differential
LO signals to drive two mixer cores. The RF input is converted
into current by the V-to-I converters that then feed into the two
mixer cores. The internal differential load of the mixers is
designed for a wideband 200 Ω output impedance from the
mixer. Reference currents to each section are generated by the
bias circuit, which can be enabled or disabled using the ENBL
pin. A detailed description of each section of the ADL5802
follows.
VPOS RF1+ RF1– GND RF2+ RF2–
24
23
22
21
20
19
1
18
GND
GND
2
17
GND
OP1+
3
16
OP2+
OP1–
4
15
OP2–
GND
5
14
GND
VPOS
6
13
VPOS
IP3
BIAS
ADL5802
7
8
9
10
11
12
ENBL GND LOIP LOIN GND VSET
The differential RF input signal is applied to a voltage-to-current
converter that converts the differential input voltage to output
currents. The V-to-I converter provides a 50 Ω input
impedance. The V-to-I section bias current can be adjusted up
or down using the VSET pin. Adjusting the current up
improves IP3 and P1dB input but degrades SSB NF. Adjusting
the current down improves SSB NF but degrades IP3 and P1dB
input. The conversion gain remains nearly constant over a wide
range of VSET pin settings, allowing the part to be adjusted
dynamically without affecting the conversion gain. The current
adjustment can be made by connecting a resistor from the
VSET pin to the positive supply to increase the bias current or
from the VSET pin to ground to decrease the bias current. The
VSET pin impedance is approximately 675 Ω in series with two
diodes and an internal current source.
MIXER CORES
The ADL5802 has two double-balanced mixers that use high
performance SiGe NPN transistors. These mixers are based on
the Gilbert cell design of four cross-connected transistors.
MIXER LOAD
Each mixer load is designed to use a pair of 100 Ω resistors connected to the positive supply. This provides a 200 Ω differential
output resistance. The mixer output should be pulled to the
positive supply externally using a pair of RF chokes or using an
output transformer with the center tap connected to the
positive supply. It is possible to exclude these components when
the mixer core current is low, but both P1dB and IP3 are then
reduced.
The mixer load output can operate from direct current (dc) up to
approximately 500 MHz into a 200 Ω load. For upconversion
applications, the mixer load can be matched using off-chip
matching components. Transmit operation up to 2 GHz is
possible. See the Applications Information section for matching
circuit details.
07882-128
GND
RF VOLTAGE TO CURRENT (V-TO-I) CONVERTER
Figure 67. ADL5802 Block Diagram
BIAS CIRCUIT
LO AMPLIFIER AND SPLITTER
The LO input is amplified using a broadband LNA and is then
split and followed by separate LO limiting amplifiers. The LNA
input impedance is nominally 50 Ω. The LO is designed to
accommodate a wide range of LO input power levels. The LO
input is conditioned by the series of amplifiers to provide a well
controlled and limited LO swing to the mixer core, resulting in
excellent IP3. The LO circuit exhibits low additive noise,
resulting in an excellent mixer noise figure and output noise
under RF blocking. For optimal performance, the LO inputs
should be driven differentially but at lower frequencies; singleended drive is acceptable.
A band gap reference circuit generates the reference currents
used by the mixers. The bias circuit can be enabled and disabled
using the ENBL pin. If the ENBL pin is grounded or left open,
the part is enabled. Pulling the ENBL pin high shuts off the bias
circuit and disables the part. However, the ENBL pin does not
alter the current in the LO section and, therefore, does not
provide a true power-down feature. Certain configurations may
require the VSET pin to be connected to the positive supply
through a resistor. This will result in an increased mixer core
current. Unless this resistor to positive supply is removed, bias
current will continue to be supplied to the mixer core.
Rev. C | Page 24 of 33
Data Sheet
ADL5802
APPLICATIONS INFORMATION
BASIC CONNECTIONS
RF AND LO PORTS
The ADL5802 features dual channel mixers with a common
local oscillator (LO). The mixer is designed to translate between
radio frequencies (RF) and intermediate frequencies (IF). For
both upconversion and downconversion applications, RF1+
(Pin 23), RF1− (Pin 22), RF2+ (Pin 20), and RF2− (Pin 19)
must be configured as the input interfaces. OP1+ (Pin 3), OP1−
(Pin 4), OP2+ (Pin 16), and OP2− (Pin 15) must be configured
as the output interfaces. Figure 68 illustrates the basic connections
for ADL5802 operation.
The RF and LO input ports are designed for differential input
impedance of approximately 50 Ω. Figure 69 and Figure 70
illustrate the RF and LO interfaces, respectively. It is
recommended that each of the RF and LO differential ports be
driven through a balun for optimum performance. It is also
necessary to ac-couple both RF and LO ports with the proper
size capacitors. Table 4 lists the recommended components for
various RF frequency bands. The characterization data is
available in the Typical Performance Characteristics section.
RF2
RF1
T3
T5
C13
C5
C14
C12
VPOS
C8
C11
24
23
22
20
21
19
VPOS RF1+ RF1– GND RF2+ RF2–
C16
GND 18
2 GND
GND 17
3 OP1+
VPOS
OP2+ 16
C15
ADL5802
T4
VPOS
T2
4 OP1–
OP2– 15
5 GND
GND 14
C9
ENBL GND LOIP LOIN GND VSET
7
VPOS
VPOS 13
6 VPOS
C6
IF2P
9
8
10
11
C7
C10
12
VSET
C2
C3
T1
LO
Figure 68. Basic Connections Schematic
Rev. C | Page 25 of 33
07882-101
VPOS
IF1P
1 GND
ADL5802
Data Sheet
RF1
frequency. A variety of suitable choke inductors is
commercially available from manufacturers such as Coilcraft
and Murata. An impedance transforming network may be
required to transform the final load impedance to 200 Ω at the
IF outputs.
RF2
T5
C13
T3
C14
23
C5
22
21
C12
20
19
07882-102
RF1+ RF1– GND RF2+ RF2–
ADL5802
1 GND
Figure 69. ADL5802 RF Interface
VPOS
2 GND
IF1P
ADL5802
3 OP1+
C16
7
8
9
C2
ADL5802
T4
ENBL GND LOIP LOIN GND
4 OP1–
11
10
5 GND
C3
T1
GND 18
07882-103
GND 17
Figure 70. ADL5802 LO Interface
OP2+ 16
Table 4. Suggested Components for the RF and LO Interfaces
1900 MHz
2500 MHz
3500 MHz
5500 MHz
T1, T3, T5
Mini-Circuits® TC1-113M+
Mini-Circuits TC1-1-13M+
Johanson Technology
2500BL14M050
Johanson Technology
3600BL14M050
Johanson Technology
5400BL15B050
C15
ADL5802
C2, C3, C5,
C12, C13, C14
100 pF
T2
OP2– 15
IF2P
GND 14
07882-104
RF and LO
Frequency
900 MHz
VPOS
100 pF
3 pF
Figure 71. Biasing the IF Port Open-Collector Outputs
Using a Center-Tapped Impedance Transformer
1.5 pF
VPOS
3 pF
C17
L3
IF PORT
1 GND
2 GND
IF1 OUT+
The IF port features an open-collector differential output
interface. It is necessary to bias the open collector outputs using
one of the schemes presented in Figure 71 and Figure 72.
ZL
ZLOAD = 200Ω
ADL5802
4 OP1–
IF1 OUT–
L4
Figure 71 shows the use of center-tapped impedance
transformers. The turns ratio of the transformer should be
selected to provide the desired impedance transformation. In
the case of a 50 Ω load impedance, a 4:1 impedance ratio
transformer should be used to transform the 50 Ω load into a
200 Ω differential load at the IF output pins.
Figure 72 shows a differential IF interface where pull-up choke
inductors are used to bias the open-collector outputs. The
shunting impedance of the choke inductors used to couple dc
current into the mixer core should be large enough at the IF
frequency of operation so as not to load down the output
current before it reaches the intended load. Additionally, the dc
current handling capability of the selected choke inductors
must be at least 45 mA. The self-resonant frequency of the
selected choke inductors must be higher than the intended IF
3 OP1+
IMPEDANCE
TRANSFORMING
NETWORK
5 GND
C18
VPOS
VPOS
GND 18
GND 17
C4
L2
IF2 OUT+
OP2+ 16
ADL5802
Rev. C | Page 26 of 33
ZLOAD = 200Ω
OP2– 15
GND 14
L1
C1
IMPEDANCE
TRANSFORMING
NETWORK
ZL
IF2 OUT–
VPOS
Figure 72. Biasing the IF Port Open-Collector Outputs
Using Pull-Up Choke Inductors
07882-105
LO
Data Sheet
ADL5802
PERFORMANCE UP TO 8 GHz
This section provides the typical performance of the ADL5802 from 6 GHz to 8 GHz. The output trace and connector loss are not
deembedded for these measurements.
VS = 5 V, TA = 25°C, IF = 200 MHz, as measured using a typical circuit schematic with a low-side local oscillator (LO), unless otherwise
noted. LO and RF ports use TCM1-83X+, IF ports use TC1-1-13M+. Insertion loss of input and output balun, and traces loss are not
extracted from the gain measurement.
Note that this performance is typical and is not guaranteed.
Table 5.
Parameter
DYNAMIC PERFORMANCE AT fRF BETWEEN 6 GHz AND 8 GHz
Power Conversion Gain
SSB Noise Figure
Input Third-Order Intercept
Test Conditions
VSET = 2.5 V
Min
Typ
−6
19
15
Rev. C | Page 27 of 33
Max
Unit
dB
dB
dBm
ADL5802
Data Sheet
EVALUATION BOARD
An evaluation board is available for the ADL5802. The standard evaluation board is fabricated using Rogers® RO3003 material. Each of the RF,
LO, and IF ports is configured for single-ended signaling via a balun transformer. The schematic for the evaluation board is shown in Figure 73.
Table 6 describes the various configuration options for the evaluation board. Layout for the board is shown in Figure 74 and Figure 75.
RF1
RF2
T5
C11
C8
VPOS
L3
C12
24
23
22
20
21
19
VPOS
1
GND
GND 18
2
GND
GND 17
R16
3
C16
OP1+
C4
L2
OP2+ 16
4
OP1–
T2
OP2– 15
IF2P
R13
C18
R10
6
C6
C9
GND 14
GND
VPOS 13
VPOS
7
VPOS
8
9
R4
10
11
R20
VPOS
C10
C7
ENBL GND LOIP LOIN GND VSET
R9
C1
R12
12
R5
VSET
R11
C2
ENBL1
C3
R23
T1
R1
VPOS
LON
LO
LOP
R22
07882-100
5
L1
07882-001
L4
R21
VPOS
IF2N
C15
R6
R15
R3
R2
R14
ADL5802
R7
IF1N
C5
GND
VPOS RF1+ RF1– GND RF2+ RF2–
C17
T4
C14
VPOS
VPOS1
R19
VPOS
IF1P
C13
T3
Figure 73. Evaluation Board Schematic
Table 6. Evaluation Board Configuration
Components
C1, C4, C6, C7, C8, C9,
C10, C11, C17, C18,
R10, R12, R19, R20,
R21
C5, C12, C13, C14, T3,
T5, RF1, RF2
C15, C16, L1, L2, L3,
L4, R2, R3, R6, R7,
R13, R14, R15, R16,
R20, R21, T2, T4, IF1,
IF2
C2, C3, R4, R5, T1, LO
R1, R9, R11, ENBL1
Function
Power supply decoupling. Nominal supply decoupling
consists of a 0.01 µF capacitor to ground in parallel with 10
pF capacitors to ground, positioned as close to the device
as possible. Series resistors are provided for enhanced
supply decoupling using optional ferrite chip inductors.
RF Channel 1 and RF Channel 2 input interfaces. Input
channels are ac-coupled through C5, C12, C13, and C14. T3
and T4 are 1:1 baluns used to interface to the 50 Ω
differential inputs.
IF Channel 1 and IF Channel 2 output interfaces. The 200 Ω
open-collector IF output interfaces are biased through the
center taps of T2 and T4 4:1 impedance transformers. C15
and C16 provide local bypassing with R20 and R21
available for additional supply bypassing. R6, R7, R13, R14,
R15, and R16 are provided for IF filtering and matching
options.
LO interface. C2 and C3 provide ac coupling for the local
oscillator input. T1 is a 1:1 balun to allow single-ended
interfacing to the differential 50 Ω local oscillator input.
Enable interface. The ADL5802 can be disabled using the 3pin ENBL1 header. The ENBL pin is pulled up to VPOS
through R9. R1 is provided as an optional termination for
the high impedance enable interface. If desired, the ENBL
pin can be driven by an external source through the ENBL
SMA connector.
Rev. C | Page 28 of 33
Default Conditions
C6, C7, C8 = 10 pF (size 0402)
C9, C10, C11 = 0.01 µF (size 0402)
C1, C4, C17, C18 = open (size 0402)
R10, R12, R19, R20, R21 = 0 Ω (size 0402)
C5, C12, C13, C14 = 100 pF (size 0402)
T3, T5 = TC1-1-13M+ (Mini-Circuits)
C15, C16 = 100 pF (size 0402)
L1, L2, L3, L4 = open (size 0805)
R2, R3, R13, R14, R15, R16, R20, R21 = 0 Ω (size 0402)
R6, R7 = open (size 0402)
T2, T4 = TC4-1W+ (Mini-Circuits)
C2, C3 = 1 nF (size 0402)
R4, R5 = open (size 0402)
T1 = TC1-1-13M+ (Mini-Circuits)
R9 = 10 kΩ (size 0402); R1, R11 = open (size 0402)
Or R1 = 10 kΩ (size 0402);R9, R11 = open (size 0402)
Or R11 = 10 kΩ (size 0402); R1, R9 = open (size 0402)
ENBL1 = 3-pin header and shunt
Data Sheet
Default Conditions
R22, R23 = open (size 0402)
07882-107
EPAD (EP)
Function
VSET bias control. R22 and R23 form an optional resistor
divider network between VPOS and GND, allowing for a
fixed bias setting. See the Typical Performance
Characteristics section to choose the recommended VSET
control voltage for the desired frequency band.
Exposed paddle. Must be soldered to ground.
07882-106
Components
R22, R23, VSET
ADL5802
Figure 74. Evaluation Board Top Layer
Figure 75. Evaluation Board Bottom Layer
Rev. C | Page 29 of 33
ADL5802
Data Sheet
OUTLINE DIMENSIONS
DETAIL A
(JEDEC 95)
0.30
0.25
0.18
0.50
BSC
P IN 1
IN D IC ATO R AR E A OP T IO N S
(SEE DETAIL A)
24
19
18
1
2.65
2.50 SQ
2.45
EXPOSED
PAD
13
TOP VIEW
0.80
0.75
0.70
PKG-004462
SEATING
PLANE
SIDE VIEW
0.50
0.40
0.30
6
7
12
BOTTOM VIEW
0.20 MIN
3.16 MIN
0.05 MAX
0.02 NOM
COPLANARITY
0.08
FOR PROPER CONNECTION OF
THE EXPOSED PAD, REFER TO
THE PIN CONFIGURATION AND
FUNCTION DESCRIPTIONS
SECTION OF THIS DATA SHEET.
09-05-2018-A
PIN 1
INDICATOR
AREA
4.10
4.00 SQ
3.90
0.20 REF
COMPLIANT TO JEDEC STANDARDS MO-220-WGGD
Figure 76. 24-Lead Lead Frame Chip Scale Package [LFCSP]
4 mm × 4 mm Body and 0.75 mm Package Height
(CP-24-7)
Dimensions shown in millimeters
ORDERING GUIDE
Model 1
ADL5802ACPZ-R7
ADL5802-EVALZ
1
Temperature
Range
−40°C to +85°C
Package Description
24-Lead Lead Frame Chip Scale Package [LFCSP]
Evaluation Board
Z = RoHS Compliant Part.
Rev. C | Page 30 of 33
Package
Option
CP-24-7
Ordering
Quantity
1,500 per Reel
1
Data Sheet
ADL5802
NOTES
Rev. C | Page 31 of 33
ADL5802
Data Sheet
NOTES
Rev. C | Page 32 of 33
Data Sheet
ADL5802
NOTES
©2009–2020 Analog Devices, Inc. All rights reserved. Trademarks and
registered trademarks are the property of their respective owners.
D07882-10/20(C)
Rev. C | Page 33 of 33
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