FEATURES
FUNCTIONAL BLOCK DIAGRAM
Rev. D
DP
DN
REFIN REFOUT REFGND SDA SCL A1
A0
ADM1062
TEMP
SENSOR
VREF
INTERNAL
DIODE
MUX
Complete supervisory and sequencing solution for up to
10 supplies
10 supply fault detectors enable supervision of supplies to
DPLIMx
In addition, the DAC output buffer is three-stated if DNLIMx >
DPLIMx. By programming the limit registers this way, the user
can make it very difficult for the DAC output buffers to be turned
on during normal system operation. The limit registers are among
the registers downloaded from the EEPROM at startup.
Rev. D | Page 24 of 35
Data Sheet
ADM1062
TEMPERATURE MEASUREMENT SYSTEM
The ADM1062 contains an on-chip, band gap temperature
sensor whose output is digitized by the on-chip, 12-bit ADC.
Theoretically, the temperature sensor and the ADC can measure
temperatures from −128°C to +128°C with a resolution of 0.125°C.
Because this exceeds the operating temperature range of the device,
local temperature measurements outside this range are not possible.
Temperature measurements from −128°C to +128°C are possible
using a remote sensor. The output code is in offset binary format,
with −128°C given by Code 0x400, 0°C given by Code 0x800,
and +128°C given by Code 0xC00.
Figure 36 shows the input signal conditioning used to measure the
output of a remote temperature sensor. This figure shows the
external sensor as a substrate transistor provided for temperature
monitoring on some microprocessors, but it could equally be
a discrete transistor such as a 2N3904 or 2N3906.
If a discrete transistor is used, the collector is not grounded and
should be linked to the base. If a PNP transistor is used, the base
is connected to the DN input, and the emitter is connected to
the DP input. If an NPN transistor is used, the emitter is connected
to the DN input, and the base is connected to the DP input.
Figure 34 and Figure 35 show how to connect the ADM1062 to
an NPN or PNP transistor for temperature measurement. To
prevent ground noise from interfering with the measurement,
the more negative terminal of the sensor is not referenced to
ground but is biased above ground by an internal diode at the
DN input.
As with the other analog inputs to the ADC, a limit register is
provided for each of the temperature input channels. Therefore,
a temperature limit can be set such that if it is exceeded, a warning
is generated and available as an input to the sequencing engine.
This enables users to control their sequence or monitor functions
based on an overtemperature or undertemperature event.
REMOTE TEMPERATURE MEASUREMENT
ADM1062
2N3904
NPN
DP
04433-070
The ADM1062 can measure the temperature of a remote diode
sensor or diode-connected transistor connected to Pin DN and
Pin DP (Pin 37 and Pin 38 on the LFCSP package and Pin 44
and Pin 45 on the TQFP package).
DN
Figure 34. Measuring Temperature Using an NPN Transistor
The forward voltage of a diode or diode-connected transistor
operated at a constant current exhibits a negative temperature
coefficient of about −2 mV/°C. Unfortunately, the absolute value
of VBE varies from device to device, and individual calibration
is required to null it, making the technique unsuitable for mass
production. The technique used in the ADM1062 is to measure
the change in VBE when the device is operated at two different
currents.
ADM1062
DP
DN
04433-071
2N3906
PNP
Figure 35. Measuring Temperature Using a PNP Transistor
The change in VBE is given by
ΔVBE = kT/q × ln(N)
where:
k is Boltzmann’s constant.
q is the charge on the carrier.
T is the absolute temperature in Kelvin.
N is the ratio of the two currents.
VDD
REMOTE
SENSING
TRANSISTOR
I
THERM DA
DP
THERM DC
DN
N×I
IBIAS
VOUT+
TO ADC
BIAS
DIODE
LOW-PASS FILTER
fC = 65kHz
Figure 36. Signal Conditioning for Remote Diode Temperature Sensors
Rev. D | Page 25 of 35
VOUT–
04433-069
CPU
ADM1062
Data Sheet
To measure ΔVBE, the sensor is switched between operating
currents of I and N × I. The resulting waveform is passed through
a 65 kHz low-pass filter to remove noise and through a chopperstabilized amplifier that amplifies and rectifies the waveform
to produce a dc voltage proportional to ΔVBE. This voltage is
measured by the ADC to produce a temperature output in 12-bit
offset binary. To further reduce the effects of noise, digital filtering
is performed by averaging the results of 16 measurement cycles.
A remote temperature measurement takes nominally 600 ms.
The results of remote temperature measurements are stored in
12-bit, offset binary format, as shown in Table 11. This format
provides temperature readings with a resolution of 0.125°C.
Table 11. Temperature Data Format
Temperature
−128°C
−125°C
−100°C
−75°C
−50°C
−25°C
−10°C
0°C
+10.25°C
+25.5°C
+50.75°C
+75°C
+100°C
+125°C
+128°C
Rev. D | Page 26 of 35
Digital Output (Hex)
0x400
0x418
0x4E0
0x5A8
0x670
0x738
0x7B0
0x800
0x852
0x8CC
0x996
0xA58
0XB20
0xBE8
0xC00
Digital Output (Binary)
010000000000
010000011000
010011100000
010110101000
011001110000
011100111000
011110110000
100000000000
100001010010
100011001100
100110010110
101001011000
101100100000
101111101000
110000000000
Data Sheet
ADM1062
APPLICATIONS DIAGRAM
12V IN
12V OUT
5V IN
5V OUT
3V IN
3V OUT
IN
DC-TO-DC1
VH
5V OUT
3V OUT
3.3V OUT
2.5V OUT
1.8V OUT
1.2V OUT
0.9V OUT
POWRON
EN
OUT
3.3V OUT
ADM1062
VP1
VP2
VP3
VP4
VX1
VX2
VX3
PDO1
PDO2
VX4
PDO6
IN
DC-TO-DC2
PDO3
PDO4
PDO5
RESET
PDO7
VX5
PDO8
EN
2.5V OUT
PWRGD
SIGNAL VALID
IN
SYSTEM RESET
DC-TO-DC3
EN
PDO9
PDO10
REFOUT
OUT
OUT
1.8V OUT
3.3V OUT
DAC1*
DP
IN
DN
REFIN VCCP VDDCAP GND
LDO
EN
OUT
0.9V OUT
3.3V OUT
10µF
10µF
10µF
IN
*ONLY ONE MARGINING CIRCUIT
SHOWN FOR CLARITY. DAC1 TO DAC6
ALLOW MARGINING FOR UP TO SIX
VOLTAGE RAILS.
EN
OUT
1.2V OUT
TRIM
DC-TO-DC4
TEMPERATURE
DIODE
2.5V OUT
MICROPROCESSOR
04433-068
3.3V OUT
Figure 37. Applications Diagram
Rev. D | Page 27 of 35
ADM1062
Data Sheet
COMMUNICATING WITH THE ADM1062
CONFIGURATION DOWNLOAD AT POWER-UP
The configuration of the ADM1062 (undervoltage/overvoltage
thresholds, glitch filter timeouts, PDO configurations, and so on)
is dictated by the contents of the RAM. The RAM comprises
digital latches that are local to each of the functions on the device.
The latches are double-buffered and have two identical latches,
Latch A and Latch B. Therefore, when an update to a function
occurs, the contents of Latch A are updated first, and then the
contents of Latch B are updated with identical data. The advantages
of this architecture are explained in detail in the Updating the
Configuration section.
The two latches are volatile memory and lose their contents at
power-down. Therefore, the configuration in the RAM must be
restored at power-up by downloading the contents of the EEPROM
(nonvolatile memory) to the local latches. This download occurs
in six steps, as follows:
1.
2.
3.
4.
5.
6.
With no power applied to the device, the PDOs are all
high impedance.
When 1.2 V appears on any of the inputs connected to the
VDD arbitrator (VH or VPx), the PDOs are all weakly
pulled to GND with a 20 kΩ resistor.
When the supply rises above the undervoltage lockout of
the device (UVLO is 2.5 V), the EEPROM starts to
download to the RAM.
The EEPROM downloads its contents to all Latch As.
When the contents of the EEPROM are completely downloaded to the Latch As, the device controller signals all
Latch As to download to all Latch Bs simultaneously,
completing the configuration download.
At 0.5 ms after the configuration download completes, the first
state definition is downloaded from the EEPROM into the SE.
Note that any attempt to communicate with the device prior to
the completion of the download causes the ADM1062 to issue
a no acknowledge (NACK).
UPDATING THE CONFIGURATION
After power-up, with all the configuration settings loaded from
the EEPROM into the RAM registers, the user may need to alter
the configuration of functions on the ADM1062, such as changing
the undervoltage or overvoltage limit of an SFD, changing the
fault output of an SFD, or adjusting the rise time delay of one of
the PDOs.
The ADM1062 provides several options that allow the user to
update the configuration over the SMBus interface. The following
three options are controlled in the UPDCFG register:
Option 1
Update the configuration in real time. The user writes to the RAM
across the SMBus, and the configuration is updated immediately.
Option 2
Update the Latch As without updating the Latch Bs. With this
method, the configuration of the ADM1062 remains unchanged
and continues to operate in the original setup until the instruction
is given to update the Latch Bs.
Option 3
Change the EEPROM register contents without changing the
RAM contents, and then download the revised EEPROM contents
to the RAM registers. With this method, the configuration of
the ADM1062 remains unchanged and continues to operate in
the original setup until the instruction is given to update the RAM.
The instruction to download from the EEPROM in Option 3 is
also a useful way to restore the original EEPROM contents if
revisions to the configuration are unsatisfactory. For example,
if the user needs to alter an overvoltage threshold, the RAM
register can be updated, as described in Option 1. However,
if the user is not satisfied with the change and wants to revert to
the original programmed value, the device controller can issue
a command to download the EEPROM contents to the RAM
again, as described in Option 3, restoring the ADM1062 to its
original configuration.
The topology of the ADM1062 makes this type of operation
possible. The local, volatile registers (RAM) are all doublebuffered latches. Setting Bit 0 of the UPDCFG register to 1 leaves
the double-buffered latches open at all times. If Bit 0 is set to 0
when a RAM write occurs across the SMBus, only the first side
of the double-buffered latch is written to. The user must then write
a 1 to Bit 1 of the UPDCFG register. This generates a pulse to
update all the second latches at once. EEPROM writes occur in
a similar way.
The final bit in this register can enable or disable EEPROM
page erasure. If this bit is set high, the contents of an EEPROM
page can all be set to 1. If this bit is set low, the contents of a
page cannot be erased, even if the command code for page
erasure is programmed across the SMBus. The bit map for the
UPDCFG register is shown in the AN-698 Application Note. A
flow diagram for download at power-up and subsequent
configuration updates is shown in Figure 38.
Rev. D | Page 28 of 35
Data Sheet
ADM1062
SMBus
E
E
P
R
O
M
L
D
DEVICE
CONTROLLER
R
A
M
L
D
D
A
T
A
U
P
D
LATCH A
LATCH B
EEPROM
FUNCTION
(OV THRESHOLD
ON VP1)
04433-035
POWER-UP
(VCC > 2.5V)
Figure 38. Configuration Update Flow Diagram
UPDATING THE SEQUENCING ENGINE
Sequencing engine (SE) functions are not updated in the same way
as regular configuration latches. The SE has its own dedicated
512-byte nonvolatile, electrically erasable, programmable, readonly memory (EEPROM) for storing state definitions. The
EEPROM provides 63 individual states, each with a 64-bit word
(one state is reserved). At power-up, the first state is loaded from
the SE EEPROM into the engine itself. When the conditions of this
state are met, the next state is loaded from the EEPROM into the
engine, and so on. The loading of each new state takes approximately 10 μs.
To alter a state, the required changes must be made directly to
the EEPROM. RAM for each state does not exist. The relevant
alterations must be made to the 64-bit word, which is then
uploaded directly to the EEPROM.
The major differences between the EEPROM and other
registers are as follows:
An EEPROM location must be blank before it can be
written to. If it contains data, the data must first be erased.
Writing to the EEPROM is slower than writing to the RAM.
Writing to the EEPROM should be restricted because it has
a limited write/cycle life of typically 10,000 write operations
due to the usual EEPROM wear-out mechanisms.
The first EEPROM is split into 16 (0 to 15) pages of 32 bytes
each. Page 0 to Page 6, starting at Address 0xF800, hold the
configuration data for the applications on the ADM1062 (such
as the SFDs and PDOs). These EEPROM addresses are the same
as the RAM register addresses, prefixed by F8. Page 7 is reserved.
Page 8 to Page 15 are for customer use.
INTERNAL REGISTERS
Data can be downloaded from the EEPROM to the RAM in one
of the following ways:
The ADM1062 contains a large number of data registers. The
principal registers are the address pointer register and the
configuration registers.
Address Pointer Register
The address pointer register contains the address that selects
one of the other internal registers. When writing to the ADM1062,
the first byte of data is always a register address that is written to
the address pointer register.
Configuration Registers
The configuration registers provide control and configuration
for various operating parameters of the ADM1062.
EEPROM
The ADM1062 has two 512-byte cells of nonvolatile EEPROM
from Register Address 0xF800 to Register Address 0xFBFF. The
EEPROM is used for permanent storage of data that is not lost
when the ADM1062 is powered down. One EEPROM cell contains
the configuration data of the device; the other contains the state
definitions for the SE. Although referred to as read-only memory,
the EEPROM can be written to, as well as read from, using the
serial bus in exactly the same way as the other registers.
At power-up, when Page 0 to Page 6 are downloaded
By setting Bit 0 of the UDOWNLD register (0xD8), which
performs a user download of Page 0 to Page 6
SERIAL BUS INTERFACE
The ADM1062 is controlled via the serial system management
bus (SMBus) and is connected to this bus as a slave device under
the control of a master device. It takes approximately 1 ms after
power-up for the ADM1062 to download from its EEPROM.
Therefore, access to the ADM1062 is restricted until the download
is complete.
Identifying the ADM1062 on the SMBus
The ADM1062 has a 7-bit serial bus slave address (see Table 12).
The device is powered up with a default serial bus address. The
five MSBs of the address are set to 00101; the two LSBs are
determined by the logical states of Pin A1 and Pin A0. This
allows the connection of four ADM1062 devices to one SMBus.
Table 12. Serial Bus Slave Address
A1 Pin
Low
Low
High
High
1
A0 Pin
Low
High
Low
High
Hex Address
0x28
0x2A
0x2C
0x2E
7-Bit Address1
0010100x
0010101x
0010110x
0010111x
x = Read/Write bit. The address is shown only as the first 7 MSBs.
Rev. D | Page 29 of 35
ADM1062
Data Sheet
The device also has several identification registers (read-only)
that can be read across the SMBus. Table 13 lists these registers
with their values and functions.
Table 13. Identification Register Values and Functions
Name
MANID
REVID
MARK1
MARK2
Address
0xF4
0xF5
0xF6
0xF7
Value
0x41
0x02
0x00
0x00
Function
Manufacturer ID for Analog Devices
Silicon revision
Software brand
Software brand
General SMBus Timing
Figure 39, Figure 40, and Figure 41 are timing diagrams for
general read and write operations using the SMBus. The SMBus
specification defines specific conditions for different types of
read and write operations, which are discussed in the Write
Operations and Read Operations sections.
The general SMBus protocol operates as follows:
Step 1
It may be an instruction telling the slave device to expect a block
write, or it may be a register address that tells the slave where subsequent data is to be written. Because data can flow in only one
direction, as defined by the R/W bit, sending a command to a
slave device during a read operation is not possible. Before a read
operation, it may be necessary to perform a write operation to
tell the slave what sort of read operation to expect and/or the
address from which data is to be read.
Step 3
When all data bytes have been read or written, stop conditions
are established. In write mode, the master pulls the data line
high during the 10th clock pulse to assert a stop condition. In
read mode, the master device releases the SDA line during the
low period before the ninth clock pulse, but the slave device
does not pull it low. This is known as a no acknowledge. The
master then takes the data line low during the low period before
the 10th clock pulse and then high during the 10th clock pulse
to assert a stop condition.
SCL Held Low Timeout
The master initiates data transfer by establishing a start condition,
defined as a high-to-low transition on the serial data (SDA) line,
while the serial clock-line (SCL) remains high. This indicates that a
data stream follows. All slave peripherals connected to the serial
bus respond to the start condition and shift in the next eight bits,
consisting of a 7-bit slave address (MSB first) plus an R/W bit.
This bit determines the direction of the data transfer, that is,
whether data is written to or read from the slave device (0 = write,
1 = read).
The peripheral whose address corresponds to the transmitted
address responds by pulling the data line low during the low
period before the ninth clock pulse, known as the acknowledge
bit, and by holding it low during the high period of this clock pulse.
All other devices on the bus remain idle while the selected device
waits for data to be read from or written to it. If the R/W bit is a 0,
the master writes to the slave device. If the R/W bit is a 1, the
master reads from the slave device.
Step 2
Data is sent over the serial bus in sequences of nine clock pulses:
eight bits of data followed by an acknowledge bit from the slave
device. Data transitions on the data line must occur during the
low period of the clock signal and remain stable during the high
period because a low-to-high transition when the clock is high
could be interpreted as a stop signal. If the operation is a write
operation, the first data byte after the slave address is a command
byte. This command byte tells the slave device what to expect next.
If the bus master holds the SCL low for a time that is a multiple
of approximately 30 ms, the ADM1062 bus interface may timeout.
If this timeout happens, the in progress transaction is NACKed,
and the transaction must be repeated. This behavior is only seen
if the I2C bus master is interrupted midtransaction by a higher
priority task that delays completion of the transaction.
False Start Detection
The data hold time specification defines the time that data must
be valid on the SDA line, following an SCL falling edge. If there
are multiple ADM1062 devices on the same bus, one of the
ADM1062 devices may see the SCL/SDA transition due to an
acknowledge (ACK) from a different device as a start condition
because of internal timing skew, which for most transactions,
this is not an issue. In a case where the data appearing on the
bus after the false start is detected happens to match the address
of another ADM1062 on the bus, that device may incorrectly ACK.
A bus master may see this ACK as another bus master talking
on the bus, halt the bus transaction, and not produce any more
clocks on the SCL. As a result, the ADM1062 device that
incorrectly ACKed continues to hold down the SDA line low.
To retry the halted bus transaction, the bus master performs a
clock flush on the SCL by sending a series of up to 16 clock pulses.
The clock flush forces the ADM1062 to release the SDA line.
Rev. D | Page 30 of 35
Data Sheet
ADM1062
1
9
1
9
SCL
0
1
0
1
A1
A0
D7
R/W
D6
D5
D4
D3
D2
D1
ACK. BY
SLAVE
START BY
MASTER
FRAME 1
SLAVE ADDRESS
FRAME 2
COMMAND CODE
1
SCL
(CONTINUED)
SDA
(CONTINUED)
9
D7
D6
D5
D4
D3
D0
ACK. BY
SLAVE
D2
D1
1
D7
D0
9
D6
D5
ACK. BY
SLAVE
FRAME 3
DATA BYTE
D4
D3
D2
D1
D0
ACK. BY
SLAVE
FRAME N
DATA BYTE
STOP
BY
MASTER
04433-036
0
SDA
Figure 39. General SMBus Write Timing Diagram
1
9
1
9
SCL
0
1
0
1
A1
A0 R/W
D7
D6
D5
D4
D3
D2
D1
ACK. BY
SLAVE
START BY
MASTER
1
SCL
(CONTINUED)
SDA
(CONTINUED)
D7
FRAME 1
SLAVE ADDRESS
D6
D5
D4
D3
9
D2
FRAME 3
DATA BYTE
D1
D0
ACK. BY
MASTER
D0
1
D7
FRAME 2
DATA BYTE
D6
D5
ACK. BY
MASTER
D4
9
D3
D2
FRAME N
DATA BYTE
D1
D0
NO ACK.
STOP
BY
MASTER
Figure 40. General SMBus Read Timing Diagram
tR
tF
t HD; STA
t LO W
SCL
t HI G H
t HD; STA
t HD; DAT
t SU; STA
t SU; STO
t SU; DAT
t BUF
P
S
S
Figure 41. Serial Bus Timing Diagram
Rev. D | Page 31 of 35
P
04433-038
SDA
04433-037
0
SDA
ADM1062
Data Sheet
SMBus PROTOCOLS FOR RAM AND EEPROM
In the ADM1062, the send byte protocol is used for two purposes:
The ADM1062 contains volatile registers (RAM) and nonvolatile registers (EEPROM). User RAM occupies Address 0x00
to Address 0xDF; the EEPROM occupies Address 0xF800 to
Address 0xFBFF.
S
WRITE OPERATIONS
The SMBus specification defines several protocols for different
types of read and write operations. The following abbreviations
are used in Figure 42 to Figure 50:
S = Start
P = Stop
R = Read
W = Write
A = Acknowledge
A = No acknowledge
Send Byte
In a send byte operation, the master device sends a single
command byte to a slave device, as follows:
3.
4.
5.
6.
W
4
5
6
A
RAM
ADDRESS
(0x00 TO 0xDF)
A
P
To erase a page of EEPROM memory. EEPROM memory
can be written to only if it is unprogrammed. Before writing
to one or more EEPROM memory locations that are already
programmed, the page(s) containing those locations must
first be erased. EEPROM memory is erased by writing a
command byte.
The master sends a command code telling the slave device
to erase the page. The ADM1062 command code for a page
erasure is 0xFE (1111 1110). Note that for a page erasure to
take place, the page address must be given in the previous
write word transaction (see the Write Byte/Word section).
In addition, Bit 2 in the UPDCFG register (Address 0x90)
must be set to 1.
1
2
S
SLAVE
ADDRESS
W
3
4
5
6
A
COMMAND
BYTE
(0xFE)
A
P
Figure 43. EEPROM Page Erasure
The ADM1062 uses the following SMBus write protocols.
1.
2.
SLAVE
ADDRESS
3
Figure 42. Setting a RAM Address for Subsequent Read
Page erasure is enabled by setting Bit 2 in the UPDCFG register
(Address 0x90) to 1. If this bit is not set, page erasure cannot
occur, even if the command byte (0xFE) is programmed across
the SMBus.
2
04433-039
1
04433-040
Data can be written to and read from both the RAM and the
EEPROM as single data bytes. Data can be written only to unprogrammed EEPROM locations. To write new data to a programmed
location, the location contents must first be erased. EEPROM
erasure cannot be done at the byte level. The EEPROM is arranged
as 32 pages of 32 bytes each, and an entire page must be erased.
To write a register address to the RAM for a subsequent single
byte read from the same address, or for a block read or a
block write starting at that address, as shown in Figure 42.
The master device asserts a start condition on SDA.
The master sends the 7-bit slave address followed by the
write bit (low).
The addressed slave device asserts an acknowledge (ACK)
on SDA.
The master sends a command code.
The slave asserts an ACK on SDA.
The master asserts a stop condition on SDA, and the
transaction ends.
Rev. D | Page 32 of 35
As soon as the ADM1062 receives the command byte,
page erasure begins. The master device can send a stop
command as soon as it sends the command byte. Page
erasure takes approximately 20 ms. If the ADM1062 is
accessed before erasure is complete, it responds with a no
acknowledge (NACK).
Data Sheet
ADM1062
Write Byte/Word
Block Write
In a write byte/word operation, the master device sends a
command byte and one or two data bytes to the slave device,
as follows:
In a block write operation, the master device writes a block of
data to a slave device. The start address for a block write must
have been set previously. In the ADM1062, a send byte operation sets a RAM address, and a write byte/word operation sets
an EEPROM address, as follows:
In the ADM1062, the write byte/word protocol is used for three
purposes:
To write a single byte of data to the RAM. In this case, the
command byte is RAM Address 0x00 to RAM Address 0xDF,
and the only data byte is the actual data, as shown in Figure 44.
1
2
3
4
5
6
7 8
The master device asserts a start condition on SDA.
The master sends the 7-bit slave address followed by
the write bit (low).
3. The addressed slave device asserts an ACK on SDA.
4. The master sends a command code that tells the slave
device to expect a block write. The ADM1062 command
code for a block write is 0xFC (1111 1100).
5. The slave asserts an ACK on SDA.
6. The master sends a data byte that tells the slave device how
many data bytes are being sent. The SMBus specification
allows a maximum of 32 data bytes in a block write.
7. The slave asserts an ACK on SDA.
8. The master sends N data bytes.
9. The slave asserts an ACK on SDA after each data byte.
10. The master asserts a stop condition on SDA to end the
transaction.
1.
2.
1
04433-041
RAM
SLAVE W A
S ADDRESS
ADDRESS
A DATA A P
(0x00 TO 0xDF)
Figure 44. Single Byte Write to the RAM
1
2
3
4
5
6
Because a page consists of 32 bytes, only the three MSBs
of the address low byte are important for page erasure. The
lower five bits of the EEPROM address low byte specify the
addresses within a page and are ignored during an erase
operation.
To write a single byte of data to the EEPROM. In this case,
the command byte is the high byte of EEPROM Address 0xF8
to EEPROM Address 0xFB. The first data byte is the low
byte of the EEPROM address, and the second data byte is
the actual data, as shown in Figure 46.
3
4
5
6
7
5
6
7
8
9
10
8
9 10
EEPROM
EEPROM
SLAVE
ADDRESS
ADDRESS
S ADDRESS W A
A
A DATA A P
HIGH BYTE
LOW BYTE
(0xF8 TO 0xFB)
(0x00 TO 0xFF)
There must be at least N locations from the start address to
the highest EEPROM address (0xFBFF) to avoid writing to
invalid addresses.
An address crosses a page boundary. In this case, both
pages must be erased before programming.
Note that the ADM1062 features a clock extend function for
writes to EEPROM. Programming an EEPROM byte takes
approximately 250 μs, which limits the SMBus clock for repeated
or block write operations. The ADM1062 pulls SCL low and
extends the clock pulse when it cannot accept any more data.
04433-043
2
Figure 45. Setting an EEPROM Address
1
4
Unlike some EEPROM devices that limit block writes to within
a page boundary, there is no limitation on the start address
when performing a block write to EEPROM, except when
7 8
EEPROM
EEPROM
SLAVE
ADDRESS
ADDRESS
S ADDRESS W A
A
A P
HIGH BYTE
LOW BYTE
(0xF8 TO 0xFB)
(0x00 TO 0xFF)
3
Figure 47. Block Write to the EEPROM or RAM
To set up a 2-byte EEPROM address for a subsequent read,
write, block read, block write, or page erase. In this case, the
command byte is the high byte of EEPROM Address 0xF8
to EEPROM Address 0xFB. The only data byte is the low
byte of the EEPROM address, as shown in Figure 45.
04433-042
2
S SLAVE
W A COMMAND 0xFC A BYTE A DATA A DATA A DATA A P
ADDRESS
(BLOCK WRITE)
COUNT
1
2
N
04433-044
The master device asserts a start condition on SDA.
The master sends the 7-bit slave address followed by the
write bit (low).
3. The addressed slave device asserts an ACK on SDA.
4. The master sends a command code.
5. The slave asserts an ACK on SDA.
6. The master sends a data byte.
7. The slave asserts an ACK on SDA.
8. The master sends a data byte or asserts a stop condition.
9. The slave asserts an ACK on SDA.
10. The master asserts a stop condition on SDA to end
the transaction.
1.
2.
Figure 46. Single Byte Write to the EEPROM
Rev. D | Page 33 of 35
ADM1062
Data Sheet
10.
11.
12.
13.
The ADM1062 uses the following SMBus read protocols.
Receive Byte
In a receive byte operation, the master device receives a single
byte from a slave device, as follows:
3.
4.
5.
6.
The master device asserts a start condition on SDA.
The master sends the 7-bit slave address followed by the
read bit (high).
The addressed slave device asserts an ACK on SDA.
The master receives a data byte.
The master asserts a NACK on SDA.
The master asserts a stop condition on SDA, and the
transaction ends.
S
R
3
4
5
6
A
DATA
A
P
04433-045
2
SLAVE
ADDRESS
Figure 48. Single Byte Read from the EEPROM or RAM Block Read
In a block read operation, the master device reads a block of
data from a slave device. The start address for a block read must
have been set previously. In the ADM1062, this is done by a
send byte operation to set a RAM address, or a write byte/word
operation to set an EEPROM address. The block read operation
itself consists of a send byte operation that sends a block read
command to the slave, immediately followed by a repeated start
and a read operation that reads out multiple data bytes, as follows:
1.
2.
3.
4.
5.
6.
7.
8.
9.
3
4
5 6
7
8
9
10
11
12
SLAVE
COMMAND 0xFD
SLAVE
BYTE
DATA
R A
A
A
W A
A S
ADDRESS
(BLOCK READ)
ADDRESS
COUNT
1
13
DATA
A
32
P
Figure 49. Block Read from the EEPROM or RAM
Error Correction
The ADM1062 provides the option of issuing a packet error
correction (PEC) byte after a write to the RAM, a write to the
EEPROM, a block write to the RAM/EEPROM, or a block read
from the RAM/ EEPROM. This option enables the user to verify
that the data received by or sent from the ADM1062 is correct.
The PEC byte is an optional byte sent after the last data byte has
been written to or read from the ADM1062. The protocol is the
same as a block read for Step 1 to Step 12 and then proceeds as
follows:
In the ADM1062, the receive byte protocol is used to read a
single byte of data from a RAM or EEPROM location whose
address has previously been set by a send byte or write
byte/word operation, as shown in Figure 48.
1
S
2
The master device asserts a start condition on SDA.
The master sends the 7-bit slave address followed by the
write bit (low).
The addressed slave device asserts an ACK on SDA.
The master sends a command code that tells the slave
device to expect a block read. The ADM1062 command
code for a block read is 0xFD (1111 1101).
The slave asserts an ACK on SDA.
The master asserts a repeat start condition on SDA.
The master sends the 7-bit slave address followed by the
read bit (high).
The slave asserts an ACK on SDA.
The ADM1062 sends a byte-count data byte that tells the
master how many data bytes to expect. The ADM1062
always returns 32 data bytes (0x20), which is the maximum
allowed by the SMBus Version 1.1 specification.
13. The ADM1062 issues a PEC byte to the master. The master
checks the PEC byte and issues another block read if the
PEC byte is incorrect.
14. A NACK is generated after the PEC byte to signal the end
of the read.
15. The master asserts a stop condition on SDA to end the
transaction.
Note that the PEC byte is calculated using CRC-8. The frame
check sequence (FCS) conforms to CRC-8 by the polynomial
C(x) = x8 + x2 + x1 + 1
See the SMBus Version 1.1 specification for details.
An example of a block read with the optional PEC byte is shown
in Figure 50.
1
S
2
3
4
5 6
7
8
9
10
11
12
SLAVE
W A COMMAND 0xFD A S SLAVE R A BYTE A DATA A
ADDRESS
(BLOCK READ)
ADDRESS
COUNT
1
Rev. D | Page 34 of 35
13 14 15
DATA
32
A PEC A P
Figure 50. Block Read from the EEPROM or RAM with PEC
04433-047
1.
2.
1
The master asserts an ACK on SDA.
The master receives 32 data bytes.
The master asserts an ACK on SDA after each data byte.
The master asserts a stop condition on SDA to end
the transaction.
04433-046
READ OPERATIONS
Data Sheet
ADM1062
OUTLINE DIMENSIONS
6.10
6.00 SQ
5.90
31
1
0.50
BSC
TOP VIEW
0.80
0.75
0.70
10
11
20
BOTTOM VIEW
0.25 MIN
FOR PROPER CONNECTION OF
THE EXPOSED PAD, REFER TO
THE PIN CONFIGURATION AND
FUNCTION DESCRIPTIONS
SECTION OF THIS DATA SHEET.
0.05 MAX
0.02 NOM
COPLANARITY
0.08
0.20 REF
SEATING
PLANE
4.25
4.10 SQ
3.95
EXPOSED
PAD
21
0.45
0.40
0.35
PIN 1
INDICATOR
40
30
05-06-2011-A
PIN 1
INDICATOR
0.30
0.25
0.18
COMPLIANT TO JEDEC STANDARDS MO-220-WJJD.
Figure 51. 40-Lead Lead Frame Chip Scale Package [LFCSP_WQ]
6 mm × 6 mm Body, Very Very Thin Quad
(CP-40-9)
Dimensions shown in millimeters
0.75
0.60
0.45
1.20
MAX
9.00
BSC SQ
37
36
48
1
PIN 1
1.05
1.00
0.95
0.15
0.05
SEATING
PLANE
0.20
0.09
7°
3.5°
0°
0.08 MAX
COPLANARITY
7.00
BSC SQ
TOP VIEW
0° MIN
(PINS DOWN)
12
13
25
24
VIEW A
VIEW A
0.50
0.27
BSC
0.22
LEAD PITCH
0.17
ROTATED 90° CCW
COMPLIANT TO JEDEC STANDARDS MS-026ABC
Figure 52. 48-Lead Thin Plastic Quad Flat Package [TQFP]
(SU-48)
Dimensions shown in millimeters
ORDERING GUIDE
Model1
ADM1062ACPZ
ADM1062ACPZ-REEL7
ADM1062ASUZ
ADM1062ASUZ-REEL7
EVAL-ADM1062TQEBZ
1
Temperature Range
−40°C to +85°C
−40°C to +85°C
−40°C to +85°C
−40°C to +85°C
Package Description
40-Lead Lead Frame Chip Scale Package [LFCSP_WQ]
40-Lead Lead Frame Chip Scale Package [LFCSP_WQ]
48-Lead Thin Plastic Quad Flat Package [TQFP]
48-Lead Thin Plastic Quad Flat Package [TQFP]
Evaluation Kit (TQFP Version)
Z = RoHS Compliant Part.
I2C refers to a communications protocol originally developed by Philips Semiconductors (now NXP Semiconductors).
©2005–2015 Analog Devices, Inc. All rights reserved. Trademarks and
registered trademarks are the property of their respective owners.
D04433-0-1/15(D)
Rev. D | Page 35 of 35
Package Option
CP-40-9
CP-40-9
SU-48
SU-48