FEATURES
FUNCTIONAL BLOCK DIAGRAM
AUX1 AUX2
REFOUT REFGND
REFIN
ADM1066
MUX
Complete supervisory and sequencing solution for up to
10 supplies
10 supply fault detectors enable supervision of supplies to
DPLIMx
In addition, the DAC output buffer is three-stated if
DNLIMx > DPLIMx. By programming the limit registers
this way, the user can make it very difficult for the DAC
output buffers to be turned on during normal system operation.
The limit registers are among the registers downloaded from
EEPROM at startup.
Rev. F | Page 24 of 36
Data Sheet
ADM1066
APPLICATIONS DIAGRAM
12V IN
12V OUT
5V IN
5V OUT
3V IN
3V OUT
IN
DC-TO-DC1
EN
VH
5V OUT
3V OUT
3.3V OUT
2.5V OUT
1.8V OUT
1.2V OUT
0.9V OUT
POWRON
OUT
3.3V OUT
ADM1066
VP1
VP2
VP3
VP4
VX1
VX2
VX3
PDO1
PDO2
VX4
PDO6
IN
DC-TO-DC2
PDO3
PDO4
PDO5
PDO7
RESET
EN
SIGNAL VALID
IN
DC-TO-DC3
PDO8
EN
PDO9
PDO10
REFOUT
2.5V OUT
PWRGD
SYSTEM RESET
VX5
OUT
OUT
1.8V OUT
3.3V OUT
DAC1*
IN
REFIN VCCP VDDCAP GND
LDO
10µF
10µF
EN
10µF
OUT
0.9V OUT
3.3V OUT
*ONLY ONE MARGINING CIRCUIT
SHOWN FOR CLARITY. DAC1 TO DAC6
ALLOW MARGINING FOR UP TO SIX
VOLTAGE RAILS.
IN
OUT
EN
1.2V OUT
TRIM
04609-068
DC-TO-DC4
Figure 34. Applications Diagram
Rev. F | Page 25 of 36
ADM1066
Data Sheet
COMMUNICATING WITH THE ADM1066
CONFIGURATION DOWNLOAD AT POWER-UP
The configuration of the ADM1066 (undervoltage/overvoltage
thresholds, glitch filter timeouts, PDO configurations, and so on)
is dictated by the contents of the RAM. The RAM comprises
digital latches that are local to each function on the device. The
latches are double-buffered and have two identical latches, Latch A
and Latch B. Therefore, when an update to a function occurs,
the contents of Latch A are updated first, and then the contents
of Latch B are updated with identical data. The advantages of
this architecture are explained in detail in the Updating the
Configuration section.
The two latches are volatile memory and lose their contents at
power-down. Therefore, the configuration in the RAM must be
restored at power-up by downloading the contents of the
EEPROM (nonvolatile memory) to the local latches. This
download occurs in steps, as follows:
1.
2.
3.
4.
5.
6.
With no power applied to the device, the PDOs are all high
impedance.
When 1.2 V appears on any of the inputs connected to the
VDD arbitrator (VH or VPx), the PDOs are all weakly
pulled to GND with a 20 kΩ resistor.
When the supply rises above the undervoltage lockout of
the device (UVLO is 2.5 V), the EEPROM starts to
download to the RAM.
The EEPROM downloads its contents to all Latch As.
When the contents of the EEPROM are completely
downloaded to the Latch As, the device controller signals
all Latch As to download to all Latch Bs simultaneously,
completing the configuration download.
At 0.5 ms after the configuration download completes, the
first state definition is downloaded from the EEPROM into
the SE.
Note that any attempt to communicate with the device prior to
the completion of the download causes the ADM1066 to issue
a no acknowledge (NACK).
UPDATING THE CONFIGURATION
After power-up, with all the configuration settings loaded from
the EEPROM into the RAM registers, the user may need to alter
the configuration of functions on the ADM1066, such as changing
the undervoltage or overvoltage limit of an SFD, changing the
fault output of an SFD, or adjusting the rise time delay of one of
the PDOs.
The ADM1066 provides several options that allow the user to
update the configuration over the SMBus interface. The following
three options are controlled in the UPDCFG register.
Option 1
Update the configuration in real time. The user writes to the
RAM across the SMBus, and the configuration is updated
immediately.
Option 2
Update the Latch As without updating the Latch Bs. With this
method, the configuration of the ADM1066 remains unchanged
and continues to operate in the original setup until the instruction
is given to update the Latch Bs.
Option 3
Change the EEPROM register contents without changing the RAM
contents, and then download the revised EEPROM contents to
the RAM registers. With this method, the configuration of the
ADM1066 remains unchanged and continues to operate in the
original setup until the instruction is given to update the RAM.
The instruction to download from the EEPROM in Option 3
is also a useful way to restore the original EEPROM contents
if revisions to the configuration are unsatisfactory. For example,
if the user needs to alter an overvoltage threshold, the RAM
register can be updated as described in Option 1. However,
if the user is not satisfied with the change and wants to revert to
the original programmed value, the device controller can issue
a command to download the EEPROM contents to the RAM
again, as described in Option 3, restoring the ADM1066 to its
original configuration.
The topology of the ADM1066 makes this type of operation
possible. The local, volatile registers (RAM) are all doublebuffered latches. Setting Bit 0 of the UPDCFG register to 1 leaves
the double-buffered latches open at all times. If Bit 0 is set to 0
when a RAM write occurs across the SMBus, only the first side
of the double-buffered latch is written to. The user must then
write a 1 to Bit 1 of the UPDCFG register. This generates a pulse
to update all the second latches at once. EEPROM writes occur
in a similar way.
The final bit in this register can enable or disable EEPROM page
erasure. If this bit is set high, the contents of an EEPROM page can
all be set to 1. If this bit is set low, the contents of a page cannot be
erased, even if the command code for page erasure is programmed
across the SMBus. The bit map for the UPDCFG register is shown
in the AN-698 Application Note at www.analog.com. A flow
diagram for download at power-up and subsequent configuration
updates is shown in Figure 35.
Rev. F | Page 26 of 36
Data Sheet
ADM1066
SMBus
E
E
P
R
O
M
L
D
DEVICE
CONTROLLER
R
A
M
L
D
D
A
T
A
U
P
D
LATCH B
LATCH A
EEPROM
FUNCTION
(OV THRESHOLD
ON VP1)
04609-035
POWER-UP
(VCC > 2.5V)
Figure 35. Configuration Update Flow Diagram
UPDATING THE SEQUENCING ENGINE
Sequencing engine (SE) functions are not updated in the same
way as regular configuration latches. The SE has its own dedicated
512-byte nonvolatile, electrically erasable, programmable, readonly memory (EEPROM) for storing state definitions, providing
63 individual states each with a 64-bit word (one state is reserved).
At power-up, the first state is loaded from the SE EEPROM into
the engine itself. When the conditions of this state are met, the
next state is loaded from the EEPROM into the engine, and so
on. The loading of each new state takes approximately 10 µs.
To alter a state, the required changes must be made directly to
the EEPROM. RAM for each state does not exist. The relevant
alterations must be made to the 64-bit word, which is then
uploaded directly to the EEPROM.
INTERNAL REGISTERS
The ADM1066 contains a large number of data registers. The
principal registers are the address pointer register and the
configuration registers.
The major differences between the EEPROM and other
registers are as follows:
•
•
•
The first EEPROM is split into 16 (0 to 15) pages of 32 bytes
each. Page 0 to Page 6, starting at Address 0xF800, hold the
configuration data for the applications on the ADM1066 (such
as the SFDs and PDOs). These EEPROM addresses are the same
as the RAM register addresses, prefixed by F8. Page 7 is
reserved. Page 8 to Page 15 are for customer use.
Data can be downloaded from the EEPROM to the RAM in one
of the following ways:
•
•
Address Pointer Register
The address pointer register contains the address that selects
one of the other internal registers. When writing to the ADM1066,
the first byte of data is always a register address that is written
to the address pointer register.
An EEPROM location must be blank before it can be
written to. If it contains data, the data must first be erased.
Writing to the EEPROM is slower than writing to the RAM.
Writing to the EEPROM should be restricted because it has
a limited write/cycle life of typically 10,000 write operations
due to the usual EEPROM wear-out mechanisms.
At power-up, when Page 0 to Page 6 are downloaded
By setting Bit 0 of the UDOWNLD register (0xD8), which
performs a user download of Page 0 to Page 6
SERIAL BUS INTERFACE
The configuration registers provide control and configuration
for various operating parameters of the ADM1066.
The ADM1066 is controlled via the serial system management
bus (SMBus) and is connected to this bus as a slave device under
the control of a master device. It takes approximately 1 ms after
power-up for the ADM1066 to download from its EEPROM.
Therefore, access to the ADM1066 is restricted until the
download is complete.
EEPROM
Identifying the ADM1066 on the SMBus
The ADM1066 has two 512-byte cells of nonvolatile EEPROM
from Register Address 0xF800 to Register Address 0xFBFF. The
EEPROM is used for permanent storage of data that is not lost
when the ADM1066 is powered down. One EEPROM cell contains
the configuration data of the device; the other contains the state
definitions for the SE. Although referred to as read-only memory,
the EEPROM can be written to, as well as read from, using the
serial bus in exactly the same way as the other registers.
The ADM1066 has a 7-bit serial bus slave address (see Table 11).
The device is powered up with a default serial bus address. The
five MSBs of the address are set to 01101; the two LSBs are
determined by the logical states of Pin A1 and Pin A0. This
allows the connection of four ADM1066s to one SMBus.
Configuration Registers
Table 11. Serial Bus Slave Address
A1 Pin
Low
Low
High
High
1
A0 Pin
Low
High
Low
High
Hex Address
0x68
0x6A
0x6C
0x6E
7-Bit Address
0110100x1
0110101x1
0110110x1
0110111x1
x = Read/write bit. The address is shown only as the first 7 MSBs.
Rev. F | Page 27 of 36
ADM1066
Data Sheet
The device also has several identification registers (read-only)
that can be read across the SMBus. Table 12 lists these registers
with their values and functions.
Table 12. Identification Register Values and Functions
Name
MANID
Address
0xF4
Value
0x41
REVID
MARK1
MARK2
0xF5
0xF6
0xF7
0x02
0x00
0x00
Function
Manufacturer ID for Analog
Devices
Silicon revision
Software brand
Software brand
It may be an instruction telling the slave device to expect a block
write, or it may be a register address that tells the slave where
subsequent data is to be written. Because data can flow in only
one direction, as defined by the R/W bit, sending a command
to a slave device during a read operation is not possible. Before
a read operation, it may be necessary to perform a write operation
to tell the slave what sort of read operation to expect and/or the
address from which data is to be read.
Step 3
The general SMBus protocol operates as follows:
When all data bytes have been read or written, stop conditions
are established. In write mode, the master pulls the data line high
during the 10th clock pulse to assert a stop condition. In read
mode, the master device releases the SDA line during the low
period before the ninth clock pulse, but the slave device does
not pull it low. This is known as a no acknowledge. The master
then takes the data line low during the low period before the
10th clock pulse and then high during the 10th clock pulse to
assert a stop condition.
Step 1
SCL Held Low Timeout
The master initiates data transfer by establishing a start condition,
defined as a high-to-low transition on the serial data line SDA,
while the serial clock line SCL remains high. This indicates that
a data stream follows. All slave peripherals connected to the serial
bus respond to the start condition and shift in the next eight bits,
consisting of a 7-bit slave address (MSB first) plus an R/W bit.
This bit determines the direction of the data transfer, that is,
whether data is written to or read from the slave device (0 = write,
1 = read).
If the bus master holds the SCL low for a time that is a multiple
of approximately 30 ms, the ADM1066 bus interface may timeout.
If this timeout happens, the in progress transaction is NACKed,
and the transaction must be repeated. This behavior is only seen
if the I2C bus master is interrupted midtransaction by a higher
priority task that delays completion of the transaction.
General SMBus Timing
Figure 36, Figure 37, and Figure 38 are timing diagrams for
general read and write operations using the SMBus. The SMBus
specification defines specific conditions for different types of
read and write operations, which are discussed in the Write
Operations and the Read Operations sections.
The peripheral whose address corresponds to the transmitted
address responds by pulling the data line low during the low
period before the ninth clock pulse, known as the acknowledge
bit, and by holding it low during the high period of this clock pulse.
All other devices on the bus remain idle while the selected device
waits for data to be read from or written to it. If the R/W bit is a 0,
the master writes to the slave device. If the R/W bit is a 1, the
master reads from the slave device.
Step 2
Data is sent over the serial bus in sequences of nine clock pulses:
eight bits of data followed by an acknowledge bit from the slave
device. Data transitions on the data line must occur during the
low period of the clock signal and remain stable during the high
period because a low-to-high transition when the clock is high
could be interpreted as a stop signal. If the operation is a write
operation, the first data byte after the slave address is a command
byte. This command byte tells the slave device what to expect next.
False Start Detection
The data hold time specification defines the time that data must
be valid on the SDA line, following an SCL falling edge. If there
are multiple ADM1066 devices on the same bus, one of the
ADM1066 devices may see the SCL/SDA transition due to an
acknowledge (ACK) from a different device as a start condition
because of internal timing skew, which for most transactions,
this is not an issue. In a case where the data appearing on the
bus after the false start is detected happens to match the address
of another ADM1066 on the bus, that device may incorrectly
ACK.
A bus master may see this ACK as another bus master talking
on the bus, halt the bus transaction, and not produce any more
clocks on the SCL. As a result, the ADM1066 device that
incorrectly ACKed continues to hold down the SDA line low.
To retry the halted bus transaction, the bus master performs a
clock flush on the SCL by sending a series of up to 16 clock pulses.
The clock flush forces the ADM1066 to release the SDA line.
Rev. F | Page 28 of 36
Data Sheet
ADM1066
1
9
1
9
SCL
0
SDA
1
1
0
1
A1
A0
D7
R/W
D6
D5
D4
D3
D2
D1
ACK. BY
SLAVE
START BY
MASTER
D0
ACK. BY
SLAVE
FRAME 1
SLAVE ADDRESS
FRAME 2
COMMAND CODE
1
9
1
9
SCL
(CONTINUED)
D7
D6
D5
D4
D3
D2
D1
D7
D0
D6
D5
ACK. BY
SLAVE
FRAME 3
DATA BYTE
D4
D3
D2
D1
D0
ACK. BY
SLAVE
FRAME N
DATA BYTE
STOP
BY
MASTER
04609-036
SDA
(CONTINUED)
Figure 36. General SMBus Write Timing Diagram
1
9
1
9
SCL
0
SDA
1
1
0
1
A1
A0 R/W
D7
D6
D5
D4
D3
D2
D1
ACK. BY
SLAVE
START BY
MASTER
1
D0
ACK. BY
MASTER
FRAME 1
SLAVE ADDRESS
9
1
FRAME 2
DATA BYTE
9
SCL
(CONTINUED)
D7
D6
D5
D4
D3
D2
D1
D0
D7
D6
D5
ACK. BY
MASTER
FRAME 3
DATA BYTE
D4
D3
D2
D1
D0
NO ACK.
FRAME N
DATA BYTE
STOP
BY
MASTER
04609-037
SDA
(CONTINUED)
Figure 37. General SMBus Read Timing Diagram
tR
tF
t HD; STA
t LO W
SCL
t HI G H
t HD; STA
t HD; DAT
t SU; STA
t SU; STO
t SU; DAT
t BUF
P
S
S
P
04609-038
SDA
Figure 38. Serial Bus Timing Diagram
SMBus PROTOCOLS FOR RAM AND EEPROM
WRITE OPERATIONS
The ADM1066 contains volatile registers (RAM) and nonvolatile
registers (EEPROM). User RAM occupies Address 0x00 to
Address 0xDF; the EEPROM occupies Address 0xF800 to
Address 0xFBFF.
The SMBus specification defines several protocols for different
types of read and write operations. The following abbreviations
are used in Figure 39 to Figure 47:
Data can be written to and read from both the RAM and the
EEPROM as single data bytes. Data can be written only to
unprogrammed EEPROM locations. To write new data to a
programmed location, the location contents must first be erased.
EEPROM erasure cannot be done at the byte level. The EEPROM
is arranged as 32 pages of 32 bytes each, and an entire page
must be erased.
Page erasure is enabled by setting Bit 2 in the UPDCFG register
(Address 0x90) to 1. If this bit is not set, page erasure cannot
occur, even if the command byte (0xFE) is programmed across
the SMBus.
Rev. F | Page 29 of 36
S = Start
P = Stop
R = Read
W = Write
A = Acknowledge
A = No acknowledge
ADM1066
Data Sheet
The ADM1066 uses the following SMBus write protocols.
Write Byte/Word
Send Byte
In a write byte/word operation, the master device sends a
command byte and one or two data bytes to the slave device, as
follows:
4.
5.
6.
In the ADM1066, the send byte protocol is used for two
purposes:
To write a register address to the RAM for a subsequent
single byte read from the same address, or for a block read
or block write starting at that address, as shown in Figure 39.
1
2
S
SLAVE
ADDRESS
W
3
4
5
6
A
RAM
ADDRESS
(0x00 TO 0xDF)
A
P
The master device asserts a start condition on SDA.
The master sends the 7-bit slave address followed by the
write bit (low).
3. The addressed slave device asserts an ACK on SDA.
4. The master sends a command code.
5. The slave asserts an ACK on SDA.
6. The master sends a data byte.
7. The slave asserts an ACK on SDA.
8. The master sends a data byte or asserts a stop condition.
9. The slave asserts an ACK on SDA.
10. The master asserts a stop condition on SDA to end the
transaction.
In the ADM1066, the write byte/word protocol is used for three
purposes:
•
04609-039
•
1.
2.
To write a single byte of data to the RAM. In this case, the
command byte is RAM Address 0x00 to RAM Address 0xDF,
and the only data byte is the actual data, as shown in Figure 41.
1
Figure 39. Setting a RAM Address for Subsequent Read
To erase a page of EEPROM memory. EEPROM memory
can be written to only if it is unprogrammed. Before writing
to one or more EEPROM memory locations that are already
programmed, the page(s) containing those locations must
first be erased. EEPROM memory is erased by writing a
command byte.
2
S
SLAVE
ADDRESS
W
3
4
5
6
A
COMMAND
BYTE
(0xFE)
A
P
•
5
6
7 8
DATA A P
To set up a 2-byte EEPROM address for a subsequent read,
write, block read, block write, or page erase. In this case, the
command byte is the high byte of EEPROM Address 0xF8
to EEPROM Address 0xFB. The only data byte is the low
byte of the EEPROM address, as shown in Figure 42.
2
1
3
SLAVE
S ADDRESS W A
4
5
6
7 8
EEPROM
EEPROM
ADDRESS
ADDRESS
A
A P
HIGH BYTE
LOW BYTE
(0xF8 TO 0xFB)
(0x00 TO 0xFF)
Figure 42. Setting an EEPROM Address
Because a page consists of 32 bytes, only the three MSBs of
the address low byte are important for page erasure. The
lower five bits of the EEPROM address low byte specify the
addresses within a page and are ignored during an erase
operation.
Figure 40. EEPROM Page Erasure
As soon as the ADM1066 receives the command byte,
page erasure begins. The master device can send a stop
command as soon as it sends the command byte. Page
erasure takes approximately 20 ms. If the ADM1066 is
accessed before erasure is complete, it responds with a
no acknowledge (NACK).
4
Figure 41. Single Byte Write to the RAM
The master sends a command code telling the slave device
to erase the page. The ADM1066 command code for a page
erasure is 0xFE (1111 1110). Note that for a page erasure to
take place, the page address must be given in the previous
write word transaction (see the Write Byte/Word section). In
addition, Bit 2 in the UPDCFG register (Address 0x90)
must be set to 1.
1
3
RAM
SLAVE W A
S ADDRESS
ADDRESS
A
(0x00 TO 0xDF)
04609-040
•
2
•
To write a single byte of data to the EEPROM. In this case,
the command byte is the high byte of EEPROM Address 0xF8
to EEPROM Address 0xFB. The first data byte is the low
byte of the EEPROM address, and the second data byte is
the actual data, as shown in Figure 43.
1
2
3
4
5
6
7
8
9 10
EEPROM
EEPROM
SLAVE
ADDRESS
ADDRESS
S
A
P
ADDRESS W A
HIGH BYTE
LOW BYTE A DATA A
(0xF8 TO 0xFB)
(0x00 TO 0xFF)
Figure 43. Single Byte Write to the EEPROM
Rev. F | Page 30 of 36
04609-043
3.
The master device asserts a start condition on SDA.
The master sends the 7-bit slave address followed by the
write bit (low).
The addressed slave device asserts an acknowledge (ACK)
on SDA.
The master sends a command code.
The slave asserts an ACK on SDA.
The master asserts a stop condition on SDA, and the
transaction ends.
04609-041
1.
2.
04609-042
In a send byte operation, the master device sends a single
command byte to a slave device, as follows:
Data Sheet
ADM1066
Block Write
6.
In a block write operation, the master device writes a block of
data to a slave device. The start address for a block write must
have been set previously. In the ADM1066, a send byte operation sets a RAM address, and a write byte/word operation sets
an EEPROM address, as follows:
In the ADM1066, the receive byte protocol is used to read a
single byte of data from a RAM or EEPROM location whose
address has previously been set by a send byte or write
byte/word operation, as shown in Figure 45.
1.
2.
2
3
4
5
6
7
8
9
There must be at least N locations from the start address to
the highest EEPROM address (0xFBFF) to avoid writing to
invalid addresses.
An address crosses a page boundary. In this case, both
pages must be erased before programming.
Note that the ADM1066 features a clock extend function for writes
to the EEPROM. Programming an EEPROM byte takes approximately 250 μs, which limits the SMBus clock for repeated or block
write operations. The ADM1066 pulls SCL low and extends the
clock pulse when it cannot accept any more data.
S
SLAVE
ADDRESS
R
3
4
5
6
A
DATA
A
P
Block Read
In a block read operation, the master device reads a block of
data from a slave device. The start address for a block read must
have been set previously. In the ADM1066, this is done by a
send byte operation to set a RAM address, or a write byte/word
operation to set an EEPROM address. The block read operation
itself consists of a send byte operation that sends a block read
command to the slave, immediately followed by a repeated start
and a read operation that reads out multiple data bytes, as follows:
1.
2.
3.
4.
Figure 44. Block Write to the EEPROM or RAM
Unlike some EEPROM devices that limit block writes to within
a page boundary, there is no limitation on the start address
when performing a block write to EEPROM, except when
2
Figure 45. Single Byte Read from the EEPROM or RAM
10
S SLAVE
W A COMMAND 0xFC A BYTE A DATA A DATA A DATA A P
ADDRESS
(BLOCK WRITE)
COUNT
1
2
N
04609-044
1
1
04609-045
The master device asserts a start condition on SDA.
The master sends the 7-bit slave address followed by
the write bit (low).
3. The addressed slave device asserts an ACK on SDA.
4. The master sends a command code that tells the slave
device to expect a block write. The ADM1066 command
code for a block write is 0xFC (1111 1100).
5. The slave asserts an ACK on SDA.
6. The master sends a data byte that tells the slave device how
many data bytes are being sent. The SMBus specification
allows a maximum of 32 data bytes in a block write.
7. The slave asserts an ACK on SDA.
8. The master sends N data bytes.
9. The slave asserts an ACK on SDA after each data byte.
10. The master asserts a stop condition on SDA to end the
transaction.
The master asserts a stop condition on SDA, and the
transaction ends.
5.
6.
7.
8.
9.
10.
11.
12.
13.
The master device asserts a start condition on SDA.
The master sends the 7-bit slave address followed by the
write bit (low).
The addressed slave device asserts an ACK on SDA.
The master sends a command code that tells the slave
device to expect a block read. The ADM1066 command
code for a block read is 0xFD (1111 1101).
The slave asserts an ACK on SDA.
The master asserts a repeat start condition on SDA.
The master sends the 7-bit slave address followed by the
read bit (high).
The slave asserts an ACK on SDA.
The ADM1066 sends a byte-count data byte that tells the
master how many data bytes to expect. The ADM1066
always returns 32 data bytes (0x20), which is the maximum
allowed by the SMBus Version 1.1 specification.
The master asserts an ACK on SDA.
The master receives 32 data bytes.
The master asserts an ACK on SDA after each data byte.
The master asserts a stop condition on SDA to end the
transaction.
READ OPERATIONS
1
The ADM1066 uses the following SMBus read protocols.
SLAVE
COMMAND 0xFD
SLAVE
BYTE
DATA
R A
A
A
S
W A
A S
ADDRESS
(BLOCK READ)
ADDRESS
COUNT
1
2
3
4
5 6
7
8
9
10
11
12
Receive Byte
1.
2.
3.
4.
5.
The master device asserts a start condition on SDA.
The master sends the 7-bit slave address followed by the
read bit (high).
The addressed slave device asserts an ACK on SDA.
The master receives a data byte.
The master asserts a NACK on SDA.
Rev. F | Page 31 of 36
DATA
A
32
Figure 46. Block Read from the EEPROM or RAM
P
04609-046
13
In a receive byte operation, the master device receives a single
byte from a slave device, as follows:
ADM1066
Data Sheet
The ADM1066 provides the option of issuing a packet error
correction (PEC) byte after a write to the RAM, a write to the
EEPROM, a block write to the RAM/EEPROM, or a block read
from the RAM/EEPROM. This option enables the user to verify
that the data received by or sent from the ADM1066 is correct.
The PEC byte is an optional byte sent after the last data byte has
been written to or read from the ADM1066. The protocol is the
same as a block read for Step 1 to Step 12 and then proceeds as
follows:
15. The master asserts a stop condition on SDA to end the
transaction.
Note that the PEC byte is calculated using CRC-8. The frame
check sequence (FCS) conforms to CRC-8 by the polynomial
C(x) = x8 + x2 + x1 + 1
See the SMBus Version 1.1 specification for details. An example
of a block read with the optional PEC byte is shown in Figure 47.
1
S
2
3
4
5 6
7
8
9
10
11
12
DATA
BYTE
SLAVE
COMMAND 0xFD
SLAVE
A
W A (BLOCK READ) A S ADDRESS R A COUNT A
1
ADDRESS
13. The ADM1066 issues a PEC byte to the master. The master
checks the PEC byte and issues another block read, if the
PEC byte is incorrect.
14. A NACK is generated after the PEC byte to signal the end
of the read.
Rev. F | Page 32 of 36
13 14 15
DATA
32
A PEC A P
Figure 47. Block Read from the EEPROM or RAM with PEC
04609-047
Error Correction
Data Sheet
ADM1066
OUTLINE DIMENSIONS
6.10
6.00 SQ
5.90
31
1
0.50
BSC
TOP VIEW
0.80
0.75
0.70
10
11
20
0.25 MIN
BOTTOM VIEW
FOR PROPER CONNECTION OF
THE EXPOSED PAD, REFER TO
THE PIN CONFIGURATION AND
FUNCTION DESCRIPTIONS
SECTION OF THIS DATA SHEET.
0.05 MAX
0.02 NOM
COPLANARITY
0.08
0.20 REF
SEATING
PLANE
4.25
4.10 SQ
3.95
EXPOSED
PAD
21
0.45
0.40
0.35
PIN 1
INDICATOR
40
30
05-06-2011-A
PIN 1
INDICATOR
0.30
0.25
0.18
COMPLIANT TO JEDEC STANDARDS MO-220-WJJD.
Figure 48. 40-Lead Frame Chip Scale Package [LFCSP_WQ]
6 mm × 6 mm Body, Very Very Thin Quad
(CP-40-9)
Dimensions shown in millimeters
0.75
0.60
0.45
1.20
MAX
9.00
BSC SQ
37
36
48
1
PIN 1
0° MIN
1.05
1.00
0.95
0.15
0.05
SEATING
PLANE
0.20
0.09
7°
3.5°
0°
0.08 MAX
COPLANARITY
7.00
BSC SQ
TOP VIEW
(PINS DOWN)
12
13
25
24
VIEW A
VIEW A
0.50
0.27
BSC
0.22
LEAD PITCH
0.17
ROTATED 90° CCW
COMPLIANT TO JEDEC STANDARDS MS-026ABC
Figure 49. 48-Lead Thin Plastic Quad Flat Package [TQFP]
(SU-48)
Dimensions shown in millimeters
ORDERING GUIDE
Model1
ADM1066ACPZ
ADM1066ACPZ-REEL
ADM1066ACPZ-REEL7
ADM1066ASUZ
ADM1066ASUZ-REEL
ADM1066ASUZ-REEL7
EVAL-ADM1066TQEBZ
1
Temperature Range
−40°C to +85°C
−40°C to +85°C
−40°C to +85°C
−40°C to +85°C
−40°C to +85°C
−40°C to +85°C
Package Description
40-Lead LFCSP_WQ
40-Lead LFCSP_WQ
40-Lead LFCSP_WQ
48-Lead TQFP
48-Lead TQFP
48-Lead TQFP
Evaluation Kit (TQFP Version)
Z = RoHS Compliant Part.
Rev. F | Page 33 of 36
Package Option
CP-40-9
CP-40-9
CP-40-9
SU-48
SU-48
SU-48
ADM1066
Data Sheet
NOTES
Rev. F | Page 34 of 36
Data Sheet
ADM1066
NOTES
Rev. F | Page 35 of 36
ADM1066
Data Sheet
NOTES
©2004–2015 Analog Devices, Inc. All rights reserved. Trademarks and
registered trademarks are the property of their respective owners.
D04609-0-1/15(F)
Rev. F | Page 36 of 36
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