ADM1067ACPZ1

Super Sequencer® with Open-Loop Margining DACs ADM1067 FEATURES Complete supervisory and sequencing solution for up to 10 supplies 10 supply fault detectors enable supervision of supplies to DPLIMn R1 (VFB − VDACOUT) R3 In addition, the DAC output buffer is three-stated, if DNLIMn > DPLIMn. By programming the limit registers in this way, the user can make it very difficult for the DAC output buffers to be turned on at all during normal system operation (these are among the registers downloaded from EEPROM at startup). Rev. B | Page 23 of 32 ADM1067 APPLICATIONS DIAGRAM 12V IN 5V IN 3V IN IN 12V OUT 5V OUT 3V OUT DC-DC1 5V OUT 3V OUT 3.3V OUT 2.5V OUT 1.8V OUT 1.2V OUT 0.9V OUT POWER_ON RESET_L VH VP1 VP2 VP3 VP4 VX1 VX2 VX3 VX4 VX5 MARGIN UP MARGIN DOWN MUP MDN EN OUT 3.3V OUT ADM1067 PDO1 PDO2 IN PDO3 PDO4 PDO5 PDO6 PDO7 PDO8 PDO9 PDO10 DAC1* POWER_GOOD SIGNAL_VALID SYSTEM RESET IN DC-DC2 EN OUT 2.5V OUT DC-DC3 EN OUT 3.3V OUT IN 1.8V OUT VCCP VDDCAP REFOUT GND 10µF 10µF 10µF 3.3V OUT *ONLY ONE MARGINING CIRCUIT SHOWN FOR CLARITY. DAC1 TO DAC6 WILL ALLOW MARGINING FOR UP TO SIX VOLTAGE RAILS. EN IN EN LDO OUT 0.9V OUT OUT 1.2V OUT TRIM 04635-068 DC-DC4 Figure 28. Applications Diagram Rev. B | Page 24 of 32 ADM1067 COMMUNICATING WITH THE ADM1067 CONFIGURATION DOWNLOAD AT POWER-UP The configuration of the ADM1067 (such as UV/OV thresholds, glitch filter timeouts, and PDO configurations) is dictated by the contents of RAM. The RAM is comprised of digital latches that are local to each of the functions on the device. The latches are double-buffered and have two identical latches, Latch A and Latch B. Therefore, when an update to a function occurs, the contents of Latch A are updated first, and then the contents of Latch B are updated with identical data. The advantages of this architecture are explained in detail in this section. The two latches are volatile memory and lose their contents at power-down. Therefore, the configuration in the RAM must be restored at power-up by downloading the contents of the EEPROM (nonvolatile memory) to the local latches. This download occurs in steps, as follows: 1. 2. With no power applied to the device, the PDOs are high impedance. When 1 V appears on any of the inputs connected to the VDD arbitrator (VH or VPn), the PDOs are weakly pulled to GND with a 20 kΩ impedance. When the supply rises above the undervoltage lockout of the device (UVLO is 2.5 V), the EEPROM starts to download to the RAM. The EEPROM downloads its contents to all Latch As. Once the contents of the EEPROM are completely downloaded to the Latch As, the device controller signals all Latch As to download to all Latch Bs simultaneously, completing the configuration download. The first state definition is downloaded from EEPROM into the SE 0.5 ms after the configuration download completes. The ADM1067 provides several options that allow the user to update the configuration over the SMBus interface. The following three options are controlled in the UPDCFG register: Option 1 Update the configuration in real time. The user writes to RAM across the SMBus and the configuration is updated immediately. Option 2 Update the Latch As without updating the Latch Bs. With this method, the configuration of the ADM1067 remains unchanged and continues to operate in the original setup until the instruction is given to update the Latch Bs. Option 3 Change EEPROM register contents without changing the RAM contents, and then download the revised EEPROM contents to the RAM registers. Again, with this method, the configuration of the ADM1067 remains unchanged and continues to operate in the original setup until the instruction is given to update the RAM. The instruction to download from the EEPROM in Option 3 is also a useful way to restore the original EEPROM contents, if revisions to the configuration are unsatisfactory. For example, if the user needs to alter an OV threshold, the RAM register can be updated as described in Option 1. However, if the user is not satisfied with the change and wants to revert to the original programmed value, the device controller can issue a command to download the EEPROM contents to the RAM again, as described in Option 3, restoring the ADM1067 to its original configuration. The topology of the ADM1067 makes this type of operation possible. The local, volatile registers (RAM) are all doublebuffered latches. Setting Bit 0 of the UPDCFG register to 1 leaves the double-buffered latches open at all times. If Bit 0 is set to 0 and a RAM write occurs across the SMBus, only the first side of the double-buffered latch is written to. The user must then write a 1 to Bit 1 of the UPDCFG register. This generates a pulse to update all the second latches at once. EEPROM writes occur in a similar way. The final bit in this register can enable or disable EEPROM page erasure. If this bit is set high, the contents of an EEPROM page can all be set to 1. If low, the contents of a page cannot be erased, even if the command code for page erasure is programmed across the SMBus. The bit map for the UPDCFG register is shown in the AN-698 Application Note. A flow chart for download at power-up and subsequent configuration updates is shown in Figure 29. 3. 4. 5. 6. Note that any attempt to communicate with the device prior to the completion of the download causes the ADM1067 to issue a no acknowledge (NACK). UPDATING THE CONFIGURATION After power-up, with all the configuration settings loaded from EEPROM into the RAM registers, the user may need to alter the configuration of functions on the ADM1067, such as changing the UV or OV limit of an SFD, changing the fault output of an SFD, or adjusting the rise time delay of one of the PDOs. Rev. B | Page 25 of 32 ADM1067 SMBus POWER-UP (VCC > 2.5V) EEPROM Figure 29. Configuration Update Flow Diagram UPDATING THE SEQUENCING ENGINE Sequencing engine (SE) functions are not updated in the same way as regular configuration latches. The SE has its own dedicated 512-byte EEPROM for storing state definitions, providing 63 individual states with a 64-bit word each (one state is reserved). At power-up, the first state is loaded from the SE EEPROM into the engine itself. When the conditions of this state are met, the next state is loaded from EEPROM into the engine, and so on. The loading of each new state takes approximately 10 μs. To alter a state, the required changes must be made directly to EEPROM. RAM for each state does not exist. The relevant alterations must be made to the 64-bit word, which is then uploaded directly to EEPROM. The major differences between the EEPROM and other registers are as follows: • • • An EEPROM location must be blank before it can be written to. If it contains data, it must first be erased. Writing to EEPROM is slower than writing to RAM. Writing to the EEPROM should be restricted, because it has a limited write/cycle life of typically 10,000 write operations due to the usual EEPROM wear-out mechanisms. The first EEPROM is split into 16 (0 to 15) pages of 32 bytes each. Page 0 to Page 6, starting at Address 0xF800, hold the configuration data for the applications on the ADM1067 (such as the SFDs and PDOs). These EEPROM addresses are the same as the RAM register addresses, prefixed by F8. Page 7 is reserved. Page 8 to Page 15 are for customer use. Data can be downloaded from EEPROM to RAM in one of the following ways: • • At power-up, when Page 0 to Page 6 are downloaded. By setting Bit 0 of the UDOWNLD register (0xD8), which performs a user download of Page 0 to Page 6. INTERNAL REGISTERS The ADM1067 contains a large number of data registers. The principal registers are the address pointer register and the configuration registers. Address Pointer Register This register contains the address that selects one of the other internal registers. When writing to the ADM1067, the first byte of data is always a register address that is written to the address pointer register. SERIAL BUS INTERFACE The ADM1067 is controlled via the serial system management bus (SMBus) and is connected to this bus as a slave device, under the control of a master device. It takes approximately 1 ms after power-up for the ADM1067 to download from its EEPROM. Therefore, access to the ADM1067 is restricted until the download is complete. Configuration Registers These registers provide control and configuration for various operating parameters of the ADM1067. EEPROM The ADM1067 has two 512-byte cells of nonvolatile, electrically erasable, programmable read-only memory (EEPROM), from Register Address 0xF800 to Register Address 0xFBFF. The EEPROM is used for permanent storage of data that is not lost when the ADM1067 is powered down. One EEPROM cell contains the configuration data of the device; the other contains the state definitions for the SE. Although referred to as read-only memory, the EEPROM can be written to, as well as read from, via the serial bus in exactly the same way as the other registers. Identifying the ADM1067 on the SMBus The ADM1067 has a 7-bit serial bus slave address. The device is powered up with a default serial bus address. The five MSBs of the address are set to 01111; the two LSBs are determined by the logical states of Pin A1 and Pin A0. This allows the connection of four ADM1067s to one SMBus. Rev. B | Page 26 of 32 04635-035 E E P R O M L D DEVICE CONTROLLER D A T A LATCH A R A M L D U P D LATCH B FUNCTION (OV THRESHOLD ON VP1) ADM1067 Table 10. Serial Bus Slave Address A0 Pin Low Low High High 1 A1 Pin Low High Low High Hex Address 0x78 0x7A 0x7C 0x7E 7-Bit Address 0111100X1 0111101X1 0111110X1 0111111X1 X = Read/Write bit. The address is shown only as the first 7 MSBs. The device also has several identification registers (read-only) that can be read across the SMBus. Table 11 lists these registers with their values and functions. Table 11. Identification Register Values and Functions Name MANID REVID MARK1 MARK2 Address 0xF4 0xF5 0xF6 0xF7 Value 0x41 0x02 0x00 0x00 Function Manufacturer ID for Analog Devices Silicon revision Software brand Software brand 2. General SMBus Timing Figure 30, Figure 31, and Figure 32 are timing diagrams for general read and write operations using the SMBus. The SMBus specification defines specific conditions for different types of read and write operations, which are discussed in the Write Operations section and Read Operations section. The general SMBus protocol operates as follows: 1. The master initiates data transfer by establishing a start condition, defined as a high-to-low transition on the serial data-line SDA, while the serial clock-line SCL remains high. This indicates that a data stream follows. All slave peripherals connected to the serial bus respond to the start condition and shift in the next 8 bits, consisting of a 7-bit slave address (MSB first) plus an R/W bit. This bit determines the direction of the data transfer, that is, whether data is written to or read from the slave device (0 = write, 1 = read). 3. The peripheral whose address corresponds to the transmitted address responds by pulling the data line low during the low period before the ninth clock pulse, known as the acknowledge bit, and by holding it low during the high period of this clock pulse. All other devices on the bus remain idle while the selected device waits for data to be read from or written to it. If the R/W bit is a 0, the master writes to the slave device. If the R/W bit is a 1, the master reads from the slave device. Data is sent over the serial bus in sequences of nine clock pulses, eight bits of data followed by an acknowledge bit from the slave device. Data transitions on the data line must occur during the low period of the clock signal and remain stable during the high period, because a low-tohigh transition when the clock is high could be interpreted as a stop signal. If the operation is a write operation, the first data byte after the slave address is a command byte. This tells the slave device what to expect next. It could be an instruction telling the slave device to expect a block write, or it could simply be a register address telling the slave where subsequent data is to be written. Because data can flow in only one direction, as defined by the R/W bit, sending a command to a slave device during a read operation is not possible. Before a read operation, it could be necessary to perform a write operation to tell the slave what sort of read operation to expect and/or the address from which data is to be read. When all data bytes have been read or written, stop conditions are established. In write mode, the master pulls the data line high during the 10th clock pulse to assert a stop condition. In read mode, the master device releases the SDA line during the low period before the ninth clock pulse, but the slave device does not pull it low. This is known as no acknowledge. The master then takes the data line low during the low period before the 10th clock pulse, and then high during the 10th clock pulse to assert a stop condition. Rev. B | Page 27 of 32 ADM1067 1 SCL 0 START BY MASTER FRAME 1 SLAVE ADDRESS SCL (CONTINUED) SDA (CONTINUED) 1 9 1 1 1 1 1 A1 A0 R/W ACK. BY SLAVE FRAME 2 COMMAND CODE 9 D7 D6 D5 D4 D3 D2 D1 D0 ACK. BY SLAVE 9 1 9 SDA D7 D6 D5 D4 D3 D2 D1 D0 ACK. BY SLAVE D7 D6 D5 D4 D3 D2 D1 D0 04635-036 04635-037 FRAME 3 DATA BYTE FRAME N DATA BYTE ACK. BY SLAVE STOP BY MASTER Figure 30. General SMBus Write Timing Diagram 1 SCL 0 START BY MASTER 1 FRAME 1 SLAVE ADDRESS 1 1 1 1 A1 A0 R/W 9 1 9 SDA D7 D6 D5 D4 D3 D2 D1 D0 ACK. BY MASTER ACK. BY SLAVE 9 1 FRAME 2 DATA BYTE SCL (CONTINUED) SDA (CONTINUED) 9 D7 D6 D5 D4 D3 D2 D1 D0 ACK. BY MASTER D7 D6 D5 D4 D3 D2 D1 D0 NO ACK. STOP BY MASTER FRAME 3 DATA BYTE FRAME N DATA BYTE Figure 31. General SMBus Read Timing Diagram tR SCL tF t HD; STA t LO W t HD; STA t HD; DAT t SU; DAT 04635-038 t HI G H t SU; STA t SU; STO SDA t BUF P S S P Figure 32. Serial Bus Timing Diagram Rev. B | Page 28 of 32 ADM1067 SMBus PROTOCOLS FOR RAM AND EEPROM The ADM1067 contains volatile registers (RAM) and nonvolatile registers (EEPROM). User RAM occupies Address 0x00 to Address 0xDF; EEPROM occupies Address 0xF800 to Address 0xFBFF. Data can be written to and read from both RAM and EEPROM as single data bytes. Data can be written only to unprogrammed EEPROM locations. To write new data to a programmed location, it must first be erased. EEPROM erasure cannot be done at the byte level. The EEPROM is arranged as 32 pages of 32 bytes each, and an entire page must be erased. Page erasure is enabled by setting Bit 2 in the UPDCFG register (Address 0x90) to 1. If this bit is not set, page erasure cannot occur, even if the command byte (0xFE) is programmed across the SMBus. • • To erase a page of EEPROM memory. EEPROM memory can be written to only if it is unprogrammed. Before writing to one or more EEPROM memory locations that are already programmed, the page or pages containing those locations must first be erased. EEPROM memory is erased by writing a command byte. The master sends a command code that tells the slave device to erase the page. The ADM1067 command code for a page erasure is 0xFE (1111 1110). Note that, for a page erasure to take place, the page address has to be given in the previous write word transaction (see the Write Byte/Word section). In addition, Bit 2 in the UPDCFG register (Address 0x90) must be set to 1. 1 S 2 SLAVE ADDRESS W 3 A 4 COMMAND BYTE (0xFE) 5 A 6 P 04635-040 WRITE OPERATIONS The SMBus specification defines several protocols for different types of read and write operations. The following abbreviations are used in Figure 33 to Figure 41. • • • • • • S P R W A A Start Stop Read Write Acknowledge No acknowledge Figure 34. EEPROM Page Erasure As soon as the ADM1067 receives the command byte, page erasure begins. The master device can send a stop command as soon as it sends the command byte. Page erasure takes approximately 20 ms. If the ADM1067 is accessed before erasure is complete, it responds with a no acknowledge (NACK). Write Byte/Word In a write byte/word operation, the master device sends a command byte and one or two data bytes to the slave device, as follows: 1. 2. The master device asserts a start condition on SDA. The master sends the 7-bit slave address followed by the write bit (low). 3. The addressed slave device asserts ACK on SDA. 4. The master sends a command code. 5. The slave asserts ACK on SDA. 6. The master sends a data byte. 7. The slave asserts ACK on SDA. 8. The master sends a data byte (or asserts a stop condition at this point). 9. The slave asserts ACK on SDA. 10. The master asserts a stop condition on SDA to end the transaction. In the ADM1067, the write byte/word protocol is used for three purposes: • To write a single byte of data to RAM. In this case, the command byte is the RAM address from 0x00 to 0xDF and the only data byte is the actual data, as shown in Figure 35. 1 2 3 4 5 6 78 04635-041 The ADM1067 uses the following SMBus write protocols. Send Byte In a send byte operation, the master device sends a single command byte to a slave device, as follows: 1. 2. 3. 4. 5. 6. The master device asserts a start condition on SDA. The master sends the 7-bit slave address followed by the write bit (low). The addressed slave device asserts ACK on SDA. The master sends a command code. The slave asserts ACK on SDA. The master asserts a stop condition on SDA and the transaction ends. In the ADM1067, the send byte protocol is used for two purposes: • To write a register address to RAM for a subsequent single byte read from the same address, or a block read or write starting at that address, as shown in Figure 33. 1 S 2 SLAVE ADDRESS W 3 A 4 RAM ADDRESS (0x00 TO 0xDF) 5 A 6 P 04635-039 RAM S SLAVE W A ADDRESS A ADDRESS (0x00 TO 0xDF) DATA A P Figure 35. Single Byte Write to RAM Figure 33. Setting a RAM Address for Subsequent Read Rev. B | Page 29 of 32 ADM1067 • To set up a 2-byte EEPROM address for a subsequent read, write, block read, block write, or page erase. In this case, the command byte is the high byte of the EEPROM address from 0xF8 to 0xFB. The only data byte is the low byte of the EEPROM address, as shown in Figure 36. 1 2 3 4 5 6 78 04635-042 Unlike some EEPROM devices that limit block writes to within a page boundary, there is no limitation on the start address when performing a block write to EEPROM, except when • There must be at least N locations from the start address to the highest EEPROM address (0xFBFF), to avoid writing to invalid addresses. An addresses cross a page boundary. In this case, both pages must be erased before programming. EEPROM EEPROM SLAVE ADDRESS ADDRESS S ADDRESS W A A AP HIGH BYTE LOW BYTE (0xF8 TO 0xFB) (0x00 TO 0xFF) • Figure 36. Setting an EEPROM Address • Because a page consists of 32 bytes, only the 3 MSBs of the address low byte are important f or page erasure. The lower five bits of the EEPROM address low byte specify the addresses within a page and are ignored during an erase operation. To write a single byte of data to EEPROM. In this case, the command byte is the high byte of the EEPROM address from 0xF8 to 0xFB. The first data byte is the low byte of the EEPROM address, and the second data byte is the actual data, as shown in Figure 37. 1 2 3 4 5 6 7 8 9 10 04635-043 Note that the ADM1067 features a clock extend function for writes to EEPROM. Programming an EEPROM byte takes approximately 250 μs, which limits the SMBus clock for repeated or block write operations. The ADM1067 pulls SCL low and extends the clock pulse when it cannot accept any more data. READ OPERATIONS The ADM1067 uses the following SMBus read protocols. Receive Byte In a receive byte operation, the master device receives a single byte from a slave device, as follows: 1. 2. 3. 4. 5. 6. The master device asserts a start condition on SDA. The master sends the 7-bit slave address followed by the read bit (high). The addressed slave device asserts ACK on SDA. The master receives a data byte. The master asserts no acknowledge on SDA. The master asserts a stop condition on SDA, and the transaction ends. EEPROM EEPROM SLAVE ADDRESS ADDRESS P S ADDRESS W A A HIGH BYTE LOW BYTE A DATA A (0xF8 TO 0xFB) (0x00 TO 0xFF) Figure 37. Single Byte Write to EEPROM Block Write In a block write operation, the master device writes a block of data to a slave device. The start address for a block write must have been set previously. In the ADM1067, a send byte operation sets a RAM address, and a write byte/word operation sets an EEPROM address, as follows: 1. 2. The master device asserts a start condition on SDA. The master sends the 7-bit slave address followed by the write bit (low). 3. The addressed slave device asserts ACK on SDA. 4. The master sends a command code that tells the slave device to expect a block write. The ADM1067 command code for a block write is 0xFC (1111 1100). 5. The slave asserts ACK on SDA. 6. The master sends a data byte that tells the slave device how many data bytes are being sent. The SMBus specification allows a maximum of 32 data bytes in a block write. 7. The slave asserts ACK on SDA. 8. The master sends N data bytes. 9. The slave asserts ACK on SDA after each data byte. 10. The master asserts a stop condition on SDA to end the transaction. 1 2 3 4 5 6 7 8 9 10 04635-044 In the ADM1067, the receive byte protocol is used to read a single byte of data from a RAM or EEPROM location whose address has previously been set by a send byte or write byte/word operation, as shown in Figure 39. 1 S 2 SLAVE ADDRESS R 3 A 4 DATA 5 A 6 P 04635-045 Figure 39. Single Byte Read from EEPROM or RAM Block Read In a block read operation, the master device reads a block of data from a slave device. The start address for a block read must have been set previously. In the ADM1067, this is done by a send byte operation to set a RAM address, or a write byte/word operation to set an EEPROM address. The block read operation itself consists of a send byte operation that sends a block read command to the slave, immediately followed by a repeated start and a read operation that reads out multiple data bytes, as follows: SLAVE BYTE S ADDRESS W A COMMAND 0xFC A COUNT A DATA A DATA A DATA A P (BLOCK WRITE) 1 2 N Figure 38. Block Write to EEPROM or RAM Rev. B | Page 30 of 32 ADM1067 1. 2. 3. 4. The master device asserts a start condition on SDA. The master sends the 7-bit slave address followed by the write bit (low). The addressed slave device asserts ACK on SDA. The master sends a command code that tells the slave device to expect a block read. The ADM1067 command code for a block read is 0xFD (1111 1101). The slave asserts ACK on SDA. The master asserts a repeat start condition on SDA. The master sends the 7-bit slave address followed by the read bit (high). The slave asserts ACK on SDA. The ADM1067 sends a byte-count data byte that tells the master how many data bytes to expect. The ADM1067 always returns 32 data bytes (0x20), which is the maximum allowed by the SMBus 1.1 specification. The master asserts ACK on SDA. The master receives 32 data bytes. The master asserts ACK on SDA after each data byte. The master asserts a stop condition on SDA to end the transaction. 2 3 4 56 7 8 9 10 11 12 Error Correction The ADM1067 provides the option of issuing a packet error correction (PEC) byte after a write to RAM, a write to EEPROM, a block write to RAM/EEPROM, or a block read from RAM/ EEPROM. This enables the user to verify that the data received by or sent from the ADM1067 is correct. The PEC byte is an optional byte sent after that last data byte has been written to or read from the ADM1067. The protocol is as follows: 1. The ADM1067 issues a PEC byte to the master. The master checks the PEC byte and issues another block read, if the PEC byte is incorrect. A no acknowledge (NACK) is generated after the PEC byte to signal the end of the read. 5. 6. 7. 8. 9. 2. Note that the PEC byte is calculated using CRC-8. The frame check sequence (FCS) conforms to CRC-8 by the polynomial 10. 11. 12. 13. 1 S C(x) = x8 + x2 + x1 + 1 See the SMBus 1.1 specification for details. An example of a block read with the optional PEC byte is shown in Figure 41. 1 2 3 4 56 7 8 9 10 11 12 S SLAVE W A COMMAND 0xFD A S SLAVE R A BYTE A DATA A ADDRESS (BLOCK READ) ADDRESS COUNT 1 SLAVE W A COMMAND 0xFD A S SLAVE R A BYTE A DATA A ADDRESS (BLOCK READ) ADDRESS COUNT 1 13 14 04635-046 13 14 15 A PEC A P 04635-047 DATA A 32 P DATA 32 Figure 40. Block Read from EEPROM or RAM Figure 41. Block Read from EEPROM or RAM with PEC Rev. B | Page 31 of 32 ADM1067 OUTLINE DIMENSIONS 6.00 BSC SQ 0.60 MAX 0.60 MAX 31 30 40 1 PIN 1 INDICATOR PIN 1 INDICATOR TOP VIEW 5.75 BCS SQ 0.50 BSC 0.50 0.40 0.30 EXPOSED PAD (BOTTOM VIEW) 4.25 4.10 SQ 3.95 10 11 21 20 0.25 MIN 4.50 REF 12° MAX 0.80 MAX 0.65 TYP 0.05 MAX 0.02 NOM 1.00 0.85 0.80 SEATING PLANE 0.30 0.23 0.18 0.20 REF COPLANARITY 0.08 COMPLIANT TO JEDEC STANDARDS MO-220-VJJD-2 Figure 42. 40-Lead Lead Frame Chip Scale Package [LFCSP_VQ] 6 mm × 6 mm Body, Very Thin Quad (CP-40) Dimensions shown in millimeters 0.75 0.60 0.45 1.20 MAX 48 1 9.00 BSC SQ 37 36 PIN 1 1.05 1.00 0.95 0.15 0.05 0° MIN SEATING PLANE 0.20 0.09 7° 3.5° 0° 0.08 MAX COPLANARITY TOP VIEW (PINS DOWN) 7.00 BSC SQ 12 13 25 24 VIEW A ROTATED 90° CCW COMPLIANT TO JEDEC STANDARDS MS-026ABC VIEW A 0.50 0.27 BSC 0.22 LEAD PITCH 0.17 Figure 43. 48-Lead Thin Plastic Quad Flat Package [TQFP] (SU-48) Dimensions shown in millimeters ORDERING GUIDE Model ADM1067ACP ADM1067ACP-REEL ADM1067ACP-REEL7 ADM1067ACPZ 1 ADM1067ASU ADM1067ASU-REEL ADM1067ASU-REEL7 ADM1067ASUZ1 EVAL-ADM1067LFEB EVAL-ADM1067TQEB 1 Temperature Range −40°C to +85°C −40°C to +85°C −40°C to +85°C −40°C to +85°C −40°C to +85°C −40°C to +85°C −40°C to +85°C −40°C to +85°C Package Description 40-Lead LFCSP_VQ 40-Lead LFCSP_VQ 40-Lead LFCSP_VQ 40-Lead LFCSP_VQ 48-Lead TQFP 48-Lead TQFP 48-Lead TQFP 48-Lead TQFP Evaluation Kit (LFCSP Version) Evaluation Kit (TQFP Version) Package Option CP-40 CP-40 CP-40 CP-40 SU-48 SU-48 SU-48 SU-48 Z = Pb-free part. ©2006 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. D04635-0-11/06(B) Rev. B | Page 32 of 32