FEATURES
FUNCTIONAL BLOCK DIAGRAM
Rev. E
REFIN
REFOUT REFGND
ADM1069
SDA SCL A1
A0
SMBus
INTERFACE
VREF
MUX
Complete supervisory and sequencing solution for up to
8 supplies
8 supply fault detectors enable supervision of supplies to
DPLIMx
In addition, the DAC output buffer is three-stated if DNLIMx >
DPLIMx. By programming the limit registers this way, the user
can make it very difficult for the DAC output buffers to be turned
on during normal system operation. The limit registers are among
the registers downloaded from EEPROM at startup.
Rev. E | Page 25 of 34
ADM1069
Data Sheet
APPLICATIONS DIAGRAM
12V IN
12V OUT
5V IN
5V OUT
3V IN
3V OUT
IN
DC-TO-DC1
EN
VH
5V OUT
3V OUT
3.3V OUT
VP1
VP2
VP3
1.25V OUT
1.2V OUT
0.9V OUT
VX1
VX2
VX3
OUT
3.3V OUT
ADM1069
PDO1
PDO2
IN
DC-TO-DC2
PDO3
PDO4
PDO5
EN
OUT
1.25V OUT
PWRGD
PDO6
SYSTEM RESET
IN
PDO7
DC-TO-DC3
POWRON
EN
VX4
1.2V OUT
DAC1
3.3V OUT
IN
OUT
10µF
10µF
EN
*ONLY ONE MARGINING CIRCUIT
SHOWN FOR CLARITY. DAC1 TO DAC4
ALLOW MARGINING FOR UP TO
FOUR VOLTAGE RAILS.
0.9V OUT
TRIM
DC-TO-DC4
Figure 34. Applications Diagram
Rev. E | Page 26 of 34
04735-068
REFOUT
REFIN VCCP VDDCAP GND
10µF
OUT
PDO8
Data Sheet
ADM1069
COMMUNICATING WITH THE ADM1069
CONFIGURATION DOWNLOAD AT POWER-UP
The configuration of the ADM1069 (undervoltage/overvoltage
thresholds, glitch filter timeouts, PDO configurations, and so on)
is dictated by the contents of the RAM. The RAM comprises
digital latches that are local to each of the functions on the device.
The latches are double-buffered and have two identical latches,
Latch A and Latch B. Therefore, when an update to a function
occurs, the contents of Latch A are updated first, and then the
contents of Latch B are updated with identical data. The advantages
of this architecture are explained in detail in the Updating the
Configuration section.
The two latches are volatile memory and lose their contents at
power-down. Therefore, the configuration in the RAM must be
restored at power-up by downloading the contents of the EEPROM
(nonvolatile memory) to the local latches. This download occurs
in steps, as follows:
1.
2.
3.
4.
5.
6.
With no power applied to the device, the PDOs are all high
impedance.
When 1.2 V appears on any of the inputs connected to the
VDD arbitrator (VH or VPx), the PDOs are all weakly pulled
to GND with a 20 kΩ resistor.
When the supply rises above the undervoltage lockout of
the device (UVLO is 2.5 V), the EEPROM starts to
download to the RAM.
The EEPROM downloads the contents to all Latch As.
When the contents of the EEPROM are completely
downloaded to the Latch As, the device controller signals
all Latch As to download to all Latch Bs simultaneously,
completing the configuration download.
At 0.5 ms after the configuration download completes, the first
state definition is downloaded from the EEPROM into
the SE.
Note that any attempt to communicate with the device prior to
the completion of the download causes the ADM1069 to issue
a no acknowledge (NACK).
UPDATING THE CONFIGURATION
After power-up, with all the configuration settings loaded from
the EEPROM into the RAM registers, the user may need to alter
the configuration of functions on the ADM1069, such as changing
the undervoltage or overvoltage limit of an SFD, changing the
fault output of an SFD, or adjusting the rise time delay of one of
the PDOs.
The ADM1069 provides several options that allow the user to
update the configuration over the SMBus interface. The
following three options are controlled in the UPDCFG register.
Option 1
Update the configuration in real time. The user writes to the RAM
across the SMBus, and the configuration is updated immediately.
Option 2
Update the Latch As without updating the Latch Bs. With this
method, the configuration of the ADM1069 remains unchanged
and continues to operate in the original setup until the instruction
is given to update the Latch Bs.
Option 3
Change the EEPROM register contents without changing the RAM
contents, and then download the revised EEPROM contents to the
RAM registers. With this method, the configuration of the
ADM1069 remains unchanged and continues to operate in the
original setup until the instruction is given to update the RAM.
The instruction to download from the EEPROM in Option 3 is
also a useful way to restore the original EEPROM contents if
revisions to the configuration are unsatisfactory. For example,
if the user must alter an overvoltage threshold, the RAM register
can be updated, as described in Option 1. However, if the user is
not satisfied with the change and wants to revert to the original
programmed value, the device controller can issue a command
to download the EEPROM contents to the RAM again, as
described in Option 3, restoring the ADM1069 to the original
configuration.
The topology of the ADM1069 makes this type of operation
possible. The local, volatile registers (RAM) are all double-buffered
latches. Setting Bit 0 of the UPDCFG register to 1 leaves the
double-buffered latches open at all times. If Bit 0 is set to 0 when a
RAM write occurs across the SMBus, only the first side of the
double-buffered latch is written to. The user must then write a 1
to Bit 1 of the UPDCFG register. This generates a pulse to update
all the second latches at once. EEPROM writes occur in a
similar way.
The final bit in this register can enable or disable EEPROM page
erasure. If this bit is set high, the contents of an EEPROM page
can all be set to 1. If low, the contents of a page cannot be erased,
even if the command code for page erasure is programmed across
the SMBus. The bit map for the UPDCFG register is shown in
the AN-721 Application Note. A flow diagram for download at
power-up and subsequent configuration updates is shown in
Figure 35.
Rev. E | Page 27 of 34
ADM1069
Data Sheet
SMBus
E
E
P
R
O
M
L
D
DEVICE
CONTROLLER
R
A
M
L
D
D
A
T
A
U
P
D
LATCH B
LATCH A
EEPROM
FUNCTION
(OV THRESHOLD
ON VP1)
04735-035
POWER-UP
(VCC > 2.5V)
Figure 35. Configuration Update Flow Diagram
UPDATING THE SEQUENCING ENGINE
Sequencing engine (SE) functions are not updated in the same
way as regular configuration latches. The SE has a dedicated 512byte EEPROM for storing state definitions, providing 63 individual
states, each with a 64-bit word (one state is reserved). At powerup, the first state is loaded from the SE EEPROM into the engine
itself. When the conditions of this state are met, the next state is
loaded from the EEPROM into the engine, and so on. The loading
of each new state takes approximately 10 µs.
To alter a state, the required changes must be made directly to
the EEPROM. RAM for each state does not exist. The relevant
alterations must be made to the 64-bit word, which is then
uploaded directly to the EEPROM.
INTERNAL REGISTERS
The major differences between the EEPROM and other
registers are as follows:
•
•
•
An EEPROM location must be blank before it can be
written to. If it contains data, the data must first be erased.
Writing to the EEPROM is slower than writing to the RAM.
Writing to the EEPROM must be restricted because it has a
limited write/cycle life of typically 10,000 write operations,
due to the usual EEPROM wear-out mechanisms.
The first EEPROM is split into 16 (0 to 15) pages of 32 bytes
each. Page 0 to Page 6, starting at Address 0xF800, hold the
configuration data for the applications on the ADM1069 (such
as the SFDs and PDOs). These EEPROM addresses are the same
as the RAM register addresses, prefixed by F8. Page 7 is
reserved. Page 8 to Page 15 are for customer use.
Data can be downloaded from the EEPROM to the RAM in one
of the following ways:
The ADM1069 contains a large number of data registers.
The principal registers are the address pointer register and
the configuration registers.
•
•
Address Pointer Register
The address pointer register contains the address that selects one
of the other internal registers. When writing to the ADM1069,
the first byte of data is always a register address that is written to
the address pointer register.
Configuration Registers
The configuration registers provide control and configuration
for various operating parameters of the ADM1069.
EEPROM
The ADM1069 has two 512-byte cells of nonvolatile, electrically
erasable, programmable read-only memory (EEPROM), from
Register Address 0xF800 to Register Address 0xFBFF. The
EEPROM is used for permanent storage of data that is not lost
when the ADM1069 is powered down. One EEPROM cell contains
the configuration data of the device; the other contains the state
definitions for the SE. Although referred to as read-only memory,
the EEPROM can be written to, as well as read from, using the
serial bus in exactly the same way as the other registers.
At power-up, when Page 0 to Page 6 are downloaded.
By setting Bit 0 of the UDOWNLD register (0xD8), which
performs a user download of Page 0 to Page 6.
SERIAL BUS INTERFACE
The ADM1069 is controlled via the serial system management
bus (SMBus) and is connected to this bus as a slave device,
under the control of a master device. It takes approximately
1 ms after power-up for the ADM1069 to download from the
EEPROM. Therefore, access to the ADM1069 is restricted until
the download is complete.
Identifying the ADM1069 on the SMBus
The ADM1069 has a 7-bit serial bus slave address (see Table 11).
The device is powered up with a default serial bus address. The
five MSBs of the address are set to 10011; the two LSBs are
determined by the logical states of Pin A1 and Pin A0. This
allows the connection of four ADM1069 devices to one SMBus.
Table 11. Serial Bus Slave Address
A1 Pin
Low
Low
High
High
1
A0 Pin
Low
High
Low
High
Hex Address
0x98
0x9A
0x9C
0x9E
7-Bit Address1
1001100x
1001101x
1001110x
1001111x
x means read/write bit. The address is shown only as the first 7 MSBs.
Rev. E | Page 28 of 34
Data Sheet
ADM1069
The device also has several identification registers (read-only)
that can be read across the SMBus. Table 12 lists these registers
with their values and functions.
Table 12. Identification Register Values and Functions
Name
MANID
REVID
MARK1
MARK2
Address
0xF4
0xF5
0xF6
0xF7
Value
0x41
0x02
0x00
0x00
Function
Manufacturer ID for Analog Devices
Silicon revision
Software brand
Software brand
General SMBus Timing
Figure 36, Figure 37, and Figure 38 are timing diagrams for
general read and write operations using the SMBus. The SMBus
specification defines specific conditions for different types of
read and write operations, which are discussed in the Write
Operations and Read Operations sections.
The general SMBus protocol operates as follows:
write, or it can be a register address that tells the slave where
subsequent data is to be written. Because data can flow in only
one direction, as defined by the R/W bit, sending a command
to a slave device during a read operation is not possible. Before
a read operation, it can be necessary to perform a write operation
to tell the slave what sort of read operation to expect and/or the
address from which data is to be read.
Step 3
When all data bytes have been read or written, stop conditions
are established. In write mode, the master pulls the data line high
during the 10th clock pulse to assert a stop condition. In read
mode, the master device releases the SDA line during the low
period before the ninth clock pulse, but the slave device does not
pull it low. This is known as a no acknowledge. The master then
takes the data line low during the low period before the 10th clock
pulse and then high during the 10th clock pulse to assert a stop
condition.
SCL Held Low Timeout
Step 1
The master initiates data transfer by establishing a start condition,
defined as a high-to-low transition on the serial data (SDA) line,
while the serial clock line (SCL) remains high. This indicates that
a data stream follows. All slave peripherals connected to the serial
bus respond to the start condition and shift in the next eight bits,
consisting of a 7-bit slave address (MSB first) plus an R/W bit.
This bit determines the direction of the data transfer, that is,
whether data is written to or read from the slave device (0 = write,
1 = read).
The peripheral whose address corresponds to the transmitted
address responds by pulling the data line low during the low period
before the ninth clock pulse, known as the acknowledge bit, and
by holding it low during the high period of this clock pulse.
All other devices on the bus remain idle while the selected device
waits for data to be read from or written to it. If the R/W bit is a 0,
the master writes to the slave device. If the R/W bit is a 1, the
master reads from the slave device.
Step 2
Data is sent over the serial bus in sequences of nine clock pulses:
eight bits of data followed by an acknowledge bit from the slave
device. Data transitions on the data line must occur during the
low period of the clock signal and remain stable during the high
period because a low-to-high transition when the clock is high
can be interpreted as a stop signal. If the operation is a write
operation, the first data byte after the slave address is a command
byte. This command byte tells the slave device what to expect next.
It can be an instruction telling the slave device to expect a block
If the bus master holds the SCL low for a time that is a multiple
of approximately 30 ms, the ADM1069 bus interface can timeout.
If this timeout happens, the in progress transaction is NACKed,
and the transaction must be repeated. This behavior is only seen
if the I2C bus master is interrupted midtransaction by a higher
priority task that delays completion of the transaction.
False Start Detection
The data hold time specification defines the time that data must
be valid on the SDA line, following an SCL falling edge. If there
are multiple ADM1069 devices on the same bus, one of the
ADM1069 devices can see the SCL/SDA transition due to an
acknowledge (ACK) from a different device as a start condition
because of internal timing skew, which for most transactions,
this is not an issue. In a case where the data appearing on the
bus after the false start is detected happens to match the address
of another ADM1069 on the bus, that device can incorrectly ACK.
A bus master can see this ACK as another bus master talking on
the bus, halt the bus transaction, and not produce any more
clocks on the SCL. As a result, the ADM1069 device that
incorrectly ACKed continues to hold down the SDA line low.
To retry the halted bus transaction, the bus master performs a
clock flush on the SCL by sending a series of up to 16 clock pulses.
The clock flush forces the ADM1069 to release the SDA line.
Rev. E | Page 29 of 34
ADM1069
Data Sheet
1
9
1
9
SCL
1
SDA
0
0
1
1
A1
A0
D7
R/W
D6
D5
D4
D3
D2
D1
ACK. BY
SLAVE
START BY
MASTER
D0
ACK. BY
SLAVE
FRAME 1
SLAVE ADDRESS
FRAME 2
COMMAND CODE
1
9
1
9
SCL
(CONTINUED)
D7
D6
D5
D4
D3
D2
D1
D7
D0
D6
D5
ACK. BY
SLAVE
FRAME 3
DATA BYTE
D4
D3
D2
D1
D0
ACK. BY
SLAVE
FRAME N
DATA BYTE
STOP
BY
MASTER
04735-036
SDA
(CONTINUED)
Figure 36. General SMBus Write Timing Diagram
1
9
1
9
SCL
1
SDA
0
0
1
1
A1
A0 R/W
D7
D6
D5
D4
D3
D2
D1
ACK. BY
SLAVE
START BY
MASTER
1
D0
ACK. BY
MASTER
FRAME 1
SLAVE ADDRESS
9
1
FRAME 2
DATA BYTE
9
SCL
(CONTINUED)
D7
D6
D5
D4
D3
D2
FRAME 3
DATA BYTE
D1
D0
D7
D6
D5
ACK. BY
MASTER
D4
D3
D2
D1
D0
NO ACK.
FRAME N
DATA BYTE
STOP
BY
MASTER
Figure 37. General SMBus Read Timing Diagram
tR
tF
t HD; STA
t LO W
SCL
t HI G H
t HD; STA
t HD; DAT
t SU; STA
t SU; STO
t SU; DAT
t BUF
P
S
S
Figure 38. Serial Bus Timing Diagram
Rev. E | Page 30 of 34
P
04735-038
SDA
04735-037
SDA
(CONTINUED)
Data Sheet
ADM1069
Data can be written to and read from both the RAM and the
EEPROM as single data bytes. Data can be written only to
unprogrammed EEPROM locations. To write new data to a
programmed location, the location contents must first be erased.
EEPROM erasure cannot be done at the byte level. The EEPROM
is arranged as 32 pages of 32 bytes each, and an entire page must
be erased.
Page erasure is enabled by setting Bit 2 in the UPDCFG register
(Address 0x90) to 1. If this bit is not set, page erasure cannot
occur, even if the command byte (0xFE) is programmed across
the SMBus.
The SMBus specification defines several protocols for different
types of read and write operations. The following abbreviations
are used in Figure 39 to Figure 47:
S = Start
P = Stop
R = Read
W = Write
A = Acknowledge
A = No acknowledge
Send Byte
In a send byte operation, the master device sends a single
command byte to a slave device, as follows:
3.
4.
5.
6.
2
S
SLAVE
ADDRESS
W
3
4
5
6
A
RAM
ADDRESS
(0x00 TO 0xDF)
A
P
To erase a page of EEPROM memory. EEPROM memory
can be written to only if it is unprogrammed. Before writing
to one or more EEPROM memory locations that are already
programmed, the page(s) containing those locations must
first be erased. EEPROM memory is erased by writing a
command byte.
The master sends a command code telling the slave device to
erase the page. The ADM1069 command code for a page
erasure is 0xFE (1111 1110). Note that, for a page erasure
to take place, the page address must be given in the previous
write word transaction (see the Write Byte/Word section).
In addition, Bit 2 in the UPDCFG register (Address 0x90)
must be set to 1.
1
2
S
SLAVE
ADDRESS
W
3
4
5
6
A
COMMAND
BYTE
(0xFE)
A
P
Figure 40. EEPROM Page Erasure
The ADM1069 uses the following SMBus write protocols.
1.
2.
1
Figure 39. Setting a RAM Address for Subsequent Read
WRITE OPERATIONS
To write a register address to the RAM for a subsequent
single byte read from the same address, or for a block read
or a block write starting at that address, as shown in Figure 39.
04735-039
The ADM1069 contains volatile registers (RAM) and nonvolatile registers (EEPROM). User RAM occupies Address 0x00 to
Address 0xDF; the EEPROM occupies Address 0xF800 to
Address 0xFBFF.
In the ADM1069, the send byte protocol is used for the following
two purposes:
04735-040
SMBus PROTOCOLS FOR RAM AND EEPROM
The master device asserts a start condition on SDA.
The master sends the 7-bit slave address followed by the
write bit (low).
The addressed slave device asserts an ACK on SDA.
The master sends a command code.
The slave asserts ACK on SDA.
The master asserts a stop condition on SDA and the
transaction ends.
Rev. E | Page 31 of 34
As soon as the ADM1069 receives the command byte,
page erasure begins. The master device can send a stop
command as soon as it sends the command byte. Page
erasure takes approximately 20 ms. If the ADM1069 is
accessed before erasure is complete, it responds with a NACK.
ADM1069
Data Sheet
Write Byte/Word
Block Write
In a write byte/word operation, the master device sends a
command byte and one or two data bytes to the slave device,
as follows:
In a block write operation, the master device writes a block of
data to a slave device. The start address for a block write must
have been set previously. In the ADM1069, a send byte operation sets a RAM address, and a write byte/word operation sets
an EEPROM address, as follows:
The master device asserts a start condition on SDA.
The master sends the 7-bit slave address followed by the
write bit (low).
3. The addressed slave device asserts an ACK on SDA.
4. The master sends a command code.
5. The slave asserts an ACK on SDA.
6. The master sends a data byte.
7. The slave asserts an ACK on SDA.
8. The master sends a data byte (or asserts a stop condition).
9. The slave asserts an ACK on SDA.
10. The master asserts a stop condition on SDA to end the
transaction.
In the ADM1069, the write byte/word protocol is used for the
following three purposes:
To write a single byte of data to the RAM. In this case, the
command byte is RAM Address 0x00 to RAM Address
0xDF, and the only data byte is the actual data, as shown in
Figure 41.
1
S
2
3
4
5
RAM
SLAVE
W A
ADDRESS
A
ADDRESS
(0x00 TO 0xDF)
6
7 8
DATA A P
The master device asserts a start condition on SDA.
The master sends the 7-bit slave address followed by
the write bit (low).
3. The addressed slave device asserts an ACK on SDA.
4. The master sends a command code that tells the slave
device to expect a block write. The ADM1069 command
code for a block write is 0xFC (1111 1100).
5. The slave asserts an ACK on SDA.
6. The master sends a data byte that tells the slave device how
many data bytes are being sent. The SMBus specification
allows a maximum of 32 data bytes in a block write.
7. The slave asserts an ACK on SDA.
8. The master sends N data bytes.
9. The slave asserts an ACK on SDA after each data byte.
10 The master asserts a stop condition on SDA to end the
transaction.
1
To set up a 2-byte EEPROM address for a subsequent read,
write, block read, block write, or page erasure. In this case,
the command byte is the high byte of EEPROM Address 0xF8
to EEPROM Address 0xFB. The only data byte is the low byte
of the EEPROM address, as shown in Figure 42.
2
3
4
5
6
7 8
EEPROM
EEPROM
ADDRESS
ADDRESS
A
A P
S SLAVE W A
LOW BYTE
HIGH BYTE
ADDRESS
(0x00 TO 0xFF)
(0xF8 TO 0xFB)
Figure 42. Setting an EEPROM Address
Because a page consists of 32 bytes, only the three MSBs of
the address low byte are important for page erasure. The
lower five bits of the EEPROM address low byte specify the
addresses within a page and are ignored during an erase
operation.
To write a single byte of data to the EEPROM. In this case, the
command byte is the high byte of EEPROM Address 0xF8
to EEPROM Address 0xFB. The first data byte is the low
byte of the EEPROM address, and the second data byte is
the actual data, as shown in Figure 43.
1
2
3
4
5
6
7
8
5
6
7
8
9
10
9 10
EEPROM
EEPROM
SLAVE
ADDRESS
ADDRESS
S ADDRESS W A
A
A DATA A P
HIGH BYTE
LOW BYTE
(0xF8 TO 0xFB)
(0x00 TO 0xFF)
There are fewer than N locations from the start address to
the highest EEPROM address (0xFBFF), which results in
writing to invalid addresses.
An address crosses a page boundary. In this case, both
pages must be erased before programming.
Note that the ADM1069 features a clock extend function for
writes to EEPROM. Programming an EEPROM byte takes
approximately 250 μs, which limits the SMBus clock for
repeated or block write operations. The ADM1069 pulls SCL
low and extends the clock pulse when it cannot accept any
more data.
04735-043
4
Unlike some EEPROM devices that limit block writes to within
a page boundary, there is no limitation on the start address
when performing a block write to EEPROM, except when
04735-042
1
3
Figure 44. Block Write to the EEPROM or RAM
Figure 41. Single Byte Write to the RAM
2
SLAVE
0xFC
BYTE A DATA A DATA A DATA A P
S ADDRESS
W A COMMAND
1
2
N
(BLOCK WRITE) A COUNT
04735-041
1.
2.
04735-044
1.
2.
Figure 43. Single Byte Write to the EEPROM
Rev. E | Page 32 of 34
Data Sheet
ADM1069
9.
The ADM1069 uses the following SMBus read protocols.
Receive Byte
In a receive byte operation, the master device receives a single
byte from a slave device, as follows:
3.
4.
5.
6.
The master device asserts a start condition on SDA.
The master sends the 7-bit slave address followed by the
read bit (high).
The addressed slave device asserts an ACK on SDA.
The master receives a data byte.
The master asserts a NACK on SDA.
The master asserts a stop condition on SDA, and the
transaction ends.
1
2
S
SLAVE
ADDRESS
R
3
4
5
6
A
DATA
A
P
04735-045
In the ADM1069, the receive byte protocol reads a single byte of
data from a RAM or EEPROM location whose address has
previously been set by a send byte or write byte/word operation,
as shown in Figure 45.
Figure 45. Single Byte Read from the EEPROM or RAM
Block Read
In a block read operation, the master device reads a block of
data from a slave device. The start address for a block read must
have been set previously. In the ADM1069, this is done by a
send byte operation to set a RAM address, or a write byte/word
operation to set an EEPROM address. The block read operation
itself consists of a send byte operation that sends a block read
command to the slave, immediately followed by a repeated start
and a read operation that reads out multiple data bytes, as
follows:
1.
2.
3.
4.
5.
6.
7.
8.
The master device asserts a start condition on SDA.
The master sends the 7-bit slave address followed by the
write bit (low).
The addressed slave device asserts an ACK on SDA.
The master sends a command code that tells the slave
device to expect a block read. The ADM1069 command
code for a block read is 0xFD (1111 1101).
The slave asserts an ACK on SDA.
The master asserts a repeat start condition on SDA.
The master sends the 7-bit slave address followed by the
read bit (high).
The slave asserts an ACK on SDA.
1
S
2
3
4
5 6
7
8
9
10
11
12
SLAVE
W A COMMAND 0xFD A S SLAVE R A BYTE A DATA A
ADDRESS
(BLOCK READ)
ADDRESS
COUNT
1
13
DATA
A
32
P
Figure 46. Block Read from the EEPROM or RAM
Error Correction
The ADM1069 provides the option of issuing a packet error
correction (PEC) byte after a write to the RAM, a write to the
EEPROM, a block write to the RAM/EEPROM, or a block read
from the RAM/ EEPROM. This option enables the user to verify
that the data received by or sent from the ADM1069 is correct.
The PEC byte is an optional byte sent after the last data byte has
been written to or read from the ADM1069. The protocol is the
same as a block read for Step 1 to Step 12 and then proceeds as
follows:
13. The ADM1069 issues a PEC byte to the master. The master
checks the PEC byte and issues another block read, if the
PEC byte is incorrect.
14. A NACK is generated after the PEC byte to signal the end
of the read.
15. The master asserts a stop condition on SDA to end the
transaction.
Note that the PEC byte is calculated using CRC-8. The frame
check sequence (FCS) conforms to CRC-8 by the polynomial
C(x) = x8 + x2 + x1 + 1
See the SMBus Version 1.1 specification for details.
An example of a block read with the optional PEC byte is shown
in Figure 47.
1
2
3
4
5 6
7
8
9
10
11
12
SLAVE
SLAVE
BYTE
DATA
COMMAND 0xFD
A
S ADDRESS W A (BLOCK READ) A S ADDRESS R A COUNT A
1
13 14 15
DATA
32
A PEC A P
Figure 47. Block Read from the EEPROM or RAM with PEC
Rev. E | Page 33 of 34
04735-047
1.
2.
10.
11.
12.
13.
The ADM1069 sends a byte-count data byte that tells the
master how many data bytes to expect. The ADM1069
always returns 32 data bytes (0x20), which is the maximum
allowed by the SMBus Version 1.1 specification.
The master asserts an ACK on SDA.
The master receives 32 data bytes.
The master asserts an ACK on SDA after each data byte.
The master asserts a stop condition on SDA to end the
transaction.
04735-046
READ OPERATIONS
ADM1069
Data Sheet
OUTLINE DIMENSIONS
0.75
0.60
0.45
1.60
MAX
9.00
BSC SQ
32
25
1
24
PIN 1
7.00
BSC SQ
TOP VIEW
(PINS DOWN)
1.45
1.40
1.35
0.15
0.05
0.20
0.09
7°
3.5°
0°
0.10 MAX
COPLANARITY
SEATING
PLANE
8
17
9
16
0.45
0.37
0.30
0.80
BSC
LEAD PITCH
VIEW A
VIEW A
ROTATED 90° CCW
COMPLIANT TO JEDEC STANDARDS MS-026-BBA
Figure 48. 32-Lead Low Profile Quad Flat Package [LQFP]
(ST-32-2)
Dimensions shown in millimeters
0.30
0.25
0.18
31
40
30
0.50
BSC
1
TOP VIEW
0.80
0.75
0.70
10
11
20
0.05 MAX
0.02 NOM
COPLANARITY
0.08
0.20 REF
SEATING
PLANE
4.25
4.10 SQ
3.95
EXPOSED
PAD
21
0.45
0.40
0.35
PIN 1
INDICATOR
BOTTOM VIEW
0.25 MIN
FOR PROPER CONNECTION OF
THE EXPOSED PAD, REFER TO
THE PIN CONFIGURATION AND
FUNCTION DESCRIPTIONS
SECTION OF THIS DATA SHEET.
COMPLIANT TO JEDEC STANDARDS MO-220-WJJD.
05-06-2011-A
PIN 1
INDICATOR
6.10
6.00 SQ
5.90
Figure 49. 40-Lead Lead Frame Chip Scale Package [LFCSP]
6 mm × 6 mm Body and 0.75 mm Package Height
(CP-40-9)
Dimensions shown in millimeters
ORDERING GUIDE
Model 1
ADM1069ASTZ
ADM1069ASTZ-REEL7
ADM1069ACPZ
ADM1069ACPZ-REEL
ADM1069ACPZ-REEL7
EVAL-ADM1069LQEBZ
1
Temperature Range
−40°C to +85°C
−40°C to +85°C
−40°C to +85°C
−40°C to +85°C
−40°C to +85°C
Package Description
32-Lead Low Profile Quad Flat Package [LQFP]
32-Lead Low Profile Quad Flat Package [LQFP]
40-Lead Lead Frame Chip Scale Package [LFCSP]
40-Lead Lead Frame Chip Scale Package [LFCSP]
40-Lead Lead Frame Chip Scale Package [LFCSP]
Evaluation Board (LQFP Version)
Z = RoHS Compliant Part.
I2C refers to a communications protocol originally developed by Philips Semiconductors (now NXP Semiconductors).
©2005–2016 Analog Devices, Inc. All rights reserved. Trademarks and
registered trademarks are the property of their respective owners.
D04735-0-6/16(E)
Rev. E | Page 34 of 34
Package Option
ST-32-2
ST-32-2
CP-40-9
CP-40-9
CP-40-9